Control method and device of permanent magnet synchronous motor and permanent magnet synchronous motor

Abstract

The application provides a control method and device of a permanent magnet synchronous motor and the permanent magnet synchronous motor, and the method comprises the following steps: S1, obtaining a phase-lagged bus voltage sampling signal by sampling and filtering a bus voltage of the permanent magnet synchronous motor; S2, performing phase compensation filtering on the bus voltage sampling signal to obtain a compensated bus voltage; S3, calculating a real-time duty cycle signal according to a Park inverse transformation output voltage and the compensated bus voltage; and S4, controlling an inverter according to the real-time duty cycle signal to drive the permanent magnet synchronous motor to operate. The application proposes a phase compensation algorithm by using the repetitive periodicity of the bus voltage, so that the compensated bus voltage value is closer to the actual bus voltage value, and the accuracy of bus voltage measurement is improved. The harmonics of the motor current can be effectively filtered out.

Description

Technical Field

[0001] This invention relates to the field of automatic control, and more specifically to a control method, apparatus, and permanent magnet synchronous motor for a permanent magnet synchronous motor. Background Technology

[0002] Improving system reliability, increasing power factor, and reducing costs are growing trends in home appliances such as refrigerators, air conditioners, and fans. However, harmonics in permanent magnet synchronous motors are often difficult to suppress.

[0003] Chinese patent CN108880373A discloses a beat frequency suppression method in an electrolytic capacitor-free permanent magnet synchronous motor air conditioning drive system. The method addresses the beat frequency phenomenon caused by the fluctuation component of twice the grid frequency contained in the DC bus voltage by adding d-axis and q-axis beat frequency voltage reference values ​​to the anti-Park module to suppress the beat frequency current.

[0004] The existing technology requires a solution that is simple to implement and can effectively suppress harmonics in permanent magnet synchronous motor systems without electrolytic capacitors.

[0005] The information disclosed in the background section above is only used to further understand the background of the present invention, and therefore may include information known to those skilled in the art that does not constitute prior art. Summary of the Invention

[0006] This invention provides a control method, device, and permanent magnet synchronous motor (PMSM). The present invention addresses the issue of phase lag and amplitude attenuation in the bus voltage after sampling and filtering. This invention proposes a phase compensation algorithm utilizing the repetitive periodicity of the bus voltage in an electrolytic capacitor-free system, making the compensated bus voltage value closer to the actual bus voltage value. Furthermore, to address the problem of numerous motor current harmonics in electrolytic capacitor-free PMSM drive systems, this invention proposes using the phase-compensated bus voltage sampling signal for real-time duty cycle calculation, which can effectively suppress motor current harmonics in electrolytic capacitor-free systems.

[0007] The first aspect of the present invention provides a control method for a permanent magnet synchronous motor, characterized in that the method includes: S1: obtaining a phase-lagging bus voltage sampling signal by sampling and filtering the bus voltage of the permanent magnet synchronous motor; S2: performing phase compensation filtering on the bus voltage sampling signal to obtain a compensated bus voltage; S3: calculating a real-time duty cycle signal based on the Park inverse transformer output voltage and the compensated bus voltage; S4: controlling an inverter to drive the permanent magnet synchronous motor to operate based on the real-time duty cycle signal.

[0008] According to an embodiment of the present invention, in S2, the SVPWM unit calculates the real-time duty cycle signal based on the voltages of the α-axis and β-axis after Park inverse transformation and the compensated bus voltage. The voltages of the α-axis and β-axis are the voltages of the d-axis and q-axis obtained by the current controller after Park inverse transformation.

[0009] According to one embodiment of the present invention, the bus capacitor of the permanent magnet synchronous motor is an electrolytic capacitor. Alternatively, the bus capacitor of the permanent magnet synchronous motor may be a film capacitor.

[0010] According to one embodiment of the present invention, in step S2, the bus voltage sampling signal is subjected to phase compensation row filtering so that the compensated bus voltage is close to the actual bus voltage.

[0011] According to one embodiment of the present invention, the lag phase in the phase-lagging bus voltage sampling signal is related to the voltage angular frequency of the permanent magnet synchronous motor and the angular frequency of the bus voltage angular fluctuation.

[0012] According to one embodiment of the present invention, in S2, the compensated bus voltage signal is obtained by acquiring the time that the phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal.

[0013] According to one embodiment of the present invention, the phase-lagging bus voltage sampling signal lags the actual bus voltage signal by a time δT, where T is the period of the bus voltage. S2 includes: recording the bus voltage data of the previous period, and obtaining the bus voltage value of the current period by delaying the bus voltage of the previous period by a time interval T-δT, i.e., u. (t) =u [t-(T-δT)] , where u (t) The current cycle bus voltage value, u [t-(T-δT)] This is the bus voltage value from the previous cycle.

[0014] According to one embodiment of the present invention, the time that the phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal is the sum of the lag time caused by sampling and filtering the bus voltage and the lag time generated by software processing in the permanent magnet synchronous motor.

[0015] According to one embodiment of the present invention, the lag time caused by sampling and filtering the bus voltage is: the ratio of the lag phase in the phase-lagped bus voltage sampling signal to the angular frequency of the bus voltage fluctuation.

[0016] According to one embodiment of the present invention, the phase-lagging bus voltage sampling signal includes a voltage change related to the lagging phase, wherein the voltage change is ΔU. a : Where ω is the voltage angular frequency of the permanent magnet synchronous motor, ω r U is the angular frequency of the bus voltage fluctuation. r U is the amplitude of the bus voltage ripple. D The DC value of the bus voltage, φ is the lag phase, U m This represents the amplitude of the fundamental input voltage of the permanent magnet synchronous motor.

[0017] A second aspect of the present invention provides a control device for a permanent magnet synchronous motor, characterized in that the device includes a voltage sampling filter, a phase compensation module, and an SVPWM algorithm module, wherein the voltage sampling filter samples and filters the bus voltage of the permanent magnet synchronous motor to obtain a phase-lagging bus voltage sampling signal; the phase compensation module performs phase compensation filtering on the bus voltage sampling signal to obtain a compensated bus voltage; the SVPWM algorithm module includes a Park inverse transform and an SVPWM unit, wherein the SVPWM unit calculates a real-time duty cycle signal based on the output voltage of the Park inverse transform and the compensated bus voltage, and outputs the real-time duty cycle signal to an inverter to drive the permanent magnet synchronous motor.

[0018] According to an embodiment of the present invention, the SVPWM algorithm module further includes a current controller, wherein the SVPWM unit calculates the real-time duty cycle signal based on the voltages of the α-axis and β-axis after the inverse Park transformation and the compensated bus voltage, wherein the voltages of the α-axis and β-axis are the voltages obtained by the current controller after the voltages of the d-axis and q-axis have undergone the inverse Park transformation.

[0019] According to one embodiment of the present invention, in the phase algorithm compensation module, the lagging phase in the phase-lagging bus voltage sampling signal is related to the voltage angular frequency of the permanent magnet synchronous motor and the angular frequency of the bus voltage fluctuation.

[0020] According to one embodiment of the present invention, in the phase algorithm compensation module, the compensated bus voltage signal is obtained by acquiring the time by which the phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal.

[0021] According to an embodiment of the present invention, in the phase algorithm compensation module, the phase-lagging bus voltage sampling signal lags the actual bus voltage signal by a time δT, where T is the period of the bus voltage. S2 includes: recording the bus voltage data of the previous period, and obtaining the bus voltage value of the current period by delaying the bus voltage of the previous period by a time interval T-δT, i.e., u. (t) =u [t-(T-δT)] , where u (t) The current cycle bus voltage value, u [t-(T-δT)]This is the bus voltage value from the previous cycle.

[0022] According to one embodiment of the present invention, in the phase algorithm compensation module, the time that the phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal is the sum of the lag time caused by sampling and filtering the bus voltage and the lag time generated by software processing in the permanent magnet synchronous motor. The lag time caused by sampling and filtering the bus voltage is the ratio of the lagging phase in the phase-lagging bus voltage sampling signal to the angular frequency of the bus voltage fluctuation.

[0023] According to an embodiment of the present invention, in the phase algorithm compensation module, the phase-lagging bus voltage sampling signal includes a voltage change related to the lagging phase, wherein the voltage change is...

[0024] Where ω is the voltage angular frequency of the permanent magnet synchronous motor, ω r U is the angular frequency of the bus voltage fluctuation. r U is the amplitude of the bus voltage ripple. D The DC value of the bus voltage, φ is the lag phase, U m This represents the amplitude of the fundamental input voltage of the permanent magnet synchronous motor.

[0025] A third aspect of the present invention provides a permanent magnet synchronous motor, characterized in that the permanent magnet synchronous motor uses the control method of the permanent magnet synchronous motor described above, or includes the control device of the permanent magnet synchronous motor described above.

[0026] This invention proposes a phase compensation algorithm that utilizes the repetitive periodicity of the bus voltage in an electrolysis-free system. This algorithm makes the compensated bus voltage value closer to the actual bus voltage value, thus improving the accuracy of bus voltage measurement. The comparison of the effects is shown in the figure. Furthermore, this invention uses the phase-compensated bus voltage sampling signal to calculate the duty cycle in real time, effectively suppressing harmonics in the motor current of the electrolysis-free system. Attached Figure Description

[0027] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A structural block diagram of a permanent magnet synchronous motor system according to an exemplary embodiment of the present invention is shown.

[0029] Figure 2 A block diagram of a control device for a permanent magnet synchronous motor according to an exemplary embodiment of the present invention is shown.

[0030] Figure 3 A block diagram of an RC filter current according to an exemplary embodiment of the present invention is shown.

[0031] Figure 4 A diagram of the uncompensated bus voltage signal is shown according to an exemplary embodiment of the present invention.

[0032] Figure 5 A diagram of the compensated bus voltage signal according to an exemplary embodiment of the present invention is shown.

[0033] Figure 6 A flowchart of a control method for a magnetic synchronous motor according to an exemplary embodiment of the present invention is shown.

[0034] Figure 7 A current spectrum diagram of a motor without phase compensation is shown according to an exemplary embodiment of the present invention.

[0035] Figure 8 A current spectrum diagram of a motor with phase compensation according to an exemplary embodiment of the present invention is shown. Specific Implementation

[0036] As used herein, the terms "first," "second," etc., can be used to describe elements in exemplary embodiments of the present invention. These terms are used only to distinguish one element from another, and the inherent features or order of the corresponding elements are not limited by the term. Unless otherwise defined, all terms used herein (including technical or scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in common dictionaries are interpreted as having the same meaning as in the context of the relevant technical field, and are not interpreted as having an ideal or overly formal meaning, unless explicitly defined as having such a meaning in this invention.

[0037] Those skilled in the art will understand that the apparatus and methods of the present invention described herein and illustrated in the accompanying drawings are non-limiting exemplary embodiments, and the scope of the invention is defined only by the claims. Features illustrated or described in conjunction with an exemplary embodiment may be combined with features of other embodiments. Such modifications and variations are included within the scope of the invention.

[0038] In the following description, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, detailed descriptions of known functions or configurations are omitted to avoid unnecessarily obscuring the key technical aspects of the invention. Furthermore, throughout the description, the same reference numerals always refer to the same circuits, modules, or units, and for the sake of brevity, repeated descriptions of the same circuits, modules, or units are omitted.

[0039] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0040] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0041] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0042] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0043] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0044] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0045] Traditional permanent magnet synchronous motor drive systems use large electrolytic capacitors for the bus capacitor, which suffers from drawbacks such as short lifespan and large size. Film capacitors, on the other hand, offer advantages such as long lifespan and small size. Therefore, replacing large electrolytic capacitors with film capacitors in motor drive systems can improve the shortcomings of traditional systems. Electrolytic capacitor-free permanent magnet synchronous motor drive systems offer advantages such as long lifespan, high power factor, low cost, high reliability, and small size. This invention utilizes the repetitive periodicity of the bus voltage in an electrolytic capacitor-free system to propose a phase compensation algorithm, making the compensated bus voltage value closer to the actual bus voltage value and improving the accuracy of bus voltage measurement. Furthermore, this invention uses the phase-compensated bus voltage sampling signal for real-time duty cycle calculation, effectively suppressing current harmonics in the electrolytic capacitor-free system motor.

[0046] Figure 1 This is a structural block diagram of a permanent magnet synchronous motor system according to an exemplary embodiment of the present invention.

[0047] like Figure 1 As shown, Figure 1 The upper part is the connection circuit structure of the permanent magnet synchronous motor, which consists of an AC power supply, an uncontrolled rectifier bridge, a bus thin-film capacitor, a three-phase voltage-source inverter, and the permanent magnet synchronous motor. Figure 1 The lower part is the control device for the permanent magnet synchronous motor, which consists of a voltage sampling filter, a phase compensation module, and an SVPWM algorithm module. The SVPWM algorithm module includes Clark transform, Park transform, position and speed feedback signal units, a speed controller, a current controller, inverse Park transform, and SWPWM algorithm units.

[0048] like Figure 1 As shown, PMSM is a permanent magnet synchronous motor; L is a filter inductor; D1, D2, D3, and D4 are four diodes forming an uncontrolled rectifier bridge; C1 is the bus capacitor, which is a small-capacity film capacitor; V1 is the voltage measurement unit; J1, J2, J3, J4, J5, and J6 are IGBT switching transistors, forming an inverter; VD1, VD2, VD3, VD4, VD5, and VD... 16 For protection diodes on the inverter; i a i b and i c Let i be the three-phase current of the PMSM. d i q This refers to the DQ axis current of the permanent magnet synchronous motor; u d u q This refers to the DQ axis voltage of the permanent magnet synchronous motor; u α u β V1 represents the αβ axis voltage of the permanent magnet synchronous motor. V2 represents the sampled bus voltage.

[0049] like Figure 1 As shown, the current i is obtained by subtracting the given rotational speed n* from the feedback rotational speed n and processing the result by the speed controller. d Instruction, i q Instructions and Feedback i q The error value of the current is processed by the current controller to obtain the voltage u. q Current i d =0 and feedback current i d The difference is calculated, and the voltage u is obtained after processing by the current controller. d u d u q After Park inverse transform to u α and u β ,u α u β and u dc (t) The signal for controlling the inverter is obtained after processing by the SVPWM module, and the inverter is used to supply power to the motor.

[0050] i abc The three-phase ABC currents of the motor are obtained from current sampling. These three-phase ABC currents are then transformed using Clarke coordinates to obtain the i-th phase in the two-phase stationary coordinate system αβ. α i β Current. i α i β The current is then transformed by Park to obtain the i in the two-phase synchronous rotating coordinate system dq. d i q Electric current.

[0051] According to one or more embodiments of the present invention, the theoretical analysis of the generation of motor current harmonics by the lag phase after bus voltage filtering is as follows:

[0052] The switching functions Sa, Sb, Sc of each phase of the inverter can be derived from the phase voltage u output by each phase. a * (t), u b * (t), u c * (t) and the bus voltage U containing pulsating components dc (t) represents:

[0053]

[0054] in: u dc (t)=U D +U r sin(ω r t),

[0055] Where ω is the voltage angular frequency of the permanent magnet synchronous motor, ω r U is the angular frequency of the bus voltage fluctuation. r This represents the ripple amplitude of the bus voltage. U D DC current of bus voltage, U m This is the fundamental amplitude of the inverter's output voltage, and also the fundamental amplitude of the motor's input voltage.

[0056] (1) If the bus voltage of the electrolysis-free system is not processed by a filter, the ideal bus voltage is u. dc (t)=U D +U r sin(ω r If t), then the voltage input to phase A of the motor is: u a(t) =u dc (t)*S a =U m sin(ωt), for the other two phases, the expression is similar to that of phase A, and will not be repeated here. Only phase A is used as an example.

[0057] Therefore, if there is no phase-lagging bus voltage, the voltage input to the motor terminals is the ideal voltage u. a(t) Since it does not contain harmonic voltage, it will not generate harmonic current. However, in practice, the bus voltage or sampling signal may contain harmonics, which must be filtered, inevitably leading to phase lag of the bus voltage.

[0058] (2) If the bus voltage in the non-electrolysis system is processed by a filter, the phase-lagging bus voltage is:

[0059] U dc (t)=U D +U r sin(ω r t-φ), where φ is the lagging phase;

[0060] The voltage input from the inverter to the motor terminal is:

[0061]

[0062] in:

[0063] The above theoretical analysis shows that the lag phase after bus voltage filtering will cause the inverter output voltage to contain ΔU. a Item, ΔU a The term is related to the angular frequency ω of the motor voltage and the angular frequency ω of the bus voltage fluctuation. rThe relevant harmonic quantities. Therefore, the bus voltage of the electrolysis-free system has a phase lag after filtering. Without phase compensation, this will increase the current harmonics of the motor in the electrolysis-free system; if a certain phase compensation can be performed, the current harmonics of the motor in the electrolysis-free system can be reduced.

[0064] Figure 2 A block diagram of a control device for a permanent magnet synchronous motor according to an exemplary embodiment of the present invention is shown.

[0065] like Figure 2 As shown, the control device for the permanent magnet synchronous motor includes a voltage sampling filter, a phase compensation module, and an SVPWM algorithm module. The voltage sampling filter samples and filters the bus voltage of the permanent magnet synchronous motor to obtain a phase-lagging bus voltage sampling signal. The phase compensation module performs phase compensation filtering on the bus voltage sampling signal to obtain a compensated bus voltage. The SVPWM algorithm module includes a Park inverse transform and an SVPWM unit. The SVPWM unit calculates a real-time duty cycle signal based on the output voltage of the Park inverse transform and the compensated bus voltage, and outputs the real-time duty cycle signal to the inverter to drive the permanent magnet synchronous motor.

[0066] According to one or more embodiments of the present invention, the specific algorithm in the phase compensation module of the present invention is as follows:

[0067] The mathematical model of the permanent magnet synchronous motor in the synchronous rotating coordinate system dq is as follows:

[0068]

[0069] Where: u d u q The voltage components of a permanent magnet synchronous motor in the synchronous rotating coordinate system dq; i d i q Let L represent the current component of the permanent magnet synchronous motor in the synchronous rotating coordinate system dq. R is the resistance of the motor stator winding; L... d and L q These are the stator direct-axis inductance and stator quadrature-axis inductance, respectively; ω e ψ is the electric angular velocity. f This refers to the rotor flux linkage of a permanent magnet motor.

[0070] The three-phase stator current i of a permanent magnet synchronous motor a i b and i c The formula for transforming from the physical ABC coordinate system to the synchronously rotating coordinate system dq is:

[0071]

[0072] Where: ia i b and i c This refers to the three-phase stator current of the permanent magnet motor. Therefore, the principle of the bus voltage phase compensation algorithm of this invention is as follows:

[0073] In a permanent magnet synchronous motor drive system without electrolytic capacitors on the bus, the bus voltage pulsates regularly and periodically at 100Hz. The waveform of the bus voltage in the current cycle repeats the waveform of the previous cycle. This repetitive periodicity can be used for phase compensation of the bus voltage. Assuming the filtered bus voltage lags the actual bus voltage by δT, and the period of the bus voltage is T, the current bus voltage can be obtained by delaying the previous cycle's bus voltage by T-δT, i.e., u (t) =u [t-(T-δT)] , where u (t) The value of the bus voltage for the current period, u [t-(T-δT)] This is the corresponding value of the bus voltage in the previous cycle.

[0074] According to one or more embodiments of the present invention, the selection of δT includes:

[0075] When a voltage sampling filter is used, it is a sampling RC filter circuit, such as... Figure 3 As shown.

[0076] Figure 3 A block diagram of an RC filter current according to an exemplary embodiment of the present invention is shown.

[0077] like Figure 3 As shown, the transfer function of the RC filter function is:

[0078] Where V1 is the sampled bus voltage before filtering; U ofilter The output is the filtered voltage; R filter C is the resistor in the filter circuit. filter The capacitor in the filter circuit; jω r The angular frequency of the bus voltage fluctuation can be, for example, 100Hz × 2π = 200π rad / s.

[0079] Phase lag caused by RC filter circuit `an tan()` is the arctangent function. The lag time caused by the bus voltage sampling circuit is... T filter Let be the filter period. Then the total phase lag time δT should include: the time δT caused by the bus voltage sampling and filtering circuit. filter The lag time δT caused by processing such as software filtering, etc. soft δT soft This can be obtained through trial and error based on experimental results. Therefore, we can conclude that:

[0080] δT=δT filter +δT soft Therefore, the range of values ​​for time δT is: δT >= δT filter

[0081] Figure 4 A diagram of the uncompensated bus voltage signal is shown according to an exemplary embodiment of the present invention. Figure 5 A diagram of the compensated bus voltage signal according to an exemplary embodiment of the present invention is shown. Figure 4 and Figure 5 The comparison shows that the phase compensation algorithm can achieve the phase compensation effect.

[0082] Figure 6 A flowchart of a control method for a magnetic synchronous motor according to an exemplary embodiment of the present invention is shown.

[0083] like Figure 6 As shown, in S1: the phase-lagging bus voltage sampling signal is obtained by sampling and filtering the bus voltage of the permanent magnet synchronous motor;

[0084] In S2: Phase compensation and row filtering are performed on the bus voltage sampling signal to obtain the compensated bus voltage;

[0085] In S3: Calculate the real-time duty cycle signal based on the Park inverse transform output voltage and the compensated bus voltage;

[0086] In S4: The inverter is controlled according to the real-time duty cycle to drive the permanent magnet synchronous motor.

[0087] According to one or more embodiments of the present invention, a bus voltage sampling signal is obtained from the voltage sampling current. This bus voltage sampling signal is then filtered by an RC filter circuit or a digital filter to obtain a phase-lagging bus voltage signal. This bus voltage signal is a repetitive periodic signal, which can be compensated for using the bus voltage phase compensation algorithm proposed herein, making the compensated bus voltage closer to the actual bus voltage. Based on the u output of the current loop PI regulator... α u β The compensated bus voltage value is input to the SVPWM unit to calculate the real-time duty cycle. The SVPWM output control signal controls the inverter to enable the permanent magnet synchronous motor to operate stably.

[0088] According to one or more embodiments of the present invention, the bus voltage sampling signal is subjected to phase compensation row filtering so that the compensated bus voltage is close to the actual bus voltage. The lag phase in the phase-lagging bus voltage sampling signal is related to the voltage angular frequency of the permanent magnet synchronous motor and the angular frequency of the bus voltage angular fluctuation. In step S2, the compensated bus voltage signal is obtained by acquiring the time that the phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal. Wherein, the time that the phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal is δT, where T is the period of the bus voltage. Step S2 includes: recording the bus voltage data of the previous period, and obtaining the bus voltage value of the current period (i.e., the compensated bus voltage signal) by delaying the bus voltage of the previous period by a time interval of T-δT. (t) =u [t-(T-δT)] , where u (t) The current cycle bus voltage value, u [t-(T-δT)] This represents the bus voltage value of the previous cycle. The time that the phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal is the sum of the lag time caused by sampling and filtering the bus voltage and the lag time generated by software processing in the permanent magnet synchronous motor. The lag time caused by sampling and filtering the bus voltage is the ratio of the lagging phase in the phase-lagging bus voltage sampling signal to the angular frequency of the bus voltage fluctuation.

[0089] Figure 7 A current spectrum diagram of a motor without phase compensation is shown according to an exemplary embodiment of the present invention. Figure 8 A current spectrum diagram of a motor with phase compensation according to an exemplary embodiment of the present invention is shown.

[0090] like Figure 7 and Figure 8 As shown, the two figures illustrate the current harmonics at 60Hz. Figure 7 The current harmonic components shown are predominantly near the third harmonic, in addition to the fundamental frequency. Figure 8 The current harmonics on display are mainly concentrated in the fundamental frequency (60Hz), while the harmonic content elsewhere is reduced. Figure 8 The current harmonics in the medium are significantly smaller than those in the medium. Figure 7 Current harmonics in the medium.

[0091] The present invention also provides a permanent magnet synchronous motor, which uses the control method of the permanent magnet synchronous motor of the present invention, or includes the control device of the permanent magnet synchronous motor of the present invention.

[0092] The accompanying drawings and detailed description of the invention, cited above as examples, serve to explain the invention but do not limit its meaning or scope as described in the claims. Therefore, those skilled in the art can readily make modifications from the above description. Furthermore, those skilled in the art can remove some of the components described herein without degrading performance, or add other components to improve performance. Additionally, those skilled in the art can change the order of steps in the method described herein depending on the process or equipment environment. Therefore, the scope of the invention should not be determined by the embodiments described above, but rather by the claims and their equivalents.

[0093] Although the invention has been described in conjunction with embodiments now considered to be achievable, it should be understood that the invention is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent configurations included within the spirit and scope of the appended claims.

Claims

1. A control method for a permanent magnet synchronous motor, characterized in that, The method includes: S1: The phase-lagging bus voltage sampling signal is obtained by sampling and filtering the bus voltage of the permanent magnet synchronous motor; S2: Perform phase compensation row filtering on the bus voltage sampling signal to obtain the compensated bus voltage; S3: Calculate the real-time duty cycle signal based on the Park inverse transform output voltage and the compensated bus voltage; S4: Control the inverter to drive the permanent magnet synchronous motor according to the real-time duty cycle; In step S2, the compensated bus voltage is close to the actual bus voltage. The lag phase in the phase-lagging bus voltage sampling signal is related to the angular frequency of the bus voltage fluctuation.

2. The method according to claim 1, characterized in that, in, The bus capacitor of the permanent magnet synchronous motor is an electrolytic capacitor.

3. The method according to claim 1, characterized in that, In S2, the compensated bus voltage signal is obtained by acquiring the time that the phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal.

4. The method according to claim 3, characterized in that, in, The phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal by a time δT, where T is the period of the bus voltage. S2 includes: recording the bus voltage data of the previous period, and obtaining the bus voltage value of the current period by delaying the previous period's bus voltage by a time interval of T-δT. , where u (t) This is the current cycle bus voltage value. This is the bus voltage value from the previous cycle.

5. The method according to claim 3, characterized in that, in, The time that the phase-lagging bus voltage sampling signal lags behind the actual bus voltage signal is: The sum of the lag time caused by sampling and filtering the bus voltage and the lag time generated by software processing in the permanent magnet synchronous motor.

6. The method according to claim 5, wherein, The lag time caused by sampling and filtering the bus voltage is the ratio of the lag phase in the phase-lagging bus voltage sampling signal to the angular frequency of the bus voltage fluctuation.

7. The method according to claim 6, wherein, The phase-lagging bus voltage sampling signal includes voltage changes related to the lagging phase, and the voltage variable is... : ； Where ω is the voltage angular frequency of the permanent magnet synchronous motor, ω r U is the angular frequency of the bus voltage fluctuation. r U is the amplitude of the bus voltage ripple. D DC bus voltage It is a lagging phase. This represents the amplitude of the fundamental input voltage of the permanent magnet synchronous motor.

8. A control device for a permanent magnet synchronous motor, characterized in that, The device includes a voltage sampling filter, a phase compensation module, and an SVPWM algorithm module, wherein... The voltage sampling filter samples and filters the bus voltage of the permanent magnet synchronous motor to obtain a phase-lagging bus voltage sampling signal. The phase compensation module performs phase compensation row filtering on the bus voltage sampling signal to obtain the compensated bus voltage; the compensated bus voltage is close to the actual bus voltage. The SVPWM algorithm module includes a Park inverse transform and an SVPWM unit. The SVPWM unit calculates the real-time duty cycle signal based on the output voltage of the Park inverse transform and the compensated bus voltage, and outputs the real-time duty cycle signal to the inverter to drive the permanent magnet synchronous motor. The compensated bus voltage is close to the actual bus voltage; the lag phase in the phase-lagging bus voltage sampling signal is related to the angular frequency of the bus voltage fluctuation.

9. A permanent magnet synchronous motor, characterized in that, The permanent magnet synchronous motor uses the control method of the permanent magnet synchronous motor according to any one of claims 1-7, or includes the control device of the permanent magnet synchronous motor according to claim 8.

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