Gate voltage bootstrap switching circuit for SAR ADC

Abstract

The present invention discloses a gate voltage bootstrap switch circuit for a SAR ADC, which includes a voltage control unit and a switch transistor unit. The voltage control unit includes a first capacitor and a second capacitor connected in parallel. One end of each of the first capacitor and the second capacitor is connected to an external power supply, and the other end of each is connected to the switch transistor unit. The switch transistor unit includes a switch MOS transistor, a first MOS transistor, and a second MOS transistor. The gate of the switch MOS transistor is connected to the other ends of the first capacitor and the second capacitor. When the capacitors discharge, the gate voltage of the switch MOS transistor rises to twice the power supply voltage. The substrate of the switch MOS transistor is commonly connected to the drain of the first MOS transistor and the source of the second MOS transistor. The drain of the second MOS transistor is connected to the source of the switch MOS transistor, and its gate is connected to the gate of the switch MOS transistor. The gate voltage bootstrap switch circuit of the present invention prevents the leakage behavior of the switch MOS transistor, reduces the on-resistance of the switch MOS transistor, and accelerates the sampling rate of the SAR ADC.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to a gate voltage bootstrap switching circuit applied to a SAR ADC. Background Technology

[0002] All SAR ADC sampling is divided into upper plate sampling and lower plate sampling. Upper plate sampling can save one clock cycle, but the requirements for the switch are relatively high; lower plate sampling does not require a switch, but it will add one clock cycle. When upper plate sampling is selected, the switch needs to be made into a gate voltage bootstrap switch in order to meet the requirements of high-precision ADC (12 bits and above).

[0003] Traditional gate voltage bootstrap switching circuits used in SAR ADCs, such as Figure 1 As shown, in Figure 1 In the diagram, M21 to M210 are MOSFETs, CS is a capacitor, clks is the sampling clock signal, clkb is the inverted version of the sampling clock signal, Vin is the input signal, Vout is the output signal, and AVD is the power supply voltage. a, b, c, and d are different circuit nodes.

[0004] When clks is low, clkb is high. At this time, MOSFETs M21, M23, M24, M27, and M28 are turned on, while the remaining MOSFETs are turned off. The voltage at node a is ground, and the voltage at node c is the power supply voltage AVD. When clks is high, MOSFETs M22, M25, M26, M29, and M210 are turned on, while the remaining MOSFETs are turned off. Since MOSFET M29 is turned on, the voltage at node a is the input signal voltage Vin. Because the voltage difference across capacitor Cs remains unchanged, the voltage change at node c is AVD + Vin. Furthermore, because MOSFET M25 is turned on, the voltage at node d is equal to the voltage at node c. Therefore, the gate voltage of MOSFET M210 is AVD + Vin. The formula for the on-resistance Ron of each MOSFET is as follows:

[0005]

[0006] In the above formula, u and Cox represent the carrier mobility and gate oxide unit capacitance, respectively; W and L represent the width and length of each MOSFET; and Vgs and Vth represent the gate-source voltage and turn-on voltage of each MOSFET, respectively. Except for the gate-source voltage Vgs, all the above variables are constants. Therefore, ensuring that the gate-source voltage Vgs remains constant guarantees the linearity of the on-resistance Ron. MOSFET M210 is the switching MOSFET in the entire switching circuit. Under any input voltage Vin, the gate-source voltage Vgs of MOSFET M210 is: Vgs = AVD + Vin - Vin = AVD, thus ensuring the linearity of the on-resistance of MOSFET M210.

[0007] However, the traditional gate voltage bootstrap switching circuits used in SAR ADCs still have the following drawbacks:

[0008] Firstly, when the power supply voltage AVD is relatively low (below 1V), the on-resistance of each MOSFET will be relatively high, which will affect the sampling speed of the SAR ADC and cause distortion.

[0009] Secondly, the substrate of the switching MOSFET M210 is connected to its source, which is connected to the input voltage Vin. If the output voltage Vout is lower than the input voltage Vin during the conversion process, leakage will occur.

[0010] Therefore, it is necessary to provide an improved gate voltage bootstrap switching circuit for SAR ADC to overcome the above-mentioned defects. Summary of the Invention

[0011] The purpose of this invention is to provide a gate voltage bootstrap switching circuit for SAR ADC. The gate voltage bootstrap switching circuit of this invention prevents leakage behavior of the switching MOSFET, reduces the on-resistance of the switching MOSFET, and speeds up the sampling rate of SAR ADC.

[0012] To achieve the above objectives, the present invention provides a gate voltage bootstrap switching circuit for a SAR ADC, comprising a voltage control unit and a switching transistor unit. The voltage control unit is connected to a power supply voltage and an external clock. The external clock generates a first clock signal and a second clock signal with opposite phases. The voltage control unit applies the power supply voltage to the switching transistor unit upon receiving different external clock signals to control the voltage of the switching transistor unit. An external signal is input to the switching transistor unit, and when the switching transistor unit is turned on under the voltage control of the voltage control unit, the external signal is output through the switching transistor unit. The voltage control unit includes a first capacitor and a second capacitor connected in parallel. One end of each of the first and second capacitors is connected to an external power supply, and the other end of each is connected to the switching transistor unit. The switching transistor unit includes a switching MOSFET, a first MOSFET, and a second MOSFET. The gate of the switching MOSFET is connected to the other end of a first capacitor and a second capacitor. When the first capacitor and the second capacitor discharge, the gate voltage of the switching MOSFET rises to twice the power supply voltage. An external signal is input to the source of the switching MOSFET, and the drain of the switching MOSFET forms an output terminal to output a signal. The substrate of the switching MOSFET is connected to the drain of the first MOSFET and the source of the second MOSFET. The source of the first MOSFET is grounded, and a first clock signal is input to the gate of the first MOSFET. The drain of the second MOSFET is connected to the source of the switching MOSFET, and its gate is connected to the gate of the switching MOSFET.

[0013] Preferably, the switching transistor unit further includes a third MOS transistor, the source of which is connected to the gate of the switching MOS transistor, and its drain is grounded, and a first clock signal is input to the gate of the third MOS transistor.

[0014] Preferably, the voltage control unit includes a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, and a voltage control switch. An external power supply voltage is input to the sources of the fourth and fifth MOSFETs. The gates of the fourth, fifth, and eighth MOSFETs are connected together and connected to the gate of the switching MOSFET. The drains of the fourth and eighth MOSFETs are connected together with one end of a first capacitor. The other end of the first capacitor is connected to the drain of the sixth MOSFET. The drain of the fifth MOSFET is connected to one end of a second capacitor. The other end of the second capacitor is connected to the source of the eighth MOSFET and the gate of the seventh MOSFET. The drains of the MOSFETs are connected together. A first clock signal is input to the gates of the sixth and seventh MOSFETs respectively. The sources of the sixth and seventh MOSFETs are both grounded. The drain of the ninth MOSFET is connected to the drain of the sixth MOSFET and the input terminal of the voltage control switch. The source of the ninth MOSFET is connected to the source of the switching MOSFET. The gate of the ninth MOSFET is connected to one control terminal of the voltage control switch and the gate of the switching MOSFET. The drain of the tenth MOSFET is connected to the drain of the fifth MOSFET. Its source is connected to the gate of the switching MOSFET. The gate of the tenth MOSFET is connected to the output terminal of the voltage control switch. A second clock signal is input to the other control terminal of the voltage control switch.

[0015] Preferably, the voltage control unit further includes an eleventh MOS transistor, the drain of which is connected to the drain of the fifth MOS transistor, and its source is connected to the gate of the tenth MOS transistor, and a first clock signal is input to the gate of the eleventh MOS transistor.

[0016] Compared with the prior art, the gate voltage bootstrap switching circuit for SAR ADC of the present invention has a first capacitor and a second capacitor connected in parallel in the voltage control unit. The upper plates of the first capacitor and the second capacitor can be charged to the power supply voltage. The first capacitor and the second capacitor are both connected to the gate of the switching MOSFET, which allows the voltage of the gate of the switching MOSFET to be pulled up to twice the power supply voltage, thereby reducing the conduction resistance of the switching MOSFET and increasing the sampling rate of the SAR ADC accordingly. In addition, the substrate of the switching MOSFET is connected to the drain of the first MOSFET. When the first MOSFET is turned off and the second MOSFET is turned on, the substrate voltage of the switching MOSFET is also the voltage of the external input signal and equal to the drain-source voltage of the switching MOSFET, preventing leakage of the switching MOSFET.

[0017] The invention will become clearer from the following description, taken in conjunction with the accompanying drawings, which are used to explain embodiments of the invention. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an existing gate voltage bootstrap switching circuit used in SAR ADCs.

[0019] Figure 2 This is a schematic diagram of the gate voltage bootstrap switching circuit for SAR ADC of the present invention. Detailed Implementation

[0020] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which similar element reference numerals denote similar elements. As described above, the present invention provides a gate voltage bootstrap switching circuit for a SAR ADC. This gate voltage bootstrap switching circuit prevents leakage behavior of the switching MOSFET, reduces the on-resistance of the switching MOSFET, and accelerates the sampling rate of the SAR ADC.

[0021] Please refer to Figure 2 , Figure 2This is a schematic diagram of the gate voltage bootstrap switching circuit for SAR ADC of the present invention. As shown in the figure, the gate voltage bootstrap switching circuit for SAR ADC of the present invention includes a voltage control unit and a switching transistor unit. The voltage control unit is connected to the power supply voltage AVD and an external clock. The external clock generates a first clock signal clkb and a second clock signal clks with opposite phases. That is, the first clock signal clkb and the second clock signal clks have the same frequency and the same amplitude, only with opposite phases. In practical applications, a pair of clock signals with opposite phases can be easily obtained by using an inverter, which will not be described in detail here. The voltage control unit applies the power supply voltage AVD to the switching transistor unit by receiving different external clock signals to control the voltage of the switching transistor unit. The external signal Vin is input to the switching transistor unit. Under the voltage control of the voltage control unit, when the switching transistor unit is turned on, the external signal is output through the switching transistor unit to form an output signal Vout, thereby realizing the switching function.

[0022] The voltage control unit includes a first capacitor C1 and a second capacitor C2 connected in parallel. One end of each capacitor is connected to an external power supply AVD, and the other end is connected to the switching transistor unit. The switching transistor unit includes a switching MOSFET M0, a first MOSFET M1, and a second MOSFET M2. The gate of the switching MOSFET M0 is connected to the other end of the first capacitor C1 and the second capacitor C2. When the first capacitor C1 and the second capacitor C2 discharge, they both apply the power supply voltage AVD to the switching MOSFET M0. The gate voltage of the switching MOSFET M0 is increased to twice the supply voltage, i.e., 2AVD. An external signal Vin is input to the source of the switching MOSFET M0, resulting in a gate voltage Vg of M0 that is: Vg = 2AVD + Vin (where Vin represents the voltage value of the external signal Vin). This means the gate-source voltage Vgs of the switching MOSFET M0 is: Vgs = (2AVD + Vin) - Vin = 2AVD, thereby reducing the on-resistance of the switching MOSFET M0 and correspondingly increasing the SAR. The ADC sampling rate; the drain of the switching MOSFET M0 forms the output terminal to output the signal Vout. The substrate of the switching MOSFET M0 is connected to the drain of the first MOSFET and the source of the second MOSFET M2. The source of the first MOSFET M1 is grounded. The first clock signal clkb is input to the gate of the first MOSFET M1. The drain of the second MOSFET M2 is connected to the source of the switching MOSFET M0, and its gate is connected to the gate of the switching MOSFET M0. When the first clock signal clkb is low, the first MOSFET M1 is turned off, and the second MOSFET M2 is turned on. At this time, the substrate voltage of the switching MOSFET M0 is also the voltage Vin of the external input signal, and is equal to the drain-source voltage of the switching MOSFET M0, thus preventing leakage of the switching MOSFET M0.

[0023] Specifically, the switching transistor unit further includes a third MOS transistor M3. The source of the third MOS transistor M3 is connected to the gate of the switching MOS transistor M0, and its drain is grounded. A first clock signal clkb is input to the gate of the third MOS transistor M3. When the first clock signal clkb is high, the third MOS transistor M3 is turned on to pull the voltage of node e to ground, so as to ensure that when the first capacitor C1 and the second capacitor C2 discharge the switching MOS transistor M0, the voltage of node e is the ground voltage of 0.

[0024] Additionally, the voltage control unit includes a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, and a voltage control switch. An external power supply voltage AVD is input to the sources of the fourth MOSFET M4 and the fifth MOSFET M5. The gates of the fourth MOSFET M4, the fifth MOSFET M5, and the eighth MOSFET M8 are all connected together and connected to the gate of the switching MOSFET M0. The drain of the fourth MOSFET M4 and the drain of the eighth MOSFET M8 are connected to the gate of the switching MOSFET M0. The drain of the first capacitor C1 and one end of the first capacitor C1 are connected together. The other end of the first capacitor C1 is connected to the drain of the sixth MOSFET M6. The drain of the fifth MOSFET M5 is connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the source of the eighth MOSFET M8 and the drain of the seventh MOSFET M7. Thus, the power supply voltage AVD charges the upper plates (one end) of the first capacitor C1 and the second capacitor C2 through the fourth MOSFET M4 and the fifth MOSFET M5 respectively until the voltage of their upper plates is the power supply voltage AVD. The first clock signal clkb is input to the gates of the sixth MOSFET M6 and the seventh MOSFET M7 respectively. The sources of the sixth MOSFET M6 and the seventh MOSFET M7 are both grounded. Thus, when the first clock signal clkb is high, the sixth MOSFET M6 and the seventh MOSFET M7 are turned on, making the lower plates (the other end) of the first capacitor C1 and the second capacitor C2 grounded (0), while also ensuring that the voltage of the upper plates of the first capacitor C1 and the second capacitor C2 is a stable power supply voltage AVD. The drain of the ninth MOSFET M9 is connected to the drain of the sixth MOSFET M6 and the input terminal of the voltage control switch. The source of the ninth MOSFET M9 is connected to the source of the switching MOSFET M0. The gate of the ninth MOSFET M9 is connected to one control terminal of the voltage control switch and the gate of the switching MOSFET M0. The drain of the tenth MOSFET M10 is connected to the drain of the fifth MOSFET M5, and its source is connected to the gate of the switching MOSFET M0. The gate of the tenth MOSFET M10 is connected to the output terminal of the voltage control switch. The second clock signal clks is input to the other control terminal of the voltage control switch. The voltage control switch is composed of two P-type and N-type MOSFETs of the same size connected to each other. When the second clock signal clks is high, the voltage control switch is open, connecting node a and node f. Conversely, when the second clock signal clks is low, the voltage control switch is closed, disconnecting node a from node f, thereby adjusting the voltage of node f.In a preferred embodiment of the present invention, the voltage control unit further includes an eleventh MOS transistor M11. The drain of the eleventh MOS transistor M11 is connected to the drain of the fifth MOS transistor M5, and its source is connected to the gate of the tenth MOS transistor M10. A first clock signal clkb is input to the gate of the eleventh MOS transistor M11. When the first clock signal clkb is high, the eleventh MOS transistor M11 is turned on, thereby applying the voltage of node d to node f, pulling up the gate voltage of the tenth MOS transistor M10, and turning off the tenth MOS transistor M10 to prevent leakage.

[0025] Please refer to the references. Figure 2 The working process and working principle of the gate voltage bootstrap switching circuit for SAR ADC of the present invention are described below:

[0026] When the first clock signal clkb is high and the second clock signal clks is low (where high level is the external power supply voltage AVD and low level is ground voltage 0), the sixth MOSFET M6 and the seventh MOSFET M7 are turned on, and the voltages at nodes a and c are low. Simultaneously, the third MOSFET M3 is turned on, pulling the voltage at node e down to ground, i.e., low. Consequently, the fourth MOSFET M4 and the fifth MOSFET M5 are turned on, and the voltages at nodes b and d are both high. Furthermore, the high level of the first clock signal clkb turns on the first MOSFET M1, pulling the voltage at node g down to ground, i.e., low. This ensures that the substrate of the switching MOSFET M0 is connected to ground during this time period. The substrate voltage is always lower than the output signal voltage Vout, effectively preventing leakage of the switching MOSFET M0. In addition, the first clock signal clkb is high, which turns on the eleventh MOSFET M11, thereby pulling up the gate voltage of the tenth MOSFET M10 and turning it off to prevent leakage. All other MOSFETs are in the off state. At the same time, because the fourth MOSFET M4 and the fifth MOSFET M5 are on, the upper plates of the first capacitor C1 and the second capacitor C2 are charged, and the charging voltage is AVD. Because the sixth MOSFET M6 and the seventh MOSFET M7 are on, the lower plates of the first capacitor C1 and the second capacitor C2 are ground voltage 0, which further ensures that the voltage of their upper plates is the power supply voltage AVD.

[0027] When the first clock signal clkb is low and the second clock signal clks is high, the voltage control switch is turned on. The voltage at node f is equal to the voltage at node a, and is low (the voltage of the lower plate of the first capacitor C1). Therefore, the tenth MOSFET M10 is turned on. At this time, the voltage at node e is pulled high (the upper plate of the second capacitor C2 discharges to node e through the tenth MOSFET M10), causing the eighth MOSFET M8, the ninth MOSFET M9, the second MOSFET M2, and the switching MOSFET M0 to turn on. Because the ninth MOSFET M9 is turned on, the voltage at node a is the external input signal voltage Vin. Furthermore, due to the capacitance characteristics, the voltage at node b... The voltage at node b is AVD + Vin. Since the eighth MOSFET M8 is turned on, the voltage at node b is equal to the voltage at node c. Due to the capacitance characteristics, the voltage at node d is AVD + (AVD + Vin) = 2AVD + Vin. Since the tenth MOSFET M10 is turned on, the voltage at node d is equal to the voltage at node e. Therefore, the gate voltage of the switching MOSFET M0 is 2AVD + Vin, and the gate-source voltage Vgs of the switching MOSFET M0 is 2AVD. At this time, the second MOSFET M2 is turned on, so the substrate voltage of the switching MOSFET M0 is also Vin, which is equal to its drain-source voltage, thus preventing leakage.

[0028] In summary, the gate voltage bootstrap switching circuit for SAR ADC of the present invention, by incorporating a first capacitor and a second capacitor connected in parallel within the voltage control unit, allows the upper plates of both capacitors to be charged to the power supply voltage AVD. Since both capacitors are connected to the gate of the switching MOSFET, the gate voltage of the switching MOSFET can be pulled up to twice the power supply voltage, thereby reducing the conduction resistance of the switching MOSFET M0 and correspondingly increasing the sampling rate of the SAR ADC. Furthermore, the substrate of the switching MOSFET M0 is connected to the drain of the first MOSFET M1. When the first MOSFET M1 is turned off while the second MOSFET M2 is turned on, the substrate voltage of the switching MOSFET M0 is also equal to the external input signal voltage Vin, and equal to the drain-source voltage of the switching MOSFET M0, preventing leakage current in the switching MOSFET M0.

[0029] The present invention has been described above in conjunction with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations made in accordance with the essence of the present invention.

Claims

1. A gate voltage bootstrap switch circuit for a SAR ADC, comprising a voltage control unit and a switch tube unit, the voltage control unit is connected with a power voltage and an external clock respectively, the external clock generates a first clock signal and a second clock signal with opposite phase, the voltage control unit applies the power voltage to the switch tube unit by receiving different external clock signals to control the voltage of the switch tube unit, an external signal is input to the switch tube unit, and the external signal is output through the switch tube unit when the switch tube unit is turned on under the voltage control of the voltage control unit; characterized in that, The voltage control unit includes a first capacitor and a second capacitor connected in parallel. One end of each of the first and second capacitors is connected to an external power supply, and the other end is connected to the switching transistor unit. The switching transistor unit includes a switching MOSFET, a first MOSFET, and a second MOSFET. The gate of the switching MOSFET is connected to the other end of the first and second capacitors. When the first and second capacitors discharge, the gate voltage of the switching MOSFET rises to twice the power supply voltage. An external signal is input to the source of the switching MOSFET, and the drain of the switching MOSFET forms an output terminal to output a signal. The substrate of the switching MOSFET is connected to the drain of the first MOSFET and the source of the second MOSFET. The source of the first MOSFET is grounded, and a first clock signal is input to the gate of the first MOSFET. The drain of the second MOSFET is connected to the source of the switching MOSFET, and its gate is connected to the gate of the switching MOSFET. The voltage control unit includes a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, and a voltage control switch. The external power supply voltage is input to the fourth MOSFET. The source of the fifth MOSFET, the gates of the fourth, fifth, and eighth MOSFETs are connected together and connected to the gate of the switching MOSFET. The drains of the fourth and eighth MOSFETs and one end of the first capacitor are connected together. The other end of the first capacitor is connected to the drain of the sixth MOSFET. The drain of the fifth MOSFET is connected to one end of the second capacitor. The other end of the second capacitor is connected to the source of the eighth MOSFET and the drain of the seventh MOSFET. A first clock signal is input to the gates of the sixth and seventh MOSFETs respectively. The sources of the sixth and seventh MOSFETs are both grounded. The drain of the ninth MOSFET is connected together with the drain of the sixth MOSFET and the input terminal of the voltage control switch. The source of the ninth MOSFET is connected to the source of the switching MOSFET. The gate of the ninth MOSFET is connected together with one control terminal of the voltage control switch and the gate of the switching MOSFET. The drain of the tenth MOSFET is connected to the drain of the fifth MOSFET, and its source is connected to the gate of the switching MOSFET. The gate of the tenth MOSFET is connected to the output terminal of the voltage control switch. A second clock signal is input to the other control terminal of the voltage control switch.

2. The gate voltage bootstrap switching circuit for a SAR ADC of claim 1, wherein, The switching transistor unit also includes a third MOS transistor, the source of which is connected to the gate of the switching MOS transistor, and its drain is grounded. A first clock signal is input to the gate of the third MOS transistor.

3. The gate voltage bootstrap switching circuit for a SAR ADC of claim 2, wherein, The voltage control unit also includes an eleventh MOS transistor, the drain of which is connected to the drain of the fifth MOS transistor, and its source is connected to the gate of the tenth MOS transistor. A first clock signal is input to the gate of the eleventh MOS transistor.

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