An 8-bit ADC circuit with step-by-step multi-bit quantization
By using an 8-bit ADC circuit with step-by-step multi-quantization, the problems of large number of hardware components, high power consumption, limited conversion speed, and insufficient tolerance for comparison errors in the high-speed, low-power design of SAR ADC circuits are solved. This achieves efficient sampling rate and linearity improvement, simplifies clock control, and improves the overall performance of the ADC.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHONGQING UNIV OF POSTS & TELECOMM
- Filing Date
- 2025-01-14
- Publication Date
- 2026-05-26
AI Technical Summary
Existing SAR ADC circuits suffer from problems in high-speed, low-power designs, such as large hardware quantity, high power consumption, large capacitor area, complex asynchronous clock module, limited conversion speed, and insufficient tolerance for comparison errors.
An 8-bit ADC circuit employing step-by-step multi-bit quantization includes a SIG-DAC capacitor array, a REF-DAC capacitor array, a six-input dynamic comparator with offset voltage calibration, an asynchronous clock module, a latch array, and a decoder module. Through the split capacitor array and asynchronous clock control, a 1-2.6-1 bit/cycle quantization mode is achieved, increasing comparator offset voltage calibration and redundant quantization width, and simplifying SAR logic.
It improves sampling rate and linearity, reduces power consumption, simplifies clock control, enhances tolerance to comparison errors, achieves 7.68 effective bits and high signal-to-noise ratio at a 1GHz sampling rate, and improves the overall performance of the ADC.
Smart Images
Figure CN119966413B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to an 8-bit ADC circuit with step-by-step multi-bit quantization. Background Technology
[0002] High-speed, low-power ADCs (analog-to-digital converters) have important applications in modern communications, radar, and the Internet of Things (IoT), especially in situations requiring high signal sampling accuracy and speed. With the rapid development of 5G, millimeter-wave radar, and IoT devices, the requirements for signal acquisition in systems are becoming increasingly stringent. These systems need to be able to process high-frequency, high-bandwidth signals at high speed while operating efficiently within a limited power budget. Commonly used ADCs include... ADC, pipeline ADC, SAR ADC, and various hybrid ADC structures.
[0003] With the continuous development of integrated circuit process technology, nanometer-scale process dimensions have brought great challenges to ADC design. SAR ADCs, with their advantages of lower power consumption and smaller area, offer a better solution to these challenges. They have demonstrated a high degree of compatibility between their structure and advanced processes, particularly in fields such as communications and radar.
[0004] To further improve the sampling rate of SAR ADCs, the quantization process of the ADC can be accelerated. For example... Figure 1 The diagram shows a traditional Multiple-bit / cycle (multiple bits per step) circuit structure, which is actually a hybrid structure of Flash + SAR, capable of quantizing M bits at once in a single conversion cycle. However, this design significantly increases the area and power consumption of the capacitor array, makes the offset mismatch between multiple comparators more pronounced, and complicates the SAR logic and timing between circuits. These factors all affect the overall conversion result of the ADC, becoming bottlenecks to ADC performance. Problems with traditional Multiple-bit / cycle SAR ADCs:
[0005] 1. The entire quantization width of the ADC needs to be... Each threshold voltage is equivalently divided into Each interval needs to be considered in a conversion cycle. The comparators work in parallel to jointly determine whether the input signal falls into a certain interval. This consumes a large number of circuit hardware components and has a high power consumption.
[0006] 2. M capacitor arrays (CDACs) are required. One is used to perform successive approximation of the main signal (SIG-DAC), and M-1 are used to generate the threshold voltage required in each conversion cycle (REF-DAC). The circuit capacitors occupy a large area.
[0007] 3. A capacitor array is needed to control the main signal using the first clock. A second clock is needed to advance the control to the threshold voltage of the first clock to generate the capacitor array. Additionally, a clock is needed to control a comparator to operate in parallel. The asynchronous clock circuit module is complex.
[0008] To improve the sampling accuracy of high-speed SAR ADCs, methods such as... Figure 2 The diagram illustrates a non-binary quantization method using a 4-bit ADC conversion process as an example. Non-binary quantization increases the number of comparisons performed by the ADC to improve its accuracy. This method primarily lengthens the overall quantization width of the ADC or the quantization width within a specific conversion cycle by adding redundancy. Problems exist in this traditional SAR ADC quantization method:
[0009] 1. The working principle of serial quantization greatly limits the conversion speed of ADC.
[0010] 2. A series of non-ideal factors may occur during the conversion process, such as incomplete CDAC settling time and comparator offset voltage error. Traditional quantization methods do not tolerate these comparison errors.
[0011] 3. Binary-controlled capacitor arrays require binary codes to control capacitor switching switches, making SAR logic complex.
[0012] In summary, there is an urgent need for a new SAR ADC circuit to improve the performance of existing SAR ADC circuits. Summary of the Invention
[0013] To address the shortcomings of existing technologies, this invention proposes an 8-bit ADC circuit with step-by-step multi-bit quantization. This circuit includes: one SIG-DAC capacitor array, one REF-DAC capacitor array, five six-input dynamic comparators CMP1~CMP5 with offset voltage calibration, one asynchronous clock module, one latch array, two enable signal modules, and two decoder modules; wherein:
[0014] The SIG-DAC capacitor array receives differential input signals VIP and VIN, connects to the Latch Array enable signal module and 5 comparators, and is used for successive approximation of the main signal;
[0015] The REF-DAC capacitor array receives differential input signals VREFP and VREFN, connects to the REF-DAC switch enable signal module and 5 comparators, and is used to generate threshold voltage.
[0016] The asynchronous clock module connects to the REF-DAC switch enable signal module, latch array, and 5 comparators;
[0017] The latch array consists of 17 latch circuits, and is also connected to a latch array enable signal module, 5 comparators, and 2 decoder modules in series. The first decoder module is used to convert the 17-bit thermometer code into 11-bit non-binary code, and the second decoder module is used to convert the 11-bit non-binary code into 8-bit binary code.
[0018] Preferably, the differential output SIG-VIP of the SIG-DAC capacitor array is connected to one positive input of the five comparators, and the differential output SIG-VIN of the SIG-DAC capacitor array is connected to one negative input of the five comparators.
[0019] Preferably, the REF-DAC capacitor array differential output REF-VIP is connected to a negative input terminal of comparators CMP1 and CMP2 and a positive input terminal of CMP4 and CMP5, and the REF-DAC capacitor array differential output REF-VIN is connected to a positive input terminal of comparators CMP1 and CMP2 and a negative input terminal of CMP4 and CMP5; a positive input terminal of comparator CMP3 is connected to VCM, and a negative input terminal is connected to VCM.
[0020] Preferably, in the asynchronous clock module, the differential output of comparator CMP3 is passed through an OR gate to generate a control signal CONTROL. The control signal CONTROL, the signal Q5 generated by the enable signal module, and the total clock CKS are connected to an NOR gate to generate an asynchronous clock signal CKC1. CKC1 is connected to comparator CMP3.
[0021] The asynchronous clock signal CKC1, the signal Q1 generated by the enable signal module, and the inverted signal Q5N of the signal Q5 generated by the enable signal module are passed through an AND gate to generate the asynchronous clock CKC2; CKC2 is connected to comparators CMP1, CMP2, CMP4 and CMP5.
[0022] Preferably, the REF-DAC capacitor array outputs the comparison threshold voltages required for 1-2.6-1 bit / cycle quantization in three consecutive conversion clocks within the middle of the five conversion clocks, which are: 0V, ± , ± ;0V, ± , ± and 0, ± , ± .
[0023] Preferably, the REF-DAC switch enable signal module generates signals Q2, Q3, and Q5 to control the switch switching of the REF-CDAC; the Latch Array enable signal module generates signals EN1, EN2, EN3, EN4, and EN5 to control the switch switching of the SIG-CDAC.
[0024] Preferably, the SIG-DAC capacitor array adopts a split capacitor array.
[0025] The beneficial effects of this invention are as follows:
[0026] The circuit structure of this invention has less hardware overhead than traditional one-step multi-bit SAR ADCs. The 2.6 bit / cycle achieves a trade-off between power consumption and speed.
[0027] This invention improves the sampling rate of SAR ADC through a step-by-step multi-bit quantization method of 1-2.6-1 bit / cycle, and performs offset voltage alignment of 5 comparators in the last clock cycle, which increases the overall performance of ADC without adding extra clock phase.
[0028] This invention increases the ADC's tolerance to comparison errors by adding a fixed redundancy to the remaining quantization width within a certain conversion clock.
[0029] This invention requires fewer total clocks, has a simpler asynchronous clock module, and more intuitive SAR logic.
[0030] The decoding process of this invention is slightly slower than the conversion process, enabling alternating operation. This prevents them from mutually occupying the 1G sampling rate.
[0031] This invention achieves an effective bit depth of 7.68 bits, an SFDR of 62.61 dB, and an SNDR of 47.99 dB at a sampling rate of 1 GHz and a Nyquist input frequency, with a power supply voltage of 1 V, thus improving the sampling rate and linearity. Attached Figure Description
[0032] Figure 1 This is a circuit structure diagram of a traditional one-step multi-bit SARADC.
[0033] Figure 2 This is a diagram of the non-binary quantization process, using 4-bit conversion as an example.
[0034] Figure 3 This is a schematic diagram of the overall circuit architecture of the SAR ADC in this invention.
[0035] Figure 4 This is an asynchronous timing diagram of the SAR ADC in this invention.
[0036] Figure 5This is a flowchart of the 8-bit quantization process of the present invention.
[0037] Figure 6 This describes the conversion process of the 8-bit SAR ADC in this invention.
[0038] Figure 7 This is a diagram of the latch array architecture in this invention.
[0039] Figure 8 This is a circuit architecture diagram of the first decoder module in this invention.
[0040] Figure 9 This is a graph showing the weight calculation during the decoding process of this invention. Detailed Implementation
[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0042] This invention proposes an 8-bit ADC circuit with step-by-step multi-bit quantization, such as... Figure 3 As shown, the circuit includes: one SIG-DAC capacitor array, one REF-DAC capacitor array, five six-input dynamic comparators CMP1~CMP5 with offset voltage calibration, one asynchronous clock module, one latch array, two enable signal modules, and two decoder modules. Wherein:
[0043] The SIG-DAC capacitor array receives differential input signals VIP and VIN, connects to the Latch Array enable signal module and five comparators, and is used for successive approximation of the main signal. Specifically, the differential output SIG-VIP of the SIG-DAC capacitor array is connected to one positive input terminal of the five comparators, and the differential output SIG-VIN of the SIG-DAC capacitor array is connected to one negative input terminal of the five comparators.
[0044] The REF-DAC capacitor array receives differential input signals VREFP and VREFN, connects to the REF-DAC switch enable signal module and five comparators, and is used to generate a threshold voltage. Specifically:
[0045] The REF-DAC capacitor array differential output REF-VIP is connected to one negative input terminal of comparators CMP1 and CMP2 and one positive input terminal of CMP4 and CMP5. The REF-DAC capacitor array differential output REF-VIN is connected to one positive input terminal of comparators CMP1 and CMP2 and one negative input terminal of CMP4 and CMP5. One positive input terminal of comparator CMP3 is connected to the external common-mode voltage VCM, and one negative input terminal is connected to the external common-mode voltage VCM.
[0046] The REF-DAC switch enable signal module generates signals Q2, Q3, and Q5 to control the switching of the REF-CDAC; the Latch Array enable signal module generates signals EN1, EN2, EN3, EN4, and EN5 to control the switching of the SIG-CDAC.
[0047] The asynchronous clock module connects to the REF-DAC switch enable signal module, latch array, and five comparators. The asynchronous clock module generates signals Q1~Q5, which are then used by the master clock CKS to generate two asynchronous clocks, CKC1 and CKC2. CKC1 primarily controls the intermediate comparator CMP3, while CKC2 primarily controls CMP1, CMP2, CMP4, and CMP5. Within the asynchronous clock module, the differential output of comparator CMP3 is ORed to generate the control signal CONTROL. CONTROL, along with signal Q5 generated by the enable signal module and the master clock CKS, is connected to a NOR gate to generate the asynchronous clock signal CKC1. The asynchronous clock signal CKC1, the signal Q1 generated by the enable signal module, and the inverted signal Q5N of signal Q5 generated by the enable signal module are ANDed to generate the asynchronous clock CKC2.
[0048] The latch array consists of 17 latch circuits, connected to a latch array enable signal module, 5 comparators, and 2 decoder modules in series. The first decoder module converts the 17-bit thermometer code into 11-bit non-binary code, and the second decoder module converts the 11-bit non-binary code into 8-bit binary code. The asynchronous timing of the entire SAR ADC is as follows: Figure 4 As shown.
[0049] The SIG-CDAC uses a split capacitor array, which reduces power consumption by half compared to a traditional binary capacitor array, and uses upper plate sampling.
[0050] The high-speed, low-power SAR ADC designed in this invention uses a quantization method of 1-2.6-1 bit / cycle. For an 8-bit quantization width, five clock cycles are used for conversion: the first clock cycle completes a 1-bit conversion, the next three clock cycles each complete a 2.6-bit conversion, and the last clock cycle completes a 1-bit conversion. The entire ADC sampling clock is 1 ns. The REF-DAC capacitor array outputs the comparison threshold voltages required for the 1-2.6-1 bit / cycle quantization method sequentially within the three consecutive conversion clock cycles in the middle of the five conversion clock cycles, which are: 0V, ±... , ± ;0V, ± , ± and 0, ± , ± The threshold voltage for the other two clock cycles is 0V.
[0051] This invention adds a fixed amount of redundancy to the remaining quantization width within a certain conversion clock cycle: ±2 LSB redundancy is added to the remaining quantization width in the first conversion clock cycle, ±1 LSB redundancy is added to the remaining quantization width in the second conversion clock cycle, ±4 LSB redundancy is added to the remaining quantization width in the third conversion clock cycle, and no redundancy is added to the remaining quantization width in the fourth conversion clock cycle. The 8-bit quantization flowchart after adding ±7 LSB redundancy is shown below. Figure 5 As shown.
[0052] The 8-bit SAR ADC conversion process designed in this invention is as follows: Figure 6 As shown. The output difference of the REF-CDAC is the threshold voltage value required by the comparator. In the asynchronous clock module, when CKC1 is high, comparator CMP3 starts comparing; when CKC1 is low, comparator CMP3 stops comparing. CKC1, Q1, and Q5N are ANDed by an AND gate to generate asynchronous clock CKC2. When CKC2 is high, comparators CMP1, CMP2, CMP4, and CMP5 start comparing; when CKC2 is low, these four comparators stop comparing. The five comparators determine the sum of the magnitudes of the input signals and output a 17-bit thermometer code (0 or 1) sequentially. When the output of a comparator is 1, it indicates that the signal is above the threshold voltage; when the output of a comparator is 0, it indicates that the signal is below the threshold voltage. EN1, EN2, EN3, EN4, and EN5 control the 17 thermometer codes T1~T17 (T1N~T17N are opposite signals) to be stored sequentially as shown. Figure 7 The latch array shown is now complete. This completes the entire ADC conversion stage: converting the differential analog signal into a 17-bit thermometer code and storing it in the latch array.
[0053] Next comes the decoding stage. A delay is added to the clock CKS during the conversion stage to generate the decoding stage timing sequence READ. The first step of the decoding circuit is as follows: Figure 8 As shown: the decoding circuits for converting T1 to B1 and T17 to B11 are the same. READ is connected to the clock terminal of a D flip-flop, T1 and T17 are connected to the enable terminal, the power supply signal AVDD is connected to the reset terminal, and the ground signal is connected to the set terminal. The conversion of T2, T3, T4, T5, and T6 to B2, B3, and B4 uses three comparators. READ is connected to the clock input of the three D flip-flops, the power supply signal is connected to the reset input, and the ground signal is connected to the set input. The output signal of T4 and the power supply signal through an AND gate is connected to the enable input of the first D flip-flop, outputting B2. The signals output from T2 to T6 through the AND gate are connected to the input of an OR gate. The other input of this OR gate is the signal output from T2N, T3N, T4N, T5, and T6 through the AND gate. The output of this OR gate is connected to the enable input of the second D flip-flop, outputting B3. The signals output from T2N, T3 to T6 through the AND gate are connected to the input of an OR gate. The other input of this OR gate is the signal output from T2N, T3N, T4N, T5N, and T6 through the AND gate. The output of this OR gate is connected to the enable input of the second D flip-flop, outputting B4. Repeating the above operations, T7~T11 will generate B5, B6, and B7, and T12~T16 will generate B8, B9, and B10. B1~B11 (B1N~B11N are the opposite signals) are 11-bit non-binary codes. The second decoding step involves a weighted operation using a full adder, while simultaneously subtracting 7 LSBs of redundant binary code, finally outputting an 8-bit binary code. The weight calculation during the decoding process is as follows... Figure 9 As shown.
[0054] This invention uses a single master clock for the entire circuit, while an asynchronous clock circuit generates two different asynchronous clocks, enabling the dynamic comparator to operate in a quantized manner. The thermometer code directly controls the successive approximation of the capacitor array output signal. The decoding process of this invention is slightly slower than the conversion process, achieving alternating operation. This prevents them from mutually occupying the 1GHz sampling rate. Redundant codes are subtracted during the second decoding. At a sampling rate of 1GHz and a Nyquist input frequency, this invention achieves an effective bit depth of 7.68 bits, an SFDR of 62.61dB, and an SNDR of 47.99dB at a 1V power supply voltage.
[0055] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. An 8-bit ADC circuit with step-by-step multi-bit quantization, characterized in that, include: One SIG-DAC capacitor array, one REF-DAC capacitor array, five six-input dynamic comparators CMP1~CMP5 with offset voltage calibration, one asynchronous clock module, one latch array, two enable signal modules, and two decoder modules; wherein: the two enable signal modules are a latch array enable signal module and a REF-DAC switch switching enable signal module; The SIG-DAC capacitor array receives differential input signals VIP and VIN, connects to the Latch Array enable signal module and 5 comparators, and is used for successive approximation of the main signal; The REF-DAC capacitor array receives differential input signals VREFP and VREFN, connects to the REF-DAC switch enable signal module and 5 comparators, and is used to generate threshold voltage. The asynchronous clock module is connected to the REF-DAC switch enable signal module, latch array, and 5 comparators. In the asynchronous clock module, the differential output of comparator CMP3 is ORed to generate the control signal CONTROL. The control signal CONTROL, the signal generated by the latch array enable signal module, and the total clock are connected to an NOR gate to generate the asynchronous clock signal CKC1. The asynchronous clock signal CKC1 is connected to comparator CMP3. The asynchronous clock module generates two different asynchronous clock signals CKC1 and CKC2; the asynchronous clock signal CKC2 is connected to comparators CMP1, CMP2, CMP4 and CMP5; The REF-DAC switch enable signal module generates signals Q2, Q3, and Q5 to control the switching of the REF-DAC capacitor array; the Latch Array enable signal module generates signals EN1, EN2, EN3, EN4, and EN5 to control the switching of the SIG-DAC capacitor array. The latch array consists of 17 latch circuits, and is also connected to a latch array enable signal module, 5 comparators, and 2 decoder modules in series. The first decoder module is used to convert the 17-bit thermometer code into 11-bit non-binary code, and the second decoder module is used to convert the 11-bit non-binary code into 8-bit binary code.
2. The 8-bit ADC circuit with step-by-step multi-bit quantization according to claim 1, characterized in that, The differential output SIG-VIP of the SIG-DAC capacitor array is connected to one positive input of the five comparators, and the differential output SIG-VIN of the SIG-DAC capacitor array is connected to one negative input of the five comparators.
3. The 8-bit ADC circuit with step-by-step multi-bit quantization according to claim 1, characterized in that, The REF-DAC capacitor array differential output REF-VIP is connected to one negative input terminal of comparators CMP1 and CMP2 and one positive input terminal of CMP4 and CMP5. The REF-DAC capacitor array differential output REF-VIN is connected to one positive input terminal of comparators CMP1 and CMP2 and one negative input terminal of CMP4 and CMP5. One positive input terminal of comparator CMP3 is connected to VCM, and one negative input terminal is connected to VCM.
4. The 8-bit ADC circuit with step-by-step multi-bit quantization according to claim 1, characterized in that, The REF-DAC capacitor array sequentially outputs the comparison threshold voltages required for 1-2.6-1 bit / cycle quantization within the middle three consecutive conversion clocks of the five conversion clocks. These voltages are: 0V, ± , ± ;0V, ± , ± and 0, ± , ± .
5. The 8-bit ADC circuit with step-by-step multi-bit quantization according to claim 1, characterized in that, The SIG-DAC capacitor array uses a split capacitor array.