A kind of special chip ADC circuit and chip of retinal prosthesis

Abstract

The application relates to the technical field of chip circuits, in particular to a special chip ADC circuit for a retinal prosthesis, which comprises a sampling switch module, a capacitor array module, a dynamic comparator, a digital control logic module and a digital correction module; the capacitor array module comprises a P-end capacitor array and an N-end capacitor array, the P-end capacitor array comprises a plurality of first capacitors connected in parallel, and each first capacitor is connected with a first control switch; the N-end capacitor array comprises a plurality of second capacitors connected in parallel, and each second capacitor is connected with a second control switch; the same direction end of the dynamic comparator is connected with the end capacitor of the P-end capacitor array, and the reverse end of the dynamic comparator is connected with the end capacitor of the N-end capacitor array; the digital control logic module is connected with the output end of the dynamic comparator; and the digital correction module is connected with the output end of the digital control logic module. The ADC circuit provided by the application is used for converting a sensor analog signal into a digital signal and realizes low power consumption and high resolution.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to the technical field of chip circuit, in particular to a retina prosthesis special chip ADC circuit and chip. BACKGROUND

[0002] At present, the retina diseases AMD (age-related macular degeneration) and RP (retinitis pigmentosa) cannot be completely cured by drugs, and need to be cured by retina prosthesis implantation technology, bypassing the damaged photoreceptors and directly connecting with the remaining retinal neurons, helping the retina damaged patients to restore vision. The retina prosthesis chip, as an implantable integrated circuit chip, needs to meet several key functions: low power consumption, small size, no risk to patient's tissue, long service life, good reliability, high integration. In the implementation function, it is needed to receive external data and energy and control to generate constant stimulation current. Compared with other implantable chips, the retina prosthesis needs to meet more stringent requirements: 1. The trade-off between the increase of the number of electrodes and the area of the chip, and the increase of the number of electrodes brings difficulty to the simultaneity of each signal; 2. Due to the small size of the physical electrode and the large impedance, a higher output voltage is needed to obtain a suitable output current; 3. For the retina implant chip, the reliability and safety need to be considered.

[0003] In order to meet the functional requirements of the retina prosthesis chip, the retina prosthesis special chip must contain the modules of radio frequency module, digital control module, electric stimulation module and sensor module. The radio frequency module is mainly used for receiving the digital information collected from the outside, and at the same time receiving external energy, and the energy is maintained through the power management module to make the chip modules work normally; the digital control module decodes the received image information and controls the stimulation module to output the corresponding current waveform; the electric stimulation module converts the digital information into analog information through DAC to generate constant current stimulation and send it to the external electrode of the chip; the sensor module detects whether the environment (temperature) around the implant is in the normal working range, and the system forms a closed loop feedback structure to ensure the normal and stable work of the chip.

[0004] However, in the existing retina prosthesis chip, most of them do not have sensor and ADC (analog-to-digital conversion) modules. The sensor module detects the environment (temperature) around the implant, and the ADC module converts the analog signal into digital signal and returns it to the control module for feedback control of the chip to ensure that the chip works stably in the normal environment. Therefore, in the chip containing the analog-to-digital conversion circuit, the circuit module also has defects, high power consumption, low sampling rate and slow data transmission. Low data rate will greatly affect the channel number of the retina prosthesis chip, and then affect the imaging effect. SUMMARY

[0005] The embodiment of the present application provides a retina prosthesis special chip ADC circuit and a chip, which are used for converting sensor analog signals into digital signals, so that low power consumption and high resolution are realized.

[0006] To solve the above technical problems, in a first aspect, the embodiment of the present application provides a retina prosthesis special chip ADC circuit, which comprises a sampling switch module, a capacitor array module, a dynamic comparator, a digital control logic module and a digital correction module; the sampling switch module comprises a first sampling switch and a second sampling switch, the first sampling switch inputs a P-end sampling analog signal, and the second sampling switch inputs an N-end sampling analog signal; the capacitor array module comprises a P-end capacitor array and an N-end capacitor array which are symmetrically distributed, the P-end capacitor array comprises a plurality of first capacitors connected in parallel, one end of each first capacitor is connected with a first control switch, and the other end is connected with the P-end sampling analog signal; the N-end capacitor array comprises a plurality of second capacitors connected in parallel, one end of each second capacitor is connected with a second control switch, and the other end is connected with the N-end sampling analog signal; a same direction end of the dynamic comparator is connected with a terminal capacitor of the P-end capacitor array, and an opposite direction end of the dynamic comparator is connected with a terminal capacitor of the N-end capacitor array; an input end of the digital control logic module is connected with an output end of the dynamic comparator; and an input end of the digital correction module is connected with an output end of the digital control logic module.

[0007] In some example embodiments, the retina prosthesis special chip ADC circuit further comprises a mismatch correction module, which is arranged between the capacitor array module and the dynamic comparator; an input end of the mismatch correction module is connected with an output end of the capacitor array module, and an output end of the mismatch correction module is connected with an input end of the dynamic comparator.

[0008] In some example embodiments, the retina prosthesis special chip ADC circuit further comprises a delay module, which is arranged between the dynamic comparator and the digital control logic module; an input end of the delay module is connected with an output end of the dynamic comparator, and an output end of the delay module is connected with an input end of the digital control logic module.

[0009] In some example embodiments, the digital control logic module comprises a successive approximation logic calculation unit; and the digital control logic module is used for inverting a lower plate level of the capacitor array module according to output data of the dynamic comparator.

[0010] In some example embodiments, the capacitor array module comprises a monolithic capacitor array structure; and the number of the first capacitors is equal to the number of the second capacitors.

[0011] In some example embodiments, the first sampling switch is a bootstrap sampling switch, and / or the second sampling switch is a bootstrap sampling switch.

[0012] In some example embodiments, the digital correction module adopts an offline fixed compensation method for digital linear compensation.

[0013] In some example embodiments, the digital correction module first adopts input and output point data for fitting, and then adopts segmented compensation.

[0014] In some example embodiments, the formula of the segmented compensation is as follows:

[0015] f 理想 =g 补偿 *f 实际 (1)

[0016] wherein g 补偿 is a function of the digital correction module, f 理想 is a function of an ideal curve, and f 实际 is a function of an actual output result.

[0017] In a second aspect, the embodiments of the present application further provide a retinal prosthesis special chip, which comprises the retinal prosthesis special chip ADC circuit according to any one of the above embodiments.

[0018] The technical scheme provided by the embodiments of the present application has at least the following advantages:

[0019] The embodiments of the present application provide a retinal prosthesis special chip ADC circuit and chip. The circuit comprises a sampling switch module, a capacitor array module, a dynamic comparator, a digital control logic module, and a digital correction module. The circuit can be integrated into a retinal prosthesis chip, converts a sensor analog signal into a digital signal, and performs feedback control to achieve low power consumption and high resolution. The circuit structure is an improved low-power SAR ADC structure. The sampling rate of the sampling switch is 1Msps, which improves the sampling rate. The capacitor array module can adopt a monolithic capacitor array structure, which saves 80% of the dynamic power consumption compared with a traditional capacitor array. The dynamic comparator can omit a pre-amplification stage, which can save static power consumption. In three aspects, power consumption is saved, which can greatly reduce the power consumption of the ADC and facilitate the integration of the implanted retinal chip. Meanwhile, a digital calibration structure is added. The linear compensation of the digital is used to compensate for the errors in the circuit conversion to meet the high-precision requirement. Based on the traditional analog-to-digital conversion circuit, the embodiments of the present application optimize the switch capacitor timing scheme, control the power consumption of the comparator, and realize the circuit design of low power consumption and high resolution. BRIEF DESCRIPTION OF DRAWINGS

[0020] One or more embodiments are illustrated by way of example in the drawings and are described herein in connection with the embodiments described. These embodiments are not intended to limit the scope of the embodiments to the embodiments described, but rather, serve as illustrations from which one skilled in the art can derive the general nature of embodiments. The drawings are not to scale and are intended for use only in conjunction with the description herein and generally indicate the features of the embodiments. Throughout the drawings, like reference numerals are used to designate like elements.

[0021] Figure 1 A structure schematic diagram of an ADC circuit special for a retinal prosthesis chip is provided for an embodiment of the present application;

[0022] Figure 2 An overall timing circuit diagram of an ADC is provided for an embodiment of the present application;

[0023] Figure 3 A digital linear compensation circuit schematic diagram is provided for an embodiment of the present application;

[0024] Figure 4 A simulation test schematic diagram is provided for an embodiment of the present application;

[0025] Figure 5 A simulation test result diagram is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0026] As can be known from the background, in the existing retinal prosthesis chip containing an analog-to-digital conversion circuit, the ADC (analog-to-digital conversion) circuit has problems of large power consumption, low sampling rate, and slow data transmission, which further affects the channel number of the retinal prosthesis chip and affects the imaging effect.

[0027] To solve the above technical problems, an ADC circuit special for a retinal prosthesis chip is provided by an embodiment of the present application, which comprises a sampling switch module, a capacitor array module 1, a dynamic comparator 2, a digital control logic module 3, and a digital correction module 4. The sampling switch module comprises a first sampling switch 101 and a second sampling switch 102. The first sampling switch 101 inputs a P-end sampling analog signal, and the second sampling switch 102 inputs an N-end sampling analog signal. The capacitor array module 1 comprises a P-end capacitor array 11 and an N-end capacitor array 12 which are symmetrically distributed. The P-end capacitor array 11 comprises a plurality of first capacitors 111 connected in parallel. One end of each first capacitor 111 is connected with a first control switch 103, and the other end is connected with the P-end sampling analog signal. The N-end capacitor array 12 comprises a plurality of second capacitors 112 connected in parallel. One end of each second capacitor 112 is connected with a second control switch 104, and the other end is connected with the N-end sampling analog signal. The same direction end of the dynamic comparator 2 is connected with the terminal capacitor of the P-end capacitor array 11, and the reverse end of the dynamic comparator 2 is connected with the terminal capacitor of the N-end capacitor array 12. The input end of the digital control logic module 3 is connected with the output end of the dynamic comparator 2. The input end of the digital correction module 4 is connected with the output end of the digital control logic module 3.

[0028] In the application, based on the low power consumption requirement of the implanted chip, the ADC circuit adopts a successive approximation register (SAR) ADC circuit structure, that is, the ADC circuit adopts a low power consumption structure, and the accuracy is improved, and the ADC circuit structure provided by the application is as shown in Figure 1 The circuit structure includes a sampling switch module, a capacitor array module 1, a dynamic comparator 2, a digital control logic module 3, and a digital correction module 4. The sampling switch module includes a first sampling switch 101 and a second sampling switch 102. The input end of the first sampling switch 101 inputs a P-end sampling analog signal VIP, which can be a DACP signal. The output end of the first sampling switch 101 is connected with the input end of a P-end capacitor array 11. The input end of the second sampling switch 102 inputs an N-end sampling analog signal VIN, and the output end of the second sampling switch 102 is connected with the input end of an N-end capacitor array 12. The capacitor array module 1 includes a symmetrically distributed P-end capacitor array 11 and an N-end capacitor array 12. The P-end capacitor array 11 includes a plurality of first capacitors 111 connected in parallel. One end of each first capacitor 111 is connected with a first control switch 103, and the other end is connected with the P-end sampling analog signal. The N-end capacitor array 12 includes a plurality of second capacitors 112 connected in parallel. One end of each second capacitor 112 is connected with a second control switch 104, and the other end is connected with the N-end sampling analog signal.

[0029] The P-end sampling analog signal VIP can be a DACP signal, and the N-end sampling analog signal VIN can be a DACN signal. The first sampling switch 101 and the second sampling switch 102 can be gate voltage bootstrap switches, and the first sampling switch 101 and the second sampling switch 102 can be two gate voltage bootstrap switches with the same structure.

[0030] The capacitor array module 1 is used for charge holding and redistribution, and mainly includes 256Cu total capacitors (wherein Cu represents a unit capacitor). The first capacitors 111 are located in the P-end capacitor array 11, and the second capacitors 112 are located in the N-end capacitor array 12. The P-end capacitor array 11 and the N-end capacitor array 12 are symmetrically distributed. The number of the first capacitors 111 is equal to the number of the second capacitors 112, and the first capacitors 111 and the second capacitors 112 are symmetrically distributed.

[0031] The plurality of first control switches 103 arranged side by side form a first switch module 13, and the plurality of second control switches 104 arranged side by side form a second switch module 14. The first switch module 13 and the second switch module 14 are symmetrically distributed. The number of the first control switches 103 is equal to the number of the first capacitors 111, and the number of the second control switches 104 is equal to the number of the second capacitors 112.

[0032] It should be noted that the first control switch 103 and the second control switch 104, the P-end capacitor array 11 and the N-end capacitor array 12 can all adopt a CDAC capacitor array. The capacitor array module 1 and the sampling switch module satisfy monolithic switch capacitor timing, and the dynamic comparator 2 can adopt a strong arm latch dynamic comparator.

[0033] Compared with the existing ADC circuit, the application greatly saves power consumption, ensures ADC precision, optimizes the capacitor area to a certain extent, and can be directly integrated into a retinal prosthesis circuit to serve as a digital-analog conversion module.

[0034] Compared with the traditional ADC capacitor structure, the application adopts a monolithic switch capacitor structure, which is half the number of the traditional capacitor structure. Taking 10 bits as an example, the traditional structure needs 2^9 maximum capacitors, and the monolithic structure has 2^8 maximum capacitors, so the chip layout area is reduced by half, and the power consumption is reduced by 20% compared with the traditional structure. Reducing the capacitor area and power consumption will bring new problems. Due to the monolithic switch control logic, it cannot guarantee that each data has the same common mode level value, which will cause the comparator to generate an offset voltage, which will sacrifice the overall precision of the ADC. Therefore, the application adopts a pure dynamic comparator, and due to the rapid transformation of the clock, part of the charge will pass through, so a digital correction module 4 is added after the SARADC to compensate for part of the error.

[0035] In some embodiments, the retinal prosthesis special chip ADC circuit described above further comprises an offset correction module 5, which is arranged between the capacitor array module 1 and the dynamic comparator 2; the input end of the offset correction module 5 is connected with the output end of the capacitor array module 1, and the output end of the offset correction module 5 is connected with the input end of the dynamic comparator 2. In order to reduce the power consumption of the digital correction module 4 as much as possible, the front circuit needs to be carefully designed, and each step error needs to be as small as possible, so the offset correction module 5 and the sampling switch module are added.

[0036] In some example embodiments, the retinal prosthesis special chip ADC circuit described above further comprises a delay module 6, which is arranged between the dynamic comparator 2 and the digital control logic module 3; the input end of the delay module 6 is connected with the output end of the dynamic comparator 2, and the output end of the delay module 6 is connected with the input end of the digital control logic module 3. The number of delay modules 6 can be set to two, as shown in Figure 1 The output end of the dynamic comparator 2 is connected with the input end of the two parallelly arranged delay modules 6.

[0037] The speed index sample 1M is divided by 13.56M clock, and the circuit timing is as followsFigure 2 The circuit uses D flip-flop to form a shift register, to generate sampling clock, comparator clock and logic control clock.

[0038] Due to the influence of comparator kickback noise and latch accumulated misadjustment, the comparator will generate a large misadjustment voltage, which will affect the voltage of sample and hold. The isolation structure is added in front of the comparator, which uses buffer and ground capacitor to connect the comparator misadjustment voltage to ground and isolate it from the sample and hold potential, so as to minimize the influence of comparator misadjustment.

[0039] In some embodiments, the digital control logic module 3 comprises successive approximation logic calculation unit (SAR-logic); the digital control logic module 3 is used to flip the lower plate level of the capacitor array module 1 according to the output data of the dynamic comparator 2. The number of successive approximation logic calculation unit can be set to two, as shown in the figure. Figure 1 Two SAR-logic are arranged in parallel, and the input ends of the two SAR-logic are connected with the output ends of the corresponding delay module 6 respectively.

[0040] In some embodiments, the capacitor array module 1 comprises monolithic capacitor array structure; the number of the first capacitor 111 is equal to the number of the second capacitor 112. As shown in the figure, the number of the first capacitor 111 is 10, and the second capacitor 112 and the first capacitor 111 are symmetrically distributed, and the number of the second capacitor 112 is also 10. Figure 1

[0041] In some embodiments, the first sampling switch 101 is a bootstrap sampling switch, and / or the second sampling switch 102 is a bootstrap sampling switch. The first sampling switch 101 and the second sampling switch 102 of the present application both use bootstrap sampling switch, so as to minimize the power consumption of the digital correction module 4 and make the error as small as possible.

[0042] In some embodiments, the digital correction module 4 uses offline fixed compensation method for digital linear compensation.

[0043] In some embodiments, the digital correction module 4 first samples the input and output point data for fitting, and then performs segmented compensation.

[0044] In some embodiments, the formula of segmented compensation is:

[0045] f 理想 = g 补偿 *f 实际 (1)

[0046] Wherein, g 补偿 is the function of the digital correction module 4, f​理想 f is a function of ideal curve 实际 f is a function of actual output result.

[0047] In order to compensate for the low-power structure error, the digital correction module 4 adopts the idea of first sampling the input and output point data for fitting, and then adopting the segmented compensation mode, as shown in formula (1), the correction module is g function. Figure 3 The principle diagram of the digital linear compensation circuit is shown. As an example, taking 8 bits as an example, when the actual output digital value is 01111111, the ideal result is 10000000, the compensation digital circuit needs to generate 00000001, and add it to the actual value to obtain the ideal result. A large number of simulation curves can be fitted to obtain an actual output curve, and the compensation curve is inversely solved, so that a digital output result with good linearity can be obtained. In order to reduce the power consumption of this part, segmented compensation is needed, so that the digital circuit can use as few gate circuits as possible. Through the digital linear compensation mode, the linearity of the ADC is improved, so as to meet the accuracy requirements of the retinal chip ADC circuit.

[0048] The application has been verified by simulation, and the simulation circuit is as shown in Figure 4 The simulation input data is a sine wave with a common mode level of 0.9V, an amplitude of 0.5, and a frequency of 100k; the clock is 13.56M, and about 1M sampling clock is generated internally, and the output result is parallel. Since the application scene is generally at a fixed frequency, only INL (integral nonlinearity) and DNL (differential nonlinearity) need to be simulated and calculated, and the simulation result is as shown in Figure 5

[0049] The ADC circuit provided by the application adopts a low-power structure as a whole, and compared with the power consumption 2.205uW@50Hz of the existing circuit structure, the power consumption of the ADC circuit of the application is about 20uW@1MHz. When converted to the same sampling frequency, the power consumption is greatly reduced. In addition, the ADC circuit of the application is provided with a digital correction module 4, and the digital compensation circuit of this part is an offline fixed compensation curve, which saves a lot of power consumption compared with real-time correction. Adding this part of the digital compensation circuit can save a lot of power consumption in the analog part, and greatly guarantee the resolution requirements of the ADC.

[0050] In the second aspect, the embodiment of the application also provides a retinal prosthesis special chip, which comprises the retinal prosthesis special chip ADC circuit described in any of the above embodiments.

[0051] ​According to the technical scheme, the embodiment of the present application provides an ADC circuit and a chip special for a retinal prosthesis, which comprises a sampling switch module, a capacitor array module 1, a dynamic comparator 2, a digital control logic module 3 and a digital correction module 4. The circuit can be integrated into a retinal prosthesis chip, converts a sensor analog signal into a digital signal, and performs feedback control to realize low power consumption and high resolution. The circuit structure is an improved low-power SAR ADC structure, the sampling rate of the sampling switch is 1Msps, and the sampling rate is improved; the capacitor array module 1 can adopt a monolithic capacitor array structure, and 80% of dynamic power consumption is saved compared with a traditional capacitor array; the dynamic comparator 2 can omit a pre-amplification stage, and static power consumption can be saved. In three aspects, power consumption is saved at the same time, the ADC power consumption can be greatly reduced, and the integration of the implanted retinal chip is facilitated. Meanwhile, a digital calibration structure is added, errors occurring in the circuit conversion are compensated by using digital linear compensation, and high precision requirements are achieved. On the basis of a traditional analog-digital conversion circuit, the embodiment of the present application optimizes a switch capacitor timing scheme, controls comparator power consumption, and realizes a low-power high-resolution circuit design.

[0052] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A retinal prosthesis dedicated chip ADC circuit, characterized by, Comprising: a sampling switch module; the sampling switch module comprises a first sampling switch and a second sampling switch, the first sampling switch inputs a P-end sampling analog signal, and the second sampling switch inputs an N-end sampling analog signal; a capacitor array module; the capacitor array module comprises a P-end capacitor array and an N-end capacitor array which are symmetrically distributed, the P-end capacitor array comprises a plurality of first capacitors connected in parallel, one end of each of the first capacitors is connected with a first control switch, and the other end is connected with the P-end sampling analog signal; the N-end capacitor array comprises a plurality of second capacitors connected in parallel, one end of each of the second capacitors is connected with a second control switch, and the other end is connected with the N-end sampling analog signal; the capacitor array module comprises a monolithic capacitor array structure; the number of the first capacitors is equal to the number of the second capacitors; a dynamic comparator; the same direction end of the dynamic comparator is connected with an end capacitor of the P-end capacitor array, and the reverse end of the dynamic comparator is connected with an end capacitor of the N-end capacitor array; a digital control logic module; the input end of the digital control logic module is connected with the output end of the dynamic comparator; a digital correction module; the input end of the digital correction module is connected with the output end of the digital control logic module; the digital correction module is used for compensating errors occurring in circuit conversion by using digital linear compensation, so as to meet high precision requirements; the digital correction module adopts an offline fixed compensation mode for digital linear compensation; the digital correction module first samples input and output point data for fitting, and then performs segmented compensation.

2. The retinal prosthesis dedicated chip ADC circuit of claim 1, wherein, Further comprising a mismatch correction module, which is arranged between the capacitor array module and the dynamic comparator; the input end of the mismatch correction module is connected with the output end of the capacitor array module, and the output end of the mismatch correction module is connected with the input end of the dynamic comparator.

3. The retinal prosthesis dedicated chip ADC circuit of claim 1, wherein, Further comprising a delay module, which is arranged between the dynamic comparator and the digital control logic module; the input end of the delay module is connected with the output end of the dynamic comparator, and the output end of the delay module is connected with the input end of the digital control logic module.

4. The retinal prosthesis dedicated chip ADC circuit of claim 1, wherein, The digital control logic module comprises a successive approximation logic calculation unit; the digital control logic module is used for flipping the lower plate level of the capacitor array module according to the output data of the dynamic comparator.

5. The retinal prosthesis dedicated chip ADC circuit of claim 1, wherein, The first sampling switch is a bootstrap sampling switch, and / or the second sampling switch is a bootstrap sampling switch.

6. A chip dedicated for a retinal prosthesis, characterized by The retinal prosthesis special chip ADC circuit comprises the chip ADC circuit according to any one of claims 1 to 5.

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