Bidirectional transceiver circuit with automatic direction and edge acceleration

Abstract

The invention discloses a bidirectional transceiver circuit with automatic direction and edge acceleration, which comprises a first transceiver and a second transceiver, and the two transceivers have the same structure and are in a symmetrical structure after being connected. The transmission direction of the bidirectional transceiver can be automatically identified and configured, a direction control signal is not needed, the bidirectional transceiver internally generates a pulse signal at the moment that an input signal changes to open strong driving output, the change of the output signal is accelerated, and the output driving capability and the transmission rate are improved; and meanwhile, an internal enable signal is generated to close strong driving output of an input side, so that input signals are prevented from being influenced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a bidirectional transceiver circuit with automatic direction and edge acceleration. Background Art

[0002] The integrated circuit industry uses transmitters to send data to one or more targets, and receivers to receive the data sent by the transmitter. Bidirectional transceivers can send and receive data at the same time, and generally require additional direction signals to control the transmission direction, and the circuit structure is complex.

[0003] As systems become more complex, transceivers are connected to more and more hosts and peripherals, and the demand for improving data transmission rates and signal integrity is also increasing. When transmitting data in both directions, in order to be driven by external input devices, bidirectional transceivers generally have weak output drive capabilities. Weak drive greatly affects the integrity of the signal at higher transmission rates. Summary of the invention

[0004] Purpose of the invention: In order to solve the problems existing in the above-mentioned prior art, the present invention provides a bidirectional transceiver circuit with automatic direction and edge acceleration.

[0005] Technical solution: The present invention discloses a bidirectional transceiver circuit with automatic direction and edge acceleration, comprising a first transceiver and a second transceiver, the two transceivers having the same structure and forming a symmetrical structure after being connected.

[0006] Further, the transceiver includes an output end, an input end, an enable output end, an enable input end, a feedback module, a driving module and an enable module; the output end of the first transceiver is connected to the input end of the second transceiver, and the output end of the second transceiver is connected to the input end of the first transceiver; the enable output end of the first transceiver is connected to the enable input end of the second transceiver, and the enable output end of the second transceiver is connected to the enable input end of the first transceiver;

[0007] The signal input end of the driving module is the input end of the transceiver, the driving signal output end of the driving module is used as the output end of the transceiver and is connected to the input end of the feedback module, the first output end of the feedback module is connected to the first feedback signal input end of the driving module, the second output end of the feedback module is connected to the second feedback signal input end of the driving module, the first pulse signal output end of the driving module is connected to the first input end of the enabling module, and the second pulse signal output end of the driving module is connected to the second input end of the enabling module;

[0008] When the input signal of a certain transceiver changes, the driving module generates a driving signal and a pulse signal according to the input signal of the transceiver, and outputs the driving signal to the output end and the feedback module, and inputs the pulse signal to the enabling module; the feedback module feeds back the feedback signal generated by the output signal change to the driving module, so that the driving module outputs stably; the enabling module generates an enabling signal to the enabling input end of another transceiver, thereby shutting down the output of the driving module of the other transceiver when the input signal changes;

[0009] When the input signal of a certain transceiver is static, the driving module generates a driving signal according to the input signal of the transceiver, and the driving signal is in phase with the input signal.

[0010] Furthermore, the driving module includes first and second inverters, first and second NAND gates, first and second NOR gates, first and second resistors; first to ten MOS tubes;

[0011] The input end of the first inverter serves as the input end of the entire transceiver, and the output end is connected to the gates of the third to sixth MOS tubes, the first input end of the second NAND gate and the second input end of the first NOR gate; the drain of the third MOS tube is connected to one end of the first resistor and the source of the seventh MOS tube, the gate of the seventh MOS tube serves as the first feedback signal input end, the drain of the seventh MOS tube is connected to the other end of the first resistor, the first input end of the first NOR gate and the drain of the fourth MOS tube; the source of the fourth MOS tube is grounded; the drain of the fifth MOS tube is connected to the drain of the eighth MOS tube, one end of the second resistor and the second input end of the second NAND gate, the gate of the eighth MOS tube serves as the second feedback signal input end, the source of the eighth MOS tube is connected to the other end of the second resistor and the drain of the sixth MOS tube, and the source of the sixth MOS tube is grounded; the output end of the first NOR gate is connected to the second input end of the first NAND gate , the first input end of the first NAND gate is used as the enable input end of the entire transceiver and is connected to the input end of the second inverter; the output end of the second NAND gate is connected to the first input end of the second NOR gate, and the second input end of the second NOR gate is connected to the output end of the second inverter; the output end of the first NAND gate is connected to the gate of the first MOS tube as the first pulse signal output end, and the output end of the second NOR gate is connected to the gate of the second MOS tube as the second pulse signal output end, the drain of the first MOS tube and the drain of the second MOS tube are connected as the output end of the transceiver and connected to the input end of the feedback module, the source of the first MOS tube is connected to the power supply, and the source of the second MOS tube is grounded; the gates of the ninth and tenth MOS tubes are both connected to the output end of the first inverter, the drains of the ninth and tenth MOS tubes are connected to each other and connected to the output end of the transceiver, the source of the ninth MOS tube is connected to the power supply, and the source of the tenth MOS is grounded.

[0012] Furthermore, among the first to tenth MOS tubes, the first, third, fifth, seventh and ninth MOS tubes are PMOS tubes, and the remaining MOS tubes are NMOS tubes.

[0013] Further, the feedback module includes a third NAND gate, a third NOR gate, third to fifth inverters, eleventh to fourteenth MOS tubes and third and fourth resistors;

[0014] The input end of the third inverter serves as the input end of the feedback module, and the output end is connected to the gates of the eleventh to fourteenth MOS tubes, the second input end of the third NOR gate and the first input end of the third NAND gate; the source of the eleventh MOS tube is connected to the power supply voltage, the drain is connected to one end of the third resistor, the other end of the third resistor is connected to the first input end of the third NOR gate and the drain of the twelfth MOS tube, and the source of the twelfth MOS tube is grounded; the source of the thirteenth MOS tube is connected to the power supply voltage, the drain is connected to the second input end of the third NAND gate and one end of the fourth resistor, the other end of the fourth resistor is connected to the drain of the fourteenth MOS tube, and the source of the fourteenth MOS tube is grounded; the output of the third NOR gate is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the driving module as the first output end of the feedback module; the output end of the third NAND gate is connected to the input end of the fifth inverter, and the output end of the fifth inverter is connected to the driving module as the second output end of the feedback module.

[0015] Furthermore, among the eleventh to fourteenth MOS tubes, the eleventh and thirteenth MOS tubes are PMOS tubes, and the remaining MOS tubes are NMOS tubes.

[0016] Further, the enabling module includes fifteenth and sixteenth MOS tubes, a sixth inverter, fourth and fifth NAND gates and a fifth resistor;

[0017] The input end of the sixth inverter serves as the second input end of the enabling module, and the output end is connected to the second input end of the fourth NAND gate. The first input end of the fourth NAND gate serves as the first input end of the enabling module, and the output end of the fourth NAND gate is connected to the gates of the fifteenth and sixteenth MOS tubes and the first input end of the fifth NAND gate; the source of the fifteenth MOS tube is connected to the power supply voltage, the drain is connected to one end of the fifth resistor and the second input end of the fifth NAND gate, the other end of the fifth resistor is connected to the drain of the sixteenth MOS tube, the source of the sixteenth MOS tube is grounded, and the output end of the fifth NAND gate serves as the enabling output end of the transceiver.

[0018] Furthermore, the fifteenth MOS tube is a PMOS tube, and the sixteenth MOS tube is an NMOS tube.

[0019] Beneficial effects: The bidirectional transceiver circuit has two transceiver circuits, the two circuits are identical and have a symmetrical structure. The present invention can automatically identify and configure the transmission direction of the bidirectional transceiver without a direction control signal. The bidirectional transceiver of the present invention generates a pulse signal internally at the moment the input signal changes to turn on the strong drive output, accelerate the output signal change, improve the output drive capability, and have a high transmission rate; at the same time, it generates an internal enable signal to turn off the strong drive output on the input side to avoid affecting the input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a circuit structure diagram of a bidirectional transceiver of the present invention;

[0021] Figure 2 is a circuit diagram of a transceiver of the present invention;

[0022] Figure 3 It is a timing waveform diagram of the bidirectional transceiver of the present invention. DETAILED DESCRIPTION

[0023] The accompanying drawings, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0024] The structure of the bidirectional transceiver of the present invention is as follows Figure 1 As shown, the circuit has two transceiver circuits, which are symmetrical and have the same circuits. A and B are the bidirectional input and output ports of the transceiver; A is used as the input IN to control the output OUT of B, and at the same time, the output enable signal EN_OUT of the B side is input to the transceiver circuit EN_IN of the A side, turning off the strong drive output of A to prevent the output change of B from affecting the input of A; Figure 1 IN is the input of the transceiver, OUT is the output of the transceiver, EN_IN is the internal enable input of the transceiver, and EN_OUT is the internal enable output of the transceiver.

[0025] The circuit diagram of a single transceiver is as follows Figure 2As shown, the input signal IN is driven to output through INV1, and the output has strong drive and weak drive. There are two states of strong drive: when the input signal rises from low level to high level, the input at one end of NOR1 drops rapidly from high level to low level. Due to the delay caused by the large resistor R1, the input at the other end of NOR1 slowly rises from low level to high level, so that the output of NOR1 generates a pulse signal, which is inverted by NAND1 to generate pulse signal D1. During the time when the pulse signal D1 is at a low level, the strong drive output tube PM1 is turned on, and the transceiver output is quickly pulled up to a high level. When the output is stable at a high level, the output signal is fed back through the INV3, NOR3, and INV4 paths to generate a pulse signal C1. During the time when the pulse signal C1 is at a low level, the PM5 tube is turned on, the resistor R1 is shorted, and D1 changes to a high level to ensure the normal function of the circuit. Similarly, when the input signal drops from high level to low level, due to the delay caused by the large resistor R2, the NAND2 output generates a pulse, which is inverted by NOR2 to generate a pulse signal D2. During the time when the pulse signal D2 is high level, the strong drive output tube NM1 is turned on, and the transceiver output is quickly pulled down to a low level. When the output is stable at a low level, the output is fed back through the INV3, NAND3, and INV5 paths to generate a pulse signal C2, turn on the NM5 tube, short-circuit the resistor R2, and change D2 to a low level. The pulse signals D1 and D2 generate a pulse enable signal EN_OUT through the INV6, NAND4, and NAND5 paths and output to the other side, so that the NAND1 output on the other side remains at a high level, the NOR2 output remains at a low level, and the strong drive output on the other side is turned off to prevent the output signal change from affecting the input signal; the weak drive PM2 and NM2 are directly driven by INV1. In static state, the weak drive output signal is in phase with the input signal to maintain the output state of the transceiver.

[0026] Ports A and B are both input and output, so signals can be transmitted bidirectionally; the static output is a weak output (i.e., the output stage composed of PM2 and NM2), and the weak output can be driven by an external input. Assuming that the signal is input to port A, the weak output on the A side is driven by the input, and the signal at port A is almost equal to the input signal, then A can be considered as the input port and B outputs the signal of A. Conversely, B is driven by the input and A is the output. Therefore, the present invention can automatically identify the transmission direction of the signal.

[0027] Figure 3The internal timing waveform of the transceiver is shown. Taking A input and B output as an example, at the rising edge of the input signal A, the circuit generates a pulse signal D1. When D1 is at a low level, a strong drive is turned on to quickly pull the output up to a high level. After the output is stabilized at a high level, the output feedback generates a pulse signal C1, making D1 a high level; at the falling edge of the input signal A, the circuit generates a pulse signal D2. When D2 is at a high level, a strong drive is turned on to quickly pull the output down to a low level. After the output is stabilized at a low level, a pulse signal C2 is generated through output feedback, making D2 a low level; while generating pulse signals D1 and D2, the circuit generates a pulse enable signal EN_OUT to turn off the strong drive output on the other side; the final output signal B is consistent with the input signal A.

[0028] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

Claims

1. A bidirectional transceiver circuit with automatic direction and edge acceleration, characterized in that, It comprises a first transceiver and a second transceiver, the two transceivers have the same structure and are symmetrical after being connected.

2. A bidirectional transceiver circuit with automatic direction and edge acceleration according to claim 1, characterized in that: The transceiver includes an output terminal, an input terminal, an enable output terminal, an enable input terminal, a feedback module, a driving module and an enable module; the output terminal of the first transceiver is connected to the input terminal of the second transceiver, and the output terminal of the second transceiver is connected to the input terminal of the first transceiver; the enable output terminal of the first transceiver is connected to the enable input terminal of the second transceiver, and the enable output terminal of the second transceiver is connected to the enable input terminal of the first transceiver; The signal input end of the driving module is the input end of the transceiver, the driving signal output end of the driving module is used as the output end of the transceiver and is connected to the input end of the feedback module, the first output end of the feedback module is connected to the first feedback signal input end of the driving module, the second output end of the feedback module is connected to the second feedback signal input end of the driving module, the first pulse signal output end of the driving module is connected to the first input end of the enabling module, and the second pulse signal output end of the driving module is connected to the second input end of the enabling module; When the input signal of a transceiver changes, the driving module generates a driving signal and a pulse signal according to the input signal of the transceiver, outputs the driving signal to the output end and the feedback module, and inputs the pulse signal to the enabling module; The feedback module feeds back the feedback signal generated by the output signal change to the driving module, so that the driving module can output stably; the enable module generates an enable signal to the enable input terminal of another transceiver, thereby turning off the output of the driving module of another transceiver when the input signal changes; When the input signal of a certain transceiver is static, the driving module generates a driving signal according to the input signal of the transceiver, and the driving signal is in phase with the input signal.

3. A bidirectional transceiver circuit with automatic direction and edge acceleration according to claim 2, characterized in that: The driving module includes first and second inverters, first and second NAND gates, first and second NOR gates, first and second resistors; and first to ten MOS tubes; The input end of the first inverter serves as the input end of the entire transceiver, and the output end is connected to the gates of the third to sixth MOS tubes, the first input end of the second NAND gate and the second input end of the first NOR gate; the drain of the third MOS tube is connected to one end of the first resistor and the source of the seventh MOS tube, the gate of the seventh MOS tube serves as the first feedback signal input end, the drain of the seventh MOS tube is connected to the other end of the first resistor, the first input end of the first NOR gate and the drain of the fourth MOS tube; the source of the fourth MOS tube is grounded; the drain of the fifth MOS tube is connected to the drain of the eighth MOS tube, one end of the second resistor and the second input end of the second NAND gate, the gate of the eighth MOS tube serves as the second feedback signal input end, the source of the eighth MOS tube is connected to the other end of the second resistor and the drain of the sixth MOS tube, and the source of the sixth MOS tube is grounded; the output end of the first NOR gate is connected to the second input end of the first NAND gate , the first input end of the first NAND gate is used as the enable input end of the entire transceiver and is connected to the input end of the second inverter; the output end of the second NAND gate is connected to the first input end of the second NOR gate, and the second input end of the second NOR gate is connected to the output end of the second inverter; the output end of the first NAND gate is connected to the gate of the first MOS tube as the first pulse signal output end, and the output end of the second NOR gate is connected to the gate of the second MOS tube as the second pulse signal output end, the drain of the first MOS tube and the drain of the second MOS tube are connected as the output end of the transceiver and connected to the input end of the feedback module, the source of the first MOS tube is connected to the power supply, and the source of the second MOS tube is grounded; the gates of the ninth and tenth MOS tubes are both connected to the output end of the first inverter, the drains of the ninth and tenth MOS tubes are connected to each other and connected to the output end of the transceiver, the source of the ninth MOS tube is connected to the power supply, and the source of the tenth MOS is grounded.

4. A bidirectional transceiver circuit with automatic direction and edge acceleration according to claim 3, characterized in that: Among the first to tenth MOS tubes, the first, third, fifth, seventh and ninth MOS tubes are PMOS tubes, and the remaining MOS tubes are NMOS tubes.

5. A bidirectional transceiver circuit with automatic direction and edge acceleration according to claim 2, characterized in that: The feedback module includes a third NAND gate, a third NOR gate, third to fifth inverters, MOS, eleventh to fourteenth MOS tubes, and third and fourth resistors; The input end of the third inverter serves as the input end of the feedback module, and the output end is connected to the gates of the eleventh to fourteenth MOS tubes, the second input end of the third NOR gate and the first input end of the third NAND gate; the source of the eleventh MOS tube is connected to the power supply voltage, the drain is connected to one end of the third resistor, the other end of the third resistor is connected to the first input end of the third NOR gate and the drain of the twelfth MOS tube, and the source of the twelfth MOS tube is grounded; the source of the thirteenth MOS tube is connected to the power supply voltage, the drain is connected to the second input end of the third NAND gate and one end of the fourth resistor, the other end of the fourth resistor is connected to the drain of the fourteenth MOS tube, and the source of the fourteenth MOS tube is grounded; the output of the third NOR gate is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the driving module as the first output end of the feedback module; The output end of the third NAND gate is connected to the input end of the fifth inverter, and the output end of the fifth inverter is connected to the driving module as the second output end of the feedback module.

6. A bidirectional transceiver circuit with automatic direction and edge acceleration according to claim 5, characterized in that: Among the eleventh to fourteenth MOS tubes, the eleventh and thirteenth MOS tubes are PMOS tubes, and the remaining MOS tubes are NMOS tubes.

7. A bidirectional transceiver circuit with automatic direction and edge acceleration according to claim 2, characterized in that: The enabling module includes a fifteenth and a sixteenth MOS tube, a sixth inverter, a fourth and a fifth NAND gate and a fifth resistor; The input end of the sixth inverter serves as the second input end of the enable module, and the output end is connected to the second input end of the fourth NAND gate. The first input end of the fourth NAND gate serves as the first input end of the enable module, and the output end of the fourth NAND gate is connected to the gates of the fifteenth and sixteenth MOS tubes and the first input end of the fifth NAND gate; the source of the fifteenth MOS tube is connected to the power supply voltage, the drain is connected to one end of the fifth resistor and the second input end of the fifth NAND gate, the other end of the fifth resistor is connected to the drain of the sixteenth MOS tube, the source of the sixteenth MOS tube is grounded, and the output end of the fifth NAND gate serves as the enable output end of the transceiver.

8. A bidirectional transceiver circuit with automatic direction and edge acceleration according to claim 7, characterized in that: The fifteenth MOS tube is a PMOS tube, and the sixteenth MOS tube is an NMOS tube.

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