Clock synchronization method and device

Abstract

The invention provides a clock synchronization method and device, and particularly relates to the technical field of vehicle-mounted audio, the method is applied to a target audio node, and the method comprises the following steps: receiving a synchronization signal, the synchronization signal having a plurality of synchronization periods; calculating a phase error of a locally generated clock signal relative to the synchronization signal in one or more synchronization periods; and adjusting the frequency of the locally generated clock signal based on the phase error, so that the locally generated clock signal is synchronized with the synchronization signal. According to the invention, the clock synchronization problem of the asynchronous audio chip in the audio system can be solved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of vehicle audio, and in particular to a clock synchronization method and device. Background Art

[0002] Current car audio chips are usually synchronous types, that is, all chips in the audio system work in the same clock domain, and the entire system only needs one reference clock BCLK.

[0003] In a system composed of synchronous car audio chips, the master node sends the audio sampling signal SYNC to each audio slave node through the serdes interface, and each slave node decodes the audio sampling synchronization signal SYNC from the data stream of the serdes interface. Subsequently, the PLL in the slave node uses the decoded SYNC signal as the input reference clock to recover the BCLK clock.

[0004] For asynchronous audio chips that do not have such dedicated PLL, the above synchronization scheme is not applicable. Summary of the invention

[0005] The purpose of the present disclosure is to provide a clock synchronization method and device for solving the technical problem that the related art cannot support clock synchronization of different asynchronous audio chips in a vehicle audio system.

[0006] In a first aspect, an embodiment of the present disclosure provides a clock synchronization method, which is applied to a target audio node. The method includes:

[0007] receiving a synchronization signal, wherein the synchronization signal has a plurality of synchronization periods;

[0008] calculating a phase error of a locally generated clock signal relative to the synchronization signal within one or more synchronization periods;

[0009] The frequency of the locally generated clock signal is adjusted based on the phase error so that the locally generated clock signal is synchronized with the synchronization signal.

[0010] In a second aspect, an embodiment of the present disclosure provides a clock synchronization device, which is applied to a target audio node, and the device includes:

[0011] An interface module, configured to receive a synchronization signal, wherein the synchronization signal has a plurality of synchronization cycles;

[0012] a phase detector module, configured to calculate a phase error of a locally generated clock signal relative to the synchronization signal within one or more synchronization periods;

[0013] A clock synchronization module is used to adjust the frequency of the locally generated clock signal based on the phase error so that the locally generated clock signal is synchronized with the synchronization signal.

[0014] In a third aspect, the present disclosure provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the method described in the first aspect.

[0015] In a fourth aspect, the present disclosure provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0016] In the present disclosure, the phase error of the locally generated clock signal of the audio node relative to the synchronization signal within one or more synchronization periods is calculated, and the frequency of the locally generated clock signal of the audio node is adjusted accordingly, so that the locally generated clock signal of the audio node and the synchronization signal are synchronized. By distributing the same synchronization signal to multiple audio nodes in the vehicle audio system, the locally generated clock signal of each audio node in the vehicle audio system is synchronized with the synchronization signal, thereby achieving clock synchronization of different asynchronous audio chips in the vehicle audio system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flowchart of a clock synchronization method provided by an embodiment of the present disclosure;

[0018] Figure 2 is a structural schematic diagram of a phase detector provided by an embodiment of the present disclosure;

[0019] Figure 3 is a structural schematic diagram of a PID module provided by an embodiment of the present disclosure;

[0020] Figure 4 is a structural diagram of a DDS module provided by an embodiment of the present disclosure;

[0021] Figure 5 is a structural schematic diagram of a vehicle audio system provided by an embodiment of the present disclosure;

[0022] Figure 6 is a schematic diagram of a simulation result of a vehicle audio system provided by an embodiment of the present disclosure;

[0023] Figure 7 is a structural diagram of a clock synchronization device provided by an embodiment of the present disclosure;

[0024] Figure 8 It is a schematic diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0026] The present disclosure provides a clock synchronization method, which is applied to a target audio node, such as Figure 1 As shown, the method includes:

[0027] Step 101: Receive a synchronization signal.

[0028] The synchronization signal has multiple synchronization periods.

[0029] Exemplarily, the target audio node may be any one of a plurality of audio nodes constituting a car audio system, each of the audio nodes corresponds to a car audio chip, and among the plurality of audio nodes, there are at least two asynchronous audio nodes, and the clock domains of at least two car audio chips corresponding to the at least two asynchronous audio nodes are independent of each other.

[0030] The synchronization signal may be a signal generated by an audio host (such as an on-board MCU) for clock synchronization of multiple locally generated clock signals of the multiple audio nodes, for example: an audio sampling synchronization signal generated by frequency division of a bit clock (BCLK) of the audio host.

[0031] Step 102: Calculate a phase error of a locally generated clock signal relative to the synchronization signal within one or more synchronization periods.

[0032] Step 103: Adjust the frequency of the locally generated clock signal based on the phase error so that the locally generated clock signal is synchronized with the synchronization signal.

[0033] The synchronization signal is used to reflect the phase of the clock signal output by the bit clock (BCLK) of the audio host. When the locally generated clock signal is synchronized with the synchronization signal, the BCLK of the audio host maintains clock synchronization with the locally generated clock signal of the target audio node.

[0034] The synchronization of the locally generated clock signal with the synchronization signal should be understood as that the rate of change (absolute value) of the phase difference between the phase of the locally generated clock signal and the phase of the synchronization signal is less than or equal to a preset error threshold.

[0035] In the present disclosure, the phase error of the locally generated clock signal of the audio node relative to the synchronization signal within one or more synchronization periods is calculated, and the frequency of the locally generated clock signal of the audio node is adjusted accordingly, so that the locally generated clock signal of the audio node and the synchronization signal are synchronized. By distributing the same synchronization signal to multiple audio nodes in the vehicle audio system, the locally generated clock signal of each audio node in the vehicle audio system is synchronized with the synchronization signal, thereby achieving clock synchronization of different asynchronous audio chips in the vehicle audio system.

[0036] In some embodiments, audio transmission control and audio processing corresponding to the target audio node can be performed based on the adjusted locally generated clock signal of the target audio node, rather than based on the synchronization signal. This ensures that the audio playback of multiple audio nodes in the vehicle audio system remains synchronized while avoiding the output frequency limitation of the clock signal caused by large periodic jitter of the synchronization signal, thereby improving the audio data transmission bandwidth that can be supported by the vehicle audio system.

[0037] In an application, to support the implementation of the above solution, an APHY-SNK interface for receiving the synchronization signal and an APHY-SRC interface for distributing the synchronization signal to other audio nodes may be provided in the target audio node.

[0038] In one embodiment, calculating the phase error of the locally generated clock signal relative to the synchronization signal within one or more synchronization periods includes:

[0039] Counting the locally generated clock signal from an initial value to obtain a count value, and resetting to the initial value and continuing to count when the count value reaches a predetermined upper limit value, wherein the predetermined upper limit value is determined based on a reference ratio value, and the reference ratio value is a ratio of a duration of one or more synchronization cycles spaced apart to an ideal frequency of the locally generated clock signal;

[0040] The count value is sampled every one or more synchronization periods, and the phase error is determined based on a difference between count values ​​obtained by two adjacent samplings.

[0041] Specifically, the greater the difference between the count values ​​obtained by two adjacent samplings, the greater the determined phase error.

[0042] Based on the above settings, the process of determining the phase error is simplified, and the resource overhead of the target audio node in clock synchronization is reduced.

[0043] Exemplarily, a free-running counter may be generated based on the local generated clock of the target audio node, and the counter may be used to count from an initial value to obtain a count value until the count value reaches a predetermined upper limit value and then reset to the initial value and continues counting.

[0044] In the process of multiple sampling of the count value, the relative operation time of any two different sampling operations in the corresponding synchronization cycle is the same, wherein the relative operation time of the sampling operation in the corresponding synchronization cycle can be understood as: the difference between the corresponding operation time of the sampling operation in the corresponding synchronization cycle and the cycle start point / cycle end point of the corresponding synchronization cycle.

[0045] Exemplarily, the process of obtaining the difference of the count value based on two adjacent samplings is:

[0046] The initial value is set to 0, and the predetermined upper limit value is 63; during the first time the counter counts from 0 to 63, the count value obtained by sampling a synchronous cycle is 12; during the second time the counter counts from 0 to 63, the count value obtained by sampling the next synchronous cycle of the synchronous cycle is 14, then the difference between the count values ​​obtained by two adjacent samplings is 2.

[0047] In one embodiment, when the sampled count value enters the locking range, a locking signal is output;

[0048] Sampling the count value every one or more synchronization periods includes:

[0049] When a rising edge or a falling edge of the synchronization signal is detected every one or more synchronization periods, the count value is sampled.

[0050] Based on the above settings, every one or more synchronization cycles, when the rising edge or falling edge of the synchronization signal is detected, the sampling operation of the count value is triggered, which can reduce the sampling deviation caused by noise and improve the reliability of the sampled count value.

[0051] Specifically, after the locally generated clock signal is synchronized with the synchronization signal, the sampled count value may enter a locking range.

[0052] For example, Figure 2 As shown, the phase detector module can be used to execute the above process to output a phase error (ERROR) and a lock signal (LOCK). Specifically:

[0053] The phase detector module includes a SYNC signal edge detector, a counter, a phase detector and a phase comparator, wherein the counter is generated by a locally generated clock (BCLK) and can run freely, that is, the counter counts the period of the locally generated clock signal from an initial value; when the SYNC signal edge detector detects a rising edge or a falling edge of the synchronization signal (SYNC) every one or more synchronization periods, the phase detector is triggered to sample a current count value from the counter, and the phase detector determines the phase error (ERROR) based on the difference in count values ​​obtained by two adjacent samplings;

[0054] In addition, the phase detector can also forward the current count value sampled from the counter to the phase comparator, so that the phase comparator can determine whether the current count value sampled this time enters the locking range. If so, a locking signal (LOCK) is output.

[0055] In one example, the locking range is determined based on a preset phase locking position P and a phase locking range W. In this example, the locking range is (PW, P+W).

[0056] When the sampled count value is set to enter the locking range, a locking signal is output to provide feedback to the component that relies on the locally generated clock signal of the target audio node through the locking signal - the frequencies of the locally generated clock signal of the target audio node and the synchronization signal tend to be consistent, thereby indicating that the component that relies on the locally generated clock signal of the target audio node can start to perform corresponding audio control based on the locally generated clock signal.

[0057] In some embodiments, after the target audio node is powered on and the locking signal is not output, a predetermined upper limit value can be determined based on the ratio of the duration of one synchronization cycle to the ideal frequency of the locally generated clock signal. At this time, the predetermined upper limit value is a first value. Periodic counting and sampling are performed based on the first value until the locking signal is output. Then, a new predetermined upper limit value is determined based on the ratio of the duration of multiple synchronization cycles to the ideal frequency of the locally generated clock signal. At this time, the predetermined upper limit value is a second value (the second value is greater than the first value). Then, periodic counting and sampling are performed based on the second value to reduce the sampling frequency after the local generated clock signal and the synchronization signal of the target audio node are synchronized, thereby reducing the energy consumption of the target audio node due to the sampling count value.

[0058] In one embodiment, adjusting the frequency of the locally generated clock signal based on the phase error includes:

[0059] Calculating an adjusted frequency control word according to the phase error;

[0060] A frequency-adjusted locally generated clock signal is obtained according to the adjusted frequency control word to reduce the phase error, thereby synchronizing the locally generated clock signal with the synchronization signal.

[0061] It should be noted that after the target audio node is powered on for the first time, the locally generated clock signal of the target audio node is obtained based on a preset default frequency control word.

[0062] Generally speaking, the phase difference between the local generated clock signal before frequency adjustment (obtained based on the default frequency control word) and the synchronization signal is greater than the phase difference between the local generated clock signal after frequency adjustment (obtained based on the adjusted frequency control word) and the synchronization signal.

[0063] Further, the calculating the adjusted frequency control word according to the phase error includes:

[0064] A PID operation is performed on the default frequency control word based on the phase error to obtain the adjusted frequency control word.

[0065] For example, Figure 3 As shown, the PID module can be applied to execute the above process to output the adjusted frequency control word. Specifically, the formula of PID operation is expressed as follows:

[0066] K(t)=K default +K p e(t)+K i e(t)+K d e(t);

[0067] The meanings of the parameters in the above formula are as follows:

[0068] K(t) is the frequency control word after adjustment, K default is the default frequency control word, and the phase error (Error) is converted by PID to form K, which refers to the proportional error. p e(t), K, which refers to the integral error I e(t) and refers to the differential error K d e(t),K p , K I t and K d They are proportional coefficient, integral coefficient and differential coefficient respectively (the specific values ​​of the three need to be determined through debugging in the application), and t can be understood as time or the number of times the frequency control word is adjusted.

[0069] In one embodiment, obtaining the frequency-adjusted locally generated clock signal according to the adjusted frequency control word includes:

[0070] A frequency-adjusted locally generated clock signal is obtained based on the phase control word, the reference clock and the adjusted frequency control word.

[0071] The above-mentioned clock signal generation action is performed by an improved direct digital synthesizer (DDS) DDS module, wherein the square wave signal has the advantages of phase continuity, stable output frequency, high resolution and fast conversion speed, which matches the clock signal output requirements. Therefore, the square wave signal can be selected as the clock signal output. Under the premise of ensuring the reliability of the locally generated clock of the target audio node, the setting of DAC (digital-to-analog converter) and LPF (low-pass filter) is omitted to save costs, and only a two-bit square wave lookup table needs to be set to use a two-bit register to store a 0 and a 1 to reduce the bit occupancy of the waveform lookup table.

[0072] For example, the improved DDS module is as follows Figure 4 As shown, the phase control word and the adjusted frequency control word are used to control the phase and frequency of the output waveform respectively. The phase accumulator is composed of an accumulator and a phase register. Each time the clock pulse of the reference clock is triggered, the accumulator adds the frequency control word and the accumulated phase data output by the phase register, and then sends the added result to the data input end of the phase register. The phase register feeds back the new phase data generated by the accumulator after the last reference clock to the input end of the accumulator, so that the accumulator continues to add the frequency control word under the action of the next reference clock. In this way, the phase accumulator linearly accumulates the phase data under the action of the reference clock. When the phase accumulator is fully accumulated, an overflow is generated. The overflow frequency is the signal frequency of the output clock signal. The output of the phase register is added to the phase control word, and the result is used as the address of the two-bit square wave lookup table, and finally a square wave signal is generated as the clock signal.

[0073] DDS output frequency formula:

[0074]

[0075] Among them, f c is the frequency of the reference clock, K is the adjusted frequency control word, N is the length of the accumulator, f bclk The frequency of the clock signal output by the DDS module.

[0076] DDS output resolution formula:

[0077]

[0078] In one example, the clock synchronization scheme described above can be applied in a car audio system composed of asynchronous chips, such as Figure 5As shown, the audio host sends a synchronization signal (SYNC) to the master node and the slave node. The phase difference between the phase of the synchronization signal (SYNC) and the phase of the bit clock signal of the audio host remains constant. The master node or the slave node performs phase error detection and frequency adjustment on the locally generated clock signal of the node through the phase detector, PID module and DDS module sequentially arranged inside it, so as to achieve synchronization with the synchronization signal of the audio host, and then achieve clock synchronization with the bit clock of the audio host, so as to finally maintain a stable clock synchronization relationship between the master node and multiple slave nodes of the vehicle audio system.

[0079] Based on this, the simulation experiment was carried out and the simulation results were obtained as follows Figure 6 As shown, after several SYNC (ws_i) signal cycles, the accumulated phase error (error) gradually decreases until the phase is locked (ws_lock=1). At this point, the synchronization of the synchronization signal and the locally generated clock signal output by the DDS module is achieved.

[0080] In general, the above clock synchronization solution can solve the clock synchronization problem of asynchronous audio chips in the audio system, and only digital circuits are needed to independently complete the design of the clock synchronization circuit, which simplifies the circuit structure. At the same time, since this solution does not require an analog PLL to generate the audio system synchronization clock BCLK, it can also reduce the production cost of the chip.

[0081] See also Figure 7 , Figure 7 A clock synchronization device is provided in an embodiment of the present disclosure, such as Figure 7 As shown, the clock synchronization device 700 includes:

[0082] The interface module 701 is used to receive a synchronization signal, wherein the synchronization signal has a plurality of synchronization cycles;

[0083] A phase detector module 702, configured to calculate a phase error of a locally generated clock signal relative to the synchronization signal within one or more synchronization periods;

[0084] The clock synchronization module 703 is used to adjust the frequency of the locally generated clock signal based on the phase error so that the locally generated clock signal is synchronized with the synchronization signal.

[0085] In one embodiment, the clock synchronization module 703 includes:

[0086] A PID algorithm module, used for calculating an adjusted frequency control word according to the phase error;

[0087] The DDS module is used to obtain a frequency-adjusted locally generated clock signal according to the adjusted frequency control word to reduce the phase error, thereby synchronizing the locally generated clock signal with the synchronization signal.

[0088] In one embodiment, the phase detector module 702 includes a counter and a phase detector:

[0089] The counter starts counting the locally generated clock signal from an initial value to obtain a count value, and when the count value reaches a predetermined upper limit value, the counter is reset to the initial value and then continues counting, wherein the predetermined upper limit value is determined based on a reference ratio value, and the reference ratio value is a ratio of a duration of one or more synchronization cycles spaced apart to an ideal frequency of the locally generated clock signal;

[0090] The phase detector samples the count value of the counter every one or more synchronization periods, and determines the phase error based on a difference between count values ​​obtained by two adjacent samplings.

[0091] In one embodiment, the phase detector module 702 further includes a phase comparator;

[0092] The phase comparator outputs a locking signal when the count value sampled by the phase detector enters a locking range;

[0093] The phase detector samples the count value of the counter when detecting a rising edge or a falling edge of the synchronization signal every one or more synchronization periods.

[0094] Specifically, the detection of the rising edge or falling edge of the synchronization signal can be completed based on the SYNC signal edge detector included in the phase detector module 702. When the SYNC signal edge detector detects the rising edge or falling edge of the synchronization signal every one or more synchronization periods, it triggers the phase detector to sample the count value of the counter.

[0095] In one embodiment, the PID algorithm module is specifically used to:

[0096] A PID operation is performed on the default frequency control word based on the phase error to obtain the adjusted frequency control word.

[0097] In one embodiment, the DDS module is specifically used for:

[0098] A frequency-adjusted locally generated clock signal is obtained based on the phase control word, the reference clock and the adjusted frequency control word.

[0099] The clock synchronization device 700 provided in the embodiment of the present disclosure can implement each process in the above-mentioned clock synchronization method embodiment, and will not be described again here to avoid repetition.

[0100] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0101] Figure 8 A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0102] like Figure 8 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 to a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0103] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0104] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSP), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as clock synchronization methods. For example, in some embodiments, the clock synchronization method may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the clock synchronization method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the clock synchronization method in any other appropriate manner (eg, by means of firmware).

[0105] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0106] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0107] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0108] As used herein, the term "machine-readable medium" refers to any computer program product, apparatus, and / or device (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0109] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0110] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0111] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0112] The present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the above Figure 1 The various processes of the method embodiment shown can achieve the same technical effect, and will not be described again here to avoid repetition.

[0113] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0114] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A clock synchronization method, characterized in that: Applied to a target audio node, the method comprises: receiving a synchronization signal, wherein the synchronization signal has a plurality of synchronization periods; calculating a phase error of a locally generated clock signal relative to the synchronization signal within one or more synchronization periods; The frequency of the locally generated clock signal is adjusted based on the phase error so that the locally generated clock signal is synchronized with the synchronization signal.

2. The method according to claim 1, characterized in that Adjusting the frequency of the locally generated clock signal based on the phase error includes: Calculating an adjusted frequency control word according to the phase error; A frequency-adjusted locally generated clock signal is obtained according to the adjusted frequency control word to reduce the phase error, thereby synchronizing the locally generated clock signal with the synchronization signal.

3. The method according to claim 1, characterized in that Calculating a phase error of a locally generated clock signal relative to the synchronization signal within one or more synchronization periods, comprising: Counting the locally generated clock signal from an initial value to obtain a count value, and resetting to the initial value and continuing to count when the count value reaches a predetermined upper limit value, wherein the predetermined upper limit value is determined based on a reference ratio value, and the reference ratio value is a ratio of a duration of one or more synchronization cycles spaced apart to an ideal frequency of the locally generated clock signal; The count value is sampled every one or more synchronization periods, and the phase error is determined based on a difference between count values ​​obtained by two adjacent samplings.

4. The method according to claim 3, characterized in that When the sampled count value enters the locking range, a locking signal is output; Sampling the count value every one or more synchronization periods includes: When a rising edge or a falling edge of the synchronization signal is detected every one or more synchronization periods, the count value is sampled.

5. The method according to claim 2, characterized in that: The step of calculating the adjusted frequency control word according to the phase error comprises: A PID operation is performed on a default frequency control word based on the phase error to obtain the adjusted frequency control word.

6. The method according to claim 5, characterized in that The step of obtaining a frequency-adjusted locally generated clock signal according to the adjusted frequency control word includes: A frequency-adjusted locally generated clock signal is obtained based on the phase control word, the reference clock and the adjusted frequency control word.

7. A clock synchronization device, characterized in that: Applied in a target audio node, the device comprises: An interface module, configured to receive a synchronization signal, wherein the synchronization signal has a plurality of synchronization cycles; a phase detector module, configured to calculate a phase error of a locally generated clock signal relative to the synchronization signal within one or more synchronization periods; A clock synchronization module is used to adjust the frequency of the locally generated clock signal based on the phase error so that the locally generated clock signal is synchronized with the synchronization signal.

8. The device according to claim 7, characterized in that The clock synchronization module comprises: A PID algorithm module, used for calculating an adjusted frequency control word according to the phase error; The DDS module is used to obtain a frequency-adjusted locally generated clock signal according to the adjusted frequency control word to reduce the phase error, thereby synchronizing the locally generated clock signal with the synchronization signal.

9. The device according to claim 7, characterized in that The phase detector module includes a counter and a phase detector: The counter starts counting the locally generated clock signal from an initial value to obtain a count value, and when the count value reaches a predetermined upper limit value, the counter is reset to the initial value and then continues counting, wherein the predetermined upper limit value is determined based on a reference ratio value, and the reference ratio value is a ratio of a duration of one or more synchronization cycles spaced apart to an ideal frequency of the locally generated clock signal; The phase detector samples the count value of the counter every one or more synchronization periods, and determines the phase error based on a difference between count values ​​obtained by two adjacent samplings.

10. The device according to claim 9, characterized in that The phase detector module also includes a phase comparator; The phase comparator outputs a locking signal when the count value sampled by the phase detector enters a locking range; The phase detector samples the count value of the counter when detecting a rising edge or a falling edge of the synchronization signal every one or more synchronization periods.

Images