GaN umosfet with gate trench filling and method of manufacturing the same

Abstract

The application discloses a gate trench filled GaN UMOSFET and a preparation method thereof. The UMOSFET comprises a semiconductor structure, a gate trench structure, a source and a drain, the gate trench structure comprises a gate and a gate trench formed in the semiconductor structure, the gate is at least partially arranged in the gate trench, and the gate and the inner wall of the gate trench are separated from each other by a dielectric layer, the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer continuously covers the inner wall of the gate trench, the second dielectric layer is a thick bottom dielectric and is filled in the bottom of the gate trench and between the gate and the first dielectric layer. By arranging the composite dielectric layer containing the thick bottom dielectric in the structure of the GaN UMOSFET, the peak electric field concentration at the bottom of the gate trench of the device can be effectively inhibited without changing the overall structure of the device, the overall electric field distribution trend of the drift region is not changed, thus the forward conduction characteristics of the device are not affected, and the breakdown characteristics of the device are greatly enhanced.

Description

TECHNICAL FIELD

[0001] The application relates to a UMOSFET device, in particular to a gate trench filled GaN UMOSFET and a preparation method thereof, and belongs to the technical field of semiconductors. BACKGROUND

[0002] A vertical GaN-based power device has the advantages of high breakdown voltage, high current density, high reliability, natural enhancement, etc. due to the peak electric field in the body, and is suitable for high-current and high-voltage fields such as electric vehicles and renewable energy. Compared with other structures, a vertical GaN trench gate metal-oxide-semiconductor field effect transistor (MOSFET) has the advantages of natural enhancement, no need for secondary epitaxy, and theoretically high breakdown voltage. In recent years, the vertical GaN trench gate MOSFET has made great progress in breakdown voltage, current density and dynamic performance. However, the trench bottom formed by etching has the phenomenon of electric field concentration, which causes the gate oxide dielectric to be easily broken down, resulting in a device breakdown voltage (V BR ) much lower than the theoretical value of the non-punch-through GaN p-n junction, which does not reach the ideal breakdown limit, limiting the improvement of the breakdown voltage of the vertical GaN trench gate MOSFET. This is an important factor affecting the off-state performance of the vertical trench gate device, and is a difficult problem to be solved at present. In view of this problem, the current solutions mainly include adding a p-GaN buried layer field shielding at the bottom of the gate trench or introducing a p-type floating island (FLI) structure in the drift region. These structures mainly change the electric field distribution of the drift region by increasing the depletion region of the p-n junction, so as to suppress the peak electric field at the bottom of the trench in the off state of the device, and protect the gate dielectric from high field. However, this structure inevitably requires additional etching and secondary epitaxy, which greatly increases the complexity and difficulty of the device process. Moreover, the introduction of the additional p-GaN structure will bring about JFET effect, thereby increasing the on-state resistance (R ON ) of the device, which is not conducive to the on-state characteristics of the device, and usually requires the introduction of a current spreading layer (CSL) with a higher doping concentration than the drift layer to solve this problem, which also makes the device preparation process more complex, has low implementability, and is currently still in the simulation stage.

[0003] Meanwhile, some studies have also been reported by introducing an additional thick bottom dielectric (TBD) layer in the gate trench, and an ethylene octene copolymer (EOC) is introduced as an additional thick bottom dielectric at the bottom of the trench of the vertical GaN trench gate MOSFET, which effectively alleviates the electric field concentration at the corner of the trench bottom, and the breakdown voltage of the device is obviously improved, but the introduction of the polymer requires additional curing and etching processes. And the cost of high-performance polymer is high, its effective life and reliability are difficult to guarantee, and there are often problems such as poor thermal stability, weak chemical stability, easy aging or degradation, and poor material compatibility, which will affect the consistency of the device process and the overall preparation cost to some extent. SUMMARY

[0004] The main purpose of the present application is to provide a gate trench filled GaN UMOSFET and a preparation method thereof to overcome the shortcomings of the prior art.

[0005] In order to achieve the above-mentioned purpose of the application, the technical scheme adopted by the present application comprises:

[0006] One aspect of the present application provides a gate trench filled GaN UMOSFET, which comprises a semiconductor structure, a trench gate structure, a source and a drain, the trench gate structure comprises a gate and a gate trench formed in the semiconductor structure, the gate is at least partially located in the gate trench, and the gate and the inner wall of the gate trench are separated by a dielectric layer, the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer at least continuously covers the inner wall of the gate trench, and the second dielectric layer at least fills the bottom of the gate trench and is located between the gate and the first dielectric layer.

[0007] Another aspect of the present application provides a method for preparing the gate trench filled GaN UMOSFET, which comprises:

[0008] Growth of a fourth GaN layer, a third GaN layer, a second GaN layer and a first GaN layer on a substrate in sequence to form a semiconductor structure, wherein the first GaN layer and the fourth GaN layer are both n-type, and the second GaN layer and the third GaN layer are respectively p-type and u-type;

[0009] Etching from the top end surface of the semiconductor structure, the etching depth reaching at least the bottom end surface of the second GaN layer, thereby forming a gate trench in the semiconductor structure;

[0010] Deposition of a first dielectric material on at least the inner wall of the gate trench to form a first dielectric layer, and then deposition of a second dielectric material in at least the gate trench to form a second dielectric layer, and the second dielectric layer at least fills the bottom of the gate trench;

[0011] A gate electrode is disposed on the second dielectric layer and at least partially disposed in the gate trench;

[0012] A source electrode and a drain electrode are disposed on the semiconductor structure and electrically connected to the first GaN layer and the fourth GaN layer, respectively.

[0013] Compared with the prior art, the present application has at least the following beneficial effects:

[0014] (1) By introducing the composite dielectric layer containing the thick bottom dielectric into the structure of the GaN UMOSFET, the peak electric field concentration at the bottom of the gate trench of the device can be effectively suppressed without changing the overall structure of the device, and the overall electric field distribution trend of the drift region is not changed, so the forward conduction characteristics of the device are not affected, thereby facilitating the substantial enhancement of the breakdown characteristics of the device.

[0015] (2) By introducing the thick bottom dielectric process into the mature process of the GaN UMOSFET, the peak electric field concentration at the bottom of the gate trench of the device is effectively suppressed without affecting the consistency of the device preparation process and substantially increasing the difficulty of the device preparation process, thereby ensuring the long-term stability and reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is a structure schematic diagram of a GaN UMOSFET in a typical embodiment of the present application;

[0018] Figure 2 is a principle schematic diagram of a GaN UMOSFET preparation process in a typical embodiment of the present application;

[0019] Figure 3 is another principle schematic diagram of a GaN UMOSFET preparation process in a typical embodiment of the present application;

[0020] Figure 4 is a partial photo (magnification 10,000 times) of a gate trench of a GaN UMOSFET without thick bottom dielectric in Comparative Example 1;

[0021] Figure 5 is a partial photo (magnification 10,000 times) of a gate trench of a GaN UMOSFET with thick bottom dielectric in Example 1;

[0022] Figure 6 is a simulation diagram of the electric field distribution in the gate trench area of the device without thick bottom dielectric in Comparative Example 1 and the device with thick bottom dielectric in Example 1;

[0023] Figure 7 is a simulation diagram of the electric field distribution in the Al2O3 gate dielectric at the bottom of the gate trench of the device without thick bottom dielectric in Comparative Example 1 and the device with thick bottom dielectric in Example 1. DETAILED DESCRIPTION

[0024] As mentioned above, for the problems caused by the electric field concentration at the bottom of the trench in the GaN trench gate MOSFET, the solutions proposed by the industry all have defects. For example, introducing p-GaN floating island in the drift layer or introducing p-GaN buried layer shielding at the bottom of the gate trench are both to reorganize the electric field distribution of the drift region by increasing the p-n junction depletion region, so that the peak electric field at the corner of the bottom of the gate trench is diffused, thereby improving the breakdown characteristics of the device. However, the structure of the secondary epitaxial p-GaN layer introduces an additional JFET region, which changes the electric field distribution of the drift region under the off-state of the device, and also affects the current density distribution when the device is turned on, increases the on-resistance, and worsens the forward opening characteristics of the device. Although the method of introducing polymer as thick bottom dielectric deposited at the bottom of the gate trench does not affect the forward characteristics of the device, it increases the cost of device preparation, and the polymer has poor thermal stability and chemical stability, which may degrade or deform under high temperature conditions, and may encounter corrosion, dissolution or chemical reaction problems during the manufacturing process, which affects the consistency of the device preparation process. Since the polymer material may also age or degrade over time, the long-term stability and reliability of the device cannot be guaranteed.

[0025] Therefore, the present inventors have long-term research and a large number of practices, and have proposed the technical solution of the present application, which is mainly to deposit a gate dielectric layer (i.e. the first dielectric layer mentioned above) in the gate trench of the GaN UMOSFET, and then fill high-k dielectric material such as silicon dioxide to form a thick bottom dielectric (i.e. the second dielectric layer mentioned above) in the gate trench. The existence of the first dielectric layer can prevent dry etching from damaging the surface of the GaN material, thereby achieving high input characteristics of the device while significantly improving the voltage withstand characteristics of the device.

[0026] The technical solution of the present application will be described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0027] Some embodiments of the present application provide a gate trench filled GaN UMOSFET (hereinafter also referred to as "device" for short), which comprises:

[0028] A semiconductor structure comprising a first GaN layer, a second GaN layer, a third GaN layer and a fourth GaN layer arranged in sequence along a first direction, wherein the first GaN layer and the fourth GaN layer are both n-type, and the second GaN layer and the third GaN layer are respectively p-type and u-type;

[0029] A gate trench structure comprising a gate trench and a gate electrode, the gate electrode being at least partially arranged in the gate trench, the gate trench having a slot opening arranged at a top end surface of the semiconductor structure and a slot bottom arranged at a bottom end surface of the second GaN layer or inside the third GaN layer, the top end surface of the semiconductor structure being away from the fourth GaN layer, the gate electrode and the inner wall of the gate trench being separated by a dielectric layer, the dielectric layer comprising a first dielectric layer and a second dielectric layer, the first dielectric layer at least continuously covering the inner wall of the gate trench, and the second dielectric layer at least filling the bottom of the gate trench and being arranged between the gate electrode and the first dielectric layer;

[0030] A source electrode in electrical contact with the first GaN layer;

[0031] A drain electrode in electrical contact with the fourth GaN layer.

[0032] In one embodiment, the gate trench is a U-shaped trench.

[0033] In one embodiment, the slot bottom of the gate trench is arranged inside the third GaN layer, i.e. below the bottom end surface of the second GaN layer, so as to ensure normal opening of the device and facilitate subsequent deposition of thick bottom dielectric.

[0034] In one embodiment, the spaces occupied by the first dielectric layer, the second dielectric layer and the gate electrode in the gate trench are respectively 1-10% (preferably 5-10%), 1-10% (preferably 5-10%) and 80-98% (preferably 80-90%) of the volume of the gate trench. For example, the spaces occupied by the first dielectric layer, the second dielectric layer and the gate electrode in the gate trench are respectively about 5%, 5% and 10% of the volume of the gate trench. With this design, the interface quality can be improved, the dielectric loss can be reduced, the electric field management can be improved, and the advantages of different dielectric materials can be brought into play.

[0035] In one embodiment, the first dielectric layer continuously extends and covers the top end surface of the semiconductor structure, so as to improve the charge at the dielectric interface and achieve passivation treatment of the surface of the semiconductor structure as a passivation layer.

[0036] Of course, in some cases, other passivation layers can also be covered on the top end surface of the semiconductor structure.

[0037] In one embodiment, the top end surface of the second dielectric layer is flush with or lower than the bottom end surface of the second GaN layer, preferably lower than the bottom end surface of the second GaN layer, to avoid affecting the forward conduction characteristics of the device.

[0038] Further, the thickness of the first dielectric layer is less than the thickness of the second dielectric layer. More preferably, the thickness of the second dielectric layer can be more than twice the thickness of the first dielectric layer. For example, the thickness of the first dielectric layer can be 1-200 nm, more preferably 10-100 nm. The thickness of the second dielectric layer can be 10-1000 nm, more preferably 50-1000 nm.

[0039] More preferably, the dielectric constant of the first dielectric material used to form the first dielectric layer is higher than the dielectric constant of the second dielectric material used to form the second dielectric layer, so that the composite dielectric layer composed of the first dielectric layer and the second dielectric layer can exert greater capacitive advantage, while significantly improving the critical breakdown field strength at the gate dielectric, thereby more effectively improving the electric field management.

[0040] Further, the material of the first dielectric layer can include but is not limited to any one or a combination of more than one of Al2O3, Si3N4, silicon oxide, AlN or HfO2.

[0041] Further, the material of the second dielectric layer can include but is not limited to silicon oxide or a curable insulating polymer (such as polyimide and other curable photoresist polymers, etc.), but inorganic dielectric materials such as silicon dioxide are more preferred because they have the advantages of excellent electrical insulation, high dielectric constant, good thermal stability, strong chemical stability, etc., and they have mature manufacturing processes, which do not affect the consistency of the device preparation process while ensuring the long-term stability and reliability of the device.

[0042] More preferably, the first dielectric layer is an Al2O3 layer, and the second dielectric layer is a silicon dioxide layer. Under the same thickness of the composite dielectric layer, this scheme can more effectively reduce the peak electric field at the bottom of the gate trench.

[0043] In one embodiment, the source and the drain form ohmic contacts with the first GaN layer and the fourth GaN layer, respectively.

[0044] Further, the materials of the gate, source and drain can be selected from but not limited to metals such as Au, Ag, Ti, Cu, alloys thereof or a stacked structure of metal elements.

[0045] Some embodiments of the present application also provide a method for preparing the gate trench filled GaN UMOSFET, which comprises:

[0046] forming a semiconductor structure by sequentially growing a fourth GaN layer, a third GaN layer, a second GaN layer and a first GaN layer on a substrate, wherein the first GaN layer and the fourth GaN layer are both n-type, and the second GaN layer and the third GaN layer are respectively p-type and u-type;

[0047] performing etching from a top end surface of the semiconductor structure to a depth at least reaching a bottom end surface of the second GaN layer, thereby forming a gate trench in the semiconductor structure;

[0048] depositing a first dielectric material on at least an inner wall of the gate trench to form a first dielectric layer, and then depositing a second dielectric material in at least the gate trench to form a second dielectric layer, and the second dielectric layer at least fills a bottom of the gate trench;

[0049] providing a gate electrode on the second dielectric layer, and the gate electrode is at least partially located in the gate trench;

[0050] and providing a source electrode and a drain electrode on the semiconductor structure, and the source electrode and the drain electrode are respectively in electrical contact with the first GaN layer and the fourth GaN layer.

[0051] In one embodiment, the preparation method can include:

[0052] performing etching from a top end surface of the semiconductor structure to a depth reaching inside of the third GaN layer, thereby forming the gate trench;

[0053] depositing a first dielectric material on the top end surface of the semiconductor structure and the inner wall of the gate trench to form a continuous first dielectric layer, and then depositing a second dielectric material on the first dielectric layer to at least fill the gate trench, and then removing the part of the second dielectric material filled in the gate trench and the second dielectric material covering the top end surface of the semiconductor structure, thereby forming the second dielectric layer, and a top end surface of the second dielectric layer is flush with or lower than a bottom end surface of the second GaN layer.

[0054] Further, the preparation method can specifically include:

[0055] depositing the second dielectric material on the first dielectric layer until the gate trench is filled with the second dielectric material and the top end surface of the semiconductor structure is covered with the second dielectric material;

[0056] at least part of the second dielectric material distributed outside the gate trench is removed by at least a polishing method, and the first dielectric layer is completely retained, and then the second dielectric material remaining on the top end surface of the semiconductor structure and the part of the second dielectric material filled in the gate trench are removed by a dry etching process, thereby forming the second dielectric layer.

[0057] In one embodiment, the preparation method can comprise activating the acceptor impurities in the second GaN layer by an annealing process in a protective atmosphere.

[0058] In one embodiment, the preparation method can comprise forming a gate trench in the semiconductor structure by a dry etching process, and then repairing the etching damage by a wet etching process to obtain a desired gate trench morphology.

[0059] In one embodiment, the preparation method can comprise, after etching the gate trench, performing a plasma surface treatment on at least the inner wall of the gate trench to reduce defect states and / or dangling bonds. The plasma used can be selected from, but not limited to, hydrogen, oxygen, nitrogen, and the like.

[0060] In one embodiment, the preparation method can comprise depositing a second dielectric material on the first dielectric layer by at least a chemical vapor deposition process such as MOCVD (metal organic chemical vapor deposition) or an atomic layer deposition (ALD) process to form the second dielectric layer.

[0061] In the present application, the substrate can be a homo-substrate (such as an intrinsic GaN substrate) or a hetero-substrate (such as a sapphire, Si, or SiC substrate, etc.).

[0062] In the above device preparation method provided in the present application, the introduction of the thick bottom dielectric process suppresses the peak electric field concentration at the bottom of the device gate trench, does not require a secondary epitaxial p-GaN layer, and does not change the overall structure of the device, so that the difficulty of the device preparation process is basically not affected. Since only the thick bottom dielectric is deposited at the bottom of the gate trench to resist the high electric field, the overall electric field distribution trend of the drift region is not changed, so the forward conduction characteristics of the device are not affected.

[0063] In one typical embodiment of the present application, a structure of a GaN UMOSFET can refer to Figure 1, which comprises a substrate 4, a semiconductor structure arranged on the substrate, a source electrode 5, a drain electrode 7 and a gate electrode 6. The semiconductor structure comprises a fourth GaN layer 10, a third GaN layer 3, a second GaN layer 2 and a first GaN layer 1 successively grown from bottom to top on the substrate 4. The first GaN layer 1 and the fourth GaN layer 10 are both n-type, in particular heavily doped n-GaN layers. The second GaN layer 2 and the third GaN layer 3 are p-type and u-type respectively. A gate trench 11 is formed in the gate region of the semiconductor structure, which extends from the surface of the first GaN layer 1 into the third GaN layer 3. Meanwhile, a first dielectric layer 8 is formed on the top surface of the semiconductor structure, which continuously covers the top surface of the semiconductor structure and the inner wall of the gate trench 11 to form a MOS structure together with the gate electrode 6. Meanwhile, a second dielectric layer 9 is filled in the bottom of the gate trench 11, which is distributed between the portion of the gate electrode 6 embedded in the gate trench 11 and the first dielectric layer 8 to form a thick bottom dielectric. The source electrode 5 and the drain electrode 7 form ohmic contacts with the first GaN layer 1 and the fourth GaN layer 10 respectively.

[0064] In the typical embodiment, the substrate 4 can be a GaN substrate, a sapphire substrate, a Si substrate or a SiC substrate, etc. The source electrode 5, the drain electrode 7 and the gate electrode 6 can all be of metal material. The first dielectric layer 8 can be of Al2O3, SiO2, silicon nitride, AlN, etc. The second dielectric layer 9 can be of silicon oxide, etc.

[0065] The typical embodiment also provides a method for manufacturing the device shown, which mainly comprises the following steps: Figure 1 The method for manufacturing the device shown mainly comprises the following steps:

[0066] S1, growing and forming the semiconductor structure on the substrate 4 by using MOCVD or the like.

[0067] S2, etching the gate trench, which comprises etching the semiconductor structure from the region corresponding to the gate electrode on the top surface of the first GaN layer 1 by using Cl-based gas or the like to a specified depth, generally below the second GaN layer 2 (i.e. the p-GaN channel layer), so as to form the gate trench 11. The etching depth can ensure the normal opening of the device, and meanwhile, since the deposition of the thick bottom dielectric will be performed subsequently, the etching depth of the gate trench here also needs to be relatively large.

[0068] S3, performing furnace-out activation, wet etching and gate trench plasma treatment, which comprises activating the Mg acceptor impurities in the second GaN layer 2 by using high-temperature annealing (usually at about 850℃) in a protective atmosphere of N2 or the like, then using wet etching to repair the etching damage to obtain an ideal groove morphology, and can use hydrogen, oxygen, nitrogen or the like plasma for surface treatment to reduce the defect states or dangling bonds.

[0069] S4, deposition of the first dielectric layer 8: The first dielectric layer is mainly used as a gate dielectric layer, and its material can be selected from one or more of Al2O3, SiO2, silicon nitride, AlN, etc. to form a MOS structure.

[0070] S5, deposition of the second dielectric layer 9 (i.e. thick bottom dielectric), which includes depositing a certain thickness of high-dielectric-constant SiO2 on the bottom of the gate trench before depositing the gate metal to form the gate 6, for resisting high electric field and suppressing the peak electric field at the bottom of the trench without affecting the forward conduction characteristics of the device. The deposition of the second dielectric layer 9 can be performed by using a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) to accurately control the deposition thickness. Further, the second dielectric layer 9 can be deposited in situ after the deposition of the first dielectric layer 8, thereby reducing the growth defects between the two different dielectric layers.

[0071] S6, source opening: The gate dielectric opening in the source region is prepared for the subsequent deposition of the source metal.

[0072] S7, drain deep etching: In the quasi-vertical device, deep etching is needed to the fourth GaN layer 10 at the bottom, and for the full-vertical device, this step can be omitted.

[0073] S8, electrode metal deposition: The source and drain metals are usually Ti / Al / Ni / Au deposited on the heavily doped n-GaN layer (the first GaN layer 1 and the fourth GaN layer 10) to form an ohmic contact, and finally the gate metal is deposited.

[0074] In the above preparation method provided by the typical embodiment, the manufacturing process of the second dielectric layer 9 can be implemented by two schemes as shown in Figure 2 、 Figure 3 .

[0075] Specifically, please refer to Figure 2 In one of the schemes, after the deposition of the first dielectric layer 8 is completed and before the deposition of the gate metal, SiO2 material 9' is deposited on the first dielectric layer 8 by using a method such as plasma-enhanced chemical vapor deposition (PETEOS), and the deposited SiO2 material is thick enough to fill the entire gate trench; then the SiO2 material surface is polished by using a method such as chemical mechanical polishing (CMP); finally, the SiO2 material is etched by using F-based gas until a certain thickness of SiO2 material remains at the bottom of the gate trench, and the top end of the remaining SiO2 material should be lower than the plane where the bottom end surface of the second GaN layer 2 is located, so as to ensure that the normal forward opening characteristics of the device are not affected, thereby completing the manufacturing of the second dielectric layer 9.

[0076] Please refer to Figure 3In another scheme, after the deposition of the first dielectric layer 8 is completed, the deposition of the SiO2 material 9' on the first dielectric layer 8 is performed before the deposition of the gate metal, by using plasma enhanced chemical vapor deposition (PETEOS) or the like, and the deposited SiO2 material is thick enough to fill the entire gate trench; then selective grinding and polishing is performed by using chemical mechanical polishing (CMP) or the like until the first dielectric layer 8 is reached; finally, selective dry or wet etching of the SiO2 material is performed by using F-based gas until a certain thickness of the SiO2 material is left at the bottom of the gate trench, and the top end of the remaining SiO2 material should be lower than the plane where the bottom end surface of the second GaN layer 2 is located, so as to ensure that the normal forward opening characteristics of the device are not affected, thereby completing the fabrication of the second dielectric layer 9.

[0077] wherein, Figure 3 The scheme shown in the figure is to use selective CMP grinding to stop grinding at the first dielectric layer 8 while achieving planarization of the second dielectric layer 9, and then to achieve local filling in the gate trench by selective dry or wet etching. Figure 2 Compared with the scheme shown in the figure, Figure 3 The scheme shown in the figure has lower etching damage to the gate trench.

[0078] In the above typical embodiments of the present application, plasma treatment is combined with ALD deposition of aluminum oxide or the like to form a low interface state protective layer (the first dielectric layer 8), and then silicon dioxide is deposited to completely fill the gate trench, and then CMP grinding is used to polish the surface silicon oxide layer, or selective CMP grinding is used to form a plane with the first dielectric layer 8 surface and the silicon oxide in the gate trench, and then selective dry or wet etching is used to achieve local filling in the gate trench, and the oxide filling process will not affect the GaN channel interface, and high-quality gate dielectric layer and thick bottom dielectric (the second dielectric layer 9) can be achieved at the same time, which can achieve high input characteristics of the device and improve the voltage withstand characteristics of the device.

[0079] The technical solutions of the present application are further explained and described below in combination with the drawings and several preferred embodiments, but the experimental conditions and setting parameters should not be regarded as limitations of the basic technical solutions of the present application. The protection scope of the present application is not limited to the following embodiments.

[0080] Embodiment 1

[0081] The structure of a GaN UMOSFET provided in this embodiment is shown in the figure. Figure 1 A method for preparing the device includes the following steps:

[0082] S1, forming a fourth GaN layer with a thickness of about 1000 nm, a third GaN layer with a thickness of about 4000 nm, a second GaN layer with a thickness of about 500 nm and a first GaN layer with a thickness of about 200 nm on a sapphire substrate by using a MOCVD process, so as to form a semiconductor structure. The first GaN layer and the fourth GaN layer are both heavily doped n-type GaN layers with a doping concentration of about 2.5e18, the third GaN layer is an intrinsic GaN layer, and the second GaN layer is a p-type GaN layer with a doping concentration of about 3e19.

[0083] S2, etching vertically downwards from the surface of the first GaN layer 1 in the gate area by using a Cl-based gas, and the etching depth is about 1200-1500 nm, so as to form a gate trench in the semiconductor structure.

[0084] S3, annealing the device structure obtained in step S2 in an N2 atmosphere, the annealing temperature is about 850 DEG C, and the annealing time is about 20-30 min. Then, cooling to room temperature, and then etching the device structure by using a tetramethylammonium hydroxide solution at room temperature, and the etching time is about 120 min.

[0085] S4, depositing an aluminum oxide with a thickness of about 50 nm on the top surface and the inner wall of the gate trench of the device structure after step S3 by using an ALD process, so as to form a first dielectric layer.

[0086] S5, depositing silicon oxide on the top surface and the gate trench of the device structure after step S4 by using a PETEOS process, until the gate trench is filled with silicon oxide, and the thickness of the silicon oxide layer on the top surface of the device structure is about 2000 nm. Then, polishing the silicon oxide layer by using a CMP process, so as to polish the surface of the silicon oxide layer, and then etching the SiO2 by using a F-based gas, until the thickness of the silicon oxide remaining in the gate trench is about 500 nm, so as to form a second dielectric layer. The space occupied by the first dielectric layer, the second dielectric layer and the gate is about 5%, 5% and 10% of the volume of the gate trench respectively.

[0087] S6, processing a window in the source area of the first dielectric layer, so as to prepare for the subsequent deposition of the source metal.

[0088] S7, mesa etching the semiconductor structure by using a Cl-based gas, until the fourth GaN layer is exposed.

[0089] S8, depositing source metal and drain metal Ti / Al / Ni / Au (the thickness is about 20 / 130 / 50 / 150 nm) on the first GaN layer and the fourth GaN layer by using a metal evaporation and metal stripping process, so as to form an ohmic contact, and then depositing gate metal Ti / Au (the thickness is about 20 / 120 nm), so as to form a source, a drain and a gate.

[0090] Comparative Example 1

[0091] The preparation method of the GaN UMOSFET provided in this comparative example is basically the same as that in Embodiment 1, except that step S5 is omitted.

[0092] Please refer to FIG. 4, Figure 5 FIG. 4 shows a partial photo of the gate trench of the GaN UMOSFET without thick bottom dielectric in Comparative Example 1, and FIG. 5 shows a partial photo of the gate trench of the GaN UMOSFET with thick bottom dielectric in Embodiment 1.

[0093] The off-state characteristics of the two devices were simulated and tested, and the electric field distribution of the devices under the same applied drain voltage is shown in FIG. 6. Figure 6 、 Figure 7 As shown in FIG. 6, the peak electric field at the bottom of the gate trench of the device with SiO2 thick bottom dielectric, i.e., the device in Embodiment 1, is effectively reduced from 5.63 MV / cm to 3.54 MV / cm. This confirms that the introduction of the thick bottom dielectric can effectively suppress the peak electric field concentration at the bottom of the gate trench, thereby facilitating the enhancement of the breakdown characteristics of the device.

[0094] Comparative Example 2

[0095] The preparation method of the GaN UMOSFET provided in this comparative example is basically the same as that in Embodiment 1, except that:

[0096] ① Step S4 is omitted.

[0097] ② In step S5, first, PETEOS process is used to deposit silicon oxide on the top end surface and inside the gate trench of the device structure after step S4, until the gate trench is filled with silicon oxide and the thickness of the silicon oxide layer on the top end surface of the device structure is about 2000 nm. Then, CMP process is used to polish and grind the silicon oxide layer to flatten the surface of the silicon oxide layer, until the thickness of the silicon oxide layer remaining on the top end surface of the device structure is about 50 nm. After that, a pattern mask is defined on the area above the silicon oxide layer in the gate trench through photolithography process, and SiO2 is etched using F-based gas until the thickness of the silicon oxide remaining at the bottom of the gate trench is about 500 nm, and the thickness of the silicon oxide layer remaining on the sidewall of the gate trench is about 50 nm. The overall time required for this step S5 is more than 3 times the total time required for steps S4 and S5 in Embodiment 1, and the cost is more than 5 times higher.

[0098] The peak electric field at the bottom of the gate trench of the device in this comparative example is about 4.73 MV / cm.

[0099] Embodiment 2

[0100] The structure of the GaN UMOSFET provided in this embodiment is basically the same as that in Embodiment 1, except that the material of the second dielectric layer is replaced by polyimide. The peak electric field at the bottom of the gate trench of the device in this embodiment is about 3.89 MV / cm.

[0101] It should be understood that the technical solutions of the present application are not limited to the specific implementation cases described above, and any technical modification made according to the technical solutions of the present application without departing from the scope of the present application and the protection scope of the claims, falls within the protection scope of the present application.

Claims

1. A gate trench filled GaN UMOSFET characterized by, Comprising: a semiconductor structure disposed on a substrate, comprising a first GaN layer (1), a second GaN layer (2), a third GaN layer (3) and a fourth GaN layer (10) disposed in sequence from top to bottom, wherein the first GaN layer (1) and the fourth GaN layer (10) are both n-type, and the second GaN layer (2) and the third GaN layer (3) are p-type and u-type respectively; a slot gate structure comprising a gate slot (11) and a gate electrode (6), wherein the gate electrode (6) is at least partially disposed in the gate slot (11), the slot opening of the gate slot (11) is disposed on the top end surface of the semiconductor structure, and the slot bottom is disposed on the bottom end surface of the second GaN layer (2) or inside the third GaN layer (3), the top end surface of the semiconductor structure is away from the fourth GaN layer (10), the gate electrode (6) and the inner wall of the gate slot (11) are isolated from each other through a dielectric layer, the dielectric layer comprises a first dielectric layer (8) and a second dielectric layer (9), the first dielectric layer (8) at least continuously covers the inner wall of the gate slot, and the second dielectric layer (9) at least fills the bottom of the gate slot (11) and is located between the gate electrode (6) and the first dielectric layer (8), the spaces occupied by the first dielectric layer, the second dielectric layer and the gate electrode in the gate slot (11) are 1-10%, 1-10% and 80-98% of the volume of the gate slot respectively; a source electrode (5) in electrical contact with the first GaN layer (1); a drain electrode (7) in electrical contact with the fourth GaN layer (10).

2. The gate trench filled GaN UMOSFET of claim 1, wherein: The gate slot (11) is a U-shaped slot.

3. The gate trench filled GaN UMOSFET of claim 1, wherein: The slot bottom of the gate slot (11) is disposed inside the third GaN layer (3).

4. The gate trench filled GaN UMOSFET of claim 1, wherein: The first dielectric layer (8) continuously extends and covers the top end surface of the semiconductor structure.

5. The gate trench filled GaN UMOSFET of claim 1, wherein: The top end surface of the second dielectric layer (9) is flush with or lower than the bottom end surface of the second GaN layer (2).

6. The gate trench filled GaN UMOSFET of claim 1, wherein: The thickness of the second dielectric layer (9) is greater than that of the first dielectric layer (8).

7. The gate trench filled GaN UMOSFET of claim 1, wherein: The thickness of the first dielectric layer (8) is 1-200 nm.

8. The gate trench filled GaN UMOSFET of claim 1, wherein: The material of the first dielectric layer (8) is any one or a combination of more than one of Al2O3, Si3N4, silicon oxide, AlN or HfO2.

9. The gate trench filled GaN UMOSFET of claim 1, wherein: The thickness of the second dielectric layer (9) is 10-1000 nm.

10. The gate trench filled GaN UMOSFET of claim 1, wherein: The material of the second dielectric layer (9) comprises silicon oxide or a curable insulating polymer.

11. The gate trench filled GaN UMOSFET of claim 1, wherein: The material of the gate electrode (6) comprises metal.

12. The gate trench filled GaN UMOSFET of claim 1, wherein: The source electrode (5) and the drain electrode (7) form ohmic contacts with the first GaN layer (1) and the fourth GaN layer (10) respectively.

13. A method of fabricating a trench-filled GaN UMOSFET according to any one of claims 1-12, characterized by, Comprising: growing a fourth GaN layer (10), a third GaN layer (3), a second GaN layer (2) and a first GaN layer (1) in sequence on a substrate to form a semiconductor structure, wherein the first GaN layer (1) and the fourth GaN layer (10) are both n-type, and the second GaN layer (2) and the third GaN layer (3) are p-type and u-type respectively; etching from the top end surface of the semiconductor structure to a depth of at least the bottom end surface of the second GaN layer (2), thereby forming a gate slot (11) in the semiconductor structure; depositing a first dielectric material on at least the inner wall of the gate trench to form a first dielectric layer (8), and then depositing a second dielectric material in the gate trench to form a second dielectric layer (9) which at least fills the gate trench (11); providing a gate electrode (6) on the second dielectric layer (9) and at least partially in the gate trench (11); and providing a source electrode (5) and a drain electrode (7) on the semiconductor structure and in electrical contact with the first GaN layer (1) and the fourth GaN layer (10), respectively.

14. The method of claim 13, wherein, Specifically comprising: etching from the top surface of the semiconductor structure to a depth inside the third GaN layer (3) to form the gate trench (11); depositing a first dielectric material on the top surface of the semiconductor structure and the inner wall of the gate trench (11) to form a continuous first dielectric layer (8), and then depositing a second dielectric material on the first dielectric layer to at least fill the gate trench (11), and then removing the second dielectric material from the top surface of the semiconductor structure and the portion of the second dielectric material in the gate trench (11) to form the second dielectric layer (9) with a top surface flush with or lower than the bottom surface of the second GaN layer (2).

15. The method of claim 14, wherein, Specifically comprising: depositing a second dielectric material on the first dielectric layer until the gate trench (11) is filled with the second dielectric material and the top surface of the semiconductor structure is covered with the second dielectric material; removing at least part of the second dielectric material outside the gate trench (11) by at least polishing, and then removing the second dielectric material from the top surface of the semiconductor structure and the portion of the second dielectric material in the gate trench (11) by dry etching to form the second dielectric layer (9).

16. The method of claim 13, wherein, Specifically comprising: activating the acceptor impurities in the second GaN layer (2) by an annealing process in a protective atmosphere.

17. The method of claim 13, wherein, Specifically comprising: forming the gate trench (11) in the semiconductor structure by a dry etching process, and then repairing the etching damage by a wet etching process.

18. The method of claim 13, wherein, Specifically comprising: after etching the gate trench (11), at least performing a plasma surface treatment on the inner wall of the gate trench (11) to reduce defect states and / or dangling bonds.

19. The method of claim 13, wherein, Specifically comprising: depositing a second dielectric material on the first dielectric layer (8) by at least chemical vapor deposition or atomic layer deposition to form the second dielectric layer (9).

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