DTI structure based on SiNx / SiO2 Liner and preparation method thereof

Abstract

The invention provides a DTI structure based on SiNx / SiO2 Liner. The DTI structure comprises a silicon substrate arranged at the bottom, a buried layer arranged on the surface of the top of the silicon substrate, an epitaxy formed by growing on the silicon substrate, and a buried layer reverse extension arranged between the buried layer and the epitaxy, the DTI deep groove sequentially penetrates through the epitaxy, the buried layer reverse extension and the buried layer and extends into the silicon substrate, the ISSG SiO2 bottom layer of the Line, the SiNx top layer of the Line and the HARP SiO2 layer are sequentially arranged in the DTI deep groove in a covering mode, and the DTI deep groove is filled with a polycrystalline silicon layer. The invention further provides a preparation method of the DTI structure based on the SiNx / SiO2 Liner, Liner oxide is replaced by two layers of NO LINs of the SiNx top layer and the ISSG SiO2 bottom layer, the additional high-temperature annealing step is reduced, the breakdown voltage of the DTI is improved, isolation electric leakage is reduced, and stress accumulation can be reduced; and meanwhile, the process of filling the HARP SiO2 layer twice and annealing twice is adopted, so that the possibility of stripping caused by overlarge stress of the HARP SiO2 layer is avoided.

Description

1. Technical Field

[0001] The present invention belongs to the field of silicon microelectronics technology and specifically relates to a method based on SiN x / DTI structure of SiO2 Liner and its preparation method. 2. Background technology

[0002] The BCD (Bipolar-CMOS-DMOS) process of integrated circuits integrates high-precision analog bipolar devices, highly integrated CMOS devices, and DMOS devices as power output stages into a single chip, optimizing circuit performance by utilizing their respective characteristics. The BCD process can significantly reduce circuit power consumption, improve system performance, increase reliability, and reduce costs.

[0003] For BCD process with feature size ≤ 0.25μm, shallow trench isolation (STI) is used for isolation between active areas (AA), and the STI shallow trench is filled with high-density plasma oxide (HDP SiO2). With the increase of operating voltage, STI isolation gradually cannot meet the isolation and leakage requirements of high operating voltage BCD, and STI isolation is upgraded to deep trench isolation (DTI). DTI can reduce isolation leakage, increase breakdown voltage, and reduce chip size. In the DTI process, reactive ion etching (RIE) is first used to form a deep trench with a width of 0.4 to 2μm and a depth of 10 to 40μm, and then a linear oxide layer (Lineroxide) is formed on the surface of the deep trench by thermal oxidation, and then annealed in a high-temperature inert gas, and finally filled with SiO2 and polysilicon (Poly Si) or only filled with SiO2.

[0004] When etching the DTI deep trench, a large number of etching defects will be generated on the sidewalls of the DTI deep trench, and the sharp top and bottom angles of the DTI deep trench will also cause parasitic leakage, reducing the isolation characteristics of the DTI. As an improvement measure, before the DTI deep trench is filled with SiO2, liner oxide will be grown by thermal oxidation and annealed at high temperature inert gas. First, liner oxide rounds the sharp top and bottom angles of the DTI deep trench to increase the contact surface; second, liner oxide avoids stress concentration and electric field concentration effects at the top and bottom angles; third, liner oxide repairs the etching damage of the Si surface at the edge of the DTI deep trench; finally, liner oxide also serves as a buffer layer when filling the DTI deep trench with SiO2. In addition, high-temperature inert gas annealing further repairs the DTI deep trench etching damage.

[0005] Since the aspect ratio of the DTI deep trench is (8-30):1, it is necessary to fill it with high aspect ratio process (HARP) SiO2 based on O3-TEOS (tetraethylorthosilicate). The deposited HARP SiO2 layer has a 10 8 Tensile stress of the order of Pa; after annealing, it becomes -10 8 The compressive stress is of the order of Pa, and the stress state is stable, and the polarity and order of magnitude no longer change with high-temperature thermal processes. In order to prevent the thicker HARP SiO2 layer from peeling off due to excessive stress, some DTI processes use the LPCVD (Low Pressure Chemical Vapor Deposition) process to fill the polysilicon layer as a stress buffer layer after filling a certain thickness of HARP SiO2 layer, because the polysilicon layer has compressive stress.

[0006] In order to further improve the isolation characteristics of DTI, it is necessary to provide a SiN-based x / SiO2 Liner’s DTI structure, and the filling of the DTI deep trench must also consider the optimization of the stress accumulation of the HARP SiO2 layer. 3. Purpose of the invention

[0008] The purpose of the present invention is to improve the isolation characteristics and reliability of the DTI structure.

[0009] First, Liner oxide is made of SiN x The two layers of Liner (top layer / ISSG SiO2 bottom layer) are replaced by NO, which improves the isolation characteristics of DTI and can reduce or even completely offset the stress accumulation of the HARP SiO2 layer. The Liner ISSG SiO2 bottom layer grown by the In-Situ Steam Generation (ISSG) process can round the sharp top and bottom angles of the DTI deep grooves, and the ISSG process also repairs and anneals the DTI deep groove etching damage, reducing the additional high-temperature annealing steps; the Liner SiN deposited by the LPCVD process x The top layer has stronger insulation capability than SiO2, SiN x The tensile stress in the top layer can reduce or even completely offset the accumulation of compressive stress in the HARP SiO2 layer after subsequent annealing.

[0010] Second, the process of filling the HARP SiO2 layer twice and annealing twice is adopted. Filling the HARP SiO2 layer twice can avoid the possibility of peeling caused by excessive tensile stress of the HARP SiO2 layer deposited once; at the same time, after annealing, the tensile stress of the HARP SiO2 layer during deposition changes to compressive stress. The compressive stress of the HARP SiO2 layer after the second high-temperature annealing is the same as that of SiN x The tensile stresses on the top layer can match or even completely offset each other, avoiding isolation leakage and device parameter drift caused by excessive stress in the DTI structure. 4. Contents of the invention

[0012] In order to achieve the above object, the present invention adopts the following technical solutions:

[0013] The present invention provides a SiN-based x The DTI structure of the SiO2 liner includes: a silicon substrate arranged at the bottom, a buried layer arranged on the top surface of the silicon substrate, an epitaxial layer grown from the silicon substrate, and a buried layer reverse extension arranged between the buried layer and the epitaxial layer; a U-shaped DTI deep groove that sequentially penetrates the epitaxial layer, the buried layer reverse extension and the buried layer and extends into the silicon substrate, the ISSG SiO2 bottom layer of the liner, the SiN x The top layer and the HARP SiO2 layer are sequentially covered in the DTI deep trench.

[0014] Preferably, the HARP SiO2 layer comprises the SiN x The top layer is a first HARP SiO2 layer and a second HARP SiO2 layer.

[0015] Preferably, it also includes a polysilicon layer for filling the DTI deep trench.

[0016] The present invention also provides a SiN-based x The preparation method of the DTI structure of / SiO2 Liner comprises the following steps:

[0017] Step S1, growth of SiO2 pad oxygen and Si3N4 barrier layer: providing a silicon substrate arranged at the bottom, a buried layer arranged on the top surface of the silicon substrate, an epitaxial layer grown from the silicon substrate, and a buried layer reverse extension arranged between the buried layer and the epitaxial layer, oxidizing and growing SiO2 pad oxygen on the epitaxial layer of the silicon substrate, and depositing a Si3N4 barrier layer by LPCVD;

[0018] Step S2, DTI deep trench etching: the active area is defined by photolithography, the Si3N4 barrier layer is dry-etched, and then the SiO2 pad oxide and epitaxy are continued to be etched to form a DTI deep trench on the surface of the silicon substrate, and the resin is removed after etching;

[0019] Step S3, growth of ISSG SiO2 bottom layer of Liner: The ISSG process grows the ISSG SiO2 bottom layer to round the sharp top and bottom angles of the DTI deep trench, and at the same time repairs the DTI deep trench etching damage through ISSG high temperature annealing, thereby reducing the additional high temperature annealing step;

[0020] Step S4, SiN Liner x Top layer growth: LPCVD deposition of SiN x Top layer, SiN x The top layer has stronger insulation capability than SiO2, SiN x The top layer has tensile stress, which can reduce or even completely offset the accumulation of compressive stress in subsequent HARP SiO2 layers;

[0021] Step S5, DTI deep trench filling with a first HARP SiO2 layer: depositing the first HARP SiO2 layer by a CVD process, and performing a first high-temperature annealing after deposition to improve the compactness of the first HARP SiO2 layer and convert the tensile stress of the first HARP SiO2 layer after deposition into a compressive stress after annealing;

[0022] Step S6, DTI deep trench filling with a second HARP SiO2 layer: depositing the second HARP SiO2 layer by a CVD process, and performing a second high-temperature annealing after deposition to improve the compactness of the second HARP SiO2 layer and convert the tensile stress of the second HARP SiO2 layer after deposition into a compressive stress after annealing;

[0023] Step S7, filling the DTI deep trench with a polysilicon layer: the DTI deep trench is completely filled with a polysilicon layer by depositing a polysilicon layer by LPCVD, and the polysilicon layer also serves as a stress buffer layer for the HARP SiO2 layer;

[0024] Step S8, DTI Chemical Mechanical Polishing (CMP): Use CMP to polish away the polysilicon layer, HARP SiO2 layer, and SiN x Top layer / ISSG SiO2 bottom layer NO two-layer Liner and part of Si3N4 barrier layer, CMP finally stops on the remaining Si3N4 barrier layer;

[0025] Step S9, complete stripping of Si3N4 barrier layer: first rinse off the SiO x N y , and then the remaining Si3N4 barrier layer is completely stripped to form a DTI structure.

[0026] Preferably, in step S2, the Si3N4 barrier layer is dry-etched, and then the SiO2 pad oxide and epitaxy are continued to be etched to form a DTI deep groove on the surface of the silicon substrate, including the following steps:

[0027] In step S21, the Si3N4 barrier layer in the DTI deep trench region is etched, the main etching gases are CF4, CH3F and O2, the etching selectivity ratio of Si3N4 to SiO2 is greater than 10:1, and the etching endpoint is selected to stay on the SiO2 pad oxygen;

[0028] In step S22, the SiO2 pad oxygen and epitaxy are penetrated and a DTI deep groove is etched on the surface of the silicon substrate. The main etching gases are Cl2, HBr and O2. The side wall angle of the formed DTI deep groove is 85°~90°, the width of the DTI deep groove is 0.4μm~2.0μm, the depth is 10μm~40μm, and the aspect ratio is (8~30):1.

[0029] Preferably, in step S3, an ISSG SiO2 bottom layer of the liner is grown by an ISSG process;

[0030] The ISSG SiO2 bottom layer is grown by ISSG oxidation with a volume ratio of H2:O2 of 1:(3-30) at a reaction temperature of 1000℃-1200℃ and a time of 20s-600s. The thickness is

[0031] Preferably, in step S4, the SiN of the Liner is deposited by LPCVD process. x Top floor;

[0032] LPCVD Deposition of SiN x The volume ratio of the reaction gas SiH2Cl2 to NH3 is 1:(0.3-10) at the top layer, the reaction temperature is 700℃-900℃, the pressure is 0.1Torr-5.0Torr, the time is 5min-40min, and the thickness is

[0033] Preferably, in step S5 and step S6, two HARP SiO2 layer depositions are used to fill the DTI deep trenches, and two high temperature anneals are used to improve the compactness of the HARP SiO2 layer;

[0034] When the HARP SiO2 layer is deposited, the volume ratio of the reaction gas TEOS to O3 is 1:(3-20), the reaction temperature is 400℃-600℃, the chamber pressure is 500Torr-700Torr, the deposition time of the first HARP SiO2 layer is 0.5min-2min, and the thickness is The deposition time of the second HARP SiO2 layer is 0.5min to 4min, and the thickness is

[0035] High temperature annealing uses inert gas (N2, He or Ar) annealing or water vapor (H2O) annealing, the temperature is 800°C to 1100°C, and the time is 5min to 60min.

[0036] Preferably, in step S7, the DTI deep trench is completely filled with a polysilicon layer by LPCVD deposition, and the polysilicon layer also serves as a stress buffer layer for the HARP SiO2 layer;

[0037] The polysilicon layer deposition reaction gas is SiH4, the temperature is 575℃~650℃, the pressure is 0.1Torr~5.0Torr, and the thickness is

[0038] Preferably, for the structure and process of filling only the first HARP SiO2 layer and the second HARP SiO2 layer in the DTI deep trench without filling the polysilicon layer, that is, only performing step S5 and step S6 without performing step S7, the deposition time of the first HARP SiO2 layer is 1 min to 8 min, and the thickness is The deposition time of the second HARP SiO2 layer is 1min to 12min, and the thickness is

[0039] 5. Effects of the Invention

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] The present invention proposes a method based on SiN x / SiO2 Liner's DTI structure. Liner oxide is made of SiN x The top layer / ISSG SiO2 bottom layer is replaced by two layers of NO Liner, which reduces the additional high-temperature annealing steps, improves the breakdown voltage of DTI, reduces isolation leakage, and reduces stress accumulation. At the same time, the process of filling the HARP SiO2 layer twice and annealing twice avoids the possibility of peeling due to excessive stress of the HARP SiO2 layer.

[0042] The ISSG SiO2 bottom layer of the Liner is grown using the ISSG process. The ISSG process can round the sharp top and bottom corners of the DTI deep trench, reducing stress concentration and electric field concentration; improve the uniformity of SiO2 at the top and bottom corners, avoiding the SiO2 thinning effect; repair the etching damage of the DTI deep trench, avoiding the generation of silicon defects at the edge of the DTI deep trench. Compared with the ordinary dry or wet oxidation growth of Liner oxide, ISSG has the following advantages: (1) The uniformity of SiO2 at the top and bottom corners is higher, (2) It avoids the drilling of the Si3N4 barrier layer during oxidation, and (3) ISSG high temperature annealing can better repair the etching damage of the DTI deep trench, reducing the additional high temperature annealing steps.

[0043] Liner's SiN is deposited using LPCVD x Top layer. SiN x The dielectric constant of SiN is about twice that of SiO2, and it has stronger insulation capability than SiO2. x The stress is 10 8 ~10 9 Pa (tensile stress), can be obtained by SiN x The Si content in the SiN is adjusted. The higher the Si content, the smaller the stress. x The tensile stress can reduce or even completely offset the accumulation of compressive stress in the HARPSiO2 layer after annealing.

[0044] Using two HARP SiO2 layers to fill can avoid a single deposited HARP SiO2 layer that is too thick and has too much tensile stress. After the first high-temperature annealing, the stress of the first deposited HARP SiO2 layer becomes compressive stress, so that the tensile stress of the two deposited HARP SiO2 layers will not accumulate, avoiding the possibility of HARP SiO2 layer peeling due to excessive stress. After the second high-temperature annealing, the stress of the two deposited HARP SiO2 layers is converted to compressive stress, which can be compared with SiN x The tensile stresses in the top layers match or even cancel each other out completely. 6. Detailed description of the drawings and their accompanying drawings

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 The SiN-based x / Schematic diagram of DTI structure of SiO2 Liner;

[0048] Figure 2 The SiN-based x / Flow chart of DTI manufacturing method of SiO2 Liner;

[0049] Figure 3 Schematic diagram of silicon substrate for growing SiO2 pad oxygen and Si3N4 barrier layer;

[0050] Figure 4 Schematic diagram of silicon substrate for completing DTI deep trench etching;

[0051] Figure 5 Schematic diagram of the ISSG SiO2 bottom layer of the ISSG process for growing Liner proposed in the present invention;

[0052] Figure 6 SiN deposited by LPCVD process proposed in the present invention x Top level schematic diagram;

[0053] Figure 7 A schematic diagram of filling the DTI deep trench with the first HARP SiO2 layer and performing the first high temperature annealing according to the present invention;

[0054] Figure 8 Schematic diagram of the deposition of the second HARP SiO2 layer for DTI deep trench filling proposed by the present invention;

[0055] Fig. 9 This is a schematic diagram after the second high temperature annealing proposed by the present invention;

[0056] Fig.10 Schematic diagram of DTI deep trench filling with polysilicon layer;

[0057] Fig.11 Schematic diagram of DTI after CMP.

[0058] Among them: 1. Silicon substrate; 2a. Buried layer; 2b. Buried layer reverse extension; 3. Epitaxy; 4. SiO2 pad oxide; 5. Si3N4 barrier layer; 6. ISSG SiO2 bottom layer; 7. SiN x Top layer; 8, HARP SiO2 layer; 8a, first HARP SiO2 layer; 8b, second HARP SiO2 layer; 9, polysilicon layer; 20, DTI deep trench. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0060] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0062] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0063] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", which does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0064] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0065] The present invention will be further described below in conjunction with the accompanying drawings and implementation modes.

[0066] See also Figures 1 to 11 The present invention provides a SiN-based x / DTI structure of SiO2 Liner, such as Figure 1 As shown, it includes a silicon substrate 1 arranged at the bottom, a buried layer 2a arranged on the top surface of the silicon substrate 1, an epitaxial layer 3 grown from the silicon substrate 1, and a buried layer reverse extension 2b arranged between the buried layer 2a and the epitaxial layer 3; a U-shaped DTI deep trench 20 that sequentially penetrates the epitaxial layer 3, the buried layer reverse extension 2b and the buried layer 2a and extends to the silicon substrate 1, a liner ISSG SiO2 bottom layer 6, a liner SiN x The top layer 7 and the HARP SiO 2 layer 8 are sequentially covered in the DTI deep trench 20 and filled with a polysilicon layer 9 .

[0067] The HARP SiO2 layer 8 includes the SiN x The top layer 7 includes a first HARP SiO 2 layer 8 a and a second HARP SiO 2 layer 8 b.

[0068] The present invention provides a SiN-based x / SiO2 Liner DTI structure manufacturing method, such as Figure 2 As shown, the following steps are included:

[0069] Step S1, growth of SiO2 pad oxygen and Si3N4 barrier layer: providing a silicon substrate at the bottom, a buried layer on the top surface of the silicon substrate, an epitaxial layer grown from the silicon substrate, and a buried layer reverse extension between the buried layer and the epitaxial layer, oxidizing and growing SiO2 pad oxygen on the epitaxial layer of the silicon substrate, and depositing a Si3N4 barrier layer by LPCVD.

[0070] like Figure 3 As shown, according to the known process, the upper surface of the original silicon substrate 1 has completed the implantation of the buried layer 2a, the push-in junction and the growth of the epitaxial 3. During the growth of the epitaxial 3, the buried layer 2a will diffuse from the lower surface of the epitaxial 3 to the epitaxial 3 to form the buried layer reverse extension 2b.

[0071] A SiO2 pad oxide 4 is grown on the upper surface of the epitaxial growth 3 by oxidation; and a Si3N4 barrier layer 5 is deposited by LPCVD to serve as a stop layer for the subsequent DTICMP.

[0072] The SiO2 pad oxide 4 is grown by dry oxidation with O2, the reaction temperature is 800℃~1000℃, the time is 1min~30min, and the thickness is

[0073] The Si3N4 barrier layer 5 is deposited by LPCVD, the volume ratio of the reaction gas SiH2Cl2 to NH3 is 1:(4-10), the reaction temperature is 700℃-900℃, the pressure is 0.1Torr-5.0Torr, the time is 20min-120min, and the thickness is

[0074] Step S2, DTI deep trench etching: the active area is defined by photolithography, the Si3N4 barrier layer is dry-etched, and then the SiO2 pad oxide and epitaxy are continued to be etched and the DTI deep trench is etched on the surface of the silicon substrate, and the resist is removed after etching.

[0075] Active area photolithography (including coating, exposure, and development) is performed, the active area is covered with photoresist, and DTI deep groove 20 is etched, and dry etching is used to adjust the different angles of the deep groove sidewall. In the first step, the Si3N4 barrier layer 5 in the DTI deep groove 20 area is etched, and the main etching gas is CF4, CH3F and O2. The etching selectivity ratio of Si3N4 to SiO2 is greater than 10:1, and the etching end point is selected to stay on the SiO2 pad oxide 4; in the second step, the DTI deep groove 20 is etched through the SiO2 pad oxide 4 and the epitaxy 3 and on the surface of the silicon substrate 1. The main etching gas is Cl2, HBr and O2. The side wall angle of the formed DTI deep groove 20 is 85° to 90°, the width of the DTI deep groove 20 is 0.4μm to 2.0μm, the depth is 10μm to 40μm, and the aspect ratio is (8 to 30):1.

[0076] After etching, the stripping is performed by dry and wet processes. The dry stripping process is O2 plasma stripping, and the wet stripping process is SPM (H2SO4:H2O2 volume ratio is 5:1) stripping. The morphology of the DTI deep groove 20 after etching and stripping is as follows: Figure 4 As shown, the active region between two adjacent DTI deep trenches 20 is the region where devices will be formed in the future.

[0077] Step S3, growth of ISSG SiO2 bottom layer of Liner: The ISSG process grows the ISSG SiO2 bottom layer to round the sharp top and bottom angles of the DTI deep trench. At the same time, the DTI deep trench etching damage is repaired by ISSG high temperature annealing, thereby reducing the additional high temperature annealing step.

[0078] like Figure 5 As shown, an ISSG SiO2 bottom layer 6 is grown on the upper surface of the DTI deep trench 20 and the Si3N4 barrier layer 5 by an ISSG process. The ISSG SiO2 bottom layer 6 is grown by an ISSG oxidation method with a volume ratio of H2:O2 of 1:(3-30) as the reaction gas, a reaction temperature of 1000°C-1200°C, a time of 20s-600s, and a thickness of

[0079] While the ISSG process is growing the ISSG SiO2 bottom layer 6, the sharp top and bottom angles of the DTI deep trench 20 are also rounded, reducing stress concentration and electric field concentration, and avoiding the thinning effect of the ISSG SiO2 bottom layer 6. The ISSG high temperature process also performs repair annealing on the etching damage of the DTI deep trench 20 to avoid silicon defects at the edge of the DTI deep trench 20, reducing additional high temperature annealing steps.

[0080] Step S4, SiN Liner x Top layer growth: LPCVD deposition of SiN x Top layer, SiN x The top layer has stronger insulation capability than SiO2, SiN x The top layer has tensile stress, which can reduce or even completely offset the accumulation of compressive stress in subsequent HARP SiO2 layers.

[0081] like Figure 6 As shown, the SiN Liner is deposited on the upper surface of the ISSG SiO2 bottom layer 6 by the LPCVD process. x Top layer 7. SiN x When the top layer 7 is deposited, the volume ratio of the reaction gas SiH2Cl2 to NH3 is 1:(0.3-10), the reaction temperature is 700℃-900℃, the pressure is 0.1Torr-5.0Torr, the time is 5min-40min, and the thickness is The volume ratio of SiH2Cl2 to NH3 can be adjusted to change the SiN x The Si content of the top layer 7, the larger the volume ratio of SiH2Cl2 to NH3, the higher the Si content.

[0082] S N x The dielectric constant of SiN is about twice that of SiO2. x The film has a higher breakdown voltage, i.e., dielectric strength, than SiO2 film of the same thickness.

[0083] LPCVD SiN x The stress is tensile stress. x The increase of Si content in SiN x The tensile stress of Si3N4 is from ~10 9 Pa is reduced to Si-rich SiN x ~10 8 Pa order of magnitude. However, the stress of the HARP SiO2 layer 8 after annealing is compressive stress. 8 Therefore, according to the measured data of HARP SiO2 layer compressive stress, the SiN x Medium Si content adjustment SiN xThe tensile stress of the top layer 7 is reduced, thereby reducing or even completely offsetting the accumulation of compressive stress in the HARP SiO2 layer 8 after subsequent annealing.

[0084] Step S5, DTI deep trench filling with a first HARP SiO2 layer: depositing the first HARP SiO2 layer by CVD process, and performing a first high temperature annealing after deposition to improve the compactness of the first HARP SiO2 layer and convert the tensile stress of the first HARP SiO2 layer after deposition into compressive stress after annealing.

[0085] like Figure 7 As shown, in SiN x The first HARP SiO2 layer 8a is deposited by CVD process on the upper surface of the top layer 7. During the HARP SiO2 deposition, the volume ratio of the reaction gas TEOS to O3 is 1:(3-20), the reaction temperature is 400°C-600°C, the chamber pressure is 500Torr-700Torr, the deposition time is 0.5min-2min, and the thickness is

[0086] After the first HARP SiO2 layer 8a is deposited, the first high temperature annealing is performed. The annealing can be performed by inert gas (N2, He or Ar) annealing or water vapor (H2O) annealing. The temperature is 800℃~1100℃ and the time is 5min~60min. The purpose of annealing is to densify the first HARP SiO2 layer 8a. At the same time, the first high temperature annealing densifies the first HARP SiO2 layer 8a after 10 8 The tensile stress of the order of Pa is transformed into -10 8 The compressive stress of the order of Pa avoids the possibility of the thicker first HARP SiO2 layer 8a peeling off due to excessive tensile stress.

[0087] Step S6, DTI deep trench filling with a second HARP SiO2 layer: deposit the second HARP SiO2 layer by CVD process, and perform a second high temperature annealing after deposition to improve the compactness of the second HARP SiO2 layer and convert the tensile stress of the second HARP SiO2 layer after deposition into compressive stress after annealing.

[0088] like Figure 8 As shown, a second HARP SiO2 layer 8b is deposited on the upper surface of the first HARP SiO2 layer 8a by CVD process. During the HARP SiO2 deposition, the volume ratio of the reaction gas TEOS to O3 is 1:(3-10), the reaction temperature is 400°C-600°C, the chamber pressure is 500Torr-700Torr, the deposition time is 0.5min-4min, and the thickness is

[0089] After the second HARP SiO2 layer 8b is deposited, a second high temperature annealing is performed. Annealing can be performed using an inert gas (N2, He or Ar) annealing or water vapor annealing. The temperature is 800°C to 1100°C and the time is 5min to 60min. The purpose of annealing is also to densify the second HARP SiO2 layer 8b. At the same time, the second high temperature annealing densifies the second HARP SiO2 layer 8b after 10 8 The tensile stress of the order of Pa also changes to -10 8 The compressive stress of the order of Pa prevents the possibility of the thicker second HARP SiO2 layer 8b peeling off due to excessive tensile stress, while the compressive stress of the first HARP SiO2 layer 8a remains basically unchanged. After annealing, the first HARP SiO2 layer 8a and the second HARP SiO2 layer 8b can be regarded as a HARP SiO2 layer 8 as a whole, with a total thickness of like Fig. 9 As shown. Finally, the compressive stress of the HARP SiO2 layer 8 can be compared with that of the SiN x The tensile stresses of the top layer 7 match each other or even completely cancel each other out, thus avoiding isolation leakage and device parameter drift caused by excessive stress in the DTI structure.

[0090] Step S7, filling the DTI deep trench with a polysilicon layer: the DTI deep trench is completely filled with a polysilicon layer by depositing a polysilicon layer by LPCVD, and the polysilicon layer also serves as a stress buffer layer for the HARP SiO2 layer.

[0091] like Fig.10 As shown, a polysilicon layer 9 is deposited on the upper surface of the HARP SiO2 layer 8 by LPCVD method, the reaction gas is SiH4, the temperature is 575℃~650℃, the pressure is 0.1Torr~5.0Torr, and the thickness is

[0092] Step S8, DTI CMP: Use CMP to grind away the polysilicon layer, HARP SiO2 layer, and SiN x Top layer / ISSG SiO2 bottom layer NO two-layer Liner and part of Si3N4 barrier layer, CMP finally stops on the remaining Si3N4 barrier layer.

[0093] The polysilicon layer 9, the HARP SiO2 layer 8, and the SiN x The top layer 7 / ISSG SiO2 bottom layer 6 has two NO liner layers and part of the Si3N4 barrier layer 5. During CMP, a certain amount of over-grinding is set, and the polysilicon layer 9, HARP SiO2 layer 8 and SiN xThe two NO liner layers of the top layer 7 / ISSG SiO2 bottom layer 6 will be polished away, and part of the Si3N4 barrier layer 5 will also be polished away. The CMP finally stops on the remaining Si3N4 barrier layer 5. The remaining Si3N4 barrier layer 5 is At the same time, since the Si3N4 barrier layer 5 has a higher hardness than the HARP SiO2 layer 8, the plane of the HARP SiO2 layer 8 will be lower than the Si3N4 barrier layer 5 after grinding, that is, a certain dishing is formed. The DTI morphology after DTI CMP is as follows: Fig.11 shown.

[0094] Step S9, complete stripping of Si3N4 barrier layer: first rinse off the SiO x N y , and then the remaining Si3N4 barrier layer is completely stripped to form a DTI structure.

[0095] SiO will form on the surface of Si3N4 barrier layer 5 x N y The natural oxide is removed by rinsing with 100:1HF (100H2O:149% HF) at a temperature of 22°C for 60s to 1200s. HF also thins the HARP SiO2 layer 8, thereby accurately controlling the height (STI height) of the HARP SiO2 layer 8 and the polysilicon layer 9 above the epitaxial layer 3.

[0096] The Si3N4 barrier layer 5 is completely stripped using H3PO4 etching solution at a temperature of 155°C to 170°C for 30min to 120min. The H3PO4 etching solution will corrode a portion of the SiO2 pad oxide 4, and the remaining SiO2 pad oxide 4 is It will be removed in the subsequent pre-oxidation rinsing process. Figure 1 The DTI structure shown.

[0097] In particular, for the structure and process of filling only the first HARP SiO2 layer 8a and the second HARP SiO2 layer 8b in the DTI deep trench 20 without filling the polysilicon layer 9, that is, only performing steps S5 and S6 without performing step S7, the first HARP SiO2 layer 8a is deposited for 1 min to 8 min and has a thickness of The deposition time of the second HARP SiO2 layer 8b is 1min to 12min, and the thickness is The total thickness of the HARP SiO2 layer 8 is In this case, the thickness of the HARP SiO2 layer 8 is very thick. If it is deposited once, it is easy to peel off due to tensile stress. Therefore, the HARP SiO2 layer is deposited twice and the tensile stress is converted into compressive stress through secondary annealing, which can effectively avoid the possibility of peeling of the HARP SiO2 layer due to excessive stress.

[0098] Example 1

[0099] Based on SiN x / SiO2 Liner 0.13μm BCD DTI process is as follows:

[0100] According to the known process, buried layer implantation, junction pushing and epitaxial growth are completed on the original silicon substrate, and the upper surface of the epitaxial growth is oxidized and grown. SiO2 pad oxide, LPCVD deposition Si3N4 barrier layer;

[0101] Active area photolithography, dry etching of DTI deep trenches with a width of 1.2μm and a depth of 20μm, and stripping after etching;

[0102] ISSG oxidation growth SiO2 is used as the bottom layer of Liner;

[0103] LPCVD deposition process S N x As the top layer of Liner;

[0104] CVD Deposition The first HARP SiO2 layer is used to fill the DTI deep trench;

[0105] After the HARP SiO2 layer is deposited, the first high temperature annealing is carried out in water vapor at a temperature of 1000°C for 20 min;

[0106] CVD deposition The second HARP SiO2 layer is used to fill the DTI deep trench;

[0107] After the HARP SiO2 layer is deposited, a second high temperature annealing is performed in water vapor at a temperature of 1000°C for 20 min;

[0108] LPCVD deposition The polysilicon layer fills the DTI deep trench;

[0109] DTI CMP, use CMP to grind away the polysilicon layer on the Si3N4 barrier layer, the HARP SiO2 layer and the SiN of the Liner x Top layer / ISSG SiO2 bottom layer, and grind off part of Si3N4 barrier layer, CMP finally stops at the remaining On Si3N4 barrier layer;

[0110] 100:1 HF rinse to remove SiO on the surface of Si3N4 barrier layer x N y , the time is 120s, because the HARP SiO2 layer is also lost by rinsing

[0111] H3PO4 corrosion liquid completely peels off the remaining Si3N4 barrier layer, time is 40min, the residual SiO2 pad thickness is (removed in the subsequent process), and finally formed a height higher than the epitaxial DTI.

[0112] Example 2

[0113] A method based on SiN provided in the first embodiment of the present application x / SiO2 Liner DTI structure and manufacturing method thereof, the second embodiment of the present application proposes another method based on SiN x / SiO2 Liner DTI structure and manufacturing method thereof The second embodiment is only a preferred embodiment of the first embodiment, and the implementation of the second embodiment will not affect the independent implementation of the first embodiment.

[0114] Based on SiN x / SiO2 Liner 0.25μm BCD DTI process is as follows:

[0115] According to the known process, buried layer implantation, junction pushing and epitaxial growth are completed on the original silicon substrate, and the upper surface of the epitaxial growth is oxidized and grown. SiO2 pad oxide, LPCVD deposition Si3N4 barrier layer;

[0116] Active area photolithography, dry etching of DTI deep trenches with a width of 2μm and a depth of 40μm, and stripping after etching;

[0117] ISSG oxidation growth SiO2 is used as the bottom layer of Liner;

[0118] LPCVD deposition process S N x As the top layer of Liner;

[0119] CVD deposition The first HARP SiO2 layer is used to fill the DTI deep trench;

[0120] After the HARP SiO2 layer is deposited, the first high temperature annealing is performed in an inert gas N2 at a temperature of 1000°C for 30 min;

[0121] CVD deposition The second HARP SiO2 layer is used to fill the DTI deep trench;

[0122] After the deposition of the HARP SiO2 layer, a second high temperature annealing was performed in an inert gas N2 at a temperature of 1000°C for 30 min;

[0123] DTI CMP, use CMP to grind away the HARP SiO2 layer on the Si3N4 barrier layer and the SiN of the Liner x Top layer / ISSGSiO2 bottom layer, and grind off part of Si3N4 barrier layer, CMP finally stops at the remaining On Si3N4 barrier layer;

[0124] 100:1 HF rinse to remove SiO on the surface of Si3N4 barrier layer x N y , time is 550s, because the HARP SiO2 layer is also lost by rinsing

[0125] H3PO4 corrosion liquid completely peels off the remaining Si3N4 barrier layer, time is 60min, the residual SiO2 pad thickness is (removed in the subsequent process), and finally formed a height higher than the epitaxial DTI.

[0126] The present invention proposes a method based on SiN x The DTI structure and manufacturing method of / SiO2 Liner have the following advantages:

[0127] 1) The ISSG-grown Liner ISSG SiO2 bottom layer improves the uniformity of the top and bottom corners of the DTI deep trench, avoids the drilling of the Si3N4 barrier layer during oxidation, better repairs the DTI deep trench etching damage, and reduces the additional high-temperature annealing steps;

[0128] 2) Liner SiN deposited by LPCVD process x The top layer has stronger insulation capability than SiO2, SiN x The tensile stress in the top layer can reduce or even completely offset the accumulation of compressive stress in subsequent thicker HARP SiO2 layers;

[0129] 3) Using two HARP SiO2 layers to fill can avoid the possibility of single-deposited HARP SiO2 layers being too thick and having too much tensile stress, which can lead to peeling; after the first high-temperature annealing, the stress of the first deposited HARP SiO2 layer becomes compressive stress, so the tensile stress of the two deposited HARP SiO2 layers will not accumulate; after the second high-temperature annealing, the stress of the two deposited HARP SiO2 layers is converted into compressive stress, which can be combined with SiN x The tensile stresses in the top layers match or even cancel each other out completely.

[0130] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A SiN-based x / SiO2 Liner's DTI structure is characterized by: include: A silicon substrate disposed at the bottom, a buried layer disposed on the top surface of the silicon substrate, an epitaxial layer grown from the silicon substrate, and a buried layer reverse extension disposed between the buried layer and the epitaxial layer; The U-shaped DTI deep trench is sequentially penetrated through the epitaxy, the buried layer reverse extension and the buried layer and extends to the silicon substrate, the ISSG SiO2 bottom layer of the liner, the SiN x The top layer and the HARP SiO2 layer are sequentially covered in the DTI deep trench.

2. A SiN-based x / SiO2 Liner's DTI structure is characterized by: The HARPSiO2 layer includes the SiN x The top layer is a first HARP SiO2 layer and a second HARP SiO2 layer.

3. A SiN-based method according to claim 1 x / SiO2 Liner's DTI structure is characterized by: The invention also includes a polysilicon layer for filling the DTI deep trench.

4. A SiN-based x The preparation method of the DTI structure of / SiO2 Liner comprises the following steps: Step S1, growth of SiO2 pad oxide and Si3N4 barrier layer: providing a silicon substrate disposed at the bottom, a buried layer disposed on the top surface of the silicon substrate, an epitaxial layer grown from the silicon substrate, and a buried layer reverse extension disposed between the buried layer and the epitaxial layer, oxidizing and growing SiO2 pad oxide on the epitaxial layer of the silicon substrate, and depositing a Si3N4 barrier layer by LPCVD; Step S2, DTI deep trench etching: The active area is defined by photolithography, the Si3N4 barrier layer is dry-etched, and then the DTI deep trench is etched on the surface of the silicon substrate through the SiO2 pad oxide and epitaxy, and the resist is removed after etching; Step S3, growth of the ISSG SiO2 bottom layer of the liner: The ISSG process grows the ISSG SiO2 bottom layer to round the sharp top and bottom corners of the DTI deep trench. At the same time, ISSG high-temperature annealing is performed to repair the DTI deep trench etching damage, thus reducing the need for additional high-temperature annealing steps. Step S4, SiN Liner x Top layer growth: LPCVD deposition of SiN x Top layer, SiN x The top layer has a stronger insulating ability than SiO2, SiN x The top layer has tensile stress, which can reduce or even completely offset the accumulation of compressive stress in subsequent HARP SiO2 layers; Step S5, filling the DTI deep trench with a first HARP SiO2 layer: depositing the first HARP SiO2 layer using a CVD process, and performing a first high-temperature annealing after deposition to improve the density of the first HARP SiO2 layer and convert the tensile stress of the first HARP SiO2 layer after deposition into compressive stress after annealing; Step S6, filling the DTI deep trench with a second HARP SiO2 layer: depositing the second HARP SiO2 layer using a CVD process, and performing a second high-temperature annealing after deposition to improve the density of the second HARP SiO2 layer and convert the tensile stress of the second HARP SiO2 layer after deposition into compressive stress after annealing; Step S7, filling the DTI deep trench with a polysilicon layer: depositing a polysilicon layer by LPCVD to completely fill the DTI deep trench, the polysilicon layer also serving as a stress buffer layer for the HARP SiO2 layer; Step S8, DTI CMP: Use CMP to grind away the polysilicon layer, HARP SiO2 layer, SiN x The top layer / ISSG SiO2 bottom layer has two NO liners and a partial Si3N4 barrier layer. The CMP finally stops on the remaining Si3N4 barrier layer. Step S9, complete stripping of the Si3N4 barrier layer: first rinse off the SiO2 on the surface of the Si3N4 barrier layer. x N y , and then the remaining Si3N4 barrier layer is completely stripped to form a DTI structure.

5. A SiN-based method according to claim 4 x / SiO2 Liner DTI structure preparation method, characterized in that, In step S2, the Si3N4 barrier layer is dry-etched, and then the SiO2 pad oxide and epitaxy are continued to be etched to form a DTI deep trench on the surface of the silicon substrate, including the following steps: In step S21, the Si3N4 barrier layer in the DTI deep trench region is etched. The main etching gases are CF4, CH3F and O2. The etching selectivity of Si3N4 to SiO2 is greater than 10:

1. The etching endpoint is selected to stay on the SiO2 pad oxygen. In step S22, a DTI deep trench is etched through the SiO2 pad oxygen and epitaxy on the surface of the silicon substrate. The main etching gases are Cl2, HBr and O2. The sidewall angle of the formed DTI deep trench is 85° to 90°, the width of the DTI deep trench is 0.4μm to 2.0μm, the depth is 10μm to 40μm, and the aspect ratio is (8 to 30):

1.

6. A SiN-based method according to claim 4 x / SiO2 Liner DTI structure preparation method, characterized in that, In step S3, the ISSG SiO2 bottom layer of the liner is grown by the ISSG process; The ISSG SiO2 bottom layer is grown by ISSG oxidation with a volume ratio of H2:O2 of 1:(3-30) at a reaction temperature of 1000℃-1200℃ and a time of 20s-600s. The thickness is 7. The SiN-based method according to claim 4 x / SiO2 Liner DTI structure preparation method, characterized in that, In step S4, the SiN Liner is deposited by LPCVD process. x Top floor; LPCVD process for depositing SiN x The volume ratio of the reaction gas SiH2Cl2 to NH3 is 1:(0.3~10) at the top layer, the reaction temperature is 700℃~900℃, the pressure is 0.1Torr~5.0Torr, the time is 5min~40min, and the thickness is 8. The SiN-based method according to claim 4 x / SiO2 Liner DTI structure preparation method, characterized in that, In steps S5 and S6, two HARP SiO2 layer depositions are performed to fill the DTI deep trenches, and two high-temperature anneals are performed to improve the density of the HARP SiO2 layer. When the HARP SiO2 layer is deposited, the volume ratio of the reaction gas TEOS to O3 is 1:(3-20), the reaction temperature is 400℃-600℃, the chamber pressure is 500Torr-700Torr, the deposition time of the first HARP SiO2 layer is 0.5min-2min, and the thickness is The deposition time of the second HARP SiO2 layer is 0.5min to 4min, and the thickness is High temperature annealing adopts inert gas (N2, He or Ar) annealing or water vapor (H2O) annealing, the temperature is 800℃~1100℃, and the time is 5min~60min.

9. The SiN-based method according to claim 4 x / SiO2 Liner DTI structure preparation method, characterized in that, In step S7, a polysilicon layer is deposited by LPCVD to completely fill the DTI deep trench. The polysilicon layer also serves as a stress buffer layer for the HARP SiO2 layer. The polysilicon layer is deposited with SiH4 as the reaction gas, the temperature is 575℃~650℃, the pressure is 0.1Torr~5.0Torr, and the thickness is 10. The SiN-based method according to claim 4 x / SiO2 Liner DTI structure preparation method, characterized in that, For the structure and process of filling only the first HARP SiO2 layer and the second HARP SiO2 layer in the DTI deep trench without filling the polysilicon layer, that is, only performing steps S5 and S6 without performing step S7, the deposition time of the first HARP SiO2 layer is 1min to 8min, and the thickness is The deposition time of the second HARP SiO2 layer is 1min to 12min, and the thickness is

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