Ultra-low power consumption and high-speed polycrystalline silicon fuse erasable programmable read-only memory

Abstract

One example includes an integrated circuit (100) having a sense amplifier (105) including: a first inverter (110) having a first positive power supply terminal, a first input, and a first output; and a second inverter (115) having a second positive power supply terminal, a second input connected to the first output, and a second output connected to the first input. The integrated circuit also includes a reference resistor (Rref) connected between a positive voltage rail (VDD) and the second positive power supply terminal. A fuse (120) is connected between the positive voltage rail and the first positive power supply terminal.

Description

[0001] The present disclosure relates to the field of semiconductor devices and, more particularly, but not exclusively, to memory cells. Background Art

[0002] Electrically programmable memory cells are used in many contexts, including trimming various analog circuits to account for manufacturing variations. Such cells consume valuable space on the IC die and can cause reliability issues. Summary of the invention

[0003] One example includes an integrated circuit having a sense amplifier including: a first inverter having a first positive power supply terminal, a first input, and a first output; and a second inverter having a second positive power supply terminal, a second input connected to the first output, and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power supply terminal. A fuse is connected between the positive voltage rail and the first positive power supply terminal.

[0004] Another example provides a method of forming an integrated circuit. A first inverter and a second inverter are formed extending into a semiconductor substrate. A fuse and a resistor are formed above the semiconductor substrate. The fuse is connected between an upper power rail and a positive power terminal of the first inverter. The resistor is connected between the upper power rail and a positive power terminal of the second inverter. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter.

[0005] Yet another example provides an integrated circuit. The integrated circuit includes a first NMOS transistor and a first PMOS transistor, the first NMOS transistor and the first PMOS transistor are formed above a semiconductor substrate and are connected to form a first inverter having a first input node and a first output node. The integrated circuit also includes a second NMOS transistor and a second PMOS transistor, the second NMOS transistor and the second PMOS transistor are formed above the semiconductor substrate and are connected to form a second inverter having a second input node and a second output node. The first output node is connected to the second input node, and the second output node is connected to the first input node. A reference resistor is connected between a positive voltage rail and a source of the first PMOS transistor, and a fuse is connected between the positive voltage rail and the source of the second PMOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A fuse memory cell circuit according to the present disclosure is shown;

[0007] Figure 2 Shown with additional components such as Figure 1 A fuse memory cell circuit of the fuse memory cell circuit shown in;

[0008] Figure 3 Presentation Figure 1 and 2 A timing diagram of operational aspects of a fused memory cell circuit;

[0009] Figure 4 Show for example Figure 2 A fuse memory cell circuit of the fuse memory cell circuit shown in , comprising a current sink connected to a fuse and a reference resistor;

[0010] Figure 5 Show for example Figure 2 An implementation of a fused memory cell circuit of the fused memory cell circuit shown in on a semiconductor die;

[0011] Figure 6 Show for example Figure 5 an array of fused memory cell circuits of the fused memory cell circuit shown in; and

[0012] Figure 7 Methods of forming integrated circuits according to various examples are shown. DETAILED DESCRIPTION

[0013] The present disclosure is described with reference to the accompanying drawings. The figures may not be drawn to scale, and the figures are provided only to illustrate the present disclosure. Several aspects of the present disclosure are described below with reference to example applications for illustration, wherein similar features correspond to similar figure numerals. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the order in which actions or events are shown, because some actions may occur in different orders and / or may occur simultaneously with other actions or events. In addition, implementation of the method according to the present disclosure may not require all of the actions or events shown.

[0014] The present application discloses various methods and apparatus that can be beneficially applied to integrated circuits (ICs), such as those including electrically programmable fuse memory cells, for example, by reducing quiescent current and providing short read times. Although such embodiments can be expected to provide improvements, such as reducing overall IC power consumption requirements, no particular result is a requirement of the described invention unless expressly recited in a particular claim.

[0015] refer to Figure 1, schematically illustrating an electrically programmable memory cell 100. The memory cell 100 includes a sense amplifier 105, which includes a latch having a first inverter 110 and a second inverter 115. The inverters 110, 115 are cross-coupled in a manner that can store bit values ​​in a quasi-static manner. For ease of description, the output of the inverter 115 is designated as the "D node", and the output of the inverter 110 is designated as the inverse of the D node or the "DZ node". The inverters 110, 115 and the other components of the memory cell 100 are configured in a left-right symmetrical manner. The "left leg" of the memory cell 100 includes a PMOS transistor MPSWL, which has a source connected to the fuse 120 and a drain connected to the positive power supply terminal of the inverter 110. The NMOS transistor MNSWL has a drain connected to the D node and a source connected to the lower power supply rail designated as VSS. Similarly, the "right leg" includes a PMOS transistor MPSWR, which has a drain connected to R ref The NMOS transistor MNSWR has a drain connected to the DZ node and a source connected to the positive power supply terminal of the inverter 115. During the positive phase of the CLKZ signal, the transistor MNSWL conductively connects the D node to VSS, and the transistor MNSWR conductively connects the DZ node to VSS. During the negative phase of CLKZ, the transistor MPSWL conductively connects the positive power supply terminal of the inverter 110 to the fuse 120, and the transistor MPSWR conductively connects the positive power supply terminal of the inverter 115 to the R ref .

[0016] The negative supply terminals of inverters 110 and 115 are connected to the lower supply rail in a non-switching manner. Conversely, inverter 110 is connected to the upper supply rail designated as VDD via transistor MPSWL and fuse 120, and inverter 115 is connected to the upper supply rail designated as VDD via transistor MPSWR and V ref The transistor MPSWL is directly connected to the first terminal of the fuse 120, and the transistor MPSWR is directly connected to the reference resistor R ref The second terminal of the fuse 120 and R ref The second terminals of both are connected to VDD.

[0017] Fuse 120 can be formed of any material that can be patterned to form a current path that can be selectively broken to produce a high resistance state between the first fuse terminal and the second fuse terminal. In various examples, and as described without implying limitation, fuse 120 is formed of polysilicon. In various examples, fuse 120 has an "hourglass" or "dog bone" shape in which a wide terminal portion having a relatively low resistance is initially connected by a narrow conductive path having an initial resistance. Sufficiently high current that produces a commensurately high current density can damage a portion of the narrow conductive path, thereby producing a programmed resistance that is generally much greater than the initial resistance. For example, fuse 120 may have a resistance R fuse , the resistance has an initial, unprogrammed value of approximately 100Ω and a programmed value of greater than 50kΩ.

[0018] Reference resistor R ref has a resistance greater than the unprogrammed resistance of fuse 120 and less than the programmed resistance of fuse 120. In one example, R ref can be R in the programmed state fuse In various examples, R is about one-half of the minimum expected value of R, such as 25 kΩ. ref Significantly greater, e.g., >100-fold.

[0019] In the non-read or quiescent state, CLK is not asserted, causing MNSWL and MNSWR to be turned on and pulling the D and DZ nodes to VSS. In the read state, CLK is asserted, allowing D and DZ to settle to the active state. This situation results in insignificant power consumption through the memory cell 100. The value of the D node in the active state is determined by R fuse and R ref As described in more detail below, if R fuse <R ref , for example, in an unprogrammed state, the D node will stabilize to an unasserted value, such as a digital "0" or FALSE state, and the DZ node will stabilize to an asserted value, such as a digital "1" or TRUE state. Conversely, if R fuse >R ref , for example, in the programmed state, the D node will stabilize to the TRUE state, and the DZ node will stabilize to the FALSE state. After stabilizing in the active state, the memory cell 100 consumes insignificant power.

[0020] Figure 2An example of a memory cell 200 is shown in which the inverter 110 is implemented by a PMOS transistor MPSAL and an NMOS transistor MNSAL, and the inverter 115 is implemented by a PMOS transistor MPSAR and an NMOS transistor MNSAR. MPSAL and MNSAL are connected at a first output node serving as a DZ node, and MPSAR and MNSAR are connected at a second output node serving as a D node. The gate terminals of MPSAL and MNSAL are connected at a first input node connected to the D node, and the gate terminals of MPSAR and MNSAR are connected at a second input node connected to the DZ node.

[0021] As previously described, in the quiescent state (e.g., CLK=FALSE and CLKZ=TRUE), transistors MNSWL and MNSWR are turned on, holding the D and DZ node values ​​to VSS. In the read state (e.g., CLK=TRUE and CLKZ=FALSE), MNSWL and MNSWR are turned off and MPSWL and MPSWR are turned on. Immediately after transitioning from the quiescent state to the active state, MPSAL and MPSAR are turned on, and MNSAL and MNSAR are turned off due to the immediately preceding VSS state of the D and DZ nodes. The state in which the D and DZ nodes are stable is determined by the race between the left leg and the right leg. The combined resistance and capacitance of the components in the left leg produce a first time constant τ L , the first time constant determines the rate at which the voltage of the DZ node increases from VSS, and the combined resistance and capacitance of the components in the right leg produce a second time constant τ R , the second time constant determines the rate at which the voltage at the D node increases from VSS. If τ L <τ R (unprogrammed state), then DZ increases to a value sufficient to turn on MNSAR, after which D can increase to a value sufficient to turn on MNSAL, and the D and DZ nodes stabilize to values ​​0 and 1, respectively. On the other hand, if τ L >τ R (programmed state), then D increases to a value sufficient to turn on MNSAL, after which DZ can increase to a value sufficient to turn on MNSAR, and nodes D and DZ settle to values ​​1 and 0, respectively.

[0022] Read operation in Figure 3 As illustrated in the figure, the figure shows the fuse =100Ω(unprogrammed) and R ref =25 kΩ Example Simulated voltage and current values ​​at various nodes of memory cell 100 with respect to time t. Before t=250 ns, CLK is not asserted (CLKZ is asserted), through fuse 120 and R refBoth currents are zero, and the voltages at the D and DZ nodes are zero. CLK is asserted at t=250ns, which produces a peak current of about 55 μA through fuse 120 and through reference resistor R ref Initially, the voltages at the D and DZ nodes increase at approximately the same rate, but within 2 to 3 ns, the voltage at the DZ node exceeds the voltage at the D node, and the state of the memory cell 100 stabilizes in the unprogrammed state. When the state of the memory cell 100 stabilizes, the memory cell 100 is switched to the unprogrammed state through the fuse 120 and R ref Therefore, it can be seen that the quiescent current is very low, such as ≤75nA, and the read time is very short, such as <17ns.

[0023] It should be noted that Figure 3 The voltages shown in are merely provided as an example and are not meant to be limiting. In this example, the circuit uses 5V transistors and operates between 0.9V and 5.5V, where 0.9V is determined by the threshold voltage of the transistors and 5.5V is determined to be the reliable operating limit of the 5V transistors. In some other examples, the voltage operating range may be extended, for example, by using low threshold voltage (LVT) devices.

[0024] Back to Figure 2 , in various examples, transistors MPSWL and MPSWR are matched, e.g., have approximately the same (within manufacturing tolerances) resistance and capacitance. For example, each of these transistors may have the same gate length (or channel length) and the same gate width (or drive current). Similarly, in various examples, MPSAL and MPSAR are matched, and MNSAL and MNSAR are matched. In some examples, all transistors in memory cell 100 are closely spaced on a semiconductor substrate so that manufacturing variations between matched transistors are negligible.

[0025] Other components of memory cell 200 include transistors MNBLOW and MNDUMMY. In a programming operation, MNBLOW is switched by the asserted PROG signal and is used to sink current through fuse 120 if in an unprogrammed state. The drive current capacity of MNBLOW is selected to support enough current to damage the narrow conductive path of fuse 120, thereby increasing the resistance from an unprogrammed value to a programmed value. The connection of MNBLOW to fuse 120 can increase the capacitance associated with the left leg of memory cell 100 and, without compensation, result in a change in the timing of operation during the previously described stabilization period. In some examples, MNDUMMY is a dummy transistor matched to the MNBLOW transistor to provide such compensation. In such examples, the source and drain of MNDUMMY are connected, so this transistor does not provide active electrical function.

[0026] In an additional example, a shunt resistor R0 is connected to the terminals of the fuse 120 to inhibit the growth of a low resistance path between the terminals after the fuse 120 is blown. In the absence of a shunt resistor, such regeneration may be caused by an electric field between the terminals. In various examples, R0 has a resistance of at least two times the predetermined minimum resistance of the fuse 120 in the programmed state. Where space permits, it may be desirable for R0 to have a resistance of at least ten times the predetermined minimum resistance of the fuse 120 in the programmed state, for example, about 500 kΩ.

[0027] Figure 4 The first bias current sink 410 is shown connected to the fuse 120 and the second bias current sink 420 is connected to R ref 1. This configuration can be used to test the operating margin of the memory cell 100 after programming the fuse 120. In one example, the minimum desired resistance of the fuse 120 after programming can be predetermined to be 50 kΩ. ref In an example having a value of 25 kΩ, the second bias current sink 420 may be configured to pass R ref Absorption bias current I ref , the bias current is the bias current I drawn by the first bias current sink 410 bias This configuration can be used to test the operating margin of the memory cell 100 after programming the fuse 120. In another example, the minimum desired resistance of the fuse 120 after programming can be predetermined to be 100 kΩ, in which case I ref Can be I bias Four times. ref Configured as I bias Multiples of this will allow R ref is less than the minimum desired resistance of the fuse in the programmed state, thereby reducing the implementation of R ref The required die area. ref When it is small, I ref Can be increased to cross R ref The desired voltage drop is generated, thereby increasing the current sink 420 and / or to R ref The size of the interconnected components, or even damage to R ref Therefore, in various instances, I ref with I bias The minimum ratio can be 2 to limit the size of such components.

[0028] When CLK is not asserted and current sinks 410, 420 are operated, a voltage V is generated at the node between fuse 120 and transistor MPSWL. fuse Similarly, in R refA voltage V is generated at the node between the transistor MPSWR ref In R ref With a value of 25kΩ and I ref =4*I fuse In the example condition, if V fuse <V ref , then R fuse can be inferred to be greater than 100kΩ. Conversely, if V fuse >V ref , then R fuse A predetermined minimum value of less than 100 kΩ may be inferred. In response to this condition that the desired margin specification may not be met, the IC implementing the memory cell 100 may be discarded.

[0029] The described principle can be generalized so that the second bias current sink 420 is configured so that I ref Than I bias n times larger. fuse =n*R ref or in R ref =25kΩ, R fuse =n*25kΩ, V fuse will be equal to V ref In addition, in general, the ratio I ref / I bias Does not need to be an integer value.

[0030] The current sinks 410, 420 may be provided by current sinks integrated into the IC, or may be provided external to the IC, such as in a multi-probe test configuration. When integrated into the IC, the current sinks 410, 420 provide the ability to determine whether the resistance of the fuse 120 meets a predetermined operating margin independent of an external tester, including after deployment in an electronic system. On the other hand, if one or both of the current sinks 410, 420 are provided externally, then I bias and / or I ref can be varied as desired to determine any operating margin ratio, and multiple test measurements can be performed to determine, for example, R fuse The actual value of .

[0031] Figure 5 Memory cell 500 is shown implemented on silicon substrate 501 in various examples. Various designations of features of memory cell 500 may correspond to features previously described. Memory cell 500 includes fuse structure 505 and shunt resistor 510, which are respectively composed of Figure 2 The fuse 120 and the shunt resistor R0 are exemplified. Figure 2 The resistor R refThe illustrated reference resistor 515 is located below the shunt resistor 510. The fuse structure 505 may be at least partially formed in a polysilicon layer or a metal interconnect layer above the substrate 501. The resistors 510 and 515 may be formed in a polysilicon layer above the substrate 501, or in a diffusion region extending into the substrate 501. The transistors 520 and 525 are illustrated. Figure 2 MNSAR and MNSAL of transistors 530 and 535 are exemplified Figure 2 MNSAR and MNSAL of transistors; transistors 540 and 545 are exemplified Figure 2 and transistors 550 and 555 are exemplified Figure 2 Each of transistors 520, 525, 530, 535, 540, 545, 550, and 555 may be formed over and into substrate 501 by any currently or future discovered method. In various examples, transistors 520 and 525 are matched, transistors 530 and 535 are matched, transistors 540 and 545 are matched, and / or transistors 550 and 555 are matched. Logic functions 560 related to other operating characteristics of memory cell 500 are located between fuse structure 505 and resistors 510, 515 and transistors 520...555.

[0032] Figure 6 An array 600 of memory cells 500 that may be formed in an integrated circuit is shown. Any number of memory cells 500 may be formed over and extending into a semiconductor substrate 601. In the example shown, a plurality (e.g., 16) of memory cells 500 are formed into a two-dimensional array. In other examples, the array of memory cells 500 may be one-dimensional, or may be arbitrarily located within the integrated circuit design.

[0033] Figure 7 A method 700 of forming an integrated circuit as described in the present disclosure is described. In step 710, a first inverter and a second inverter are formed to extend into a semiconductor substrate. The first inverter has a first positive power supply terminal, a first output at a first output node, and a first input node. The second inverter has a second positive power supply terminal, a second output at a second output node, and a second input node.

[0034] In step 720 , fuses and resistors are formed over a semiconductor substrate.

[0035] In step 730, a fuse is connected between the upper power rail and a first positive power terminal of the first inverter.

[0036] In step 740, a resistor is connected between the upper power rail and a second positive power terminal of the second inverter.

[0037] In step 750, the output node of the first inverter is connected to the input node of the second inverter, and the output node of the second inverter is connected to the input node of the first inverter.

[0038] In step 760, a first switch is connected between the fuse and the positive power supply terminal of the first inverter, and a second switch is connected between the resistor and the positive power supply terminal of the second inverter.

[0039] In step 770, a third switch is connected between the output node of the first inverter and the lower power rail, and a fourth switch is connected between the output node of the second inverter and the lower power rail. The first switch and the second switch are configured to provide a low resistance during a first phase of the control signal, and the third switch and the fourth switch are configured to provide a low resistance during a second phase of the control signal.

[0040] In step 780, a fifth switch is connected between the fuse and the negative power rail, and a sixth switch is connected to a reference resistor. The fifth switch is configured to provide a low resistance in response to a programming signal.

[0041] Although various embodiments of the present disclosure have been described above, it should be understood that they are presented only as examples and not as limitations. Many changes may be made to the disclosed embodiments according to the disclosure herein without departing from the spirit or scope of the present disclosure. Therefore, the breadth and scope of the present invention should not be limited by any of the above embodiments. Instead, the scope of the present disclosure should be limited according to the following claims and their equivalents.

Claims

1. An integrated circuit, comprising: A sense amplifier comprising: A first inverter having a first positive power supply terminal, a first input terminal and a first output terminal; and a second inverter having a second positive power supply terminal, a second input terminal connected to the first output terminal, and a second output terminal connected to the first input terminal; a reference resistor connected between the positive voltage rail and the second positive power supply terminal; as well as A fuse is connected between the positive voltage rail and the first positive power supply terminal.

2. The integrated circuit of claim 1, further comprising a programming transistor connected to the fuse and a dummy transistor connected to the reference resistor.

3. The integrated circuit of claim 1, further comprising a shunt resistor connected in parallel with the fuse.

4. The integrated circuit of claim 1, further comprising a first switching transistor connected between the fuse and the first positive power supply terminal, and a second switching transistor connected between the reference resistor and the second positive power supply terminal.

5. The integrated circuit of claim 4, further comprising a third switch transistor connected between the first output terminal and a lower voltage rail, and a fourth switch transistor connected between the second output terminal and the lower voltage rail. 6 . The integrated circuit of claim 1 , wherein under a condition that a resistance of the fuse is greater than a resistance of the reference resistor, the first output terminal is configured to stabilize to a FALSE state, and the second output terminal is configured to stabilize to a TRUE state.

7. The integrated circuit of claim 1, wherein the fuse is a polysilicon fuse.

8. The integrated circuit of claim 1, further comprising a current sink connected to the fuse.

9. The integrated circuit of claim 8, wherein the current sink is a first current sink, and the integrated circuit further comprises a second current sink connected to the reference resistor.

10. The integrated circuit of claim 9, wherein the first current sink is configured to generate a first current and the second current sink is configured to generate a second current that is at least twice the first current.

11. A method of forming an integrated circuit, comprising: forming a first inverter and a second inverter extending into the semiconductor substrate; forming fuses and resistors over the semiconductor substrate; connecting the fuse between an upper power rail and a positive power terminal of the first inverter; connecting the resistor between the upper power rail and a positive power terminal of the second inverter; and The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first inverter.

12. The method of claim 11, further comprising connecting a shunt resistor in parallel with the fuse between the positive power supply terminal of the first inverter.

13. The method of claim 11, further comprising connecting a first transistor between the fuse and the positive power supply terminal of the first inverter, and connecting a second transistor between the resistor and the positive power supply terminal of the second inverter. 14 . The method of claim 13 , wherein the output of the second inverter is configured to stabilize to a TRUE state under the condition that the first transistor and the second transistor are in a low resistance state and a resistance of the fuse is greater than a resistance of the resistor.

15. The method of claim 11, wherein the first inverter and the second inverter are each implemented by a respective PMOS transistor and a respective NMOS transistor. The method of claim 11 , wherein the fuse is a polysilicon fuse.

17. The method of claim 11, further comprising connecting a programming transistor to the fuse.

18. The method of claim 17, further comprising connecting a dummy transistor to the resistor, the dummy transistor matching the programming transistor.

19. The method of claim 11, further comprising connecting a first current sink configured to generate a first current to the fuse, and connecting a second current sink configured to generate a second current to the resistor, the second current being at least twice the first current.

20. An integrated circuit comprising: A first NMOS transistor and a first PMOS transistor formed over a semiconductor substrate, the first NMOS transistor and the first PMOS transistor being connected to form a first inverter having a first input node and a first output node; a second NMOS transistor and a second PMOS transistor formed over the semiconductor substrate, the second NMOS transistor and the second PMOS transistor being connected to form a second inverter having a second input node and a second output node, the first output node being connected to the second input node, and the second output node being connected to the first input node; and a reference resistor connected between the positive voltage rail and the source of the first PMOS transistor; and A fuse is connected between the positive voltage rail and a source of the second PMOS transistor.

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