Memory, storage system, and operating method of memory

Abstract

The application discloses a memory, a storage system and an operating method of the memory, and belongs to the technical field of storage. In the method, an operation instruction from a controller is received, and a plurality of initial word line identifiers in the operation instruction are mapped into a plurality of physical word line identifiers; an operation corresponding to the operation instruction is performed on a plurality of first type storage unit rows through a plurality of first type word lines indicated by the plurality of physical word line identifiers; wherein at least one third type storage unit row is distributed between a first storage unit row and a second storage unit row in the plurality of first type storage unit rows, and data stored in the plurality of first type storage unit rows corresponds to a same check data. Through the method, a plurality of data corresponding to the same check data can be written into discontinuous storage unit rows. In this way, the data stored in adjacent storage unit rows can be respectively corrected through at least two check data, so that the data protection capability is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a storage system, and a method of operating the memory. Background Technology

[0002] When writing data to memory such as 3D NAND (NAND gate), checksum data can be generated based on the written data to prevent errors in subsequent data reads. This way, when data is read from the memory, it is verified against the checksum data. If the verification fails, the correct data can be recovered from the checksum data. Ensuring successful data recovery in the event of verification failure is currently a hot research topic. Summary of the Invention

[0003] This application provides a memory, a memory system, and a method for operating the memory, which can be used to improve data protection capabilities. The technical solution is as follows:

[0004] On one hand, a memory is provided, the memory comprising:

[0005] A storage array comprising multiple rows of storage cells;

[0006] Multiple word lines, each word line being coupled to one of the multiple rows of memory cells; and

[0007] Peripheral circuitry, coupled to the plurality of word lines and configured as follows:

[0008] Receive an operation command from the controller, the operation command carrying multiple initial word line identifiers;

[0009] Map the plurality of initial word line identifiers to a plurality of physical word line identifiers;

[0010] The operation corresponding to the operation instruction is executed on multiple first-type memory cells through multiple first-type word lines indicated by the multiple physical word line identifiers;

[0011] Among them, at least one third type of storage unit row is distributed between the first storage unit row and the second storage unit row in the plurality of first type of storage unit rows, and the data stored in the plurality of first type of storage unit rows corresponds to the same verification data.

[0012] Optionally, the peripheral circuit is configured as follows:

[0013] Each initial word line identifier among the plurality of initial word line identifiers is treated as a pseudo word line identifier, and the physical word line identifier corresponding to each initial word line identifier is obtained from the stored mapping relationship between pseudo word line identifiers and physical word line identifiers.

[0014] Optionally, the mapping relationship includes the mapping relationship between the first pseudo-word line identifier and the first physical word line identifier, and the mapping relationship between the second pseudo-word line identifier and the second physical word line identifier;

[0015] The two memory cell rows coupled to the two word lines indicated by the first pseudo-word line identifier and the second pseudo-word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical identifier.

[0016] Optionally, the first pseudo-character line is identified as the first pseudo-character line number, the second pseudo-character line is identified as the second pseudo-character line number, and the difference between the first pseudo-character line number and the second pseudo-character line number is 1;

[0017] The first physical word line is identified as the first physical word line number, the second physical word line is identified as the second physical word line number, and the difference between the first physical word line number and the second physical word line number is greater than 1.

[0018] Optionally, the number of the first pseudo-character line is less than the number of the second pseudo-character line;

[0019] The second physical word line number is the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

[0020] Optionally, at least one third type of storage cell row is distributed between each pair of adjacent first type storage cell rows.

[0021] Optionally, the number of third-type storage cell rows distributed between each pair of adjacent storage cell rows in the plurality of first-type storage cell rows is a reference number.

[0022] Optionally, the peripheral circuit is configured as follows:

[0023] If a word line mapping instruction is received from the controller, the operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers is performed.

[0024] Optionally, the peripheral circuit is further configured as follows:

[0025] If no word line mapping instruction is received from the controller, the operation corresponding to the operation instruction is performed on multiple second-type memory cell rows through multiple second-type word lines indicated by the multiple initial word line identifiers;

[0026] The plurality of second-type storage cell rows are consecutive rows of storage cells in the storage array, and the data stored in the plurality of second-type storage cell rows corresponds to the same verification data.

[0027] Optionally, the operation instruction includes a write instruction, which further carries multiple data to be written that correspond one-to-one with the multiple initial word line identifiers;

[0028] The peripheral circuit is configured as follows:

[0029] The data to be written corresponding to each initial word line identifier is taken as the data to be written corresponding to the corresponding physical word line identifier, and programming operations are performed on the multiple first-type storage cell rows through the multiple first-type word lines to store the multiple data to be written into the multiple first-type storage cell rows.

[0030] Optionally, the operation instructions include read instructions;

[0031] The peripheral circuit is configured as follows:

[0032] Read operations are performed on the multiple first-class word lines to obtain the data stored in the multiple first-class storage cell rows respectively.

[0033] Optionally, the peripheral circuit is further configured as follows:

[0034] If the data stored in a third storage cell row among the plurality of first-class storage cell rows is erroneous, then an initial word line identifier corresponding to the physical word line identifier of the third storage cell row is determined;

[0035] The verification data is obtained based on the determined initial word line identifier;

[0036] The data stored in the third storage unit row is corrected based on the verification data.

[0037] On the other hand, a storage system is provided, the storage system including a memory and a controller coupled to the memory and configured to control the memory;

[0038] The controller is configured to send the operation instruction to the memory, the operation instruction carrying multiple initial word line identifiers;

[0039] The memory is configured to: receive the operation instruction, map the plurality of initial word line identifiers to a plurality of physical word line identifiers; and execute the operation corresponding to the operation instruction on a plurality of first-type memory cells through the plurality of first-type word lines indicated by the plurality of physical word line identifiers.

[0040] Among them, at least one third type of storage unit row is distributed between the first storage unit row and the second storage unit row in the plurality of first type of storage unit rows, and the data stored in the plurality of first type of storage unit rows corresponds to the same verification data.

[0041] Optionally, the controller is further configured to send a word line mapping instruction to the memory;

[0042] The memory is also configured to: in response to the word line mapping instruction, perform an operation to map the plurality of initial word line identifiers to the plurality of physical word line identifiers.

[0043] Optionally, the controller is further configured to: not send the word line mapping instruction to the memory;

[0044] The memory is further configured to perform the operation corresponding to the operation instruction on a plurality of second-type memory cell rows through a plurality of second-type word lines indicated by the plurality of initial word line identifiers;

[0045] The plurality of second-type storage cell rows are consecutive rows of storage cells in the storage array, and the data stored in the plurality of second-type storage cell rows corresponds to the same verification data.

[0046] Optionally, the operation instruction includes a write instruction, which further carries multiple data to be written that correspond one-to-one with the multiple initial word line identifiers;

[0047] The memory is configured to: treat the data to be written corresponding to each initial word line identifier as the data to be written corresponding to the corresponding physical word line identifier, and perform programming operations on the multiple first-type memory cell rows through the multiple first-type word lines to store the multiple data to be written into the multiple first-type memory cell rows.

[0048] Optionally, the operation instructions include read instructions;

[0049] The memory is configured to perform read operations on the plurality of first-type memory cell rows through the plurality of first-type word lines to obtain the data stored in the plurality of first-type memory cell rows respectively;

[0050] The memory is further configured to send a read data result to the controller, the read data result carrying data stored in the plurality of first-type memory cell rows respectively;

[0051] The controller is configured to receive the read data result.

[0052] On the other hand, a method for operating a memory is provided, the method comprising:

[0053] Receive an operation command from the controller, the operation command carrying multiple initial word line identifiers;

[0054] Map the plurality of initial word line identifiers to a plurality of physical word line identifiers;

[0055] The operation corresponding to the operation instruction is executed on multiple first-type memory cells through multiple first-type word lines indicated by the multiple physical word line identifiers;

[0056] Among them, at least one third type of storage unit row is distributed between the first storage unit row and the second storage unit row in the plurality of first type of storage unit rows, and the data stored in the plurality of first type of storage unit rows corresponds to the same verification data.

[0057] Optionally, mapping the plurality of initial word line identifiers to a plurality of physical word line identifiers includes:

[0058] Each initial word line identifier among the plurality of initial word line identifiers is treated as a pseudo word line identifier, and the physical word line identifier corresponding to each initial word line identifier is obtained from the stored mapping relationship between pseudo word line identifiers and physical word line identifiers.

[0059] Optionally, the mapping relationship includes the mapping relationship between the first pseudo-word line identifier and the first physical word line identifier, and the mapping relationship between the second pseudo-word line identifier and the second physical word line identifier;

[0060] The two memory cell rows coupled to the two word lines indicated by the first pseudo-word line identifier and the second pseudo-word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical identifier.

[0061] Optionally, the first pseudo-character line is identified as the first pseudo-character line number, the second pseudo-character line is identified as the second pseudo-character line number, and the difference between the first pseudo-character line number and the second pseudo-character line number is 1;

[0062] The first physical word line is identified as the first physical word line number, the second physical word line is identified as the second physical word line number, and the difference between the first physical word line number and the second physical word line number is greater than 1.

[0063] Optionally, the number of the first pseudo-character line is less than the number of the second pseudo-character line;

[0064] The second physical word line number is the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

[0065] Optionally, at least one third type of storage cell row is distributed between each pair of adjacent first type storage cell rows.

[0066] Optionally, the number of third-type storage cell rows distributed between each pair of adjacent storage cell rows in the plurality of first-type storage cell rows is a reference number.

[0067] Optionally, mapping the plurality of initial word line identifiers to a plurality of physical word line identifiers includes:

[0068] If a word line mapping instruction is received from the controller, the operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers is performed.

[0069] Optionally, the method further includes:

[0070] If no word line mapping instruction is received from the controller, the operation corresponding to the operation instruction is performed on multiple second-type memory cell rows through multiple second-type word lines indicated by the multiple initial word line identifiers;

[0071] The plurality of second-type storage cell rows are consecutive rows of storage cells in the storage array, and the data stored in the plurality of second-type storage cell rows corresponds to the same verification data.

[0072] Optionally, the operation instruction includes a write instruction, which further carries multiple data to be written that correspond one-to-one with the multiple initial word line identifiers;

[0073] The operation corresponding to the operation instruction is executed on multiple first-type memory cells through multiple first-type word lines indicated by the multiple physical word line identifiers, including:

[0074] The data to be written corresponding to each initial word line identifier is taken as the data to be written corresponding to the corresponding physical word line identifier, and programming operations are performed on the multiple first-type storage cell rows through the multiple first-type word lines to store the multiple data to be written into the multiple first-type storage cell rows.

[0075] Optionally, the operation instructions include read instructions;

[0076] The operation corresponding to the operation instruction is executed on multiple first-type memory cells through multiple first-type word lines indicated by the multiple physical word line identifiers, including:

[0077] Read operations are performed on the multiple first-class word lines to obtain the data stored in the multiple first-class storage cell rows respectively.

[0078] Optionally, the method further includes:

[0079] If the data stored in a third storage cell row among the plurality of first-class storage cell rows is erroneous, then an initial word line identifier corresponding to the physical word line identifier of the third storage cell row is determined;

[0080] The verification data is obtained based on the determined initial word line identifier;

[0081] The data stored in the third storage unit row is corrected based on the verification data.

[0082] In this embodiment, since at least one third type of storage cell row is distributed between the first and second storage cell rows in a plurality of first type storage cell rows, and the data stored in the plurality of first type storage cell rows corresponds to the same check data, the method provided in this embodiment can write multiple data corresponding to the same check data into non-contiguous storage cell rows. This allows adjacent storage cell rows in the storage array to store data corresponding to different check data. Thus, even if adjacent storage cell rows are too close together and their charges interfere with each other, causing the data stored in adjacent storage cell rows to err simultaneously, since the data stored in adjacent storage cell rows corresponds to different check data, the data stored in adjacent storage cell rows can be corrected separately using at least two check data, thereby improving data protection capabilities. Attached Figure Description

[0083] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0084] Figure 1 This is a schematic diagram of a storage system 10 provided in an embodiment of this application;

[0085] Figure 2 This is a schematic diagram of a storage device provided in an embodiment of this application;

[0086] Figure 3 This is a schematic diagram of another storage device provided in an embodiment of this application;

[0087] Figure 4 This is a schematic diagram of a memory 100 provided in an embodiment of this application;

[0088] Figure 5 This is a cross-sectional schematic diagram of a storage array 110 including storage strings 111 provided in an embodiment of this application;

[0089] Figure 6 This is a schematic diagram of a peripheral circuit provided in an embodiment of this application;

[0090] Figure 7 This is a flowchart of an operation method for a memory provided in an embodiment of this application;

[0091] Figure 8This is a flowchart of another memory operation method provided in an embodiment of this application;

[0092] Figure 9 This is a data writing flowchart provided in an embodiment of this application;

[0093] Figure 10 This is a data reading flowchart provided in an embodiment of this application;

[0094] Figure 11 This is a flowchart of another memory operation method provided in an embodiment of this application;

[0095] Figure 12 This is a flowchart of another memory operation method provided in an embodiment of this application;

[0096] Figure 13 This is a schematic diagram of the structure of a controller provided in an embodiment of this application. Detailed Implementation

[0097] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0098] Figure 1 This is a schematic diagram of a storage system 10 provided in an embodiment of this application. For example... Figure 1 As shown, the storage system 10 includes: one or more memories 100, and a controller 200 coupled to the memories 100 and configured to control the memories 100.

[0099] Controller 200 can be configured to control operations performed by memory 100, such as read, erase, and program operations. Controller 200 can also be configured to manage various functions related to data stored or to be stored in memory 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, and wear leveling. Optionally, controller 200 can also be configured to handle error correcting codes (ECCs) for data read from or written to memory 100. Controller 200 can also perform any other suitable functions, such as formatting memory 100.

[0100] The controller 200 can also communicate with external devices according to a specific communication protocol. For example, the controller 200 can communicate with external devices through at least one of various interface protocols. Interface protocols may include Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Development Environment (IDE), FireWire, etc.

[0101] In some embodiments, the controller 200 and one or more memories 100 can be integrated into various types of electronic devices. These electronic devices may be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In such a scenario, such as... Figure 1 As shown, the storage system 10 also includes a host 300. A controller 200 is coupled to the host 300. The controller 200 can manage the data stored in the memory 100 and communicate with the host 300 to perform the functions of the aforementioned electronic device.

[0102] In other embodiments, the controller 200, and one or more memories 100, can be integrated into various types of storage devices.

[0103] As an example, such as Figure 2As shown, the controller 200 and a single memory 100 can be integrated into the memory card 400. The memory card 400 may include PCMCIA (PC) cards, CompactFlash (CF) cards, Smart Media (SM) cards, memory sticks, Multi-Media Cards (MMC), RS-MMC, micro-MMC, Secure Digital (SD) cards, Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 400 may also include a connector 410 for coupling the memory card 400 to the host.

[0104] As another example, such as Figure 3 As shown, the controller 200 and multiple memories 100 can be integrated into a solid-state drive (SSD) 500. The solid-state drive 500 may also include a connector 510 for coupling the solid-state drive 500 to the host. The storage capacity and / or operating speed of the solid-state drive 500 is greater than that of the memory card 400.

[0105] also, Figures 1 to 3 The memory 100 can be any memory involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 will be explained below.

[0106] Figure 4 This is a schematic diagram of a memory 100 provided in an embodiment of this application. Figure 4 As shown, the memory 100 includes:

[0107] Storage array 110, which includes multiple rows of storage cells;

[0108] Multiple word lines 120 are coupled to multiple rows of memory cells;

[0109] Peripheral circuitry 130 is coupled to a plurality of word lines 120 and configured to perform operations such as programming (i.e., writing data) or reading data on a selected memory cell line among a plurality of memory cell lines, wherein the selected memory cell line is the memory cell line coupled to the selected word line, wherein, in order to perform operations such as programming or reading data, peripheral circuitry 130 is configured to perform the memory operation method provided in the embodiments of this application.

[0110] Storage array 110 can be a NAND flash memory storage array. For example... Figure 1As shown, the NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, each memory string 111 extending vertically above the substrate (not shown). In some embodiments, each memory string 111 includes a plurality of memory cells 112 that are coupled in series and stacked vertically.

[0111] like Figure 4 As shown, each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also called the bottom select gate (BSG) or source selector, and the drain select gate is also called the top select gate (TSG) or drain selector. The source select gate 113 and the drain select gate 114 can be configured to activate the selected memory string 111 during read and program operations.

[0112] In some embodiments, the drain selection gate 114 of each memory string 111 is coupled to a corresponding bit line 115, and data can be read from or written to the bit line 115 via an output bus (not shown).

[0113] In some embodiments, each memory string 111 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 116. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselect voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 117.

[0114] like Figure 4 As shown, the storage string 111 can be organized into multiple blocks 140. For any one of the multiple blocks 140, the block 140 can have a source line (SL) 118. The sources of all storage strings 111 in the block 140 are coupled through the source line 118. The source line is also called the common source line or array common source (ACS).

[0115] The source line 118 can be used for grounding, so that the source of each memory cell in the memory string of block 140 can be grounded in some subsequent operations. Optionally, in some other operations, the source of each memory cell in the memory string of block 140 can also be connected to a high voltage through the source line 118.

[0116] Each block 140 is the basic data unit used for the erase operation, meaning that all memory cells 112 on the same block 140 are erased simultaneously. To erase memory cells 112 in a selected block, an erase voltage (Vers) (e.g., a high positive voltage (20V or higher)) can be biased and coupled to the source line of the selected block.

[0117] It should be understood that, in other embodiments, erasure operations may be performed at the half-block level, at the quarter-block level, or at any suitable fractional level with any suitable number of blocks or blocks.

[0118] like Figure 4 As shown, the same layer of storage cells 112 of adjacent storage strings 111 in the same block 140 can be coupled through word lines 120. Word lines 120 are used to select which layer of storage cells 112 in the block 140 is affected by read and program operations.

[0119] In some embodiments, each word line 120 is coupled to a page 150 to which the memory cell 112 belongs, and the page 150 is a basic data unit for programming operations. The size of the page 150 may be related to the number of memory strings 111 coupled by word lines 120 in a block 140. Each word line 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in the corresponding page 150. It is understood that a memory cell row is a plurality of memory cells 112 located on the same page 150.

[0120] It should be noted that within a block of 140, storage units at the same level correspond to the same word line, but storage units at the same level can be divided into one or more pages. That is, a word line can couple to one or more pages. For example, for SLC, a word line couples to one page, and for MLC, a word line couples to two pages.

[0121] Figure 5 This is a cross-sectional schematic diagram of a storage array 110 including storage strings 111, provided in an embodiment of this application. Figure 5 As shown, the storage string 111 may extend vertically over the substrate 101 and through the stacked layer 102. The substrate 101 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0122] The stacked layer 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in the stacked layer 102 can determine the number of memory cells 112 in the memory array 110.

[0123] The gate conductive layer 103 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In other embodiments, each gate conductive layer 103 includes a doped polysilicon layer. Furthermore, each gate conductive layer 103 may include a control gate surrounding the memory cell 112, and may extend laterally at the top of the stacked layer 102 as a DSG line 116, at the bottom of the stacked layer 102 as an SSG line 117, or between the DSG line 116 and the SSG line 117 as a word line 120.

[0124] like Figure 5 As shown, the memory string 111 includes a channel structure 105 extending vertically through the stacked layer 102. In some embodiments, the channel structure 105 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). The semiconductor channel includes silicon, such as polycrystalline silicon. The memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer.

[0125] In some embodiments, the channel structure 105 has a cylindrical shape (e.g., a pillar shape). The layers in the semiconductor channel and the memory film are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order.

[0126] It should be understood that, despite Figure 5 As not shown, the memory array 110 may also include other additional components, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0127] Return to reference Figure 4 The peripheral circuitry 130 can be coupled to the memory array 110 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116. The peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 110 by applying voltage and / or current signals to and sensing voltage and / or current signals from the memory cells 112 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116.

[0128] Peripheral circuitry 130 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry 130 is shown, including a page buffer / sensor amplifier 131, a column decoder / bit line (BL) driver 132, a row decoder / word line (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.

[0129] Page buffer / sensor amplifier 131 can be configured to read data from memory array 110 and program (write) data to memory array 110 according to control signals from control logic unit 135. For example, page buffer / sensor amplifier 131 can store a page of programming data (write data) to be programmed into a page 130 of memory array 110. Page buffer / sensor amplifier 131 can also perform a verification operation to ensure that data has been correctly programmed into memory cell 112 coupled to selected word line 120. Page buffer / sensor amplifier 131 can also sense a low-power signal from bit line 115, which represents a data bit stored in memory cell 112, and amplify a small voltage swing to a recognizable logic level during read operations.

[0130] The column decoder / bit line driver 132 can be configured to be controlled by the control logic unit 135 and to select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 134.

[0131] The row decoder / word line driver 133 can be configured to be controlled by the control logic unit 135 and to select / deselect block 140 of the memory array 110 and to select / deselect word lines 120 of block 140. The row decoder / word line driver 133 can also be configured to drive word lines 120 using word line voltages (VWL) generated from a voltage generator 134. In some embodiments, the row decoder / word line driver 133 can also select / deselect and drive SSG lines 117 and DSG lines 116. As described in detail below, the row decoder / word line driver 133 is configured to perform erase operations on memory cells 112 coupled to one or more selected word lines 120.

[0132] Voltage generator 134 can be configured to be controlled by control logic unit 135 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 110.

[0133] The control logic unit 135 can be coupled to various circuits in the peripheral circuitry described above and is configured to control the operation of each circuit.

[0134] Register 136 can be coupled to control logic unit 135. The register may include a status register, a command register, and an address register to store status information, command opcodes (OP codes), and command addresses for controlling the operation of each circuit in the peripheral circuitry.

[0135] Interface (I / F) 137 can be coupled to control logic unit 135 and act as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 135, as well as to buffer status information received from control logic unit 135 and relay it to the host. Interface 137 can also be coupled to column decoder / bit line driver 132 via data bus 138 and act as a data I / O interface and data buffer to buffer data and relay it to or from memory array 110.

[0136] The above description of the memory-related hardware embodiments has similar beneficial effects to the method embodiments described below. For technical details not disclosed in the memory-related hardware embodiments, please refer to the description of the method embodiments in this application for understanding.

[0137] based on Figures 1 to 6 The controller 200, as shown in the memory diagram, can write data to or read data from memory cells in the memory array 110 via peripheral circuitry 130 within the memory 100. After data is written to a memory cell, the charge stored in that cell reaches a specified state. However, the charge stored in the cell may subsequently change due to environmental influences, potentially leading to data read errors later. Therefore, after writing data to the memory array, verification data is generated and stored. If a data read error occurs later, the stored verification data can be used to correct the read data and recover the correct data.

[0138] There are several ways to generate checksum data. For example, methods include 1WL_RAID (redundant array of independent disks), 2WL_RAID, ..., nWL_RAID. 1WL_RAID can be understood as generating one set of checksum data for data stored in several consecutive rows of storage units. nWL_RAID can be understood as generating n sets of checksum data for data stored in several consecutive rows of storage units, where n is a positive integer greater than 1.

[0139] A larger n indicates a greater number of checksums generated for data stored in several consecutive rows of storage units. This means that even if more than two rows of storage units contain corrupted data, the correct data can still be recovered based on these multiple checksums. Therefore, a larger n indicates a greater protection capability of the nWL_RAID method.

[0140] In this scenario, the parity data can be stored in SRAM (static random-access memory). However, a large n in this case can lead to increased SRAM costs. Alternatively, the parity data can be stored in a storage array. In this case, a large n in this scenario can result in cumbersome write operations to the memory, leading to reduced memory write performance. Therefore, in many scenarios, parity data can be generated using 1WL_RAID to avoid the problems associated with nWL_RAID.

[0141] Currently, the number of write layers (WL) in 3D NAND is increasing, leading to a continuous decrease in the width between adjacent WLs. In this situation, the charges stored in adjacent memory cell rows coupled with adjacent WLs can easily interfere with each other, increasing the probability of simultaneous errors in the data stored in adjacent memory cell rows coupled with adjacent WLs. However, in 1WL_RAID mode, since several consecutive memory cell rows store only one set of parity data, only one memory cell row is allowed to have corrupted data. If two or more (including two) memory cell rows have corrupted data, it is impossible to recover the correct data based on the parity data.

[0142] Based on this, embodiments of this application provide a method for operating a memory. The method provided by these embodiments allows for simultaneous errors in adjacent memory cell rows while generating parity data using 1WL_RAID, indirectly achieving the protection capability of nWL_RAID.

[0143] The operation method of the memory provided in the embodiments of this application will be explained below.

[0144] Figure 7 This is a flowchart illustrating a memory operation method provided in an embodiment of this application. The method is applied to... Figure 1-6 The peripheral circuitry of the memory shown is exemplarily applied to a control logic unit within the peripheral circuitry. Subsequent embodiments will be explained using the peripheral circuitry as the execution entity. For example... Figure 7 As shown, the method includes the following steps.

[0145] Step 701: The peripheral circuit receives an operation command from the controller, which carries multiple initial word line identifiers.

[0146] In some embodiments, the controller can write data to the memory array via operation instructions. In this scenario, the controller sends an operation instruction including a write instruction to the memory, and the memory's peripheral circuitry receives the operation instruction. The write instruction also carries multiple data items to be written, each corresponding to a plurality of initial word line identifiers. Subsequently, the peripheral circuitry can write the data to be written into the memory cell rows corresponding to the plurality of initial word line identifiers through steps 702 and 703.

[0147] When the controller sends a write command to the memory, it also generates a set of verification data corresponding to the multiple sets of data to be written. For example, the write command may also carry the verification data to store it in the memory array. Optionally, the controller may also store the verification data in other storage devices, such as SRAM. This application embodiment does not limit the method by which the controller stores the verification data.

[0148] In other embodiments, the controller can read data from the memory array via an operation instruction. In this scenario, the controller sends an operation instruction, including a read instruction, to the memory, and the memory's peripheral circuitry receives the operation instruction. The peripheral circuitry can then read data from the memory cell rows corresponding to the multiple initial word line identifiers via steps 702 and 703.

[0149] The initial word line identifier is used to uniquely identify a word line. For example, the initial word line identifier can be an initial word line number. For instance, multiple initial word line identifiers could be WL1-WL5. Alternatively, the initial word line identifier can also be other symbols that can identify a word line; for example, multiple initial word line identifiers could be Wla-WLe.

[0150] Step 702: The peripheral circuit maps multiple initial word line identifiers to multiple physical word line identifiers.

[0151] In this embodiment of the application, in order to avoid writing multiple data to be written to several consecutive rows of storage cells corresponding to the same verification data, when the peripheral circuit receives the write instruction sent by the controller, it can also map multiple initial word line identifiers in the write instruction to multiple physical word line identifiers, so that the storage cell rows indicated by the multiple mapped physical word line identifiers are not consecutive.

[0152] That is, in the embodiments of this application, the peripheral circuit does not directly write data according to the word line indicated by the initial word line identifier in the write instruction, but maps the initial word line identifier in the write instruction according to certain rules, so that data can be written according to the word line indicated by the mapped physical word line identifier in the future.

[0153] Correspondingly, when the peripheral circuit receives a read command from the controller, it also needs to map the initial word line identifier carried in the read command to the physical word line identifier in order to read the correct data.

[0154] In some embodiments, the peripheral circuit can map multiple initial word line identifiers to multiple physical word line identifiers in the following way: each initial word line identifier among the multiple initial word line identifiers is treated as a pseudo word line identifier, and the physical word line identifier corresponding to each initial word line identifier is obtained from the stored mapping relationship between pseudo word line identifiers and physical word line identifiers.

[0155] Figure 8 This is a flowchart of another memory operation method provided in an embodiment of this application. For example... Figure 8 As shown, when the peripheral circuit receives an operation command from the controller, it first maps the initial word line identifier in the operation command to a physical word line identifier according to the mapping relationship between the pseudo word line identifier and the physical word line identifier, and then executes the operation command based on the mapped physical word line identifier.

[0156] To improve the efficiency of writing or reading data, a mapping relationship between pseudo-word line identifiers and physical word line identifiers can be pre-configured in the peripheral circuitry. This way, when the peripheral circuitry needs to write data, it can directly map the initial word line identifier based on this mapping relationship.

[0157] Alternatively, the mapping relationship described above may not be configured in the peripheral circuitry. In this scenario, when the peripheral circuitry needs to write or read data, it can temporarily map the initial word line identifier according to a certain algorithm. Subsequent embodiments will illustrate mapping through mapping relationships.

[0158] To facilitate understanding, the mapping relationship is explained below.

[0159] In some embodiments, the mapping relationship includes a mapping relationship between a first pseudo-word line identifier and a first physical word line identifier, and a mapping relationship between a second pseudo-word line identifier and a second physical word line identifier. Specifically, the two memory cell rows coupled to the two word lines indicated by the first pseudo-word line identifier and the second pseudo-word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical word line identifier.

[0160] The mapping relationship may include multiple pseudo-character line identifiers and physical character line identifiers corresponding to these multiple pseudo-character line identifiers. The first pseudo-character line identifier and the second pseudo-character line identifier may be two of the multiple pseudo-character line identifiers.

[0161] Since the two memory cell rows coupled by the first pseudo-word line identifier and the second pseudo-word line identifier are adjacent, and there are other memory cell rows distributed between the two memory cell rows coupled by the first physical word line identifier and the second physical identifier, this mapping relationship can achieve the following: when the memory cell rows indicated by multiple initial word line identifiers are continuous, the memory cell rows indicated by multiple mapped physical word line identifiers are not continuous.

[0162] For example, the first pseudo-word line is identified by its first pseudo-word line number, and the second pseudo-word line is identified by its second pseudo-word line number. The difference between the first pseudo-word line number and the second pseudo-word line number is 1, meaning that the two memory cell rows indicated by the first pseudo-word line number and the second pseudo-word line number are adjacent. The first physical word line is identified by its first physical word line number, and the second physical word line is identified by its second physical word line number. The difference between the first physical word line number and the second physical word line number is greater than 1, meaning that other memory cell rows are distributed between the two memory cell rows indicated by the first physical word line number and the second physical word line number.

[0163] In some scenarios, the difference between the two physical word line numbers mapped from every two adjacent pseudo-word line numbers can be set to a fixed value. In this scenario, when the first pseudo-word line number is less than the second pseudo-word line number, the second physical word line number can be the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

[0164] For example, if the reference value is 5, then the difference between the two physical word line numbers after mapping each pair of adjacent pseudo-word line labels is 5.

[0165] Table 1 is a schematic diagram of a mapping relationship provided in an embodiment of this application. As shown in Table 1, the physical character line identifiers corresponding to pseudo-character line identifiers WL1-WL5 are WL1, WL6, WL11, WL16, and WL21, respectively. The physical character line identifiers corresponding to pseudo-character line identifiers WL6-WL10 are WL26, WL31, WL36, WL41, and WL46, respectively. The physical character line identifiers corresponding to pseudo-character line identifiers WL11-WL15 are WL51, WL56, WL61, WL66, and WL71, respectively.

[0166] Among them, the five data corresponding to pseudo-character line identifiers WL1-WL5 correspond to the same set of verification data, the five data corresponding to pseudo-character line identifiers WL6-WL10 correspond to the same set of verification data, and the five data corresponding to pseudo-character line identifiers WL11-WL16 correspond to the same set of verification data. The explanations of the other verification data in Table 1 will not be explained one by one.

[0167] As shown in Table 1, for 5 data corresponding to the same set of verification data, when the controller needs to write these 5 data, although the 5 initial word line numbers carried in the write command sent by the controller are 5 consecutive initial word line numbers, after the peripheral circuit maps these 5 initial word line numbers according to Table 1, the difference between the two physical word line numbers corresponding to each of the two adjacent initial word line numbers is 5. This enables the 5 data to be written into 5 memory cell rows in sequence, and there are also 5 other memory cell rows distributed between each of the two adjacent memory cell rows.

[0168] Table 1

[0169]

[0170] The mapping relationships shown in Table 1 can be pre-written into the peripheral circuitry by technicians. For example, this is written into the registers of the peripheral circuitry. The control logic units in the peripheral circuitry retrieve this mapping relationship from the registers when they need to map the initial identifier to a physical word line identifier.

[0171] In other scenarios, the difference between the two physical word line numbers mapped from each adjacent pseudo-word line number may not be set to a fixed value. For example, it can be set to a difference that varies according to a certain pattern. For instance, the physical word line numbers corresponding to pseudo-word line identifiers WL1-WL5 are WL1, WL3, WL6, WL10, and WL15, respectively. The difference between the two physical word line numbers mapped from each adjacent pseudo-word line number increases sequentially according to the pattern 2, 3, 4, and 5.

[0172] In other scenarios, each pseudo-word line number can be processed according to certain mathematical rules, and the resulting number is the corresponding physical word line number. This method also ensures that adjacent pseudo-word line numbers are mapped to non-adjacent physical word line numbers. For example, pseudo-word line identifiers WL1-WL5 correspond to physical word line identifiers WL2, WL6, WL12, WL20, and WL30, respectively. The physical word line number mapped to each pseudo-word line number is obtained by multiplying the pseudo-word line number by 2.

[0173] The above examples illustrate the representation of the mapping relationship. It should be noted that the mapping relationship provided in this application is not limited to the above-mentioned representations. The mapping relationship provided in this application includes any mapping relationship that can map adjacent pseudo-word line numbers to two non-contiguous physical word line numbers, which will not be illustrated one by one here.

[0174] Furthermore, the above explanation uses the character line identifier as the character line number as an example. Optionally, when the character line identifier is another symbol used to identify character lines, the mapping relationship can also be designed in the same way.

[0175] Step 703: The peripheral circuit executes the operation corresponding to the operation instruction on multiple first-type memory cell rows through multiple first-type word lines indicated by multiple physical word line identifiers. Among these, at least one third-type memory cell row is distributed between the first and second memory cell rows, and the data stored in the multiple first-type memory cell rows corresponds to the same check data.

[0176] The first type of storage cell row can be understood as a first type of word-line coupled storage cell row; therefore, it can also be called a selected storage cell row. The third type of storage cell row can be understood as any storage cell row other than the first type of word-line coupled storage cell row; therefore, it can also be called a non-selected storage cell row.

[0177] In some embodiments, in order to maximize the protection capability of the verification data, at least one third type of storage cell row is distributed between each two adjacent storage cell rows in the plurality of first type of storage cell rows.

[0178] In other words, for several data points corresponding to the same verification data, there are no adjacent storage cell rows in the storage cell rows where these data points are stored. This is to avoid the inability to recover the correct data when data in adjacent storage cell rows is corrupted.

[0179] For example, the number of third-class storage cell rows distributed between every two adjacent storage cell rows in multiple first-class storage cell rows is a reference number.

[0180] For example, when the difference between the two physical self-word line identifiers corresponding to two adjacent pseudo-word line identifiers in the mapping relationship in step 702 is a parameter value, the number of third-class storage cell rows distributed between each pair of adjacent storage cell rows in multiple first-class storage cell rows is a reference number. The reference value is the same as the reference number, for example, 5 in both reference Table 1.

[0181] Optionally, in multiple rows of first-class storage cells, at least one row of third-class storage cells may be distributed between each pair of partially adjacent rows, with the two pairs of partially adjacent rows being physically adjacent. Compared to multiple rows of first-class storage cells forming a continuous row of storage cells in the storage array, this scheme can also improve the protection capability of verification data.

[0182] In step 702, when the physical word line identifier corresponding to the initial word line is obtained through the mapping relationship, the specific distribution of the third type of storage cell rows between each two adjacent storage cell rows in the multiple first type of storage cell rows is related to the physical word line identifier corresponding to the pseudo word line identifier in the mapping relationship.

[0183] As shown in Table 1, assuming multiple initial word line identifiers are WL1-WL5, the corresponding physical word line identifiers after mapping are WL1, WL6, WL11, WL16, and WL21, respectively. In this scenario, multiple rows of first-type memory cells are five rows of memory cells coupled together as WL1, WL6, WL11, WL16, and WL21. Among them, there are five rows of third-type memory cells distributed between every two adjacent rows of memory cells.

[0184] For other examples of third-class storage cell rows distributed between every two adjacent storage cell rows in multiple first-class storage cell rows, please refer to the above content, and they will not be listed here again.

[0185] Furthermore, as can be seen from step 701, the operation instructions can include both write and read instructions. Step 703 will be explained below in two scenarios.

[0186] Scenario 1: Operation instructions include write instructions.

[0187] In Scenario 1, the implementation method of performing operation instructions on multiple first-class storage cell rows through multiple first-class word lines indicated by multiple physical word line identifiers can be as follows: take the data to be written corresponding to each initial word line identifier as the data to be written corresponding to the corresponding physical word line identifier, and perform programming operations on multiple first-class storage cell rows through multiple first-class word lines to store multiple data to be written into multiple first-class storage cell rows.

[0188] Since at least one third-type storage cell row is distributed between the first and second storage cell rows in multiple first-type storage cell rows, and the data stored in multiple first-type storage cell rows corresponds to the same check data, the method provided in this application embodiment can write multiple data corresponding to the same check data into non-contiguous storage cell rows. This allows adjacent storage cell rows in the storage array to store data corresponding to different check data. Thus, even if adjacent storage cell rows are too close together and their charges interfere with each other, causing the data stored in adjacent storage cell rows to malfunction simultaneously, since the data stored in adjacent storage cell rows corresponds to different check data, the data stored in adjacent storage cell rows can be corrected separately using at least two check data, thereby improving data protection capabilities.

[0189] Figure 9 This is a data writing flowchart provided in an embodiment of this application. For example... Figure 9 As shown, the data writing process includes the following steps.

[0190] (1) The controller acquires the data to be written to the storage array.

[0191] (2) The controller divides the data to be written into multiple data, each data corresponding to a set of consecutive WL numbers, such as WL1-5 corresponding to one set of data to be written, and WL6-10 corresponding to one set of data to be written.

[0192] (3) The controller generates multiple verification data based on multiple data sets.

[0193] In some embodiments, the check data can be generated using a parity check. For example, for any given set of data, the total number of bits that are 1 in the binary encoding is determined, and check data is generated to record the parity of this total number. This allows for subsequent verification of the read data based on the check data.

[0194] The above examples illustrate how validation data can be generated. Alternatively, other methods can also be used to generate validation data, which will not be illustrated here.

[0195] (4) The controller sends a write instruction to the memory. The write instruction carries multiple data and a consecutive WL number corresponding to each data.

[0196] (5) The memory receives a write instruction and performs the following operations on each piece of data and its corresponding consecutive WL number:

[0197] Each WL number in the consecutive WL numbers is used as a pseudo WL number, and the corresponding physical WL number is obtained by mapping according to the mapping relationship, resulting in several non-consecutive physical WL numbers. Then, the data is written sequentially into several non-consecutive storage cell rows indicated by the non-consecutive physical WL numbers.

[0198] In addition, during the data writing process, since several data corresponding to the same check data are written to non-contiguous rows of storage cells, the programming disturbance caused to adjacent rows of storage cells can be reduced when writing data to the storage array.

[0199] Scenario 2: Operation instructions include read instructions.

[0200] In Scenario 2, the implementation of the operation corresponding to the operation instruction on multiple Class 1 storage cell rows by multiple Class 1 word lines indicated by multiple physical word lines can be as follows: perform a read operation on multiple Class 1 storage cell rows by multiple Class 1 word lines to obtain the data stored in the multiple Class 1 storage cell rows respectively.

[0201] In addition, after acquiring the data stored in the multiple rows of the first type of storage cells, the peripheral circuit can also send a read data result to the controller. This read data result carries the data stored in the multiple rows of the first type of storage cells, so that the controller can receive the read data result. The controller determines the data to be read based on this read data result.

[0202] In addition, after the peripheral circuit obtains the data stored in multiple rows of first-class memory cells, if the data stored in the third memory cell row among the multiple rows of first-class memory cells is erroneous, it determines the initial word line identifier corresponding to the physical word line identifier of the third memory cell row; obtains the verification data based on the determined initial word line identifier; and corrects the data stored in the third memory cell row based on the verification data.

[0203] In this embodiment, after acquiring the data stored in multiple rows of first-type storage units, the peripheral circuit can verify whether there is any erroneous data in these data rows. This application does not limit the method by which the peripheral circuit verifies whether there is erroneous data in the read data. For example, the peripheral circuit can send the read data to the controller, and the host connected to the controller can determine whether there is erroneous data in the read data.

[0204] In some embodiments, when the controller writes data to the storage array, it also generates a correspondence between initial word line identifiers and check data. This correspondence can be stored in the storage array or in other storage devices. When the correspondence is stored in the storage array, the peripheral circuitry can obtain the identifier of the check data corresponding to the initial word line identifier of the physical word line identifier of the third storage cell row based on the correspondence, and then obtain the check data based on the identifier of the check data. When the correspondence is stored in other storage devices, the peripheral circuitry can send the initial word line identifier corresponding to the physical word line identifier of the third storage cell row to the other storage devices, and the other storage devices can obtain the identifier of the check data corresponding to the initial word line identifier of the physical word line identifier of the third storage cell row based on the correspondence, and then the peripheral circuitry can obtain the check data based on the identifier of the check data.

[0205] There are several ways for the peripheral circuit to retrieve the verification data based on its identifier. For example, when the verification data is stored in a storage array, the peripheral circuit can directly read the verification data based on its identifier. As another example, when the verification data is stored in another storage device, the peripheral circuit can directly read the verification data from that storage device via the controller based on its identifier.

[0206] Furthermore, the implementation method for determining the initial word line identifier corresponding to the physical word line identifier of the third memory cell row by the peripheral circuit can refer to the implementation method of mapping the initial word line identifier to the physical word line identifier in step 702. For example, the initial word line identifier corresponding to the physical word line identifier of the third memory cell row can be determined by the mapping relationship shown in Table 1, which will not be described in detail here.

[0207] In some embodiments, after the peripheral circuitry acquires the data stored in multiple rows of first-type memory cells, it can directly send this data to the controller. The controller then determines whether there is any erroneous data and corrects the erroneous data based on a pre-stored mapping relationship between initial word line identifiers and check data. In this scenario, since the controller stores the mapping relationship between initial word line identifiers and check data, the controller does not need to perform word line mapping and can directly correct the erroneous data based on the pre-stored mapping relationship.

[0208] Figure 10 This is a data reading flowchart provided in an embodiment of this application. For example... Figure 10 As shown, the data reading process includes the following steps.

[0209] (1) The controller sends a read instruction to the memory. The read instruction carries several consecutive WL numbers corresponding to the data to be read, such as WL1-5, WL6-10, etc.

[0210] (2) The memory receives a read instruction and performs the following operations on each consecutive WL number:

[0211] Each WL number in the consecutive WL numbers is used as a pseudo WL number, and the corresponding physical WL number is obtained by mapping according to the mapping relationship. Then, the corresponding data is read from the storage cell row indicated by the physical WL number corresponding to each pseudo WL number to obtain the data corresponding to the consecutive WL numbers in this part, and the read data result is sent to the controller.

[0212] (3) The controller verifies and corrects the reading data based on the verification data corresponding to the consecutive WL numbers of each part.

[0213] The technical effects of the solutions provided in the embodiments of this application will be further explained below with reference to Tables 1 and 2.

[0214] Table 2

[0215]

[0216] In Table 2, when the peripheral circuit receives a write command, it directly writes data according to the word lines indicated by the initial word line identifiers. For example, the write command carries five initial word line numbers, WL1-5, and five data points, all corresponding to the same set of check data. Upon receiving this write command, the peripheral circuit directly stores these five data points into the five memory cell rows coupled to WL1-5 respectively. Thus, the five data points corresponding to the same set of check data are written into five consecutive memory cell rows. Subsequently, if the data stored in two adjacent memory cell rows within these five consecutive rows is corrupted, it is impossible to recover the data stored in those two adjacent memory cell rows based on the check data.

[0217] However, as shown in Table 1, for the five data corresponding to the same set of verification data, although the five initial word line numbers carried in the write instruction sent by the controller are five consecutive initial word line numbers, after the peripheral circuit maps these five initial word line numbers according to Table 1, the difference between the two physical word line numbers corresponding to each of the two adjacent initial word line numbers is 5.

[0218] For example, a write instruction carries five initial word line numbers, WL1-5, and five data items, all corresponding to the same parity data. Upon receiving this write instruction, the peripheral circuit determines the physical word line numbers mapped from the initial word line numbers WL1-5 to WL1, WL6, WL11, WL16, and WL21 according to Table 1. These five data items are then stored in the five memory cell rows coupled to WL1, WL6, WL11, WL16, and WL21, respectively. Thus, the five data items corresponding to the same parity data are written into five spaced memory cell rows, with five third-type memory cell rows distributed between each pair of adjacent rows. If subsequently, if the data stored in two adjacent memory cell rows within a consecutive row is incorrect—for example, if the data stored in two adjacent memory cell rows coupled to WL1 and WL2 are both incorrect—the data stored in the two adjacent memory cell rows coupled to WL1 and WL2 correspond to different parity data, corrections can be performed based on the corresponding parity data.

[0219] Furthermore, in this embodiment, the controller can also control whether the peripheral circuit executes the operation instructions according to steps 702 and 703. Based on this, in some embodiments, in step 702, the implementation of mapping multiple initial word line identifiers to multiple physical word line identifiers can be as follows: if a word line mapping instruction is received from the controller, the peripheral circuit performs the operation of mapping multiple initial word line identifiers to multiple physical word line identifiers.

[0220] Figure 11 This is a flowchart illustrating the operation instructions of another memory provided in an embodiment of this application. For example... Figure 11 As shown, when the peripheral circuit receives an operation command from the controller, it first determines whether a word line mapping command has been received from the controller at the current time. If the determination result is yes, then steps 702 and 703 are executed. That is, the peripheral circuit maps multiple initial word line identifiers to multiple physical word line identifiers, and performs the operation corresponding to the operation command on multiple first-type memory cell rows through multiple first-type word lines indicated by multiple physical word line identifiers. Among them, at least one third-type memory cell row is distributed between the first and second memory cell rows in the multiple first-type memory cell rows, and the data stored in the multiple first-type memory cell rows corresponds to the same check data.

[0221] Accordingly, if the peripheral circuit does not receive a word line mapping instruction from the controller, the peripheral circuit performs the operation corresponding to the operation instruction on multiple second-type memory cell rows through multiple second-type word lines indicated by multiple initial word line identifiers; wherein, multiple second-type memory cell rows are multiple consecutive memory cell rows in the memory array, and the data stored in multiple second-type memory cell rows corresponds to the same check data.

[0222] Figure 12 This is a flowchart illustrating the operation instructions of another memory provided in an embodiment of this application. For example... Figure 12 As shown, when the peripheral circuit receives an operation instruction from the controller, it first determines whether a word line mapping instruction has been received from the controller at the current time. If the determination result is no, steps 702 and 703 are not executed. Instead, the operation corresponding to the operation instruction is executed on multiple second-type memory cells through multiple second-type word lines indicated by multiple initial word line identifiers.

[0223] Based on this, in scenarios where it is necessary to determine whether the peripheral circuit executes the operation instructions according to steps 702 and 703, such as in scenarios where the data to be written is of high importance, the controller can send a word line mapping instruction to the peripheral circuit so that the peripheral circuit executes steps 702 and 703 in response to the word line mapping instruction, thereby improving the protection capability of the verification data for the data to be written.

[0224] Optionally, in scenarios where it is not necessary for the peripheral circuit to execute the operation instructions according to steps 702 and 703, such as in scenarios where the importance of the data to be written is generally low, the controller may not send word line mapping instructions to the peripheral circuit, so that the peripheral circuit can directly perform operations on the memory cell indicated by the initial word line identifier.

[0225] Among them, the word line mapping instruction can be predix CMD (a command).

[0226] In summary, in this embodiment, since at least one third type of storage cell row is distributed between the first and second storage cell rows in multiple first type storage cell rows, and the data stored in the multiple first type storage cell rows corresponds to the same check data, the method provided in this embodiment can write multiple data corresponding to the same check data into non-contiguous storage cell rows. This allows adjacent storage cell rows in the storage array to store data corresponding to different check data. Thus, even if adjacent storage cell rows are too close together and their charges interfere with each other, causing the data stored in adjacent storage cell rows to err simultaneously, since the data stored in adjacent storage cell rows corresponds to different check data, the data stored in adjacent storage cell rows can be corrected separately using at least two check data, thereby improving data protection capabilities.

[0227] based on Figure 7 The embodiments shown in this application also provide a memory, which includes: a memory array including a plurality of memory cell rows; a plurality of word lines respectively coupled to the plurality of memory cell rows; and peripheral circuitry coupled to the plurality of word lines and configured to implement the operation method of the memory provided in this application.

[0228] Specifically, the peripheral circuit is configured to: receive an operation instruction from the controller, the operation instruction carrying multiple initial word line identifiers; map the multiple initial word line identifiers to multiple physical word line identifiers; and execute the operation corresponding to the operation instruction on multiple first-class memory cell rows through the multiple first-class word lines indicated by the multiple physical word line identifiers; wherein, at least one third-class memory cell row is distributed between the first and second memory cell rows in the multiple first-class memory cell rows, and the data stored in the multiple first-class memory cell rows corresponds to the same check data.

[0229] Optionally, the peripheral circuit is configured to: treat each initial word line identifier among multiple initial word line identifiers as a pseudo word line identifier, and obtain the physical word line identifier corresponding to each initial word line identifier from the stored mapping relationship between pseudo word line identifiers and physical word line identifiers.

[0230] Optionally, the mapping relationship includes the mapping relationship between the first pseudo-word line identifier and the first physical word line identifier, and the mapping relationship between the second pseudo-word line identifier and the second physical word line identifier; the two memory cell rows coupled by the two word lines indicated by the first pseudo-word line identifier and the second pseudo-word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled by the two word lines indicated by the first physical word line identifier and the second physical identifier.

[0231] Optionally, the first pseudo-character line is identified by the first pseudo-character line number, the second pseudo-character line is identified by the second pseudo-character line number, and the difference between the first pseudo-character line number and the second pseudo-character line number is 1; the first physical character line is identified by the first physical character line number, the second physical character line is identified by the second physical character line number, and the difference between the first physical character line number and the second physical character line number is greater than 1.

[0232] Optionally, the number of the first pseudo-word line is less than the number of the second pseudo-word line; the number of the second physical word line is the sum of the number of the first physical word line and a reference value, where the reference value is a positive integer.

[0233] Optionally, at least one third-class storage cell row is distributed between every two adjacent storage cell rows in the plurality of first-class storage cell rows.

[0234] Optionally, the number of third-class storage cell rows distributed between each pair of adjacent storage cell rows in the plurality of first-class storage cell rows is a reference number.

[0235] Optionally, the peripheral circuitry is configured to: if a word line mapping instruction is received from the controller, perform an operation to map multiple initial word line identifiers to multiple physical word line identifiers.

[0236] Optionally, the peripheral circuit is further configured to: if no word line mapping instruction is received from the controller, perform the operation corresponding to the operation instruction on multiple second-type memory cell rows through multiple second-type word lines indicated by multiple initial word line identifiers; wherein, the multiple second-type memory cell rows are multiple consecutive memory cell rows in the memory array, and the data stored in the multiple second-type memory cell rows corresponds to the same check data.

[0237] Optionally, the operation instructions include write instructions, which also carry multiple data to be written, each corresponding one-to-one with a plurality of initial word line identifiers. The peripheral circuitry is configured to: treat the data to be written corresponding to each initial word line identifier as the data to be written corresponding to the corresponding physical word line identifier, and perform programming operations on a plurality of first-class memory cell rows through a plurality of first-class word lines to store the multiple data to be written into the plurality of first-class memory cell rows.

[0238] Optionally, the operation instructions include read instructions. The peripheral circuitry is configured to perform read operations on multiple rows of first-class memory cells via multiple first-class word lines to obtain the data stored in each row of first-class memory cells.

[0239] Optionally, the peripheral circuit is further configured to: if the data stored in the third storage cell row among the multiple first-type storage cell rows is erroneous, determine the initial word line identifier corresponding to the physical word line identifier of the third storage cell row; obtain verification data based on the determined initial word line identifier; and correct the data stored in the third storage cell row based on the verification data.

[0240] For details on how the functions of the aforementioned peripheral circuits are implemented, please refer to [reference needed]. Figure 7 The embodiments shown will not be described in detail here.

[0241] In addition, embodiments of this application also provide a storage system including a memory and a controller coupled to the memory and configured to control the memory.

[0242] The controller is configured to send operation instructions to the memory, the operation instructions carrying multiple initial word line identifiers. The memory is configured to receive the operation instructions, map the multiple initial word line identifiers to multiple physical word line identifiers, and execute the operations corresponding to the operation instructions on multiple first-class memory cell rows through the multiple first-class word lines indicated by the multiple physical word line identifiers.

[0243] Among them, there is at least one third type of storage unit row distributed between the first and second storage unit rows in the multiple first type of storage unit rows, and the data stored in the multiple first type of storage unit rows corresponds to the same verification data.

[0244] Optionally, the controller is further configured to send a word line mapping instruction to the memory; the memory is further configured to, in response to the word line mapping instruction, perform an operation to map a plurality of initial word line identifiers to a plurality of physical word line identifiers.

[0245] Optionally, the controller is further configured to: not send word line mapping instructions to the memory; the memory is further configured to: perform operations corresponding to operation instructions on multiple second-type memory cell rows through multiple second-type word lines indicated by multiple initial word line identifiers. Here, the multiple second-type memory cell rows are multiple consecutive memory cell rows in the memory array, and the data stored in the multiple second-type memory cell rows corresponds to the same parity data.

[0246] Optionally, the operation instructions include write instructions, which also carry multiple data to be written, each corresponding one-to-one with a plurality of initial word line identifiers. The memory is configured to: treat the data to be written corresponding to each initial word line identifier as the data to be written corresponding to the corresponding physical word line identifier, and perform programming operations on a plurality of first-class memory cell rows through a plurality of first-class word lines to store the multiple data to be written into the plurality of first-class memory cell rows.

[0247] Optionally, the operation instructions include read instructions. The memory is configured to: perform read operations on multiple rows of first-class memory cells via multiple first-class word lines to obtain data stored in the multiple rows of first-class memory cells respectively; the memory is also configured to: send read data results to the controller, the read data results carrying the data stored in the multiple rows of first-class memory cells respectively; the controller is configured to: receive the read data results.

[0248] The implementation methods of the above-mentioned controller and memory functions can be referred to Figure 7 The embodiments shown will not be described in detail here.

[0249] Figure 13 This is a schematic diagram of the structure of a controller provided in an embodiment of this application. Figure 13 As shown, the controller 1300 includes a processing unit 1301, which may, for example, be an MCU (microcontroller unit) or the like.

[0250] The controller 1300 is used to implement the functions of the controller in the aforementioned embodiments, so as to realize the storage system provided in this application embodiment. For specific implementation details, please refer to... Figure 7 The embodiments shown will not be described in detail here.

[0251] In addition, embodiments of this application also provide a peripheral circuit, wherein the control logic unit of the peripheral circuit includes at least one software module, which is used to implement... Figure 7 Any step in the memory operation method of the illustrated embodiment.

[0252] In addition, embodiments of this application also provide a computer storage medium on which instructions are stored, which are executed by peripheral circuits in the memory. Figure 7 Any step in the memory operation method of the illustrated embodiment.

[0253] On the other hand, a computer program product containing instructions is provided, which is implemented when the instructions are executed in the peripheral circuit. Figure 7 Any step in the memory operation method of the illustrated embodiment.

[0254] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0255] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory, characterized in that, The memory includes: A storage array comprising multiple rows of storage cells; Multiple word lines, each word line being coupled to one of the multiple rows of memory cells; and Peripheral circuitry, coupled to the plurality of word lines and configured as follows: Receive an operation command from the controller, the operation command carrying multiple initial word line identifiers; Map the plurality of initial word line identifiers to a plurality of physical word line identifiers; The operation corresponding to the operation instruction is executed on multiple first-type memory cells through multiple first-type word lines indicated by the multiple physical word line identifiers; Among them, at least one third type of storage unit row is distributed between the first storage unit row and the second storage unit row in the plurality of first type of storage unit rows, and the data stored in the plurality of first type of storage unit rows corresponds to the same verification data.

2. The memory as claimed in claim 1, characterized in that, The peripheral circuit is configured as follows: Each initial word line identifier is treated as a pseudo word line identifier, and the physical word line identifier corresponding to each initial word line identifier is obtained from the stored mapping relationship between pseudo word line identifiers and physical word line identifiers.

3. The memory as described in claim 2, characterized in that, The mapping relationship includes the mapping relationship between the first pseudo-word line identifier and the first physical word line identifier, and the mapping relationship between the second pseudo-word line identifier and the second physical word line identifier; The two memory cell rows coupled to the two word lines indicated by the first pseudo-word line identifier and the second pseudo-word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical word line identifier.

4. The memory as described in claim 3, characterized in that, The first pseudo-character line is identified by the first pseudo-character line number, the second pseudo-character line is identified by the second pseudo-character line number, and the difference between the first pseudo-character line number and the second pseudo-character line number is 1; The first physical word line is identified as the first physical word line number, the second physical word line is identified as the second physical word line number, and the difference between the first physical word line number and the second physical word line number is greater than 1.

5. The memory as claimed in claim 4, characterized in that, The number of the first pseudo-character line is less than the number of the second pseudo-character line; The second physical word line number is the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

6. The memory as claimed in claim 1, characterized in that, In each of the plurality of first-class storage cell rows, at least one third-class storage cell row is distributed between every two adjacent storage cell rows.

7. The memory as claimed in claim 6, characterized in that, The number of third-class storage cell rows distributed between each pair of adjacent first-class storage cell rows is a reference number.

8. The memory as claimed in claim 1, characterized in that, The peripheral circuit is configured as follows: If a word line mapping instruction is received from the controller, the operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers is performed.

9. The memory as claimed in claim 8, characterized in that, The peripheral circuit is also configured to: If no word line mapping instruction is received from the controller, the operation corresponding to the operation instruction is performed on multiple second-type memory cell rows through multiple second-type word lines indicated by the multiple initial word line identifiers; The plurality of second-type storage cell rows are consecutive rows of storage cells in the storage array, and the data stored in the plurality of second-type storage cell rows corresponds to the same verification data.

10. The memory as claimed in claim 1, characterized in that, The operation instructions include a write instruction, which also carries multiple data to be written that correspond one-to-one with the multiple initial word line identifiers. The peripheral circuit is configured as follows: The data to be written corresponding to each initial word line identifier is taken as the data to be written corresponding to the corresponding physical word line identifier, and programming operations are performed on the multiple first-type storage cell rows through the multiple first-type word lines to store the multiple data to be written into the multiple first-type storage cell rows.

11. The memory as claimed in claim 1, characterized in that, The operation instructions include read instructions; The peripheral circuit is configured as follows: Read operations are performed on the multiple first-class word lines to obtain the data stored in the multiple first-class storage cell rows respectively.

12. The memory as claimed in claim 11, characterized in that, The peripheral circuit is also configured to: If the data stored in a third storage cell row among the plurality of first-class storage cell rows is erroneous, then an initial word line identifier corresponding to the physical word line identifier of the third storage cell row is determined; The verification data is obtained based on the determined initial word line identifier; The data stored in the third storage unit row is corrected based on the verification data.

13. A storage system, characterized in that, The storage system includes a memory and a controller coupled to the memory and configured to control the memory; The controller is configured to send an operation instruction to the memory, the operation instruction carrying multiple initial word line identifiers; The memory is configured to: receive the operation instruction, map the plurality of initial word line identifiers to a plurality of physical word line identifiers; and execute the operation corresponding to the operation instruction on a plurality of first-type memory cells through the plurality of first-type word lines indicated by the plurality of physical word line identifiers. Among them, at least one third type of storage unit row is distributed between the first storage unit row and the second storage unit row in the plurality of first type of storage unit rows, and the data stored in the plurality of first type of storage unit rows corresponds to the same verification data.

14. The storage system as claimed in claim 13, characterized in that, The controller is also configured to send word line mapping instructions to the memory; The memory is also configured to: in response to the word line mapping instruction, perform an operation to map the plurality of initial word line identifiers to the plurality of physical word line identifiers.

15. The storage system as claimed in claim 14, characterized in that, The controller is also configured to: not send the word line mapping instruction to the memory; The memory is further configured to perform the operation corresponding to the operation instruction on a plurality of second-type memory cell rows through a plurality of second-type word lines indicated by the plurality of initial word line identifiers; The plurality of second-type storage cell rows are consecutive rows of storage cells in the storage array of the memory, and the data stored in the plurality of second-type storage cell rows corresponds to the same verification data.

16. The storage system as claimed in claim 13, characterized in that, The operation instructions include a write instruction, which also carries multiple data to be written that correspond one-to-one with the multiple initial word line identifiers. The memory is configured to: treat the data to be written corresponding to each initial word line identifier as the data to be written corresponding to the corresponding physical word line identifier, and perform programming operations on the multiple first-type storage cell rows through the multiple first-type word lines to store the multiple data to be written into the multiple first-type storage cell rows.

17. The storage system as claimed in claim 13, characterized in that, The operation instructions include read instructions; The memory is configured to perform read operations on the plurality of first-type memory cell rows through the plurality of first-type word lines to obtain the data stored in the plurality of first-type memory cell rows respectively; The memory is further configured to send a read data result to the controller, the read data result carrying data stored in the plurality of first-type memory cell rows respectively; The controller is configured to receive the read data result.

18. A method for operating a memory, characterized in that, The method includes: Receive an operation command from the controller, the operation command carrying multiple initial word line identifiers; Map the plurality of initial word line identifiers to a plurality of physical word line identifiers; The operation corresponding to the operation instruction is executed on multiple first-type memory cells through multiple first-type word lines indicated by the multiple physical word line identifiers; Among them, at least one third type of storage unit row is distributed between the first storage unit row and the second storage unit row in the plurality of first type of storage unit rows, and the data stored in the plurality of first type of storage unit rows corresponds to the same verification data.

19. The method as described in claim 18, characterized in that, The step of mapping the plurality of initial word line identifiers to a plurality of physical word line identifiers includes: Each initial word line identifier is treated as a pseudo word line identifier, and the physical word line identifier corresponding to each initial word line identifier is obtained from the stored mapping relationship between pseudo word line identifiers and physical word line identifiers.

20. The method as described in claim 19, characterized in that, The mapping relationship includes the mapping relationship between the first pseudo-word line identifier and the first physical word line identifier, and the mapping relationship between the second pseudo-word line identifier and the second physical word line identifier; The two memory cell rows coupled to the two word lines indicated by the first pseudo-word line identifier and the second pseudo-word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical word line identifier.

21. The method as described in claim 20, characterized in that, The first pseudo-character line is identified by the first pseudo-character line number, the second pseudo-character line is identified by the second pseudo-character line number, and the difference between the first pseudo-character line number and the second pseudo-character line number is 1; The first physical word line is identified as the first physical word line number, the second physical word line is identified as the second physical word line number, and the difference between the first physical word line number and the second physical word line number is greater than 1.

22. The memory as claimed in claim 21, characterized in that, The number of the first pseudo-character line is less than the number of the second pseudo-character line; The second physical word line number is the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

23. The method as described in claim 18, characterized in that, In each of the plurality of first-class storage cell rows, at least one third-class storage cell row is distributed between every two adjacent storage cell rows.

24. The method as described in claim 23, characterized in that, The number of third-class storage cell rows distributed between each pair of adjacent first-class storage cell rows is a reference number.

25. The method as described in claim 18, characterized in that, The step of mapping the plurality of initial word line identifiers to a plurality of physical word line identifiers includes: If a word line mapping instruction is received from the controller, the operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers is performed.

26. The method as described in claim 25, characterized in that, The method further includes: If no word line mapping instruction is received from the controller, the operation corresponding to the operation instruction is performed on multiple second-type memory cell rows through multiple second-type word lines indicated by the multiple initial word line identifiers; The plurality of second-type storage cell rows are consecutive rows of storage cells in the storage array of the memory, and the data stored in the plurality of second-type storage cell rows corresponds to the same verification data.

27. The method as described in claim 18, characterized in that, The operation instructions include a write instruction, which also carries multiple data to be written that correspond one-to-one with the multiple initial word line identifiers. The operation corresponding to the operation instruction is executed on multiple first-type memory cells through multiple first-type word lines indicated by the multiple physical word line identifiers, including: The data to be written corresponding to each initial word line identifier is taken as the data to be written corresponding to the corresponding physical word line identifier, and programming operations are performed on the multiple first-type storage cell rows through the multiple first-type word lines to store the multiple data to be written into the multiple first-type storage cell rows.

28. The method as described in claim 18, characterized in that, The operation instructions include read instructions; The operation corresponding to the operation instruction is executed on multiple first-type memory cells through multiple first-type word lines indicated by the multiple physical word line identifiers, including: Read operations are performed on the multiple first-class word lines to obtain the data stored in the multiple first-class storage cell rows respectively.

29. The method as described in claim 28, characterized in that, The method further includes: If the data stored in a third storage cell row among the plurality of first-class storage cell rows is erroneous, then an initial word line identifier corresponding to the physical word line identifier of the third storage cell row is determined; The verification data is obtained based on the determined initial word line identifier; The data stored in the third storage unit row is corrected based on the verification data.

Images