Semiconductor device interface defect testing method and system

Abstract

The invention relates to the technical field of semiconductors, and provides a semiconductor device interface defect testing method and system. The method comprises the steps that a pulse voltage signal with a rising edge and a falling edge is applied to a grid electrode of the semiconductor device, in the rising edge stage, minority carriers are captured by interface defects, and substrate current generated by capturing the minority carriers by the interface defects is detected in real time within the time period when the capturing time is smaller than the rising edge time; in the falling edge stage, the interface defects release minority carriers, and in the time period when the release time is shorter than the falling edge time, recombination current generated by recombination of the minority carriers released by the interface defects and majority carriers is detected in real time; according to the substrate current and the recombination current which are detected in real time, the interface defect density with the capture time smaller than the rising edge time and the release time smaller than the falling edge time is calculated. According to the method, accurate characterization of interface defects of different time constants under specified bias voltage can be realized by regulating and controlling the numerical values of the rising edge time and the falling edge time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device interface defect testing method and system. Background Art

[0002] For semiconductor devices, especially metal oxide semiconductor (MOS) devices, the performance and reliability of MOS devices are related to the interface quality of the MOS interface. For MOSFET devices, the presence of interface defects can cause the threshold voltage of the device to drift, the degradation of the subthreshold swing, and the reduction of mobility under low field, which seriously affects the performance and reliability of the device. Therefore, it is necessary to characterize and analyze the interface defects of MOSFET devices.

[0003] At present, a large number of interface characterization techniques are focused on analyzing the density of interface defects and their distribution with energy levels. For example, traditional charge pump method, Terman method, conductivity method, S factor method and other methods require the characterization of interface capacitance, but due to various parasitic effects, the characterization of interface defects with a response frequency exceeding 2M (that is, interface defects formed at the contact point between two adjacent parts of the crystal due to different orientations, compositions, structures and lattice constants) will produce erroneous results. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a semiconductor device interface defect testing method and system.

[0005] The semiconductor device interface defect testing method provided by the present invention comprises:

[0006] At the first moment of low level, a pulse voltage signal with rising and falling edges is applied to the gate of the semiconductor device. In the rising edge stage, the interface defects of the semiconductor device capture minority carriers. In a time period when the capture time is less than the rising edge time, the substrate current generated by the minority carriers captured by the interface defects is detected in real time.

[0007] Keeping the gate biased at a high level voltage and maintaining it until the second moment to ensure that all interface defects capture minority carriers;

[0008] At the second moment of high level, the bias voltage of the gate gradually decreases to a low level. In the falling edge stage, the interface defects release minority carriers. In the time period when the release time is less than the falling edge time, the composite current generated by the recombination of the minority carriers released by the interface defects and the majority carriers in the semiconductor device is detected in real time.

[0009] According to the substrate current and the recombination current obtained by real-time detection, the interface defect density where the capture time is less than the rising edge time and the release time is less than the falling edge time is calculated.

[0010] In an embodiment of the present invention, the interface defect density where the capture time is less than the rising edge time and the release time is less than the falling edge time is calculated based on the substrate current and the composite current detected in real time, including:

[0011] Calculating the integral of the substrate current in a time period where the capture time is less than the rise time;

[0012] Calculate the integral of the composite current during the period where the release time is less than the falling edge time;

[0013] The difference between the integral of the substrate current and the integral of the recombination current was calculated as the interface defect density.

[0014] In the embodiment of the present invention, the calculation formula of the interface defect density is:

[0015]

[0016] Among them, D it is the interface defect density, t is the first moment, T rise is the rising edge time, t1 is the second moment, T fall is the falling edge time, I b The substrate current generated by the capture of minority carriers by interface defects, I b ' is the recombination current generated by the recombination of minority carriers released by interface defects with majority carriers in semiconductor devices, and dt is the integral function.

[0017] In an embodiment of the present invention, the method further includes:

[0018] The duration of the rising edge and the duration of the falling edge of the pulse voltage signal are changed to achieve the characterization of the interface defect density under different capture time constants and different release time constants.

[0019] In the embodiment of the present invention, the duration for maintaining the gate bias at a high level voltage is at least two orders of magnitude greater than the rising edge time and the falling edge time.

[0020] In an embodiment of the present invention, the doping type of the substrate of the semiconductor device is n-type, and the minority carriers captured by the interface defects are holes; or, the doping type of the substrate of the semiconductor device is p-type, and the minority carriers captured by the interface defects are electrons.

[0021] In an embodiment of the present invention, the doping type of the substrate of the semiconductor device is n-type, and the majority carriers in the semiconductor device are holes; or, the doping type of the substrate of the semiconductor device is p-type, and the majority carriers in the semiconductor device are electrons.

[0022] In the embodiment of the present invention, the low level is an off-state level of the semiconductor device, and the high level is an on-state level of the semiconductor device.

[0023] The present invention also provides a semiconductor device interface defect testing system, comprising:

[0024] A pulse signal generating device, used for generating a pulse voltage signal with a rising edge and a falling edge, and applying the pulse voltage signal to the gate of the semiconductor device;

[0025] The current detection device is used to detect in real time the substrate current generated by the interface defects capturing minority carriers during the rising edge stage, during the period when the capturing time is less than the rising edge time; after all the interface defects have captured minority carriers, in the falling edge stage, during the process of the interface defects releasing minority carriers, during the period when the releasing time is less than the falling edge time, to detect in real time the composite current generated by the minority carriers released by the interface defects and the majority carriers in the semiconductor device.

[0026] The calculation module is used to calculate the interface defect density whose capture time is less than the rising edge time and whose release time is less than the falling edge time according to the substrate current and the composite current detected in real time.

[0027] The present invention uses the substrate current generated by the capture and release process of minority carriers by interface defects as a basis to accurately evaluate the MOS interface defect density under different time constants. The interface defect testing method of the present invention has the advantages of large window, high precision, simple test system construction, etc., and can realize the defect characterization at different time constants at the interface of semiconductor devices.

[0028] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0030] Figure 1 is a flow chart of a semiconductor device interface defect testing method provided by an embodiment of the present invention;

[0031] Figure 2 It is a structural diagram of the test system of the double pulse charge pump method;

[0032] Figure 3 is a graph of the applied gate voltage versus time in the dual-pulse charge pump method;

[0033] Figure 4 Is the rising edge T rise Stage, schematic diagram of carrier capture by interface defects;

[0034] Figure 5 is the falling edge T fall Schematic diagram of the interface defect releasing carriers in the first stage;

[0035] Figure 6 This is the distribution diagram of interface defects under different capture time and release time. DETAILED DESCRIPTION

[0036] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0037] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0038] As introduced in the background technology, existing interface characterization technologies are focused on analyzing the density of interface defects and their distribution with energy levels. Traditional methods require characterization of interface capacitance, but due to various parasitic effects, characterization of interface defects with response frequencies exceeding 2M will produce erroneous results. The traditional method of analyzing the time constant and release time constant of interface defects by statistical methods has problems such as small window and difficult analysis and processing, and cannot achieve accurate characterization of interface defects under different capture constants and release time constants.

[0039] In response to the above problems, the inventors found that the traditional charge pump method for characterizing interface defects uses the capture and release process of carriers by interface defects, and does not need to measure the capacitance of the interface, which is expected to achieve accurate characterization of the interface defect density under different time constants of the MOS interface large window. Therefore, a new interface defect characterization technology was studied based on the traditional charge pump method to analyze the capture time constant and release time constant of interface defects.

[0040] The embodiment of the present invention provides a semiconductor device interface defect testing method, which is based on the dual-pulse charge-pumping method to characterize the interface defect density at different response time constants at the interface of the MOS device in real time. The method uses the substrate current generated by the capture and release process of minority carriers by interface defects as a basis to accurately evaluate the MOS interface defect density at different time constants. The method applies a pulse voltage with a rising edge and a falling edge to the gate of the MOS device. During the rising edge, the MOS interface defects begin to capture minority carriers and generate substrate current. Only interface defects with a capture time less than the rising edge time can capture carriers during the rising edge. Similarly, during the falling edge stage, the MOS interface defects begin to release minority carriers. The majority carriers and minority carriers recombine to generate substrate current. Only interface defects with a release time constant less than the falling edge time release carriers during the falling edge. By integrating and then subtracting the current values ​​during the rising and falling edges, the density of interface defects within the specified time constant interval can be obtained. Then, by adjusting the values ​​of the rising and falling edge times, the accurate characterization of MOS interface defects with different time constants under a specified bias can be achieved. The method has the advantages of large window, high precision, and simple system construction, and can achieve defect characterization at different time constants at the interface of semiconductor devices.

[0041] The technical solution of the present invention is described in detail below through specific embodiments. It should be noted that the embodiment of the present invention only takes MOSFET devices as an example to describe the characterization of interface defects of MOSFET devices. The semiconductor devices involved in the technical solution of the present invention include but are not limited to field effect transistors (MOSFET), MOS capacitor devices, etc.

[0042] Figure 1 FIG. 1 is a flow chart of a semiconductor device interface defect testing method provided by an embodiment of the present invention. Figure 1 As shown, the semiconductor device interface defect testing method of this embodiment includes the following steps:

[0043] S101, at the first moment of low level, a pulse voltage signal with rising and falling edges is applied to the gate of the semiconductor device, in the rising edge stage, the interface defects of the semiconductor device capture minority carriers, and in a time period when the capture time is less than the rising edge time, the substrate current generated by the interface defects capturing minority carriers is detected in real time;

[0044] S102, keeping the gate biased at a high level voltage and maintaining it until a second moment to ensure that all interface defects capture minority carriers;

[0045] S103, at the second moment of the high level, the bias voltage of the gate gradually decreases to a low level, and in the falling edge stage, the interface defects release minority carriers, and in a time period where the release time is less than the falling edge time, the recombination current generated by the recombination of the minority carriers released by the interface defects and the majority carriers in the semiconductor device is detected in real time;

[0046] S104, calculating the interface defect density where the capture time is less than the rising edge time and the release time is less than the falling edge time according to the substrate current and the recombination current detected in real time.

[0047] Specifically, in the above step S104, the integral of the substrate current in the time period when the capture time is less than the rising edge time is first calculated, and then the integral of the composite current in the time period when the release time is less than the falling edge time is calculated, and then the difference between the integral of the substrate current and the integral of the composite current is calculated to obtain the interface defect density.

[0048] Specifically, the method further includes the following steps: changing the duration of the rising edge and the duration of the falling edge of the pulse voltage signal to achieve characterization of the interface defect density under different capture time constants and different release time constants.

[0049] In a specific embodiment, the method steps for characterizing the interface defect density at different response time constants in a MOS device based on a dual pulse charge pump method are as follows:

[0050] (1) At the low level time t, a pulse voltage signal with rising and falling edges is applied to the gate of the semiconductor device. capture Less than the rising edge time T rise The substrate current I generated by capturing minority carriers from interface defects of semiconductor devices is detected in real time within a period of time. b ;

[0051] (2) keeping the gate biased at a high level voltage until time t1, ensuring that all interface defects capture minority carriers, that is, ensuring that all interface defects are filled;

[0052] (3) At the high level t1, the gate bias voltage gradually drops to the low level voltage, and the falling edge time is T fall , at the release time T emission Less than the falling edge time T fall During the time period, the interface defects of semiconductor devices release minority carriers, and the composite current I generated by the recombination of minority carriers released by interface defects and majority carriers in semiconductor devices is detected in real time. b ';

[0053] (4) Based on the substrate current I obtained by real-time detection b and the composite current I b 'Calculate the capture time T capture Less than the rising edge time T rise , and the release time T emission Less than the falling edge time T fall The interface defect density is calculated as follows:

[0054]

[0055] Among them, D it is the interface defect density, T rise is the rising edge time, T fall is the falling edge time, I b The substrate current generated by the capture of minority carriers by interface defects, I b ' is the recombination current generated by the recombination of minority carriers released by interface defects with majority carriers in semiconductor devices, and dt is the integral function.

[0056] (5) By changing the rising edge time T rise The size and falling edge time T fall The size of can be used to characterize the interface defect density under different capture time constants and release time constants.

[0057] In a specific embodiment, the duration of maintaining the gate bias at a high level voltage is relative to the rising edge time T rise and falling edge time T fall , at least two orders of magnitude larger than them.

[0058] In a specific embodiment, in the above step S101, if the doping type of the substrate of the semiconductor device is n-type, the minority carriers captured by the interface defects are holes; if the doping type of the substrate of the semiconductor device is p-type, the minority carriers captured by the interface defects are electrons.

[0059] In a specific embodiment, in the above step S103, if the doping type of the substrate of the semiconductor device is n-type, the majority carriers in the semiconductor device are holes; if the doping type of the substrate of the semiconductor device is p-type, the majority carriers in the semiconductor device are electrons.

[0060] It should be noted that in the above embodiments, only the capture process of carriers by interface defects is considered in the rising edge stage, and only the release process of carriers by interface defects is considered in the falling edge stage. The "high level" and "low level" described in the above embodiments are not the actual numerical values ​​of the levels, but are only a description to distinguish two different gate voltage values. "High level" refers to the on-state level of the device, and "low level" refers to the off-state level of the device.

[0061] The embodiment of the present invention also provides a semiconductor device interface defect testing system, comprising: a pulse signal generating device, a current detection device and an operation module. The pulse signal generating device is used to generate a pulse voltage signal with a rising edge and a falling edge, and apply the pulse voltage signal to the gate of the semiconductor device. The current detection device is used to detect the substrate current generated by the interface defects capturing minority carriers in real time during the rising edge stage, in the process of the interface defects of the semiconductor device capturing minority carriers, in the time period when the capture time is less than the rising edge time; after all the interface defects have captured minority carriers, in the falling edge stage, in the process of the interface defects releasing minority carriers, in the time period when the release time is less than the falling edge time, the composite current generated by the minority carriers released by the interface defects and the majority carriers in the semiconductor device is detected in real time. The operation module is used to calculate the interface defect density with a capture time less than the rising edge time and a release time less than the falling edge time according to the substrate current and the composite current obtained by real-time detection. By adjusting the values ​​of the rising edge and falling edge time of the pulse voltage signal by the pulse signal generating device, the accurate characterization of interface defects with different time constants under a specified bias voltage can be achieved.

[0062] In one example, using Figure 2 The test system shown in FIG. 1 is based on the dual-pulse charge pump method to characterize the interface defect density at different response time constants in MOS devices. Figure 3 As shown in the figure, the voltage applied to the gate in the dual pulse charge pump method changes with time, and the time t0-t1 is the rising edge T rise And, t2-t3 time is the falling edge T fall Taking a conventional Si nMOSFET device as an example, the method includes the following steps:

[0063] (1) First, at t = 1s, a pulse voltage signal with a rising edge is applied to the gate of the MOS device. The rising edge time T rise =10ns, high level voltage V g1=3V, capture time T capture Less than T rise Interface defects capture minority carriers to generate I b , real-time detection of the rising edge device I b ,like Figure 4 As shown;

[0064] (2) Secondly, keep the gate biased at a high level voltage until time t = 1.00001s to ensure that all interface defects are filled;

[0065] (3) Then, at t = 1.00001s, the gate bias gradually drops to a low level, and the low level voltage V g2 =0V, falling edge time T fall =5ns, release time T emission Less than T fall The interface defects release minority carriers, and the majority carriers and minority carriers recombine to produce I b ', real-time detection of the falling edge device's I b ',like Figure 5 As shown;

[0066] (4) Then, by calculating the integral, we can get T capture Less than T rise , and T emission Less than T fall The interface defect density D it ,

[0067] (5) Finally, by changing T rise and T fall size, to achieve the characterization of interface defect density under different capture time constants and different release time constants, such as Figure 6 shown.

[0068] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The schemes in the embodiments of the present invention may be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0069] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0070] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0071] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0072] Although preferred embodiments of the present invention have been described, additional changes and modifications may be made to these embodiments by those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A semiconductor device interface defect testing method, characterized in that: include: At the first moment of low level, a pulse voltage signal with rising and falling edges is applied to the gate of the semiconductor device. In the rising edge stage, the interface defects of the semiconductor device capture minority carriers. In a time period when the capture time is less than the rising edge time, the substrate current generated by the minority carriers captured by the interface defects is detected in real time. Keeping the gate biased at a high level voltage and maintaining it until the second moment to ensure that all interface defects capture minority carriers; At the second moment of high level, the bias voltage of the gate gradually decreases to a low level. In the falling edge stage, the interface defects release minority carriers. In the time period when the release time is less than the falling edge time, the composite current generated by the recombination of the minority carriers released by the interface defects and the majority carriers in the semiconductor device is detected in real time. According to the substrate current and the recombination current obtained by real-time detection, the interface defect density where the capture time is less than the rising edge time and the release time is less than the falling edge time is calculated.

2. The semiconductor device interface defect testing method according to claim 1, characterized in that: According to the substrate current and the composite current obtained by real-time detection, the interface defect density whose capture time is less than the rising edge time and whose release time is less than the falling edge time is calculated, including: Calculating the integral of the substrate current in a time period where the capture time is less than the rise time; Calculate the integral of the composite current during the period where the release time is less than the falling edge time; The difference between the integral of the substrate current and the integral of the recombination current was calculated as the interface defect density.

3. The semiconductor device interface defect testing method according to claim 2, characterized in that: The calculation formula of the interface defect density is: Among them, D it is the interface defect density, t is the first moment, T rise is the rising edge time, t1 is the second moment, T fall is the falling edge time, I b The substrate current generated by the capture of minority carriers by interface defects, I b ' is the recombination current generated by the recombination of minority carriers released by interface defects with majority carriers in semiconductor devices, and dt is the integral function.

4. The semiconductor device interface defect testing method according to claim 1, characterized in that: The method further comprises: The duration of the rising edge and the duration of the falling edge of the pulse voltage signal are changed to achieve the characterization of the interface defect density under different capture time constants and different release time constants.

5. The semiconductor device interface defect testing method according to claim 1, characterized in that: The duration for maintaining the gate bias at a high level voltage is at least two orders of magnitude greater than the rising edge time and the falling edge time.

6. The semiconductor device interface defect testing method according to claim 1, characterized in that: The doping type of the substrate of the semiconductor device is n-type, and the minority carriers captured by the interface defects are holes; Alternatively, the doping type of the substrate of the semiconductor device is p-type, and the minority carriers captured by the interface defects are electrons.

7. The semiconductor device interface defect testing method according to claim 1, characterized in that: The doping type of the substrate of the semiconductor device is n-type, and the majority carriers in the semiconductor device are holes; Alternatively, the doping type of the substrate of the semiconductor device is p-type, and the majority carriers in the semiconductor device are electrons.

8. The semiconductor device interface defect testing method according to claim 1, characterized in that: The low level is an off-state level of the semiconductor device, and the high level is an on-state level of the semiconductor device.

9. The semiconductor device interface defect testing method according to claim 1, characterized in that: The semiconductor device is a MOSFET device or a MOS capacitor device.

10. A semiconductor device interface defect testing system, characterized in that: include: A pulse signal generating device, used for generating a pulse voltage signal with a rising edge and a falling edge, and applying the pulse voltage signal to the gate of the semiconductor device; The current detection device is used to detect in real time the substrate current generated by the interface defects capturing minority carriers during the rising edge stage, during the period when the capturing time is less than the rising edge time; after all the interface defects have captured the minority carriers, in the falling edge stage, during the process of the interface defects releasing the minority carriers, during the period when the releasing time is less than the falling edge time, to detect in real time the composite current generated by the minority carriers released by the interface defects and the majority carriers in the semiconductor device. The calculation module is used to calculate the interface defect density whose capture time is less than the rising edge time and whose release time is less than the falling edge time according to the substrate current and the composite current detected in real time.

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