Semiconductor device interface defect testing method and system

Abstract

The present invention relates to the field of semiconductor technology, and provides a method and system for testing interface defects in semiconductor devices. The method comprises: applying a pulse voltage signal with a rising edge and a falling edge to the gate of the semiconductor device; during the rising edge phase, the interface defects capture minority carriers; and in a time period where the capture time is less than the rising edge time, detecting in real time the substrate current generated by the minority carriers captured by the interface defects; during the falling edge phase, the interface defects release minority carriers; and in a time period where the release time is less than the falling edge time, detecting in real time the recombination current generated by the minority carriers released by the interface defects and the majority carriers; and calculating, based on the substrate current and recombination current detected in real time, the density of interface defects where the capture time is less than the rising edge time and the release time is less than the falling edge time. The present invention can achieve accurate characterization of interface defects with different time constants under a specified bias voltage by regulating the values of the rising edge and falling edge times.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and system for testing interface defects of semiconductor devices. Background Art

[0002] For semiconductor devices, especially metal oxide semiconductor (MOS) devices, MOS device performance and reliability are closely related to the quality of the MOS interface. For MOSFET devices, the presence of interface defects can cause threshold voltage drift, degradation of subthreshold swing, and reduction of low-field mobility, severely impacting device performance and reliability. Therefore, characterization and analysis of MOSFET interface defects are essential.

[0003] At present, a large number of interface characterization technologies are focused on analyzing the density of interface defects and their distribution with energy levels. For example, traditional charge pump method, Terman method, conductivity method, S-factor method and other methods require the characterization of interface capacitance, but due to various parasitic effects, the characterization of interface defects with a response frequency exceeding 2M (that is, interface defects formed at the contact point between two adjacent parts of the crystal due to different orientations, compositions, structures and lattice constants) will produce erroneous results. Summary of the Invention

[0004] In order to solve the above problems, the present invention provides a method and system for testing interface defects of semiconductor devices.

[0005] The present invention provides a method for testing interface defects of semiconductor devices, comprising:

[0006] At the first low-level moment, a pulse voltage signal with a rising edge and a falling edge is applied to the gate of the semiconductor device. During the rising edge phase, the interface defects of the semiconductor device capture minority carriers. During a period where the capture time is less than the rising edge time, the substrate current generated by the minority carriers captured by the interface defects is detected in real time.

[0007] Keeping the gate bias at a high voltage level and maintaining it until the second moment to ensure that all interface defects capture minority carriers;

[0008] At the second moment of high level, the bias voltage of the gate gradually drops to a low level. During the falling edge stage, the interface defects release minority carriers. During the period when the release time is less than the falling edge time, the recombination current generated by the recombination of the minority carriers released by the interface defects and the majority carriers in the semiconductor device is detected in real time.

[0009] Based on the substrate current and recombination current obtained by real-time detection, the interface defect density where the capture time is less than the rising edge time and the release time is less than the falling edge time is calculated.

[0010] In an embodiment of the present invention, the interface defect density where the capture time is less than the rising edge time and the release time is less than the falling edge time is calculated based on the substrate current and the recombination current obtained by real-time detection, including:

[0011] Calculating the integral of the substrate current during a period where the capture time is less than the rise time;

[0012] Calculate the integral of the composite current during the period where the release time is less than the falling edge time;

[0013] The difference between the integral of the substrate current and the integral of the recombination current was calculated as the interface defect density.

[0014] In the embodiment of the present invention, the calculation formula of the interface defect density is:

[0015] ;

[0016] Among them, D it is the interface defect density, t0 is the first moment, T rise is the rising edge time, t2 is the second moment, T fall is the falling edge time, I b The substrate current generated by the capture of minority carriers by interface defects, I b ' is the recombination current generated by the recombination of minority carriers released by interface defects with majority carriers in the semiconductor device, and dt is the integral function.

[0017] In an embodiment of the present invention, the method further includes:

[0018] The duration of the rising edge and the duration of the falling edge of the pulse voltage signal are changed to achieve the characterization of the interface defect density under different capture time constants and different release time constants.

[0019] In the embodiment of the present invention, the duration for maintaining the gate bias at a high-level voltage is at least two orders of magnitude greater than the rising edge time and the falling edge time.

[0020] In an embodiment of the present invention, the doping type of the substrate of the semiconductor device is n-type, and the minority carriers captured by the interface defects are holes; or, the doping type of the substrate of the semiconductor device is p-type, and the minority carriers captured by the interface defects are electrons.

[0021] In an embodiment of the present invention, the doping type of the substrate of the semiconductor device is n-type, and the majority carriers in the semiconductor device are holes; or, the doping type of the substrate of the semiconductor device is p-type, and the majority carriers in the semiconductor device are electrons.

[0022] In the embodiment of the present invention, the low level is an off-state level of the semiconductor device, and the high level is an on-state level of the semiconductor device.

[0023] The present invention also provides a semiconductor device interface defect testing system, comprising:

[0024] a pulse signal generating device for generating a pulse voltage signal with a rising edge and a falling edge, and applying the pulse voltage signal to the gate of the semiconductor device;

[0025] The current detection device is used to detect in real time the substrate current generated by the interface defects capturing minority carriers during the rising edge phase, during a period in which the capture time is less than the rising edge time; and to detect in real time the recombination current generated by the minority carriers released by the interface defects and the majority carriers in the semiconductor device during the falling edge phase, during a period in which the release time is less than the falling edge time, after all the interface defects have captured the minority carriers.

[0026] The calculation module is used to calculate the interface defect density with a capture time less than the rising edge time and a release time less than the falling edge time based on the substrate current and the composite current obtained by real-time detection.

[0027] This method uses the substrate current generated by the capture and release of minority carriers by interface defects to accurately assess MOS interface defect density at different time constants. This interface defect testing method offers advantages such as a large window, high accuracy, and simple test system setup, enabling characterization of defects at semiconductor device interfaces at different time constants.

[0028] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0030] Figure 1 This is a flow chart of a semiconductor device interface defect testing method provided by one embodiment of the present invention;

[0031] Figure 2 This is a structural diagram of the test system of the dual-pulse charge pump method;

[0032] Figure 3 is a graph showing the change in gate voltage applied over time in the dual-pulse charge pump method;

[0033] Figure 4 Is the rising edge T rise Stage, schematic diagram of carrier capture by interface defects;

[0034] Figure 5 Is the falling edge T fall Schematic diagram of the interface defect releasing carriers in the stage;

[0035] Figure 6 This is the distribution diagram of interface defects under different capture time and release time. DETAILED DESCRIPTION

[0036] To make the technical solutions and advantages of the embodiments of the present invention more clearly understood, exemplary embodiments of the present invention are further described in detail below with reference to the accompanying drawings. It should be noted that the embodiments described are only a portion of the embodiments of the present invention, and are not an exhaustive list of all embodiments. It should be noted that the embodiments of the present invention and the features thereof may be combined with each other unless they conflict.

[0037] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of such features.

[0038] As described in the background, existing interface characterization techniques focus on analyzing the density of interface defects and their distribution with energy levels. Traditional methods require characterizing interface capacitance, but various parasitic effects can lead to erroneous results when characterizing interface defects with a response frequency exceeding 2 MHz. Traditional statistical methods for analyzing the time constants and release time constants of interface defects suffer from a small window and difficult analysis and processing, making it impossible to accurately characterize interface defects at different capture and release time constants.

[0039] To address these issues, the inventors discovered that the traditional charge pump method for characterizing interface defects exploits the carrier capture and release processes of interface defects and does not require measuring the interface capacitance. This method offers the potential for accurately characterizing interface defect density across a large MOS interface window at varying time constants. Therefore, a new interface defect characterization technique, based on the traditional charge pump method, was developed to analyze the capture and release time constants of interface defects.

[0040] An embodiment of the present invention provides a semiconductor device interface defect testing method based on a dual-pulse charge-pumping method to characterize the interface defect density at different response time constants at the MOS device interface in real time. This method utilizes the substrate current generated by the capture and release of minority carriers by interface defects to accurately assess the MOS interface defect density at different time constants. This method applies a pulse voltage with rising and falling edges to the gate of the MOS device. During the rising edge, MOS interface defects begin to capture minority carriers, generating substrate current. Only interface defects with a capture time shorter than the rising edge can capture carriers during the rising edge. Similarly, during the falling edge, MOS interface defects begin to release minority carriers. Majority carriers and minority carriers recombine to generate substrate current. Only interface defects with a release time constant shorter than the falling edge can release carriers during the falling edge. By integrating and then subtracting the current values during the rising and falling edges, the density of interface defects within a specified time constant interval can be determined. Subsequently, by adjusting the rising and falling edge times, the MOS interface defects with different time constants under a specified bias voltage can be accurately characterized. This method has the advantages of a large window, high accuracy, and simple system setup, and can characterize defects at different time constants at the interface of semiconductor devices.

[0041] The following describes the technical solution of the present invention in detail through specific embodiments. It should be noted that the present embodiments use MOSFET devices as an example only to describe the characterization of interface defects in MOSFET devices. The semiconductor devices involved in the technical solution of the present invention include, but are not limited to, field-effect transistors (MOSFETs), MOS capacitors, and the like.

[0042] Figure 1 FIG. 1 is a flow chart of a method for testing interface defects of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device interface defect testing method of this embodiment includes the following steps:

[0043] S101, at a first low-level moment, applying a pulse voltage signal with a rising edge and a falling edge to the gate of the semiconductor device, wherein during the rising edge phase, interface defects of the semiconductor device capture minority carriers, and within a time period where the capture time is less than the rising edge time, detecting in real time the substrate current generated by the minority carriers captured by the interface defects;

[0044] S102, keeping the gate biased at a high level voltage and maintaining it until a second moment to ensure that all interface defects capture minority carriers;

[0045] S103, at the second moment of the high level, the bias voltage of the gate gradually decreases to a low level. During the falling edge phase, the interface defects release minority carriers. During a period where the release time is less than the falling edge time, the recombination current generated by the minority carriers released by the interface defects and the majority carriers in the semiconductor device is detected in real time.

[0046] S104 , calculating the interface defect density where the capture time is less than the rising edge time and the release time is less than the falling edge time based on the substrate current and the recombination current detected in real time.

[0047] Specifically, in the above step S104, the integral of the substrate current in the time period when the capture time is less than the rising edge time is first calculated, then the integral of the recombination current in the time period when the release time is less than the falling edge time is calculated, and then the difference between the integral of the substrate current and the integral of the recombination current is calculated to obtain the interface defect density.

[0048] Specifically, the above method further includes the following steps: changing the duration of the rising edge and the duration of the falling edge of the pulse voltage signal to achieve characterization of the interface defect density under different capture time constants and different release time constants.

[0049] In a specific embodiment, the method steps for characterizing the interface defect density of a MOS device at different response time constants based on a dual-pulse charge pump method are as follows:

[0050] (1) At the low level t0, a pulse voltage signal with rising and falling edges is applied to the gate of the semiconductor device. T capture Less than rising edge time T rise Real-time detection of semiconductor device interface defects and substrate current generated by capturing minority carriers within a certain period of time I b ;

[0051] (2) Keep the gate bias at a high level voltage from time t1 to time t2 to ensure that all interface defects capture minority carriers, that is, to ensure that all interface defects are filled;

[0052] (3) From the high level t2 to t3, the gate bias voltage gradually drops to the low level voltage, and the falling edge time is T fall , at the release time T emission Less than the falling edge time T fall During the time period, the interface defects of semiconductor devices release minority carriers, and the recombination current generated by the recombination of minority carriers released by interface defects and majority carriers in semiconductor devices is detected in real time. I b ';

[0053] (4) Substrate current obtained based on real-time detection I b and the composite current I b 'Calculate capture time T capture Less than rising edge time T rise , and release time T emission Less than the falling edge time T fall The interface defect density is calculated as follows:

[0054] ;

[0055] in, D it is the interface defect density, T rise is the rising edge time, T fall is the falling edge time, I b The substrate current is generated by the capture of minority carriers by interface defects. I b ' is the recombination current generated by the recombination of minority carriers released by interface defects with majority carriers in semiconductor devices, dt is the integral function.

[0056] (5) By changing the rising edge time T rise The size and falling edge time T fall The size of can be used to characterize the interface defect density under different capture time constants and release time constants.

[0057] In one embodiment, the duration of maintaining the gate bias at a high level voltage is relative to the rising edge time. Trise and falling edge time T fall , which is at least two orders of magnitude larger than them.

[0058] In a specific embodiment, in the above step S101, if the doping type of the substrate of the semiconductor device is n-type, the minority carriers captured by the interface defects are holes; if the doping type of the substrate of the semiconductor device is p-type, the minority carriers captured by the interface defects are electrons.

[0059] In a specific embodiment, in the above step S103, if the doping type of the substrate of the semiconductor device is n-type, the majority carriers in the semiconductor device are holes; if the doping type of the substrate of the semiconductor device is p-type, the majority carriers in the semiconductor device are electrons.

[0060] It should be noted that in the above embodiments, only the carrier capture process by interface defects is considered during the rising phase, and only the carrier release process by interface defects is considered during the falling phase. The "high level" and "low level" described in the above embodiments do not represent actual numerical values; they are merely descriptors used to distinguish between two different gate voltage values. "High level" refers to the device's on-state voltage, and "low level" refers to the device's off-state voltage.

[0061] An embodiment of the present invention also provides a semiconductor device interface defect testing system, comprising: a pulse signal generator, a current detection device, and a calculation module. The pulse signal generator is configured to generate a pulse voltage signal with rising and falling edges, and apply the pulse voltage signal to the gate of the semiconductor device. The current detection device is configured to detect in real time the substrate current generated by minority carrier capture by interface defects in the semiconductor device during the rising phase, when the capture time is less than the rising phase. After all interface defects have captured minority carriers, in the falling phase, when the interface defects release minority carriers, in real time, when the release time is less than the falling phase, the current detection device detects the recombination current generated by the minority carriers released from the interface defects and the majority carriers in the semiconductor device. The calculation module is configured to calculate, based on the substrate current and recombination current detected in real time, the density of interface defects with capture times less than the rising phase and release times less than the falling phase. By regulating the rising and falling phases of the pulse voltage signal through the pulse signal generator, accurate characterization of interface defects with different time constants under a specified bias voltage can be achieved.

[0062] In one example, using Figure 2 The test system shown in FIG. 1 is based on the dual-pulse charge pump method to characterize the interface defect density of MOS devices at different response time constants. Figure 3As shown in the figure, the voltage applied to the gate in the dual pulse charge pump method changes with time, and the time t0-t1 is the rising edge T rise , t2-t3 time is the falling edge T fall Taking a conventional Si nMOSFET device as an example, the method includes the following steps:

[0063] (1) First, at t=1s, a pulse voltage signal with a rising edge is applied to the gate of the MOS device. The rising edge time is T rise =10ns, high level voltage V g1 =3V, capture time T capture Less than T rise Interface defects capture minority carriers to generate I b , real-time detection of rising edge devices I b ,like Figure 4 As shown;

[0064] (2) Secondly, keep the gate bias at a high level voltage until time t = 1.00001s to ensure that all interface defects are filled;

[0065] (3) Then, at t=1.00001s, the gate bias gradually drops to a low level, and the low-level voltage V g2 =0V, falling edge time T fall = 5ns, release time T emission Less than T fall The interface defects release minority carriers, and the majority carriers and minority carriers recombine to produce I b ', real-time detection of falling edge devices I b ',like Figure 5 As shown;

[0066] (4) Then, by calculating the integral, we can get T capture Less than T rise ,and T emission Less than T fall Interface defect density D it ,

[0067] ;

[0068] (5) Finally, by changing T rise as well as T fall size, to achieve the characterization of interface defect density under different capture time constants and different release time constants, such as Figure 6 shown.

[0069] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk drives, CD-ROMs, optical storage devices, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention may be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0070] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0071] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0072] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0073] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such changes and modifications as fall within the scope of the claims and their equivalents.

Claims

1. A method for testing interface defects of a semiconductor device, characterized in that: include: At the first low-level moment, a pulse voltage signal with a rising edge and a falling edge is applied to the gate of the semiconductor device. During the rising edge phase, the interface defects of the semiconductor device capture minority carriers. During a period where the capture time is less than the rising edge time, the substrate current generated by the minority carriers captured by the interface defects is detected in real time. Keeping the gate bias at a high voltage level and maintaining it until the second moment to ensure that all interface defects capture minority carriers; At the second moment of high level, the bias voltage of the gate gradually drops to a low level. During the falling edge stage, the interface defects release minority carriers. During the period when the release time is less than the falling edge time, the recombination current generated by the recombination of the minority carriers released by the interface defects and the majority carriers in the semiconductor device is detected in real time. Based on the substrate current and recombination current obtained by real-time detection, the interface defect density where the capture time is less than the rising edge time and the release time is less than the falling edge time is calculated.

2. The semiconductor device interface defect testing method according to claim 1, wherein: Based on the substrate current and recombination current obtained by real-time detection, the interface defect density where the capture time is less than the rising edge time and the release time is less than the falling edge time is calculated, including: Calculating the integral of the substrate current during a period where the capture time is less than the rise time; Calculate the integral of the composite current during the period where the release time is less than the falling edge time; The difference between the integral of the substrate current and the integral of the recombination current is calculated as the integral value of the interface defect density.

3. The semiconductor device interface defect testing method according to claim 2, wherein: The calculation formula of the interface defect density is: ； Among them, D it is the interface defect density, t0 is the first moment, T rise is the rising edge time, t2 is the second moment, T fall is the falling edge time, I b The substrate current generated by the capture of minority carriers by interface defects, I b ' is the recombination current generated by the recombination of minority carriers released by interface defects with majority carriers in the semiconductor device, and dt is the integral function.

4. The semiconductor device interface defect testing method according to claim 1, wherein: The method further comprises: The duration of the rising edge and the duration of the falling edge of the pulse voltage signal are changed to achieve the characterization of the interface defect density under different capture time constants and different release time constants.

5. The semiconductor device interface defect testing method according to claim 1, wherein: The duration for maintaining the gate bias at the high-level voltage is at least two orders of magnitude greater than the rising edge time and the falling edge time.

6. The semiconductor device interface defect testing method according to claim 1, wherein: The doping type of the substrate of the semiconductor device is n-type, and the minority carriers captured by the interface defects are holes; Alternatively, the doping type of the substrate of the semiconductor device is p-type, and the minority carriers captured by the interface defects are electrons.

7. The semiconductor device interface defect testing method according to claim 1, wherein: The doping type of the substrate of the semiconductor device is n-type, and the majority carriers in the semiconductor device are holes; Alternatively, the doping type of the substrate of the semiconductor device is p-type, and the majority carriers in the semiconductor device are electrons.

8. The semiconductor device interface defect testing method according to claim 1, wherein: The low level is an off-state level of the semiconductor device, and the high level is an on-state level of the semiconductor device.

9. The semiconductor device interface defect testing method according to claim 1, wherein: The semiconductor device is a MOSFET device or a MOS capacitor device.

10. A semiconductor device interface defect testing system, characterized in that: include: a pulse signal generating device for generating a pulse voltage signal with a rising edge and a falling edge, and applying the pulse voltage signal to the gate of the semiconductor device; The current detection device is used to detect in real time the substrate current generated by the interface defects capturing minority carriers during the rising edge phase, during a period in which the capture time is less than the rising edge time; and to detect in real time the recombination current generated by the minority carriers released by the interface defects and the majority carriers in the semiconductor device during the falling edge phase, during a period in which the release time is less than the falling edge time, after all the interface defects have captured the minority carriers. The calculation module is used to calculate the interface defect density with a capture time less than the rising edge time and a release time less than the falling edge time based on the substrate current and the composite current obtained by real-time detection.

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