A solar cell, a method for manufacturing the same, a stacked cell, and a photovoltaic module

Abstract

The application discloses a solar cell, a preparation method of the solar cell, a laminated cell and a photovoltaic module, and belongs to the technical field of semiconductors. The solar cell comprises a semiconductor substrate and a first locally heavily doped semiconductor layer located on a main surface of the semiconductor substrate. The first locally heavily doped semiconductor layer has the same or opposite conductivity type as the semiconductor substrate, and the doping concentration of an edge region of the first locally heavily doped semiconductor layer is higher than that of a central region. The doping concentration of the first locally heavily doped semiconductor layer is optimized and designed, so that the doping concentration of the edge region is higher than that of the central region, thereby effectively inhibiting the serious carrier recombination phenomenon existing at the edge of the contact window of the locally doped semiconductor layer, fundamentally strengthening the field effect passivation ability of the edge, and effectively reducing the edge recombination current density to a very low level and improving the open circuit voltage and the fill factor of the cell.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and more specifically, relates to a solar cell, its preparation method, and tandem cells and photovoltaic modules. Background Technology

[0002] A solar cell is a photoelectric conversion semiconductor device, typically a homojunction diode structure formed from a single semiconductor material, or a heterojunction (HJT) diode structure formed by combining two or more semiconductor materials. The semiconductor material absorbs sunlight from the environment, generating electrons and holes, commonly referred to as photogenerated carriers. After being separated by the built-in electric field of the diode, electrons and holes accumulate in the n-type and p-type semiconductor regions, respectively, forming a potential.

[0003] As crystalline silicon solar cells advance towards higher efficiency, passivated contact structures based on doped polycrystalline silicon have become a key path to improve performance. However, in the fabrication process of this type of cell, selective patterning and windowing of the doped region across the entire surface is required (for example, in BC cells, the contact area between the metal electrode and the emitter / base is usually located on the back of the silicon wafer, and its complex patterned interface introduces a large number of etching edges; in bifacial cells, patterning is also performed to reduce parasitic absorption in the front crystalline silicon layer). This windowing etching process inevitably creates a large number of physical edges, disrupting the integrity of the crystal lattice and introducing high-density dangling bonds and defect states. These contact window edges become strong recombination centers for minority carriers, leading to severe edge recombination, significantly weakening the advantages of passivated contact structures, and particularly restricting the simultaneous optimization of open-circuit voltage and fill factor, becoming a recognized efficiency bottleneck in the industry.

[0004] Specifically, in traditional doped polycrystalline silicon passivated contact structures, uniform doping distribution and planar interface design are insufficient to effectively suppress carrier recombination at the contact window edges. Locally doped polycrystalline silicon fabricated using existing processes often has insufficient built-in electric field strength at the window edges, failing to effectively repel minority carriers. Simultaneously, sharp physical edges lead to concentrated electric field lines, forming electric field peaks that further exacerbate recombination. Furthermore, before lateral transport to the metal electrode, carriers must pass through these high-defect-density window edge regions; due to the lack of efficient longitudinal transport channels, their recombination probability increases significantly. These factors collectively constrain the open-circuit voltage and fill factor of the battery, becoming a key bottleneck limiting further improvements in conversion efficiency.

[0005] Therefore, effectively suppressing the severe carrier recombination phenomenon at the edge of the contact window of the locally doped semiconductor layer is of great significance for improving the open-circuit voltage and fill factor of the battery, and thus improving the battery conversion efficiency. Summary of the Invention

[0006] One of the objectives of this invention is to provide a solar cell that optimizes the doping concentration of the first locally heavily doped semiconductor layer so that the doping concentration of its edge region is higher than that of its center region. This effectively suppresses severe carrier recombination at the edge of the contact window of the locally doped semiconductor layer, fundamentally enhancing the field-effect passivation capability of the edge. Consequently, it can effectively reduce the edge recombination current density to an extremely low level and improve the open-circuit voltage and fill factor of the cell.

[0007] The second objective of this invention is to provide a method for preparing the above-mentioned solar cell. By employing a laser patterning process to selectively open the first doped semiconductor layer and precisely controlling the laser patterning process parameters, a local high-temperature field can be induced at the edge of the opened region, driving the doped elements to undergo directional redistribution towards the interface edge, thereby forming a selectively heavily doped region with a significantly higher doping concentration at the edge region than at the center region.

[0008] The present invention also provides a stacked battery, wherein the bottom cell of the stacked battery uses the above-mentioned solar cell.

[0009] The present invention also provides a photovoltaic module comprising the above-described solar cells or tandem cells.

[0010] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0011] The first aspect of the present invention provides a solar cell, comprising: Semiconductor substrate; A first locally heavily doped semiconductor layer located on a main surface of a semiconductor substrate, the conductivity type of the first locally heavily doped semiconductor layer being the same as or opposite to that of the semiconductor substrate, and the doping concentration of its edge region being higher than that of its center region; and A metal electrode is located on the side of the first partially heavily doped semiconductor layer away from the semiconductor substrate and forms an ohmic contact with the first partially heavily doped semiconductor layer.

[0012] According to any of the technical solutions described in the first aspect of the present invention, the first locally heavily doped semiconductor layer is N-type doped or P-type doped; wherein: If the first locally heavily doped semiconductor layer is N-type doped, the effective doping concentration in its edge region is 5 × 10⁻⁶. 20 cm -3 ~10×10 20 cm -3 The effective doping concentration in its central region is 1×10⁻⁶. 20 cm -3 ~5×10 20 cm-3 Alternatively, the effective doping concentration in the edge region may be 1.01 to 10 times that in the center region. If the first locally heavily doped semiconductor layer is P-type doped, its effective doping concentration in the edge region is 5 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3 The effective doping concentration in its central region is 2×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 Alternatively, the effective doping concentration in the edge region may be 1.1 to 100 times that in the center region.

[0013] According to any of the technical solutions described in the first aspect of the present invention, at least one main surface of the semiconductor substrate is provided with raised platforms that are raised relative to the surface and arranged in an array, and the first locally heavily doped semiconductor layer is correspondingly disposed on the raised platforms.

[0014] According to any of the technical solutions described in the first aspect of the present invention, the thickness of the first locally heavily doped semiconductor layer along the thickness direction of the solar cell is 0.05 μm to 5 μm.

[0015] According to any of the technical solutions described in the first aspect of the present invention, a second heavily doped semiconductor layer is provided on one of the main surfaces of the semiconductor substrate, wherein one of the first partially heavily doped semiconductor layer and the second heavily doped semiconductor layer is an N-type doped semiconductor layer and the other is a P-type doped semiconductor layer.

[0016] In some embodiments, the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer are both located on the back surface of the semiconductor substrate and are alternately distributed along the width direction of the semiconductor substrate.

[0017] Furthermore, an isolation region is provided between the first partially heavily doped semiconductor layer and the second heavily doped semiconductor layer to provide insulation and isolation between the first partially heavily doped semiconductor layer and the second heavily doped semiconductor layer. A tunneling passivation layer is provided between at least one of the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer and the semiconductor substrate; And / or the doping concentration at the edge region of the second heavily doped semiconductor layer is higher than the doping concentration at its center region.

[0018] In other embodiments, one of the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer is located on the back surface of the semiconductor substrate, and the other is located on the light-facing surface of the semiconductor substrate.

[0019] Furthermore, the second heavily doped semiconductor layer can be a fully doped or partially doped semiconductor layer. When the second heavily doped semiconductor layer is a partially doped semiconductor layer, the doping concentration in its edge region is also higher than the doping concentration in its center region.

[0020] A second aspect of the present invention provides a method for preparing a solar cell as described in the first aspect of the present invention, comprising: A substrate is provided, the substrate including a semiconductor substrate, wherein a first doped semiconductor layer is provided on one of the main surfaces of the semiconductor substrate, the first doped semiconductor layer having the same or opposite conductivity type as the semiconductor substrate; The first doped semiconductor layer is selectively opened, and a groove is formed in the opened region to expose the semiconductor substrate, thereby forming a first locally heavily doped semiconductor layer, wherein the doping concentration of the edge region of the first locally heavily doped semiconductor layer is higher than the doping concentration of the center region.

[0021] According to any of the technical solutions described in the second aspect of the present invention, a laser patterning process combined with alkaline etching is used to selectively open the first doped semiconductor layer, and a groove is formed in the opened area to expose the semiconductor substrate.

[0022] Furthermore, the laser patterning process includes two laser patterning processes. The process parameters for the first laser patterning process include: energy density of 0.5-0.9 J / cm³. 2 Pulse frequency: 500-800kHz; Scan speed: 60-90m / s; The process parameters for the second laser patterning include: energy density 1.0-3.0 J / cm³. 2 Pulse frequency: 100-400kHz, scan speed: 10-50m / s.

[0023] According to any of the technical solutions described in the second aspect of the present invention, the method further includes: forming a second heavily doped semiconductor layer on a main surface of a semiconductor substrate, wherein one of the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer is an N-type doped semiconductor layer and the other is a P-type doped semiconductor layer.

[0024] A third aspect of the present invention also provides a stacked battery, comprising: sequentially stacked and connected: Top battery; Intermediate connection layer; and The bottom battery employs a solar cell as described in the first aspect of the present invention.

[0025] A fourth aspect of the present invention also provides a photovoltaic module, comprising any of the aforementioned solar cells or tandem cells.

[0026] Compared with the prior art, the technical solution provided by this invention has the following advantages: (1) The present invention provides a first locally heavily doped semiconductor layer on at least one main surface (light-facing surface and / or back-facing surface) of a solar cell and optimizes its doping concentration, which is different from the existing uniform doping, or selectively heavily doped in the central region corresponding to the metal electrode, so that the doping concentration of the edge region of the first locally heavily doped semiconductor layer is higher than that of the central region, thereby forming an efficient edge recombination defense system, effectively suppressing the recombination phenomenon of charge carriers in the edge region, and thus helping to improve the open circuit voltage (Voc) and fill factor (FF) of the cell.

[0027] (2) Preferably, the present invention uses a laser patterning process to selectively open the first doped semiconductor layer and form a groove in the opened area to expose the semiconductor substrate, thereby preparing the first locally heavily doped semiconductor layer; furthermore, by further optimizing the process parameters of the laser patterning process, it is beneficial to further ensure the doping concentration distribution of the first locally heavily doped semiconductor layer, effectively suppress the recombination phenomenon of carriers in the edge region, and thus ensure the performance of the obtained battery. Attached Figure Description

[0028] Figures 1-4 This is a schematic diagram of the structure of each stage in the fabrication process of the solar cell in Embodiment 1 of the present invention; Figure 5 The diagram shown is a schematic diagram of the structure of the solar cell obtained in Embodiment 4 of the present invention; Figure 6 The figure shown is the ECV curve of the solar cell in Embodiment 4 of the present invention; Figure 7 This is a photograph of a solar cell obtained according to one embodiment of the present invention.

[0029] In the figure: 10, first locally heavily doped semiconductor layer; 101, selectively heavily doped region; 102, lightly doped region; 20, first tunneling passivation layer; 30, second heavily doped semiconductor layer; 40, second tunneling passivation layer; 50, semiconductor substrate; 501, phosphorus-doped polysilicon region; 502, isolation region; 503, boron-doped polysilicon region. Detailed Implementation

[0030] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to be constructed and operated in a specific orientation. Furthermore, some of the above terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application according to the specific circumstances.

[0031] Furthermore, in this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Moreover, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0032] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate for the embodiments of this application described herein.

[0033] It should be understood that all terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0034] The terms “comprising”, “including”, etc., as used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0035] Furthermore, the terms "installation," "setup," "equipped with," and "connection" as used herein should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0036] As the efficiency of crystalline silicon solar cells approaches its theoretical limit, carrier recombination at the interface has become the primary factor restricting performance improvement. To address this, passivation contact technologies based on doped polycrystalline silicon thin films (such as TOPCon and POLO) have emerged. This technology achieves excellent interface passivation and selective carrier transport by growing an ultrathin layer of silicon oxide on the silicon wafer surface and then covering it with a doped polycrystalline silicon layer, resulting in a significant improvement in the open-circuit voltage and efficiency of the cell.

[0037] In existing battery structures, selective patterning and windowing of the aforementioned continuous passivation layers is unavoidable. Back-contact battery fabrication processes based on laser-assisted film opening combined with wet etching are a mainstream technology for achieving back-electrode patterning. However, this technology has inherent physical limitations in interface control and electric field management, specifically as follows: (1) Poor quality of patterned interface and severe edge recombination: The combination of laser ablation and subsequent alkaline etching processes creates a rough and uneven interface at the lateral edge of the doped polycrystalline silicon layer when defining the emitter region. This region suffers from significant lattice damage and high dangling bond density, becoming a highly active recombination center. More importantly, existing processes cannot effectively passivate this etched edge in situ or afterward, resulting in a recombination rate of minority carriers at this location that is much higher than that in the bulk region and on the front side, constituting one of the key bottlenecks limiting the improvement of the battery open-circuit voltage (Voc).

[0038] (2) Poor doping distribution and insufficient field passivation capability: Conventional global diffusion processes cannot form a specific doping concentration gradient at the patterned edge. The doping concentration in the edge region is comparable to that at the center of the platform, and may even be locally depleted due to defect-enhanced diffusion, failing to establish a sufficiently strong edge local field effect passivation. The weak electric field cannot effectively repel minority carriers away from the high-defect edge interface, resulting in a persistently high recombination current density (J0).

[0039] (3) Bottleneck in carrier transport path: The sharp and highly recombination edge morphology constitutes a "transport bottleneck" for carriers transported from the front to the back electrode. Carriers need to bypass or cross this high-defect region, which increases the probability of them being captured and recombinated. This not only increases the series resistance, but also directly damages the fill factor (FF) and short-circuit current (Jsc) of the battery.

[0040] In summary, the fundamental flaw of existing technologies in fabricating the emitter of back-contact solar cells lies in the generation of active edges characterized by "high recombination, strong electric field, and weak passivation," which affects the photoelectric conversion efficiency of BC solar cells.

[0041] Similarly, for other batteries that require selective patterning to form locally doped semiconductor layers on the surface of a semiconductor substrate, such as forming locally doped semiconductor layers (N-type or P-type) on the front or back of a bifacial battery, the problem of severe carrier recombination at the edge of the contact window is also faced.

[0042] To address the technical problem of severe carrier recombination in the edge regions of existing locally doped semiconductor layers, this application provides a solar cell comprising: A semiconductor substrate, the semiconductor substrate comprising two main surfaces disposed opposite to each other, namely a light-facing surface and a back-lighting surface; A first locally heavily doped semiconductor layer located on one of the main surfaces of a semiconductor substrate, wherein the doping concentration of the edge region of the first locally heavily doped semiconductor layer is higher than the doping concentration of its central region; and A metal electrode is located on the side of the first partially heavily doped semiconductor layer away from the semiconductor substrate and forms an ohmic contact with the first partially heavily doped semiconductor layer.

[0043] This application optimizes the doping concentration distribution of the first locally heavily doped semiconductor layer, constructing a highly efficient edge recombination defense system through selective heavy doping in its edge region. The stronger built-in electric field effectively repels minority carriers away from the high-defect edge interface. Simultaneously, it provides a low-resistance, high-efficiency lateral transport channel for carriers (especially those collected in the edge region), enabling them to be quickly collected by the electrodes and significantly reducing the residence time and recombination probability in the high-defect region. This synergistic effect ultimately manifests as a simultaneous increase in the cell's open-circuit voltage (Voc) and fill factor (FF), thereby improving the cell's photoelectric conversion efficiency.

[0044] Specifically, in this application, "first locally heavily doped semiconductor layer" refers to a doping process performed only on a portion of the surface of one side of the semiconductor substrate, relative to the entire surface doping, i.e., there is an undoped region on that side surface.

[0045] It should be noted that this application does not specifically limit the material and conductivity type of the semiconductor substrate. The material can be a silicon substrate (monocrystalline silicon or polycrystalline silicon), or cadmium telluride, copper indium gallium selenide, or perovskite substrates, etc. Optionally, the conductivity type of the semiconductor substrate can be an N-type semiconductor substrate (e.g., an N-type monocrystalline silicon substrate) or a P-type semiconductor substrate (e.g., a P-type monocrystalline silicon substrate). Furthermore, the solar cell of this application does not have special requirements for the cell type. It is applicable to any type of cell that requires the formation of a locally doped semiconductor layer on the cell surface through a patterning process, resulting in severe carrier recombination in the patterned edge region. Specifically, it can be applied to TOPCon, interdigitated back contact, or perovskite / silicon tandem cells.

[0046] Furthermore, the first locally heavily doped semiconductor layer can be located on the light-receiving surface (or front side) of the semiconductor substrate, or on the back surface (or back side) of the semiconductor substrate, or the first locally heavily doped semiconductor layer can be provided on both sides. Its conductivity type can be the same as or opposite to that of the semiconductor substrate. Here, the light-receiving surface and the back surface refer to two opposing surfaces distributed along the thickness direction of the solar cell.

[0047] Furthermore, the first locally heavily doped semiconductor layer can be either N-type or P-type doped. It should be understood that the doping concentration in the edge region of the first locally heavily doped semiconductor layer is higher than that in its central region. There is no restriction on the doping concentration distribution in the edge region of the first locally heavily doped semiconductor layer; it can be uniformly doped or have a certain doping concentration gradient, such as decreasing from both sides of the first locally heavily doped semiconductor layer inwards. More specifically, the doping concentration of the first locally heavily doped semiconductor layer decreases gradually from both sides of its edges inwards.

[0048] In a further preferred embodiment, if the first locally heavily doped semiconductor layer is N-type doped, then the effective doping concentration in its edge region is 5 × 10⁻⁶. 20 cm -3 ~10×10 20 cm -3 The effective doping concentration in its central region is 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 Alternatively, the effective doping concentration in the edge region may be 1.01 to 10 times that in the center region. If the first locally heavily doped semiconductor layer is P-type doped, the effective doping concentration in its edge region is 5 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3The effective doping concentration in its central region is 2×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 Alternatively, the effective doping concentration in the edge region may be 1.1 to 100 times that in the center region.

[0049] By further optimizing and controlling the doping concentration in the edge and center regions of the first locally heavily doped semiconductor layer, it is beneficial to further ensure its application effect and enhance the suppression of carrier recombination in the edge region.

[0050] According to some embodiments of the present invention, at least one main surface of the semiconductor substrate is provided with raised platforms that are raised relative to the surface and arranged in an array, and the first locally heavily doped semiconductor layer is correspondingly disposed on the raised platforms.

[0051] Specifically, the first locally heavily doped semiconductor layer and the bump platform can be made of the same semiconductor material, for example, by directly using a diffusion process to form a doped semiconductor layer on the surface of the bump platform; similarly, the first locally heavily doped semiconductor layer and the bump platform can also be made of different heterogeneous materials, for example, by using a chemical vapor deposition process to form a doped semiconductor layer on the surface of the bump platform.

[0052] In addition, it should be understood that the raised platform and the semiconductor substrate can be integrally formed from the same material, or the raised platform can be a heterogeneous material layer grown on the surface of the semiconductor substrate by deposition or epitaxy. The heterogeneous material includes one or more combinations of polycrystalline silicon, microcrystalline silicon, silicon nitride, doped silicon oxide, etc.

[0053] In some alternative embodiments, the thickness of the first locally heavily doped semiconductor layer is 0.05 μm to 5 μm along the thickness direction of the solar cell.

[0054] It should be noted that this application does not have any special requirements for the shape of the raised platform. Its cross-section can be a standard rectangular structure or an irregular structure. For example, its cross-sectional shape can be an irregular polygon, or a combination of at least two conventional geometric shapes, or an asymmetrical trapezoid or a cone with an arc-shaped protrusion on one side. Furthermore, the irregular polygon preferably has 3-8 sides, and at least two sides have different lengths. The combination of at least two conventional geometric shapes can be a combination of a rectangle and a semicircle, a triangle and a trapezoid, or a regular hexagon and a rhombus, etc.

[0055] In a further optional embodiment of the present invention, the height of the raised platform is 0.1μm to 5μm, for example, it can be 0.1μm, 0.3μm, 0.5μm, 1μm, 2μm, 3μm, 4μm, 4.5μm or 5μm, etc.; along the direction of the raised platform array, the spacing between adjacent raised platforms is 50μm to 5000μm, for example, it can be 50μm, 100μm, 200μm, 500μm, 800μm, 1000μm, 1200μm, 1500μm, 2000μm, 3000μm, 4000μm or 5000μm, etc.; along the direction of the raised platform array, the maximum bottom dimension of a single raised platform is 200μm to 1000μm.

[0056] In some alternative embodiments, a passivation layer is provided on the side surface of the first locally heavily doped semiconductor layer away from the semiconductor substrate, or on the side of the protrusion platform not covered by the first locally heavily doped semiconductor layer. The passivation layer is one or more of aluminum oxide, silicon nitride, silicon oxynitride, or silicon oxide layers, and its thickness is 5 nm to 80 nm.

[0057] Furthermore, a second heavily doped semiconductor layer is provided on one of the main surfaces of the semiconductor substrate. One of the first partially heavily doped semiconductor layer and the second heavily doped semiconductor layer is an N-type doped semiconductor layer, and the other is a P-type doped semiconductor layer. The first partially heavily doped semiconductor layer and the second heavily doped semiconductor layer can be located on the same main surface of the semiconductor substrate, or they can be located on different main surfaces of the semiconductor substrate.

[0058] Specifically, in one embodiment, both the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer are located on the back surface of the semiconductor substrate and are along the width direction of the semiconductor substrate (here, along...). Figure 4 , Figure 5 The solar cells are arranged in alternating horizontal and transverse directions (i.e., the width of the paper), meaning that the solar cells are back-contact cells and the second doped semiconductor layer is also a locally doped semiconductor layer. By compressing the width of the space charge region at the edge of the raised platform through the high-doping characteristics at the edges, carrier recombination losses can be reduced, and the transport efficiency to the back-contact electrode can be improved.

[0059] Optionally, the first locally heavily doped semiconductor layer can be a P-type doped semiconductor layer or an N-type doped semiconductor layer; wherein, the P-type doped semiconductor layer can be a doped silicon-containing film layer, specifically including one or more of the following stacked structures: polycrystalline silicon thin film, intrinsic amorphous silicon thin film, microcrystalline silicon thin film, and silicon-based composite materials (such as SiC, SiO2-doped silicon, etc.), and its doping element can be one or more of boron, aluminum, gallium, and indium; for example, the P-type doping element is boron. The N-type doped semiconductor layer can be an N-type doped polycrystalline silicon layer or an N-type doped silicon-containing film layer, and its doping element can be one or more of phosphorus, arsenic, antimony, and bismuth; for example, the N-type doping element is phosphorus.

[0060] Furthermore, an isolation region is provided between the first partially heavily doped semiconductor layer and the second heavily doped semiconductor layer to provide insulation between them. The surface of the isolation region can be a polished surface or a textured pyramid structure.

[0061] Optionally, a tunneling passivation layer is provided between at least one of the first partially heavily doped semiconductor layer and the second heavily doped semiconductor layer and the semiconductor substrate. The tunneling passivation layer, together with the first partially heavily doped semiconductor layer and / or the second heavily doped semiconductor layer, forms a passivation contact structure, thereby effectively reducing carrier recombination and improving the performance of the back contact solar cell.

[0062] In a further preferred embodiment, a first tunneling passivation layer and a second tunneling passivation layer are respectively provided between the first locally heavily doped semiconductor layer, the second heavily doped semiconductor layer and the semiconductor substrate. The materials of the first tunneling passivation layer and the second tunneling passivation layer can be the same or different, and can specifically include at least one of various dielectric materials, such as silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide. Exemplarily, the first tunneling passivation layer and the second tunneling passivation layer are made of the same material, both being silicon oxide layers containing silicon oxide.

[0063] In another implementation, one of the first partially heavily doped semiconductor layer and the second heavily doped semiconductor layer is located on the back surface of the semiconductor substrate, and the other is located on the light-facing surface of the semiconductor substrate; that is, the solar cell is a bifacial cell. It should be noted that, in this case, the first partially heavily doped semiconductor layer can be located on either the light-facing or back surface of the semiconductor substrate, and can be either an N-type or P-type doped semiconductor layer, depending on the conductivity type of the semiconductor substrate.

[0064] For example, the semiconductor substrate of the bifacial battery is an N-type single crystal silicon substrate, with a first locally heavily doped semiconductor layer (N-type) on the backlight side and a second heavily doped semiconductor layer (P-type) on the light-facing side.

[0065] Optionally, the second heavily doped semiconductor layer can be doped across the entire surface or partially doped. When the second heavily doped semiconductor layer is also partially doped, its doping concentration at the edges can be higher than that at the center. In this case, both the light-facing and back-facing surfaces of the semiconductor substrate have arrayed raised platforms, with the first and second heavily doped semiconductor layers respectively positioned on these platforms. However, it should be noted that the arrangement density, height, or cross-sectional shape of the raised platforms on the light-facing and back-facing surfaces can be the same or different to accommodate the absorption requirements of double-sided incident light.

[0066] This application also provides a method for preparing a solar cell, comprising: A substrate is provided, the substrate including a semiconductor substrate, wherein a first doped semiconductor layer is provided on one of the main surfaces of the semiconductor substrate, the first doped semiconductor layer having the same or opposite conductivity type as the semiconductor substrate; The first doped semiconductor layer is selectively opened, and a groove is formed in the opened region to expose the semiconductor substrate, thereby forming a first locally heavily doped semiconductor layer, wherein the doping concentration of the edge region of the first locally heavily doped semiconductor layer is higher than the doping concentration of the center region.

[0067] Optionally, the first doped semiconductor layer is selectively opened using laser patterning and alkaline etching, and grooves are formed in the opened area to expose the semiconductor substrate.

[0068] As one feasible implementation, the laser patterning process includes two laser patterning operations. The first laser patterning is used to selectively open the first doped semiconductor layer, and its process parameters include: energy density 0.5-0.9 J / cm². 2 The pulse frequency is 500-800kHz, and the scanning speed is 60-90m / s; preferably, the specific process parameters include an energy density of 0.6-0.9J / cm³. 2 Pulse frequency: 550-750kHz, scan speed: 65-85m / s.

[0069] The second laser patterning is used to further process the edge region of the first doped semiconductor layer after the film-opening process, to form a first locally heavily doped semiconductor layer with a higher edge doping concentration than the central region. Its process parameters include: energy density 1.0-3.0 J / cm². 2The pulse frequency is 100-400kHz, and the scan speed is 10-50m / s; preferably, the energy density is 1.5-3.0J / cm³. 2 The pulse frequency is 100-350kHz, and the scan speed is 15-50m / s; more preferably, the energy density is 1.5-2.5J / cm³. 2 Pulse frequency: 100-300kHz, scan speed: 20-45m / s.

[0070] However, it should be noted that the laser patterning process in this application is not limited to the specific process mentioned above (two laser patterning processes). It can also be done once, or three or four times, as long as the purpose of this application can be achieved to form a first locally heavily doped semiconductor layer with a higher edge doping concentration than the central region.

[0071] Furthermore, the preparation method further includes: forming a second heavily doped semiconductor layer on a main surface of a semiconductor substrate, wherein one of the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer is an N-type doped semiconductor layer and the other is a P-type doped semiconductor layer.

[0072] It should be noted that the distribution location, doping concentration, and doping type of the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer in the preparation method are the same as those in the previous description of the structure of the solar cell, and will not be repeated here.

[0073] This application also provides a stacked battery, comprising: sequentially stacked and connected: Top battery; Intermediate connection layer; and The bottom battery is any of the solar cells described above in this application.

[0074] This application also provides a photovoltaic module comprising any of the aforementioned solar cells, or any of the aforementioned tandem cells.

[0075] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings and specific examples. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0076] It should also be noted that, due to space limitations, only bifacial batteries and back-contact batteries are used as examples for illustration below, but the scope of protection of this application is not actually limited by the type of battery in the embodiments or the specific distribution location, doping concentration, etc. of the first local heavily doped semiconductor layer.

[0077] Example 1 This embodiment uses a back-contact battery (without doped extended structure) as an example for illustration. The battery cell fabrication process in this embodiment includes the following steps: S01. An N-type single-crystal silicon substrate with a resistivity of 10 Ω·cm and a thickness of 200 μm is provided. After double-sided polishing and standard cleaning, boron Poly passivated contact structures are sequentially prepared on its surface (backlight side).

[0078] Specifically, firstly, an ultrathin tunneling oxide layer (i.e., tunneling passivation layer) with a thickness of 2 nm is grown by thermal oxidation or chemical methods; then, an intrinsic amorphous silicon / polycrystalline silicon layer with a thickness of 300 nm is deposited on it using low-pressure chemical vapor deposition (LPCVD); next, the silicon layer is boron-doped to form the first doped semiconductor layer by a high-temperature diffusion process, and simultaneously a borosilicate glass (BSG) layer with a thickness of 50 nm is formed on its surface, finally forming a complete p+poly-Si / SiO2 layer. x Passivated contact structures, such as Figure 1 As shown.

[0079] S02. Using a pulsed laser system of a specific wavelength, a laser patterning process and alkaline etching are used to selectively open the first doped semiconductor layer, and a groove is formed in the opened area to expose the semiconductor substrate, thereby forming a first locally heavily doped semiconductor layer. The doping concentration of the edge region of the first locally heavily doped semiconductor layer is higher than that of the center region.

[0080] Specifically, the laser patterning process described in this embodiment includes two laser patterning processes. First, a first laser patterning process is used to selectively open the film in the region outside the preset first doped region (the future boron emitter region or the first locally heavily doped region) to accurately remove the BSG layer in that region. Then, a second laser patterning process is used to process the edge region of the first doped semiconductor layer after the film opening process again to form a first locally heavily doped semiconductor layer with a higher edge doping concentration than the central region.

[0081] The specific process parameters for the first laser patterning process include: energy density 0.5-0.9 J / cm³. 2 The pulse frequency is 500-800kHz, and the scanning speed is 60-90m / s; specifically, in this embodiment, the energy density is 0.9J / cm³. 2Pulse frequency: 500kHz, scan speed: 60m / s.

[0082] The specific parameters of the second laser patterning process include: energy density 1.0-3.0 J / cm³. 2 The pulse frequency is 100-400kHz, and the scanning speed is 10-50m / s. Specifically, in this embodiment, the energy density is 2J / cm³. 2 Pulse frequency: 200kHz, scan speed: 40m / s.

[0083] By precisely controlling parameters such as laser energy density, pulse frequency, and scanning trajectory in the second laser patterning process, a localized high-temperature field is induced at the boundary between the open-film region and the non-open-film region. This thermal field, through the synergistic effect of thermal gradient and surface tension, drives the boron impurities in the boron-doped polysilicon layer at the boundary to undergo directional enrichment and redistribution towards the edge region, thereby forming a first locally heavily doped semiconductor layer (in this embodiment, a boron-doped polysilicon layer). The doping concentration in the edge region of this first locally heavily doped semiconductor layer is higher than that in its central region.

[0084] Subsequently, a first alkaline etching process is performed, using an alkaline solution (such as KOH or NaOH) to completely remove the silicon layer (BSG, boron-doped polycrystalline silicon, and part of the tunneling oxide layer) in the laser-etched area, creating a 4μm deep recess to expose the underlying monocrystalline silicon substrate. This recess depth can be precisely controlled by adjusting the alkaline solution concentration, temperature, and etching time; however, this is existing technology and will not be elaborated upon here. The cell structure after this step is shown below. Figure 2 As shown S03. On the entire silicon wafer surface with the stepped structure (protruding platform) treated in step S02, a stacked structure for passivation contacts in the n+ region is sequentially deposited: first, a tunneling oxide layer with a thickness of 2 nm is grown, followed by a phosphorus-doped polycrystalline silicon layer with a thickness of 300 nm, and finally a phosphorus silicate glass (PSG) layer is formed on its surface, as follows. Figure 3 As shown.

[0085] S04. Next, a third laser patterning process is performed to selectively remove the PSG layer located at the edges of the future raised and recessed areas. The process parameters for the third laser patterning process are: energy density 0.9 J / cm³. 2 Pulse frequency: 500kHz, scan speed: 60m / s.

[0086] Finally, by combining a second alkaline etching process with hydrofluoric acid (HF) cleaning, the etching selectivity of the alkaline solution for each region (heavily boron-doped polysilicon, phosphorus-doped polysilicon, and exposed monocrystalline silicon) is utilized to form the final interdigitated back contact electrode structure consisting of "boron-doped polysilicon region (boron emitter) - monocrystalline gap region - phosphorus-doped polysilicon region (phosphorus base)".

[0087] Combination Figure 4 As shown, the solar cell of this embodiment includes a semiconductor substrate 50. The backlight side surface of the semiconductor substrate 50 includes phosphorus-doped polycrystalline silicon regions 501 and boron-doped polycrystalline silicon regions 503 that are alternately distributed along its width direction, and an isolation region 502 is provided between the phosphorus-doped polycrystalline silicon regions 501 and the boron-doped polycrystalline silicon regions 503. The boron-doped polycrystalline silicon regions 503 have a first protrusion platform, and the phosphorus-doped polycrystalline silicon regions 501 have a second protrusion platform.

[0088] Specifically, along the thickness direction of the solar cell, in this embodiment, the surface of the first protruding platform is sequentially provided with a first tunneling passivation layer 20 and a first locally heavily doped semiconductor layer 10 from the inside out, and the first locally heavily doped semiconductor layer 10 includes selectively heavily doped regions 101 located at both edges (e.g., Figure 7 (As shown) and the lightly doped region 102 located in the middle, wherein the selectively heavily doped region 101 has a doping concentration of 2 × 10⁻⁶. 20 cm -3 The doping concentration of the lightly doped region 102 is 6 × 10⁻⁶. 19 cm -3 In this embodiment, the surface of the second protruding platform is provided with a second tunneling passivation layer 40 and a second heavily doped semiconductor layer 30 from the inside out.

[0089] Example 2 This embodiment uses a back-contact battery (without doped extended structure) as an example for illustration. The battery cell fabrication process in this embodiment includes the following steps: S01. An N-type single-crystal silicon substrate with a resistivity of 10 Ω·cm and a thickness of 200μm is provided. After double-sided polishing and standard cleaning, boron Poly passivated contact structures are sequentially prepared on its surface.

[0090] First, an ultrathin tunneling oxide layer with a thickness of 2 nm is grown using thermal oxidation or chemical methods. Then, a 300 nm thick intrinsic amorphous silicon / polycrystalline silicon layer is deposited on top of this layer using low-pressure chemical vapor deposition (LPCVD). Next, boron doping is performed on this silicon layer using a high-temperature diffusion process, simultaneously forming a 50 nm thick borosilicate glass (BSG) layer on its surface, ultimately forming a complete p+poly-Si / SiO₂ layer. x Passivated contact structure.

[0091] S02. Using a pulsed laser system of a specific wavelength, a first laser patterning process is employed to selectively scan the area outside the preset boron emitter region, precisely removing the BSG layer in that area. Subsequently, a first alkaline etching is performed, using an alkaline solution (such as KOH or NaOH) to completely remove the silicon layer (BSG, boron-doped polycrystalline silicon, and part of the tunneling oxide layer) in the laser-etched area, etching a depression with a depth of 4μm to expose the underlying single-crystal silicon substrate.

[0092] The specific working parameters of the first laser patterning process are: energy density 0.9 J / cm³. 2 Pulse frequency: 500kHz, scan speed: 60m / s.

[0093] S03. On the entire silicon wafer surface with a stepped structure treated in step S02, a stacked structure for passivation contacts in the n+ region is deposited sequentially: first, a tunneling oxide layer with a thickness of 2 nm is grown, then a phosphorus-doped polysilicon layer (i.e., the first doped semiconductor layer) with a thickness of 300 nm is deposited, and finally a phosphorus silicon glass (PSG) layer is formed on its surface.

[0094] S04. Next, a laser patterning process is performed to selectively remove the PSG layer located at the edges of the future raised and recessed areas.

[0095] The laser patterning process includes two laser patterning processes: a second laser patterning process and a third laser patterning process. Specifically, the second laser patterning process is first used to selectively open the film in the region outside the preset phosphorus emitter region to accurately remove the BSG layer in that region. Then, the third laser patterning process is used to process the edge region of the first doped semiconductor layer after the film opening process again to form a first locally heavily doped semiconductor layer with a higher edge doping concentration than the central region.

[0096] The specific parameters of the second laser patterning process include: energy density 0.5-0.9 J / cm³. 2 The pulse frequency is 500-800kHz, and the scanning speed is 60-90m / s; specifically, in this embodiment, the energy density is 0.9J / cm³. 2 The pulse frequency is 500kHz, and the scanning speed is 60m / s. The specific parameters of the third laser patterning process include: energy density 1.0-3.0J / cm³. 2 The pulse frequency is 100-400kHz, and the scanning speed is 10-50m / s. Specifically, in this embodiment, the energy density is 1.5J / cm³. 2 Pulse frequency: 300kHz, scan speed: 40m / s.

[0097] By precisely controlling parameters such as laser energy density, pulse frequency, and scanning trajectory, a localized high-temperature field is induced at the boundary between the open-film region and the non-open-film region. This thermal field, through the synergistic effect of thermal gradient and surface tension, drives the phosphorus impurities in the phosphorus-doped polycrystalline silicon layer at the boundary to undergo directional enrichment and redistribution towards the edge region, thereby forming a first locally heavily doped semiconductor layer (in this embodiment, a phosphorus-doped polycrystalline silicon layer). The doping concentration in the edge region of this first locally heavily doped semiconductor layer is higher than that in its central region.

[0098] Finally, through a combination of a second alkaline etching and hydrofluoric acid (HF) cleaning process, the final interdigitated back contact electrode structure, consisting of a boron-doped polycrystalline silicon region (boron emitter), a single-crystal gap region, and an exposed monocrystalline silicon region, is formed in a self-aligned manner by utilizing the difference in etching selectivity of the alkaline solution on each region (heavily doped boron polycrystalline silicon, phosphorus-doped polycrystalline silicon, and exposed monocrystalline silicon). That is, the first locally heavily doped semiconductor layer 10 of the solar cell obtained in this embodiment is a phosphorus-doped polycrystalline silicon layer, which includes selectively heavily doped regions 101 located at both edges and a lightly doped region 102 located in the middle.

[0099] Specifically, in this embodiment, the doping concentration of the selectively heavily doped region 101 is 8 × 10⁻⁶. 20 cm -3 The doping concentration of the lightly doped region 102 is 3 × 10⁻⁶. 20 cm -3 .

[0100] Example 3 This embodiment uses a back-contact battery (without doped extended structure) as an example for illustration. The battery cell fabrication process in this embodiment includes the following steps: S01. An N-type single-crystal silicon substrate with a resistivity of 10 Ω·cm and a thickness of 200 μm is provided. After double-sided polishing and standard cleaning, boron Poly passivated contact structures are sequentially prepared on its surface.

[0101] First, an ultrathin tunneling oxide layer with a thickness of 2 nm is grown using thermal oxidation or chemical methods. Then, a 300 nm thick intrinsic amorphous silicon / polycrystalline silicon layer is deposited on top of this layer using low-pressure chemical vapor deposition (LPCVD). Next, boron doping is performed on this silicon layer using a high-temperature diffusion process, simultaneously forming a 50 nm thick borosilicate glass (BSG) layer on its surface, ultimately forming a complete p+ poly-Si / SiO₂ layer. x Passivated contact structure.

[0102] S02. Using a pulsed laser system of a specific wavelength, a first laser patterning process is used to selectively open the film in the region outside the preset first doped region (i.e., the future boron emitter region) to precisely remove the BSG layer in that region.

[0103] Then, the edge region of the first doped semiconductor layer after the film opening process is processed again using the second laser patterning process to form a first locally heavily doped semiconductor layer with a higher edge doping concentration than the central region.

[0104] Subsequently, a first alkaline etching process is performed, using an alkaline solution (such as KOH or NaOH) to completely remove the silicon layer (BSG, boron-doped polysilicon, and part of the tunneling oxide layer) in the laser-etched area, creating a 3μm deep depression to expose the underlying single-crystal silicon substrate. This depression depth is precisely controlled by the alkaline solution concentration, temperature, and etching time.

[0105] The specific parameters of the first laser patterning process include: energy density 0.9 J / cm³. 2 The pulse frequency is 500 kHz, and the scanning speed is 60 m / s. Specific parameters of the second laser patterning process include: energy density 2.5 J / cm², pulse frequency 200 kHz, and scanning speed 40 m / s. By precisely controlling the laser's energy density, pulse frequency, and other parameters, a localized high-temperature field is induced at the boundary between the open-film region and the non-open-film region. This thermal field, through the synergistic effect of thermal gradient and surface tension, drives the boron impurities in the boron-doped polycrystalline silicon layer at the boundary to undergo directional enrichment and redistribution towards the edge region, thereby forming the first selectively heavily doped region.

[0106] S03. On the entire silicon wafer surface with a stepped structure treated in step S02, a stacked structure for passivation contacts in the n+ region is deposited sequentially: first, a tunneling oxide layer with a thickness of 1.5 nm is grown, then a phosphorus-doped polycrystalline silicon layer with a thickness of 200 nm is deposited, and finally a phosphorus silicon glass (PSG) layer is formed on its surface.

[0107] S04. Next, a third laser patterning process is performed to selectively remove the PSG layer located at the edges of the future raised and recessed regions. Then, a fourth laser patterning process is used to form a second locally heavily doped semiconductor layer with a higher edge doping concentration than the center.

[0108] Specifically, the specific process parameters of the third laser patterning process in this embodiment include: energy density 0.9 J / cm³. 2 The pulse frequency is 500kHz, and the scanning speed is 60m / s. The specific process parameters for the fourth laser patterning process include: energy density 2J / cm². 2The pulse frequency is 300 kHz, and the scanning speed is 40 m / s. By precisely controlling parameters such as laser energy density, pulse frequency, and scanning trajectory, a localized high-temperature field is induced at the boundary between the open-film region and the non-open-film region. This thermal field, through the synergistic effect of thermal gradient and surface tension, drives the boron impurities in the boron-doped polycrystalline silicon layer at the boundary to undergo directional enrichment and redistribution towards the edge region, thereby forming a second selectively heavily doped region.

[0109] Finally, through a combination of a second alkaline etching and hydrofluoric acid (HF) cleaning process, the etching selectivity difference of the alkaline solution on each region (heavily doped boron polycrystalline silicon, phosphorus doped polycrystalline silicon, and exposed monocrystalline silicon) is utilized to self-align and form the final interdigitated back contact electrode structure consisting of "boron doped polycrystalline silicon region (boron emitter) - monocrystalline gap region - phosphorus doped polycrystalline silicon region (phosphorus base)". That is, in this embodiment, the phosphorus doped polycrystalline silicon layer and the boron doped polycrystalline silicon layer of the obtained solar cell are both locally heavily doped semiconductor layers, meaning that the doping concentration at both edges is higher than the doping concentration in the central region, or the doping concentration gradually decreases inward from both edges of the phosphorus doped polycrystalline silicon layer and the boron doped polycrystalline silicon layer.

[0110] Specifically, in this embodiment, the edge doping concentration of the boron-doped polysilicon layer is 3 × 10⁻⁶. 20 cm -3 The doping concentration in the middle is 6×10 19 cm -3 The edge doping concentration of the obtained phosphorus-doped polycrystalline silicon layer is 9 × 10⁻⁶. 20 cm -3 The doping concentration in the middle is 3×10 20 cm -3 .

[0111] Example 4 This embodiment uses a back-contact battery (with a doped extended structure) as an example for illustration. The battery cell fabrication process in this embodiment includes the following steps: S01. An N-type single-crystal silicon substrate with a resistivity of 10 Ω·cm and a thickness of 150 μm is provided. After double-sided polishing and standard cleaning, boron Poly passivated contact structures are sequentially prepared on its surface.

[0112] First, an ultrathin tunneling oxide layer with a thickness of 1.5 nm is grown using thermal oxidation or chemical methods. Then, a 200 nm thick intrinsic amorphous silicon / polycrystalline silicon layer is deposited on top of this layer using low-pressure chemical vapor deposition (LPCVD). Next, boron doping is performed on this silicon layer using a high-temperature diffusion process, simultaneously generating a 50 nm thick borosilicate glass (BSG) layer on its surface, ultimately forming a complete p+ poly-Si / SiO₂ layer. x Passivated contact structure.

[0113] S02. Using a pulsed laser system with a specific wavelength, a first laser patterning process is employed to selectively open and scan the area outside the preset first doped region (i.e., the future boron emitter region) to precisely remove the BSG layer in that region. In this embodiment, the specific process parameters for the first laser patterning process include: energy density 0.7 J / cm². 2 Pulse frequency: 700kHz, scan speed: 70m / s.

[0114] Then, the edge region of the first doped semiconductor layer after the film opening process is processed again using the second laser patterning process to form a first locally heavily doped semiconductor layer with a higher edge doping concentration than the central region.

[0115] The specific parameters for the second laser patterning process include: energy density 1.5 J / cm³. 2 The pulse frequency is 300 kHz, and the scanning speed is 50 m / s. By precisely controlling the laser's energy density, pulse frequency, and other parameters, a localized high-temperature field is induced at the boundary between the open-film region and the non-open-film region. This thermal field, through the synergistic effect of thermal gradient and surface tension, drives the boron impurities in the boron-doped polycrystalline silicon layer at the boundary to undergo directional enrichment and redistribution towards the edge region, thereby forming a selectively heavily doped region 101.

[0116] Subsequently, the first alkaline etching is performed, using an alkaline solution (such as KOH or NaOH) to completely remove the silicon layer (BSG, boron-doped polysilicon, and part of the tunneling oxide layer) in the laser-etched area, etching out a depression with a depth of 3 μm to expose the underlying single-crystal silicon substrate.

[0117] S03. On the entire silicon wafer surface with a stepped structure treated in step S02, a stacked structure for passivation contacts in the n+ region is deposited sequentially: first, a tunneling oxide layer with a thickness of 1.5 nm is grown, then a phosphorus-doped polycrystalline silicon layer with a thickness of 200 nm is deposited, and finally a phosphorus silicon glass (PSG) layer is formed on its surface.

[0118] S04. Next, a third laser patterning process is performed to selectively remove the PSG layer located at the edges of future raised and recessed areas. The process parameters for the third laser patterning process are: energy density 0.9 J / cm³. 2 Pulse frequency: 500kHz, scan speed: 60m / s.

[0119] Finally, through a combined process of second alkaline etching and hydrofluoric acid (HF) cleaning, two functions are simultaneously achieved: 1) Utilizing the difference in etching selectivity of the alkaline solution for different regions (heavily boron-doped polysilicon, phosphorus-doped polysilicon, and exposed monocrystalline silicon), a self-aligned final interdigitated back contact electrode structure is formed, consisting of "boron-doped polysilicon region (boron emitter) - monocrystalline gap region - phosphorus-doped polysilicon region (phosphorus base)," specifically as follows: Figure 5 As shown; 2) Since the heavily doped edge region formed in step S02 has extremely high resistance to alkaline etching, after two alkaline etchings, the region is retained and naturally forms a raised structure extending to the side, thereby achieving a significant improvement in the edge passivation performance of the battery. That is, unlike the solar cell in Example 1, the two sides of the first locally heavily doped semiconductor layer 10 protrude outward to the outside of the semiconductor substrate corresponding to the first tunneling passivation layer 20 and the first raised platform.

[0120] The ECV curve of the battery cell prepared in this embodiment is shown in the figure below. Figure 6 As shown, combined with Figure 6 It can be seen that the boron doping concentration in the heavily doped edge region is 1×10⁻⁶. 20 cm -3 The boron doping concentration in the central region is 6 × 10⁻⁶. 19 cm -3 It can be seen that the boron doping concentration in the edge region is higher than that in the center region, which can effectively enhance edge passivation, reduce carrier recombination in the edge region, improve the open-circuit voltage and fill factor of the cell, and thus improve the cell efficiency.

[0121] Example 5 This embodiment uses a bifacial solar cell as an example for illustration, wherein the semiconductor substrate is an N-type single-crystal silicon substrate, and the first locally heavily doped semiconductor layer is located on the light-facing side of the single-crystal silicon substrate. The fabrication method of this bifacial solar cell includes: S01. Provide an N-type single crystal silicon substrate with a resistivity of 10 Ω·cm and a thickness of 220 μm. After texturing, boron expansion is performed on the front side of the silicon wafer as a boron expansion surface to form a P-region with a sheet resistance of 400Ω / □. The back side is then passed through a chain machine to remove BSG, and a slot machine is used to polish the back side.

[0122] S02, phosphorus Poly passivated contact structures are sequentially prepared on its back side; First, an ultrathin tunneling oxide layer with a thickness of 2 nm is grown using thermal oxidation or chemical methods. Then, a 400 nm thick intrinsic amorphous silicon / polycrystalline silicon layer is deposited on top of this layer using low-pressure chemical vapor deposition (LPCVD). Next, phosphorus doping is performed on this silicon layer using a high-temperature diffusion process, simultaneously generating a phosphosilicate glass (PSG) layer on its surface, ultimately forming a complete n+ poly-Si / SiO₂ layer. xPassivated contact structure.

[0123] S03. Using a pulsed laser system of a specific wavelength, a first laser patterning process is used to selectively open the film and scan the area outside the pre-set metal contact area on the light-facing surface of the solar cell to accurately remove the BSG layer in that area; and a second laser patterning process is used to process the edge area of ​​the first doped semiconductor layer after the film opening process again to form a first locally heavily doped semiconductor layer with a higher edge doping concentration than the central area.

[0124] Subsequently, a first alkaline etching process is performed, using an alkaline solution (such as KOH or NaOH) to completely remove the silicon layer (BSG and boron diffusion layer) in the laser-etched area, creating a 2μm deep depression to expose the underlying single-crystal silicon substrate. This depression depth can be precisely controlled by adjusting the alkaline solution concentration, temperature, and etching time.

[0125] The specific parameters of the first laser patterning process include: energy density 0.5 J / cm³. 2 Pulse frequency: 600kHz, scan speed: 80m / s.

[0126] The specific parameters of the second laser patterning process include: energy density 2.0 J / cm³. 2 The pulse frequency is 200 kHz, and the scanning speed is 30 m / s. By precisely controlling parameters such as laser energy density and pulse frequency, a local high-temperature field is induced at the boundary between the open-film region and the non-open-film region. This thermal field, through the synergistic effect of thermal gradient and surface tension, drives the boron impurities in the boron-doped polycrystalline silicon layer at the boundary to undergo directional enrichment and redistribution towards the edge region, thereby forming an edge-selective heavily doped region.

[0127] In this embodiment, the edge doping concentration of the boron-doped polysilicon layer is 2.5 × 10⁻⁶. 20 cm -3 The doping concentration in the middle is 5×10 19 cm -3 .

[0128] Example 6 This embodiment uses a bifacial battery as an example for illustration, wherein the semiconductor substrate is an N-type single-crystal silicon substrate, and the first locally heavily doped semiconductor layer is located on the back surface of the single-crystal silicon substrate. The fabrication method of this bifacial battery includes: S01. Provide an N-type single crystal silicon substrate with a resistivity of 10 Ω·cm and a thickness of 220 μm. After texturing, boron expansion is performed on the front side of the silicon wafer as a boron expansion surface to form a P-region with a sheet resistance of 400Ω / □. The back side is then passed through a chain machine to remove BSG, and a slot machine is used to polish the back side.

[0129] S02, phosphorus Poly passivated contact structures are sequentially prepared on its back side; First, an ultrathin tunneling oxide layer with a thickness of 2 nm is grown using thermal oxidation or chemical methods. Then, a 400 nm thick intrinsic amorphous silicon / polycrystalline silicon layer is deposited on top of this layer using low-pressure chemical vapor deposition (LPCVD). Next, phosphorus doping is performed on this silicon layer using a high-temperature diffusion process, simultaneously generating a phosphosilicate glass (PSG) layer on its surface, ultimately forming a complete n+ poly-Si / SiO₂ layer. x Passivated contact structure.

[0130] S03. Using a pulsed laser system of a specific wavelength band, firstly, a first laser patterning process is used to selectively open the film and scan the area outside the preset metal contact area on the back surface of the battery cell to accurately remove the PSG layer in that area; then, a second laser patterning process is used to process the edge area of ​​the first doped semiconductor layer after the film opening again to form a first locally heavily doped semiconductor layer with a higher edge doping concentration than the central area.

[0131] In this embodiment, the specific process parameters of the first laser patterning process include: energy density 0.9 J / cm³. 2 Pulse frequency: 600kHz, scan speed: 80m / s.

[0132] The specific parameters of the second laser patterning process include: energy density 2.0 J / cm³. 2 The pulse frequency is 200 kHz, and the scanning speed is 30 m / s. By precisely controlling parameters such as laser energy density, pulse frequency, and scanning trajectory, a local high-temperature field is induced at the boundary between the open-film region and the non-open-film region. This thermal field, through the synergistic effect of thermal gradient and surface tension, drives the phosphorus impurities in the phosphorus-doped polycrystalline silicon layer at the boundary to undergo directional enrichment and redistribution towards the edge region, thereby forming an edge-selective heavily doped region.

[0133] Subsequently, a first alkaline etching process is performed, using an alkaline solution (such as KOH or NaOH) to completely remove the silicon layer (PSG, phosphorus-doped polysilicon, and part of the tunneling oxide layer) in the laser-etched area, creating a 2μm deep depression to expose the underlying single-crystal silicon substrate. This depression depth can be precisely controlled by adjusting the alkaline solution concentration, temperature, and etching time.

[0134] In this embodiment, the edge doping concentration of the obtained phosphorus-doped polysilicon layer is 1×10⁻⁶. 21 cm -3 The edge doping concentration is 5×10 20 cm -3 .

[0135] Comparative Example 1 Taking the back contact battery as an example, its manufacturing process is basically the same as in Example 3, with the main difference being: In both S02 and S04, only one laser patterning process is performed, and the process parameters for the laser patterning process are: energy density 0.9 J / cm³. 2 The pulse frequency was 500 kHz, and the scan speed was 60 m / s. The doping concentration of the boron-doped polysilicon layer obtained after doping was 6 × 10⁻⁶. 19 cm -3 The phosphorus-doped polycrystalline silicon layer has a doping concentration of 3 × 10⁻⁶. 20 cm -3 This means that the doping is basically uniform, and that is, neither the boron-doped polysilicon layer nor the phosphorus-doped polysilicon layer obtained in this comparative example has a heavily doped edge region.

[0136] Comparative Example 2 Taking a bifacial battery as an example, its fabrication process is basically the same as in Example 6, the main difference being that only the first laser patterning process is performed in S03, and the second laser patterning process is not performed. In this example, the doping concentration of the phosphorus-doped polycrystalline silicon layer is 5 × 10⁻⁶. 19 cm -3 The doping is basically uniform, meaning there are no heavily doped edge regions. The electrical performance data of the solar cells obtained in Examples 1-6 and Comparative Examples 1 and 2 are shown in Table 1 below. As can be seen from Table 1, by setting the heavily doped edge regions, the recombination phenomenon of carriers in the edge regions of the doped semiconductor layer can be effectively suppressed, thereby improving the open-circuit voltage (Voc), fill factor, and conversion efficiency of the cell.

[0137] Table 1 Electrical performance data of the examples and comparative examples

Claims

1. A solar cell, characterized in that, include: Semiconductor substrate; A first locally heavily doped semiconductor layer is located on a main surface of a semiconductor substrate. The conductivity type of the first locally heavily doped semiconductor layer is the same as or opposite to that of the semiconductor substrate, and the doping concentration of its edge region is higher than that of its center region. as well as A metal electrode is located on the side of the first partially heavily doped semiconductor layer away from the semiconductor substrate and forms an ohmic contact with the first partially heavily doped semiconductor layer.

2. The solar cell according to claim 1, characterized in that, If the first locally heavily doped semiconductor layer is N-type doped, the effective doping concentration in its edge region is 5 × 10⁻⁶. 20 cm -3 ~10×10 20 cm -3 The effective doping concentration in its central region is 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 Alternatively, the effective doping concentration in the edge region may be 1.01 to 10 times that in the center region. If the first locally heavily doped semiconductor layer is P-type doped, its effective doping concentration in the edge region is 5 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3 The effective doping concentration in its central region is 2×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 Alternatively, the effective doping concentration in the edge region may be 1.1 to 100 times that in the center region.

3. The solar cell according to claim 1, characterized in that, At least one main surface of the semiconductor substrate is provided with raised platforms that are raised relative to the surface and arranged in an array, and the first locally heavily doped semiconductor layer is correspondingly disposed on the raised platforms.

4. The solar cell according to claim 3, characterized in that, Along the thickness direction of the solar cell, the thickness of the first locally heavily doped semiconductor layer is 0.05 μm to 5 μm.

5. The solar cell according to any one of claims 1-4, characterized in that, One of the main surfaces of the semiconductor substrate is provided with a second heavily doped semiconductor layer, wherein one of the first partially heavily doped semiconductor layer and the second heavily doped semiconductor layer is an N-type doped semiconductor layer and the other is a P-type doped semiconductor layer.

6. The solar cell according to claim 5, characterized in that, The first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer are both located on the back surface of the semiconductor substrate and are alternately distributed along the width direction of the semiconductor substrate.

7. The solar cell according to claim 6, characterized in that, An isolation region is provided between the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer; A tunneling passivation layer is provided between at least one of the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer and the semiconductor substrate; And / or the doping concentration at the edge region of the second heavily doped semiconductor layer is higher than the doping concentration at its center region.

8. The solar cell according to claim 5, characterized in that, One of the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer is located on the back surface of the semiconductor substrate, and the other is located on the light-facing surface of the semiconductor substrate.

9. The solar cell according to claim 8, characterized in that, The second doped semiconductor layer is either a full-area doped semiconductor layer or a partially doped semiconductor layer. When the second doped semiconductor layer is a partially doped semiconductor layer, the doping concentration in its edge region is higher than the doping concentration in its center region.

10. A method for preparing a solar cell as described in any one of claims 1-9, characterized in that, include: A substrate is provided, the substrate including a semiconductor substrate, wherein a first doped semiconductor layer is provided on one of the main surfaces of the semiconductor substrate, the first doped semiconductor layer having the same or opposite conductivity type as the semiconductor substrate; The first doped semiconductor layer is selectively opened, and a groove is formed in the opened region to expose the semiconductor substrate, thereby forming a first locally heavily doped semiconductor layer, wherein the doping concentration of the edge region of the first locally heavily doped semiconductor layer is higher than the doping concentration of the center region.

11. The method for preparing a solar cell according to claim 10, characterized in that, The first doped semiconductor layer is selectively opened using laser patterning and alkaline etching, and grooves are formed in the opened area to expose the semiconductor substrate.

12. The method for preparing a solar cell according to claim 11, characterized in that, The laser patterning process includes two laser patterning steps. The process parameters for the first laser patterning step include: energy density 0.5-0.9 J / cm³. 2 Pulse frequency: 500-800kHz; Scan speed: 60-90m / s; The process parameters for the second laser patterning include: energy density 1.0-3.0 J / cm³. 2 Pulse frequency: 100-400kHz, scan speed: 10-50m / s.

13. The method for preparing a solar cell according to any one of claims 10-12, characterized in that, Also includes: A second heavily doped semiconductor layer is formed on a main surface of a semiconductor substrate. One of the first locally heavily doped semiconductor layer and the second heavily doped semiconductor layer is an N-type doped semiconductor layer, and the other is a P-type doped semiconductor layer.

14. A stacked battery, characterized in that, Including sequentially stacked connections: Top battery; Intermediate connection layer; and The bottom battery is a solar cell according to any one of claims 1-10.

15. A photovoltaic module, characterized in that, The solar cell includes any one of claims 1-10, or is prepared by any one of the preparation methods of claims 11-13, or includes the tandem cell as described in claim 14.

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