Chirped digital signal generation method and system based on linear feedback shift register

Abstract

The present invention relates to a chirped digital signal generation method based on a linear feedback shift register. First, according to a target configuration signal, the start and end frequency control words and the signal change rate control word of each effective period of the chirp signal are configured. Then, for each period in a single cycle, the frequency control word FCW and the phase control word PCW are successively accumulated with time steps, and the phase control word PCW is synchronously superimposed in combination with the phase jitter pseudo-random value of the linear feedback shift register. Finally, a table lookup and a complement operation are performed to obtain amplitude signals output successively to form a period signal. The single-cycle target chirped digital signal is efficiently formed from the period signals. At the same time, a corresponding system is designed. The design scheme provides higher spectrum performance and realizes the generation of complex multi-segment linear frequency modulation signals without significantly increasing hardware resources, thereby enhancing the flexible configuration capability of the direct frequency synthesizer.

Description

Technical Field

[0001] The invention relates to a chirped digital signal generation method and system based on a linear feedback shift register, and belongs to the technical field of frequency synthesis. Background Art

[0002] Direct digital synthesizer (DDS) is an important method in frequency synthesis technology. Traditional DDS systems usually require complex external control logic and large-capacity lookup tables when generating linear frequency modulation (chirp) signals, resulting in large hardware resource usage and poor flexibility. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a chirped digital signal generation method based on a linear feedback shift register, which adopts a new design strategy to efficiently and accurately obtain the chirped digital signal.

[0004] To solve the above technical problems, the present invention adopts the following technical solution: the present invention designs a chirped digital signal generation method based on a linear feedback shift register. According to the target configuration signal, the following steps are performed to obtain a corresponding single-cycle target chirped digital signal, and then obtain a corresponding target chirped digital periodic signal;

[0005] Step A. According to the target configuration signal, configure the start frequency control word, the end frequency control word, and the signal change rate control word of each chirp signal valid period in a single cycle, and then enter step B;

[0006] Step B. Based on the delay duration control word and pause duration control word in the target configuration signal, each delay period, each pause period, and each chirp signal valid period in a single cycle is considered. For each period in the single cycle, the signal change rate control word corresponding to the period is sequentially accumulated over time to update the frequency control word FCW. Simultaneously, using the phase shift control word as the initial value, the frequency control word FCW is sequentially accumulated over time to update the phase control word PCW. Furthermore, for each phase control word PCW, the corresponding amplitude value is obtained in combination with the phase jitter pseudo-random value of the linear feedback shift register. The corresponding amplitude signal is output to construct a period signal. The period signals are then sequentially used to form the single-cycle target chirp digital signal.

[0007] As a preferred technical solution of the present invention: in step A, based on the start frequency control word and the end frequency control word of each chirp signal segment in the target configuration signal, combined with the linear frequency modulation signal configuration enable signal used to configure each chirp signal segment to be in an effective state or an ineffective state, the start frequency control word and the end frequency control word of each chirp signal effective time period in a single cycle are sequentially configured with the preset start frequency control word as the starting point;

[0008] At the same time, according to the target signal change rate control word in the target configuration signal and in combination with the linear frequency modulation signal configuration enable signal, the signal change rate control word of each chirp signal effective period in a single cycle is configured with the target signal change rate control word.

[0009] As a preferred technical solution of the present invention: in step B, based on the signal change rate control word corresponding to the preset delay period and the signal change rate control word corresponding to the preset pause period being 0, the following steps B1 to B2 are performed sequentially for each period in the single cycle;

[0010] Step B1. If the time period is a delay period, the frequency control word FCW is updated with the starting frequency control word of the next time period in its order, and the process proceeds to step B2;

[0011] If the time period is a pause period, the frequency control word FCW is updated with the ending frequency control word of the previous time period, and the process proceeds to step B2;

[0012] If the time period is a chirp signal valid time period, the frequency control word FCW is updated with the starting frequency control word of the chirp signal valid time period, and the process proceeds to step B2;

[0013] Step B2. Execute steps B2-1 to B2-3 for the time period to construct a time period signal.

[0014] Step B2-1. For the frequency control word FCW, the signal change rate control word corresponding to the time period is incrementally updated with the current time step, and proceeds to step B2-2;

[0015] Step B2-2. Determine whether the time period is the first time period in a single cycle. If so, construct the phase control word PCW using the phase shift control word in the target configuration signal. Incrementally update the phase control word PCW with the frequency control word FCW at the current time step, and then proceed to step B2-4. Otherwise, incrementally update the phase control word PCW with the frequency control word FCW at the current time step, and then proceed to step B2-3.

[0016] Step B2-3. For the phase control word PCW, a pseudo-random phase jitter value equal to the number of bits in the low-order portion of the frequency control word FCW, generated by the linear feedback shift register, is superimposed and updated with the current time step. The amplitude value corresponding to the frequency control word FCW is obtained by combining a phase-to-amplitude conversion table that maps addresses to amplitudes. The corresponding amplitude signal is output, and the process then proceeds to step B2-4.

[0017] Step B2-4. If the period is a delay period or a pause period, it is determined whether the accumulated time step is equal to the delay duration control word or the pause duration control word in the target configuration signal. If so, the process ends for that period; otherwise, it proceeds to the next time step and returns to step B2-1.

[0018] If the time period is a chirp signal valid time period, determine whether the frequency control word FCW is equal to the end frequency control word of the chirp signal valid time period. If so, the processing for this time period ends; otherwise, enter the next time step and return to step B2-1.

[0019] As a preferred technical solution of the present invention, step B2-3 includes the following steps:

[0020] Step B2-3-1. Generate a phase jitter pseudo-random value with a number of bits equal to the number of bits in the low-order area of ​​the phase control word PCW by a linear feedback shift register, and superimpose it with the phase control word PCW. Update the phase control word PCW, and then proceed to step B2-3-2.

[0021] Step B2-3-2 obtains the phase control word PCW high area data, and based on the high area data except the first 2 bits of data other than the remaining data, the phase amplitude conversion table of the preset address and amplitude mapping relationship is searched to obtain the amplitude value corresponding to the remaining data, and then proceeds to step B2-3-3;

[0022] Step B2-3-3. Use the first two bits of the high-order data to perform complement update on the amplitude values ​​corresponding to the remaining data, and output the corresponding amplitude signal.

[0023] Corresponding to the above, the technical problem to be solved by the present invention is to provide a system for generating a chirped digital signal based on a linear feedback shift register, so as to accurately obtain the chirped digital signal with efficient and flexible hardware configuration.

[0024] In order to solve the above technical problems, the present invention adopts the following technical solutions: the present invention designs a system for a chirped digital signal generation method based on a linear feedback shift register, comprising a configuration signal receiving and processing module, a chirped signal control module, a chirped signal phase control word accumulation module, and a phase amplitude conversion module, wherein the configuration signal receiving and processing module is connected and communicated with the chirped signal phase control word accumulation module, the chirped signal control module is connected and communicated with the configuration signal receiving and processing module and the chirped signal phase control word accumulation module respectively, the configuration signal receiving and processing module receives the target configuration signal to execute step A, and sends the result obtained in step A to the chirped signal phase control word accumulation module, and at the same time the configuration signal receiving and processing module converts the target configuration signal into the chirped signal phase control word accumulation module. The phase shift enable signal, phase shift control word, delay duration control word, and pause duration control word in the signal are sent to the chirp signal control module; based on the chirp signal control module controlling the chirp signal phase control word accumulation module according to the partial signal in the received target configuration signal, the chirp signal phase control word accumulation module executes step B to accumulate and update the phase control word PCW; the linear feedback shift register is located in the phase-amplitude conversion module, the chirp signal phase control word accumulation module is connected and communicated with the phase-amplitude conversion module, the chirp signal phase control word accumulation module sends the obtained phase control word PCW to the phase-amplitude conversion module, and the phase-amplitude conversion module executes step B according to the phase control word PCW to construct a time period signal.

[0025] As a preferred technical solution of the present invention: the configuration signal receiving and processing module includes two multiplexers, one of which is used to receive the linear frequency modulation signal configuration enable signal in the target configuration signal, and the start frequency control word and the end frequency control word of each chirp signal segment, and configure the start frequency control word and the end frequency control word of each chirp signal valid period in sequence in a single cycle;

[0026] Another multiplexer is used to receive the linear frequency modulation signal configuration enable signal and the target signal change rate control word in the target configuration signal, and configure the signal change rate control word of each chirp signal valid period in a single cycle.

[0027] As a preferred technical solution of the present invention, the configuration signal receiving and processing module further includes a serial peripheral interface (SPI). An input end of the SPI is used to receive a target configuration signal from an external source. An output end of the SPI is connected to the input ends of two multiplexers in the configuration signal receiving and processing module. The SPI transmits a portion of the processed target configuration signal to each multiplexer. Simultaneously, an output end of the SPI is connected to the chirp signal control module. The SPI transmits a portion of the processed target configuration signal to the chirp signal control module.

[0028] As a preferred technical solution of the present invention: the chirp signal phase control word accumulation module includes a multiplexer, a frequency control word accumulator, and a phase control word accumulator; wherein the chirp signal control module is connected to and communicates with the multiplexer, the frequency control word accumulator, and the phase control word accumulator respectively, the multiplexer is connected to and communicates with the frequency control word accumulator, the frequency control word accumulator is simultaneously connected to and communicates with the phase control word accumulator, the frequency control word accumulator receives the signal change rate control word of each chirp signal valid period output by the configuration signal receiving processing module in step A, the multiplexer receives the start frequency control word and the end frequency control word of each chirp signal valid period in sequence in a single cycle output by the configuration signal receiving processing module in step A, and in the chirp signal control module The block controls the multiplexer and the frequency control word accumulator according to the delay duration control word and the pause duration control word in the target configuration signal. The frequency control word accumulator is linked to the multiplexer to execute the frequency control word FCW in step B, which is accumulated successively along the time step, and the frequency control word FCW updated successively is sent to the phase control word accumulator. The chirp signal control module controls the frequency control word accumulator and the phase control word accumulator according to the phase shift enable signal and the phase shift control word in the target configuration signal. The phase control word accumulator is linked to the frequency control word accumulator to execute the phase control word PCW in step B, which is accumulated successively along the time step, and the successively updated phase control word PCW constitutes the successive output of the chirp signal phase control word accumulation module along the time step.

[0029] As a preferred technical solution of the present invention: the phase-amplitude conversion module also includes a superposition module, a phase address converter, a table lookup module, and a complement module, wherein one of the input ends of the superposition module constitutes the input end of the phase-amplitude conversion module, the other input end of the superposition module is connected to the linear feedback shift register, and the output end of the superposition module is connected to the input end of the phase address converter. The superposition module superimposes and updates the phase control word PCW outputted successively from the chirp signal phase control word accumulation module in combination with the phase jitter pseudo-random value generated by the linear feedback shift register, and outputs the phase control word PCW to the phase address converter; one of the output ends of the phase address converter is connected to the input end of the table lookup module, the phase The other output end of the address converter is connected to the output end of the table lookup module and the input end of the complement module. The phase address converter obtains the high-order area data of the frequency control word FCW and sends the remaining data in the high-order area data except the first two bits to the table lookup module. At the same time, the phase address converter sends the first two bits of the high-order area data to the complement module. The table lookup module searches the phase-amplitude conversion table with a preset address-amplitude mapping relationship based on the remaining data in the high-order area data except the first two bits, obtains the amplitude value corresponding to the remaining data, and sends it to the complement module. The complement module uses the first two bits of the high-order area data to complement the amplitude value corresponding to the remaining data and outputs the corresponding amplitude signal.

[0030] The chirped digital signal generation method and system based on the linear feedback shift register of the present invention, using the above technical solution, has the following technical effects compared with the prior art:

[0031] The chirped digital signal generation method based on the linear feedback shift register designed in the present invention first configures the start and end frequency control words and the signal change rate control word of each chirp signal effective period according to the target configuration signal; then considers each delay period, each pause period, and each chirp signal effective period in a single cycle, sequentially accumulates the frequency control word FCW and the phase control word PCW in sequence with the time step for each period, and combines the phase jitter pseudo-random value of the linear feedback shift register to synchronously superimpose the phase control word PCW, and finally performs a table lookup and a complement operation to obtain The amplitude signals output successively are formed into time period signals, and then the signals of each time period are used to efficiently form a single-cycle target chirp digital signal. A corresponding system is designed, which is composed of a signal receiving and processing module, a chirp signal control module, a chirp signal phase control word accumulation module, and a phase-amplitude conversion module to jointly implement the design method. The overall design scheme provides higher spectral performance, especially in terms of spurious-free dynamic range (SFDR). It also realizes the generation of complex multi-segment linear frequency modulation signals without significantly increasing hardware resources, thereby enhancing the flexible configuration capability of the direct frequency synthesizer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a system structure diagram of the chirped digital signal generation method designed by the present invention;

[0033] Figure 2 Schematic diagram of the state transition of the state machine included in the chirp signal control module in the system designed by the present invention;

[0034] Figure 3 This is a frequency-time diagram of the output signal that matches the state transition of the chirp signal control module in the system designed by the present invention;

[0035] Figure 4 The figure is a schematic diagram of the improvement in spurious-free dynamic range performance achieved by using a linear feedback shift register to perform phase dithering in the chirp signal phase control word accumulation module designed in the present invention. DETAILED DESCRIPTION

[0036] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0037] The chirp digital signal generation method based on linear feedback shift register designed by the present invention is based on the target configuration signal and the unified system clock. Figure 1 As shown, the following steps A to B are performed to obtain a corresponding single-cycle target chirped digital signal, and then obtain a corresponding target chirped digital periodic signal.

[0038] Step A. Press Figure 2 and Figure 3 As shown, according to the start frequency control word and the end frequency control word of each chirp signal segment in the target configuration signal, in combination with the linear frequency modulation signal configuration enable signal used to configure each chirp signal segment to be in a valid state or an invalid state, with the preset start frequency control word as the starting point, the start frequency control word and the end frequency control word of each chirp signal valid time period in a single cycle are sequentially configured; at the same time, according to the target signal change rate control word in the target configuration signal, in combination with the linear frequency modulation signal configuration enable signal, the signal change rate control word of each chirp signal valid time period in a single cycle is configured with the target signal change rate control word; then the process proceeds to step B.

[0039] Step B. Press Figure 1As shown, according to the delay time control word and pause time control word in the target configuration signal, each delay period, each pause period, and each chirp signal valid period in a single cycle are considered, and the signal change rate control word corresponding to the period is successively accumulated with the time step for each period in the single cycle, and the frequency control word FCW is updated. The phase control word FCW is synchronously accumulated with the time step using the phase shift control word as the initial value, and the phase control word PCW is updated. Then, each phase control word PCW is synchronously and successively combined with the phase jitter pseudo-random value of the linear feedback shift register. The corresponding amplitude value is obtained, the corresponding amplitude signal is output, and the time period signal is constructed; then, the single-cycle target chirp digital signal is sequentially constructed from the time period signals. In practical applications, the linear feedback shift register specifically adopts a left-shift feedback shift register (LFSR). The left-shift feedback shift register (LFSR) can generate pseudo-random numbers with certain statistical characteristics. Specifically, the feedback polynomial of the LFSR is selected and optimized to achieve lower noise characteristics and higher randomness, increase the randomness of the output signal, thereby reducing the distortion caused by phase truncation and improving the spurious-free dynamic range (SFDR).

[0040] In actual application, the above step B, according to the delay time control word and the pause time control word in the target configuration signal, considers each delay period, each pause period, and each chirp signal valid period in a single cycle, based on the signal change rate control word corresponding to the preset delay period and the signal change rate control word corresponding to the preset pause period are both 0, and sequentially for each period in the single cycle, according to Figure 1 As shown, perform the following steps B1 to B2.

[0041] Step B1. If the time period is a delay period, the frequency control word FCW is updated with the starting frequency control word of the next time period in its order, and the process proceeds to step B2;

[0042] If the time period is a pause period, the frequency control word FCW is updated with the ending frequency control word of the previous time period, and the process proceeds to step B2;

[0043] If the time period is the chirp signal valid time period, the frequency control word FCW is updated with the starting frequency control word of the chirp signal valid time period, and the process goes to step B2.

[0044] Make necessary adjustments and preparations as described above to ensure continuity and stability of signal output. The module supports reserved delays to accommodate the response time of external devices.

[0045] Step B2. Execute steps B2-1 to B2-3 for the time period along with the time step to construct a time period signal.

[0046] Step B2-1. For the frequency control word FCW, incrementally update the signal change rate control word corresponding to the time period along with the current time step, and proceed to step B2-2.

[0047] Step B2-2. Determine whether the time period is the first time period in a single cycle. If so, construct the phase control word PCW using the phase shift control word in the target configuration signal. Incrementally update the phase control word PCW with the frequency control word FCW at the current time step, and then proceed to step B2-4. Otherwise, incrementally update the phase control word PCW with the frequency control word FCW at the current time step, and then proceed to step B2-3.

[0048] Step B2-3. For the phase control word PCW, a pseudo-random phase jitter value generated by the linear feedback shift register, whose number of bits is equal to the low-order bit field of the frequency control word FCW, is superimposed and updated along with the current time step. Combined with the phase-to-amplitude conversion table that maps preset addresses to amplitudes, the amplitude value corresponding to the frequency control word FCW is obtained, the corresponding amplitude signal is output, and then the process proceeds to step B2-4.

[0049] In actual application, the above steps B2-3 are Figure 1 As shown, the following steps B2-3-1 to B2-3-3 are actually performed.

[0050] Step B2-3-1. Generate a phase jitter pseudo-random value with the same number of bits as the low-order bit area of ​​the phase control word PCW by the linear feedback shift register, superimpose it with the phase control word PCW, update the phase control word PCW, and then proceed to step B2-3-2.

[0051] Step B2-3-2. Obtain the high-order data in the phase control word PCW, and search the phase-amplitude conversion table with a preset address-amplitude mapping relationship based on the remaining data in the high-order data except the first two bits, obtain the amplitude value corresponding to the remaining data, and then proceed to step B2-3-3; the remaining data in the high-order data except the first two bits is the actual table address.

[0052] Step B2-3-3. Use the first two bits of the high-order data to perform complement update on the amplitude values ​​corresponding to the remaining data, and output the corresponding amplitude signal.

[0053] Step B2-4. If the period is a delay period or a pause period, it is determined whether the accumulated time step is equal to the delay duration control word or the pause duration control word in the target configuration signal. If so, the process ends for that period; otherwise, it proceeds to the next time step and returns to step B2-1.

[0054] If the time period is a chirp signal valid time period, determine whether the frequency control word FCW is equal to the end frequency control word of the chirp signal valid time period. If so, the processing for this time period ends; otherwise, enter the next time step and return to step B2-1.

[0055] In practical application, a specific system is further designed to implement the chirped digital signal generation method based on linear feedback shift register. Figure 1 As shown, the system includes a configuration signal receiving and processing module, a chirp signal control module, a chirp signal phase control word accumulation module, and a phase amplitude conversion module, wherein the configuration signal receiving and processing module is connected and communicated with the chirp signal phase control word accumulation module, and the chirp signal control module is connected and communicated with the configuration signal receiving and processing module and the chirp signal phase control word accumulation module respectively. The configuration signal receiving and processing module receives the target configuration signal to execute step A, and sends the result obtained in step A to the chirp signal phase control word accumulation module. At the same time, the configuration signal receiving and processing module converts the phase shift enable signal, phase shift control word, delay time control word, The pause duration control word is sent to the chirp signal control module; based on the chirp signal control module controlling the chirp signal phase control word accumulation module according to a portion of the target configuration signal received by the chirp signal control module, the chirp signal phase control word accumulation module executes step B to accumulate and update the phase control word PCW; the linear feedback shift register is located in the phase-amplitude conversion module, the chirp signal phase control word accumulation module is connected and communicated with the phase-amplitude conversion module, the chirp signal phase control word accumulation module sends the obtained phase control word PCW to the phase-amplitude conversion module, and the phase-amplitude conversion module executes step B according to the phase control word PCW to construct a time period signal.

[0056] In a specific design application, the configuration signal receiving and processing module includes two multiplexers, one of which is used to receive the linear frequency modulation signal configuration enable signal in the target configuration signal, as well as the start frequency control word and end frequency control word of each chirp signal segment, and configure the start frequency control word and end frequency control word of each chirp signal valid time period in sequence in a single cycle; the other multiplexer is used to receive the linear frequency modulation signal configuration enable signal and the target signal change rate control word in the target configuration signal, and configure the signal change rate control word of each chirp signal valid time period in a single cycle.

[0057] The designed configuration signal receiving and processing module also includes a serial peripheral interface SPI. The input end of the serial peripheral interface SPI is used to receive the target configuration signal from the outside. The output end of the serial peripheral interface SPI is connected to the input ends of the two multiplexers in the configuration signal receiving and processing module. The serial peripheral interface SPI sends part of the data in the target configuration signal it processes to each multiplexer respectively. At the same time, the output end of the serial peripheral interface SPI is connected to the chirp signal control module. The serial peripheral interface SPI sends part of the data in the target configuration signal it processes to the chirp signal control module.

[0058] The chirp signal phase control word accumulation module is designed to include a multiplexer, a frequency control word accumulator, and a phase control word accumulator; wherein the chirp signal control module is connected to and communicates with the multiplexer, the frequency control word accumulator, and the phase control word accumulator respectively, the multiplexer is connected to and communicates with the frequency control word accumulator, the frequency control word accumulator is connected to and communicates with the phase control word accumulator at the same time, the frequency control word accumulator receives the signal change rate control word of each chirp signal valid period output by the configuration signal receiving processing module executing step A, the multiplexer receives the starting frequency control word and the ending frequency control word of each chirp signal valid period in sequence in the single cycle output by the configuration signal receiving processing module executing step A, and the chirp signal control module receives the starting frequency control word and the ending frequency control word of each chirp signal valid period in sequence in the single cycle output by the configuration signal receiving processing module executing step A, and the chirp signal control module receives the starting frequency control word and the ending frequency control word of each chirp signal valid period in sequence in accordance with the target configuration. Under the control of the delay duration control word and the pause duration control word in the signal on the multiplexer and the frequency control word accumulator, the frequency control word accumulator is linked to the multiplexer to execute the frequency control word FCW in step B, which is accumulated successively along the time step, and the frequency control word FCW updated successively is sent to the phase control word accumulator. Under the control of the chirp signal control module on the frequency control word accumulator and the phase control word accumulator according to the phase shift enable signal and the phase shift control word in the target configuration signal, the phase control word accumulator is linked to the frequency control word accumulator to execute the phase control word PCW in step B, which is accumulated successively along the time step, and the successively updated phase control word PCW constitutes the successive output of the chirp signal phase control word accumulation module along the time step.

[0059] The designed phase-amplitude conversion module also includes a superposition module, a phase address converter, a lookup table module, and a complement module, wherein one of the input ends of the superposition module constitutes the input end of the phase-amplitude conversion module, the other input end of the superposition module is connected to the linear feedback shift register, and the output end of the superposition module is connected to the input end of the phase address converter. The superposition module superimposes and updates the phase control word PCW output successively from the chirp signal phase control word accumulation module in combination with the phase jitter pseudo-random value generated by the linear feedback shift register, and outputs the phase control word PCW to the phase address converter; one of the output ends of the phase address converter is connected to the input end of the lookup table module, and the other output end of the phase address converter is connected to the output end of the lookup table module. The input end of the complement code module is connected, and the phase address converter obtains the high-order area data of the frequency control word FCW, and sends the remaining data in the high-order area data except the first 2 bits to the table lookup module. At the same time, the phase address converter sends the first 2 bits of the high-order area data to the complement code module. The remaining data in the high-order area data except the first 2 bits are the actual table address quantity; the table lookup module searches the phase-amplitude conversion table with a preset address and amplitude mapping relationship based on the remaining data in the high-order area data except the first 2 bits, obtains the amplitude value corresponding to the remaining data, and sends it to the complement code module. The complement code module uses the first 2 bits of the high-order area data to complement the amplitude value corresponding to the remaining data and outputs the corresponding amplitude signal.

[0060] In practical applications, the design of the present invention is Figure 4 The diagram shows the improvement in spurious-free dynamic range performance achieved by using a linear feedback shift register to perform phase dithering on the chirp signal phase control word accumulation module. It is clear that the present invention can minimize the impact of clock jitter on the signal, ensure high accuracy in signal amplitude adjustment, and maintain the quality of the output signal.

[0061] The chirped digital signal generation method based on a linear feedback shift register designed in the above technical solution first configures the start and end frequency control words and the signal change rate control word of each chirp signal effective period according to the target configuration signal; then, considering each delay period, each pause period, and each chirp signal effective period in a single cycle, the frequency control word FCW and the phase control word PCW are successively accumulated for each period with the time step, and the phase control word PCW is synchronously superimposed with the phase jitter pseudo-random value of the linear feedback shift register. Finally, a table lookup and complement operation are performed to obtain the amplitude signals output successively to form a period signal, and then the single-cycle target chirped digital signal is efficiently constructed from the period signals.

[0062] The above design improves the spurious-free dynamic range (SFDR), ensuring better signal quality at specific frequencies, reducing spurious components in the spectrum, and improving overall signal clarity and reliability. Precise clock management and synchronization mechanisms minimize the impact of clock jitter on the signal, ensuring high accuracy in signal amplitude adjustment and maintaining output signal quality. The lookup table design uses a high-precision amplitude quantization method to better restore the signal waveform.

[0063] The present invention also designs a corresponding system. The design method is implemented by a configuration signal receiving and processing module, a chirp signal control module, a chirp signal phase control word accumulation module, and a phase-amplitude conversion module. The system dynamically adjusts the frequency and phase control words to achieve flexible generation of multi-segment linear frequency modulation signals, enabling the system to quickly respond to external changes and providing a richer spectrum output option. Users can set different frequency modulation rates and phase adjustment strategies based on actual application scenarios. Furthermore, the chirp signal control module introduces a state machine unit to implement complex spectrum configurations. This allows the system to flexibly configure multiple spectrum output modes to meet the needs of different application scenarios without significantly increasing hardware resources. The state machine design supports multi-state transitions, enabling rapid switching between different signal segment configurations.

[0064] The design provides stronger chirp signal configuration capabilities by adding state machine units without significantly increasing the overall hardware resources of the lookup table structure direct frequency synthesizer. It also uses the phase control word to determine the phase jitter amount, enabling it to have better spurious-free dynamic range (SFDR) spectrum performance at certain special frequency points.

[0065] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the scope of knowledge possessed by ordinary technicians in this field without departing from the spirit of the present invention.

Claims

1. A chirped digital signal generation method based on a linear feedback shift register, characterized in that: According to the target configuration signal, the following steps are performed to obtain a corresponding single-cycle target chirped digital signal, and then obtain a corresponding target chirped digital periodic signal; Step A. According to the target configuration signal, configure the start frequency control word, the end frequency control word, and the signal change rate control word of each chirp signal valid period in a single cycle, and then enter step B; Step B. Based on the delay duration control word and pause duration control word in the target configuration signal, each delay period, each pause period, and each chirp signal valid period in a single cycle is considered. The frequency control word FCW is updated by sequentially accumulating the signal change rate control word corresponding to each period over a time step. Simultaneously, using the phase shift control word as the initial value, the frequency control word FCW is sequentially accumulated over a time step to update the phase control word PCW. Furthermore, the corresponding amplitude value is obtained for each phase control word PCW in combination with the phase jitter pseudo-random value of the linear feedback shift register. The corresponding amplitude signal is output to construct a period signal. The period signals are then sequentially used to form the single-cycle target chirp digital signal. In the above step B, based on the signal change rate control word corresponding to the preset delay period and the signal change rate control word corresponding to the preset pause period being 0, the following steps B1 to B2 are performed sequentially for each period in the single cycle; Step B1. If the time period is a delay period, the frequency control word FCW is updated with the starting frequency control word of the next time period in its order, and the process proceeds to step B2; If the time period is a pause period, the frequency control word FCW is updated with the ending frequency control word of the previous time period, and the process proceeds to step B2; If the time period is a chirp signal valid time period, the frequency control word FCW is updated with the starting frequency control word of the chirp signal valid time period, and the process proceeds to step B2; Step B2. Execute steps B2-1 to B2-3 for the time period to construct a time period signal. Step B2-1. For the frequency control word FCW, the signal change rate control word corresponding to the time period is incrementally updated with the current time step, and proceeds to step B2-2; Step B2-2 determines whether the period is the first period in a single cycle, if the target configuration signal phase shift control word constitutes the phase control word PCW, and for the phase control word PCW, the frequency control word FCW is incrementally updated with the current time step, and then proceeds to step B2-4; Otherwise, directly update the phase control word PCW with the frequency control word FCW according to the current time step, and then go to step B2-3; Step B2-3. For the phase control word PCW, a pseudo-random phase jitter value equal to the number of bits in the low-order portion of the frequency control word FCW, generated by the linear feedback shift register, is superimposed and updated with the current time step. The amplitude value corresponding to the frequency control word FCW is obtained by combining a phase-to-amplitude conversion table that maps addresses to amplitudes. The corresponding amplitude signal is output, and the process then proceeds to step B2-4. Step B2-4. If the period is a delay period or a pause period, it is determined whether the cumulative time step is equal to the target configuration signal delay duration control word or pause duration control word, if so, the process ends for that period; Otherwise, proceed to the next time step and return to step B2-1; If the time period is a chirp signal valid time period, determine whether the frequency control word FCW is equal to the end frequency control word of the chirp signal valid time period. If so, the processing for this time period ends; otherwise, enter the next time step and return to step B2-1.

2. The chirped digital signal generation method based on a linear feedback shift register according to claim 1, characterized in that: In step A, based on the start frequency control word and the end frequency control word of each chirp signal segment in the target configuration signal, in combination with the linear frequency modulation signal configuration enable signal used to configure each chirp signal segment to be in an effective state or an ineffective state, the start frequency control word and the end frequency control word of each chirp signal effective time period in a single cycle are sequentially configured starting from the preset start frequency control word; At the same time, according to the target signal change rate control word in the target configuration signal and in combination with the linear frequency modulation signal configuration enable signal, the signal change rate control word of each chirp signal effective period in a single cycle is configured with the target signal change rate control word.

3. The chirped digital signal generation method based on a linear feedback shift register according to claim 1, characterized in that , the step B2-3 includes the following steps: Step B2-3-1. Generate a phase jitter pseudo-random value with a number of bits equal to the number of bits in the low-order area of ​​the phase control word PCW by a linear feedback shift register, and superimpose it with the phase control word PCW. Update the phase control word PCW, and then proceed to step B2-3-2. Step B2-3-2 obtains the phase control word PCW high area data, and based on the high area data except the first 2 bits of data other than the remaining data, the phase amplitude conversion table of the preset address and amplitude mapping relationship is searched to obtain the amplitude value corresponding to the remaining data, and then proceeds to step B2-3-3; Step B2-3-3. Use the first two bits of the high-order data to perform complement update on the amplitude values ​​corresponding to the remaining data, and output the corresponding amplitude signal.

4. A system for implementing the chirped digital signal generation method based on a linear feedback shift register according to any one of claims 1 to 3, characterized in that: The system includes a configuration signal receiving and processing module, a chirp signal control module, a chirp signal phase control word accumulation module, and a phase amplitude conversion module. The configuration signal receiving and processing module is connected and communicated with the chirp signal phase control word accumulation module. The chirp signal control module is connected and communicated with the configuration signal receiving and processing module and the chirp signal phase control word accumulation module respectively. The configuration signal receiving and processing module receives the target configuration signal to execute step A, and sends the result obtained in step A to the chirp signal phase control word accumulation module. At the same time, the configuration signal receiving and processing module converts the phase shift enable signal, phase shift control word, delay time control word, pause time control word, and phase amplitude conversion word in the target configuration signal into the phase shift enable signal, phase shift control word, delay time control word, and pause time control word in the target configuration signal. The duration control word is sent to the chirp signal control module; based on the chirp signal control module controlling the chirp signal phase control word accumulation module according to a portion of the received target configuration signal, the chirp signal phase control word accumulation module executes step B to accumulate and update the phase control word PCW; the linear feedback shift register is located in the phase-amplitude conversion module, the chirp signal phase control word accumulation module is connected and communicated with the phase-amplitude conversion module, the chirp signal phase control word accumulation module sends the obtained phase control word PCW to the phase-amplitude conversion module, and the phase-amplitude conversion module executes step B according to the phase control word PCW to construct a time period signal.

5. The system for generating a chirped digital signal based on a linear feedback shift register according to claim 4, characterized in that: The configuration signal receiving and processing module includes two multiplexers, one of which is used to receive the linear frequency modulation signal configuration enable signal in the target configuration signal, as well as the start frequency control word and the end frequency control word of each chirp signal segment, and configure the start frequency control word and the end frequency control word of each chirp signal valid period in sequence in a single cycle; Another multiplexer is used to receive the linear frequency modulation signal configuration enable signal and the target signal change rate control word in the target configuration signal, and configure the signal change rate control word of each chirp signal valid period in a single cycle.

6. The system for generating a chirped digital signal based on a linear feedback shift register according to claim 5, characterized in that: The configuration signal receiving and processing module further includes a serial peripheral interface (SPI). An input end of the SPI is used to receive a target configuration signal from an external source. An output end of the SPI is connected to the input ends of two multiplexers in the configuration signal receiving and processing module. The SPI transmits a portion of the processed target configuration signal to each multiplexer. Simultaneously, an output end of the SPI is connected to the chirp signal control module. The SPI transmits a portion of the processed target configuration signal to the chirp signal control module.

7. The system for generating a chirped digital signal based on a linear feedback shift register according to claim 4, characterized in that: The chirp signal phase control word accumulation module includes a multiplexer, a frequency control word accumulator, and a phase control word accumulator; wherein the chirp signal control module is connected to and communicates with the multiplexer, the frequency control word accumulator, and the phase control word accumulator respectively, the multiplexer is connected to and communicates with the frequency control word accumulator, the frequency control word accumulator is connected to and communicates with the phase control word accumulator at the same time, the frequency control word accumulator receives the signal change rate control word of each chirp signal valid period output by the configuration signal receiving processing module executing step A, the multiplexer receives the starting frequency control word and the ending frequency control word of each chirp signal valid period in sequence in the single cycle output by the configuration signal receiving processing module executing step A, and the chirp signal control module receives the signal change rate control word of each chirp signal valid period in sequence according to the target configuration. Under the control of the delay duration control word and the pause duration control word in the signal on the multiplexer and the frequency control word accumulator, the frequency control word accumulator is linked to the multiplexer to execute the frequency control word FCW in step B, which is accumulated successively along the time step, and the frequency control word FCW updated successively is sent to the phase control word accumulator. Under the control of the chirp signal control module on the frequency control word accumulator and the phase control word accumulator according to the phase shift enable signal and the phase shift control word in the target configuration signal, the phase control word accumulator is linked to the frequency control word accumulator to execute the phase control word PCW in step B, which is accumulated successively along the time step, and the successively updated phase control word PCW constitutes the successive output of the chirp signal phase control word accumulation module along the time step.

8. The system for generating a chirped digital signal based on a linear feedback shift register according to claim 4, characterized in that: The phase-amplitude conversion module further includes a superposition module, a phase address converter, a table lookup module, and a complement module, wherein one of the input ends of the superposition module constitutes the input end of the phase-amplitude conversion module, the other input end of the superposition module is connected to the linear feedback shift register, and the output end of the superposition module is connected to the input end of the phase address converter. The superposition module superimposes and updates the phase control word PCW outputted successively from the chirp signal phase control word accumulation module in combination with the phase jitter pseudo-random value generated by the linear feedback shift register, and outputs the phase control word PCW to the phase address converter; one of the output ends of the phase address converter is connected to the input end of the table lookup module, and the other input end of the phase address converter is connected to the input end of the table lookup module. An output end is connected to the output end of the table lookup module and the input end of the complement module. The phase address converter obtains the high-order area data of the frequency control word FCW and sends the remaining data in the high-order area data except the first two bits to the table lookup module. At the same time, the phase address converter sends the first two bits of the high-order area data to the complement module. The table lookup module searches the phase-amplitude conversion table with a preset address-amplitude mapping relationship based on the remaining data in the high-order area data except the first two bits, obtains the amplitude value corresponding to the remaining data, and sends it to the complement module. The complement module uses the first two bits of the high-order area data to complement the amplitude value corresponding to the remaining data and outputs the corresponding amplitude signal.

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