Signal generation device and signal generation method

Abstract

The present invention provides a signal generating device and a signal generating method capable of greatly increasing an adjustable maximum phase difference between signals output from each of a plurality of transceivers. The signal generation device is provided with: a phase acquisition processing unit (31b) that acquires a voltage value measured by a phase detection unit while changing the phase of a trigger pattern output from each transceiver from an initial value; a phase difference calculation processing unit (31c) that calculates, on the basis of the relationship between the voltage value acquired by the phase acquisition processing unit (31b) and the amount of change in the phase of the trigger pattern from the initial value, an initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the trigger pattern; and a phase shift processing unit (31d) that shifts the phase of the trigger pattern from the initial value by the amount of the initial phase difference such that the phase difference between the divided clock or the external clock selected by the clock selection unit and the trigger pattern becomes a value within a predetermined range.

Description

Technical Field

[0001] The present invention relates to a signal generating device and a signal generating method, and in particular to a signal generating device and a signal generating method having a transceiver for converting and outputting parallel data into high-speed serial data. Background Art

[0002] With the speed increase of communication standards such as Ethernet (registered trademark) 800GbE (Gigabit Ethernet) or PCIe (registered trademark) (Peripheral Component Interconnect Express) 6th Generation, the signal transmission method is also represented by PAM (Pulse Amplitude Modulation) 4, and is no longer a simple two-value digital signal such as NRZ (Non Return to Zero). In the future, transmission methods such as PAM8 and PAM16 are also considered to be standardized. When developing or testing products using these signals, a test signal source is required.

[0003] This signal source can certainly generate signals such as PAM4 and PAM8, but it is preferable to generate signals that have passed through a specific transmission path or that have been emphasized or filtered. Therefore, a high-speed arbitrary waveform generator (AWG) that can simulate and generate arbitrary waveforms and exceed 100Gsps (G Symbol / s) is required.

[0004] In AWG, users need to be able to freely set the analog waveform to be output. And, of course, since arbitrary signals need to be generated, the waveform needs to be set with numerical data. Therefore, AWG needs a mechanism to convert digital data output from FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) into analog data. This conversion itself can be achieved by a digital analog converter (DAC).

[0005] However, when the output rate of the required analog data is high speed, not only is it necessary to input the signal that is accelerated by multiplexing based on a multiplexer (MUX) into the DAC, but also the influence of the phase difference between the multiple input signals input to the DAC or its preceding MUX cannot be ignored. For example, when the output rate of the FPGA is 32Gsps and the bit resolution of the DAC is 8 bits, it is preferred that the maximum phase difference between all the signals input to the MUX is less than 0.1UI (Unit Interval) (3.125ps).

[0006] Here, by using the technology described in Patent Document 1, the maximum phase difference between all signals input to the MUX can be adjusted to a value less than 0.1 UI or close to this value.

[0007] Patent Document 1: Japanese Patent No. 6346212

[0008] However, the technique described in Patent Document 1 may adjust the phase of the signal input to the MUX at a position shifted by 1 clock (1UI). This occurs when the phases of the signals before the adjustment are greatly shifted.

[0009] Specifically, the technology described in Patent Document 1 cannot cope with the case where a phase difference of more than 1UI occurs between the signals before adjustment. Moreover, even if the phase difference between the signals before adjustment is suppressed to within 1UI in advance by other methods, there are technical and cost issues such as the need to add a mechanism to adjust the clock phase applied to the transceiver of the FPGA, etc., and the measurement of the phase adjustment amount that changes according to the frequency. In the case of FPGA, the phase difference between the transceivers may change each time it is started or reset. In this case, the phase adjustment amount needs to be remeasured each time it is started or reset. In addition, depending on the FPGA used, it is possible that the phase difference of the output signal cannot be suppressed to within 1UI at first.

[0010] In this case, when multiplexing signals using MUX, unexpected data is generated. For example, when the data is used as a test signal for a bit error rate tester (BERT), the test signal itself has errors, so the correct bit error rate (error rate) cannot be measured. Summary of the invention

[0011] The present invention has been made to solve such conventional problems, and an object of the present invention is to provide a signal generating device and a signal generating method capable of significantly increasing an adjustable maximum phase difference between signals outputted from a plurality of transceivers.

[0012] In order to solve the above-mentioned problems, the signal generating device involved in the present invention has the following structure, that is, it comprises: a parallel data output unit 11, which outputs multi-bit parallel data; and a plurality of transceivers 20, which have a FIFO (First-In First-Out) 21 for storing N-bit parallel data among the multi-bit parallel data output from the parallel data output unit, and converting the N-bit parallel data stored in the FIFO into 1-bit serial data, and the signal generating device 1 comprises: a phase synchronization control unit 31, which controls the phase of the 1-bit serial data converted by each of the transceivers; a divided clock output unit 14, which outputs a divided clock obtained by dividing the frequency of an external clock; a division ratio setting unit 33, which sets the division ratio of the divided clock in the divided clock output unit, and a clock selection unit 17, which selects either the external clock or the divided clock a rate control unit 34, which performs the following control, i.e., outputs a trigger pattern of half the frequency of the divided clock or the external clock selected by the clock selection unit from each of the transceivers as the 1-bit serial data; and a phase detection unit 40, which measures a voltage value corresponding to a phase difference between the divided clock or the external clock selected by the clock selection unit and the trigger pattern, the phase synchronization control unit comprising: a phase acquisition processing unit 31b, which performs a phase acquisition processing, wherein the phase acquisition processing changes the phase of the trigger pattern from an initial value while The phase detection unit 31a performs a phase difference calculation process, wherein the phase difference calculation process calculates the initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the trigger mode based on the relationship between the voltage value obtained by the phase acquisition process and the amount of change in the phase of the trigger mode from the initial value; and the phase shift process 31d performs a phase shift process, wherein the phase shift process shifts the phase of the trigger mode from the initial value by the amount of the initial phase difference so that the phase difference between the divided clock or the external clock selected by the clock selection unit and the trigger mode becomes a value within a specified range. The phase synchronization control unit repeatedly performs the phase acquisition process, the phase difference calculation process and the phase shift process while gradually reducing the division ratio through the division ratio setting unit. The clock selection unit selects the external clock to replace the divided clock after performing the phase acquisition process, the phase difference calculation process and the phase shift process when the division ratio is a predetermined minimum value.

[0013] With this configuration, the signal generating device according to the present invention can reduce the maximum phase difference between serial data outputted from a plurality of transceivers to less than 0.1 UI based on an external clock reference.

[0014] Furthermore, the signal generating device of the present invention can significantly increase the maximum adjustable phase difference between the serial data respectively outputted from the plurality of transceivers after startup or reset.

[0015] Furthermore, the signal generating device of the present invention does not require an additional mechanism such as a delay circuit outside the FPGA for suppressing the phase difference between serial data before adjustment to within 1UI in advance, and therefore does not require an investigation of the parameters applied to the additional mechanism after the product is manufactured.

[0016] Furthermore, the signal generating device involved in the present invention can be configured as follows, that is, the division ratio is an integer that is a power of 2, and the clock selection unit selects the external clock to replace the divided clock after performing the phase acquisition processing, the phase difference calculation processing and the phase shift processing when the division ratio is 2.

[0017] Furthermore, the signal generating device involved in the present invention can be configured as follows: that is, each of the transceivers comprises: a PISO (Parallel-In Serial-Out) 22, which converts the N-bit parallel data read out from the FIFO according to the read clock signal into the 1-bit serial data; a usage determination unit 23, which performs the first and second usage determination processes for determining whether the usage of the FIFO is above the usage threshold; and a phase adjustment unit 24, which performs the first phase adjustment process for reducing the phase of the read clock signal by a predetermined amount and the second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount, the phase synchronization control unit further comprising a usage control processing unit 31a, the usage control processing unit 31a performs a usage control process for controlling the usage of the FIFO, the usage control processing unit uses the start of outputting the serial data from each of the transceivers as a condition, causing the usage determination unit to perform the first usage determination process, the usage control processing unit determines that each of the transceivers has been used by the first usage determination process. The phase adjustment unit performs the first phase adjustment process on the condition that the usage of the FIFO of the transceiver is greater than the usage threshold; the usage control unit performs the second usage determination process on the condition that the number of times the usage of the FIFO of each transceiver is less than the usage threshold through the first usage determination process reaches the first determination number; the usage control unit performs the second phase adjustment process on the condition that the usage of the FIFO of each transceiver is less than the usage threshold through the second usage determination process; the usage control unit terminates the phase adjustment of the read clock signal on the condition that the number of times the usage of the FIFO of each transceiver is greater than the usage threshold through the second usage determination process reaches the second determination number.

[0018] That is, the signal generating device according to the present invention performs a usage control process to align the usage of FIFOs of all channels to half before starting the phase acquisition process, the phase difference calculation process, and the phase shift process. With this structure, the signal generating device according to the present invention can, for example, move the phase of the trigger pattern to the maximum positive and negative sides within the range of -1UI to +1UI during the phase acquisition process when the usage of the FIFO is equivalent to 2UI of the divided clock with the maximum division ratio.

[0019] Furthermore, the signal generating method involved in the present invention has the following structure, that is, it uses a signal generating device 1, and the signal generating device 1 has: a parallel data output unit 11, which outputs multi-bit parallel data; and a plurality of transceivers 20, which have a FIFO (First-In First-Out) 21 that stores N bits of parallel data among the multi-bit parallel data output from the parallel data output unit, and converts the N bits of parallel data stored in the FIFO into 1-bit serial data. The signal generating method is characterized in that the signal generating device 1 has: a divided clock output unit 14, which outputs a divided clock obtained by dividing the frequency of an external clock; a clock selection unit 17, which selects any one of the external clock and the divided clock; and a phase detection unit 40, which measures a voltage value corresponding to a phase difference between the divided clock or the external clock selected by the clock selection unit and the 1-bit serial data, and the signal generating device 1 controls the phase difference between the divided clock or the external clock selected by the clock selection unit and the 1-bit serial data. The signal generation method comprises: a frequency division ratio setting step S14, S20, setting the frequency division ratio of the frequency division clock to the frequency division clock output unit; a rate control step S15, S22, outputting a trigger pattern of half the frequency of the frequency division clock or the external clock selected by the clock selection unit from each of the transceivers as the 1-bit serial data; a phase acquisition processing step S16, S23, performing a phase acquisition processing, wherein the phase acquisition processing changes the phase of the trigger pattern from an initial value while acquiring the phase of the trigger pattern from an initial value. The voltage value measured by the phase detection unit; phase difference calculation processing steps S17 and S24, executing phase difference calculation processing, the phase difference calculation processing calculates the initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the trigger mode based on the relationship between the voltage value obtained by the phase acquisition processing step and the change in the phase of the trigger mode from the initial value; phase shift processing steps S18 and S25, executing phase shift processing, the phase shift processing shifts the phase of the trigger mode from the initial value by the initial phase difference so that the phase difference between the divided clock or the external clock selected by the clock selection unit and the trigger mode becomes a value within a specified range; steps S15 to S20, while gradually reducing the division ratio through the division ratio setting step, repeatedly executing the phase acquisition process, the phase difference calculation process and the phase shift process; and an external clock selection step S21, after executing the phase acquisition process, the phase difference calculation process and the phase shift process when the division ratio is a predetermined minimum value, the clock selection unit selects the external clock to replace the divided clock.

[0020] Furthermore, the signal generating method involved in the present invention can be structured as follows, that is, the division ratio is an integer that is a power of 2, and in the external clock selection step, after performing the phase acquisition processing, the phase difference calculation processing and the phase shift processing when the division ratio is 2, the external clock is selected to replace the divided clock.

[0021] Furthermore, the signal generation method involved in the present invention can be configured as follows, that is, each of the transceivers comprises: a PISO (Parallel-In Serial-Out) 22, which converts the N-bit parallel data read from the FIFO according to the read clock signal into the 1-bit serial data; a usage determination unit 23, which performs the first and second usage determination processes for determining whether the usage of the FIFO is above a usage threshold; and a phase adjustment unit 24, which performs the first phase adjustment process for reducing the phase of the read clock signal by a predetermined amount and the second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount, and the phase synchronization control unit comprises a usage control processing unit 31a, which performs the usage control process for controlling the usage of the FIFO, the usage control processing unit causing the usage determination unit to perform the first usage determination process based on the start of outputting the serial data from each of the transceivers, and the usage control processing unit determines that each of the transceivers is used by the first usage determination process. The phase adjustment unit performs the first phase adjustment process on the condition that the usage of the FIFO is greater than the usage threshold; the usage control unit performs the second usage determination process on the condition that the number of times the usage of the FIFO of each transceiver is less than the usage threshold through the first usage determination process reaches the first determination number; the usage control unit performs the second phase adjustment process on the condition that the usage of the FIFO of each transceiver is less than the usage threshold through the second usage determination process; the usage control unit terminates the phase adjustment of the read clock signal on the condition that the number of times the usage of the FIFO of each transceiver is greater than the usage threshold through the second usage determination process reaches the second determination number.

[0022] Effects of the Invention

[0023] The present invention provides a signal generating device and a signal generating method which can significantly increase the adjustable maximum phase difference between signals respectively outputted from a plurality of transceivers. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1It is a block diagram showing the structure of a signal generating device according to an embodiment of the present invention.

[0025] Figure 2 Yes means Figure 1 A block diagram of a part of the structure of a data output unit included in a signal generating device.

[0026] Figure 3 yes Figure 1 A schematic diagram of a phase detection unit included in a signal generating device.

[0027] Figure 4 This is a block diagram showing the configuration of one channel of the transceiver unit.

[0028] Figure 5 It is used to illustrate the Figure 1 State transition diagram of phase synchronization processing of a signal generating device.

[0029] Figure 6 This is a block diagram showing the structure of the FPGA control unit included in the data output unit.

[0030] Figure 7 This is a diagram showing the relationship between a trigger pattern output from one channel of a data output unit and a clock.

[0031] Figure 8 This is a graph showing the relationship between the voltage value corresponding to the duty ratio of the phase detection signal measured by the phase detection unit and the amount of change from the initial value of the phase of the trigger pattern.

[0032] Fig. 9 1 is a diagram for explaining the phase shift processing of the trigger mode of each channel of the phase synchronization control unit provided in the FPGA control unit. Fig. 9 (a) in the figure shows that the initial phase difference of the trigger mode of all channels is positively distributed. Fig. 9 (b) in the figure shows that the initial phase difference of the trigger mode of each channel is distributed in either positive or negative form. Fig. 9 (c) shows the case where the initial phase difference of the trigger pattern of each channel has a positive or negative distribution and the positive distribution and the negative distribution are separated by more than 0.5 UI.

[0033] Fig.10 This is a diagram showing the amount of phase shift based on the trigger pattern of the phase synchronization control unit for each frequency division ratio.

[0034] Fig.11 It means use Figure 1 A flowchart of a process of a signal generating method of a signal generating device.

[0035] Fig.12This is a diagram showing the phase relationship of the trigger pattern of each channel after the usage amount control process.

[0036] Fig.13 This is a diagram showing the phase relationship of the trigger mode of each channel when the division ratio of the divided clock is 64. Fig.13 (a) is a simplified diagram showing the timing of the trigger pattern from the transceiver of each channel after the initial phase difference is calculated by the phase difference calculation process. Fig.13 (b) is a diagram showing in simplified form the timing of the trigger pattern from the transceiver of each channel after the phase is shifted by the phase shift process.

[0037] Fig.14 This is a diagram showing the phase relationship of the trigger mode of each channel when the division ratio of the divided clock is 4. Fig.14 (a) is a simplified diagram showing the timing of the trigger pattern from the transceiver of each channel after the initial phase difference is calculated by the phase difference calculation process. Fig.14 (b) is a diagram showing in simplified form the timing of the trigger pattern from the transceiver of each channel after the phase is shifted by the phase shift process.

[0038] Fig.15 This is a diagram showing the phase relationship of the trigger mode of each channel when the division ratio of the divided clock is 2. Fig.15 (a) is a simplified diagram showing the timing of the trigger pattern from the transceiver of each channel after the initial phase difference is calculated by the phase difference calculation process. Fig.15 (b) is a diagram showing in simplified form the timing of the trigger pattern from the transceiver of each channel after the phase is shifted by the phase shift process.

[0039] Fig.16 is a diagram showing the phase relationship of the trigger pattern of each channel when the external clock is selected by the clock selection unit. Fig.16 (a) is a simplified diagram showing the timing of the trigger pattern from the transceiver of each channel after the initial phase difference is calculated by the phase difference calculation process. Fig.16 (b) is a diagram showing in simplified form the timing of the trigger pattern from the transceiver of each channel after the phase is shifted by the phase shift process. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of a signal generating device and a signal generating method according to the present invention will be described with reference to the drawings.

[0041] Figure 1The signal generating device 1 according to the present embodiment shown in the figure includes a data output unit 10, a clock selecting unit 17, a phase detecting unit 40, a MUX 50, an amplifier 52, an ADC 55, a DAC 60, an operating unit 65, and a control unit 70. The data output unit 10 is configured on, for example, an FPGA or an ASIC, but the following description assumes that they are configured on an FPGA.

[0042] The data output section 10 includes a parallel data output section 11 , a plurality of transceiver sections 12 - 1 to 12 - p , a clock generation section 13 , a divided clock output section 14 , and an FPGA control section 15 .

[0043] The parallel data output unit 11 has an internal memory (not shown) that stores a series of data sequences of a predetermined pattern in advance, or an operation circuit (not shown) that generates the data sequences. Figure 2 In the example shown, the parallel data output section 11 outputs 32×N bits of parallel data.

[0044] The parallel data output unit 11 outputs a pattern of a PAM signal composed of a multi-value K (K is an integer greater than or equal to 2) of, for example, two or more values ​​as 32×N-bit parallel data, based on the pattern information input from the operation unit 65. The parallel data output unit 11 generates a pattern of a PAM signal composed of any multi-value K such as an NRZ signal (K=2), a PAM3 signal (K=3), a PAM4 signal (K=4), a PAM5 signal (K=5), a PAM6 signal (K=6), a PAM7 signal (K=7), a PAM8 signal (K=8), etc. Here, the pattern information refers to information on the pattern of the PAM signal such as the value of K and the type of pattern (for example, a PRBS (Pseudo Random Binary Sequence) pattern, a SSPRQ (Short Stress Pattern Random Quaternary) pattern, or an arbitrary pattern).

[0045] The data output unit 10 includes p transceiver units 12 - 1 to 12 - p . Figure 1 and Figure 2 Although an example of p=8 is shown, in the present invention, the number of transceiver units 12 is not limited to 8, and may be any number.

[0046] like Figure 2 As shown, the clock signal generated by the clock generation unit 13 is distributed to each transceiver unit 12 .

[0047] Each transceiver unit 12 includes, for example, four transceivers 20-0 to 20-3. Each transceiver 20 is an output unit of FPG A and outputs a digital signal of 0 or 1. Each transceiver 20 converts N-bit parallel data stored in a FIFO 21 described later among 32×N-bit parallel data output from the parallel data output unit 11 into 1-bit serial data at the timing of the clock signal generated by the clock generating unit 13. Here, N is an integer greater than 2.

[0048] That is, each transceiver unit 12 converts 4×N-bit parallel data output from the parallel data output unit 11 into 4-bit parallel data and outputs the data. That is, the data output unit 10 outputs 4-bit parallel data for 8 channels, in other words, serial data for 32 channels.

[0049] The divided clock output unit 14 outputs a divided clock obtained by dividing the frequency of the external clock. The maximum frequency of the divided clock is half the frequency of the external clock. For example, the divided clock output unit 14 is composed of a transceiver with the same structure as each transceiver 20.

[0050] The clock selection unit 17 selects one of the external clock and the divided clock according to the clock selection signal output from the clock selection signal output unit 35 described later. In this specification, the divided clock and the external clock are simply referred to as "clock". The external clock is, for example, a 32 GHz pulse signal.

[0051] The phase detection unit 40 measures a voltage value corresponding to the phase difference between the divided clock or external clock selected by the clock selection unit 17 and the trigger pattern output from each transceiver 20. The trigger pattern is a 1-bit serial data that alternately repeats "0" and "1", and is output from each transceiver 20 when performing the phase acquisition process, phase difference calculation process, and phase shift process described later. As for the phase detection unit 40, one is respectively arranged at the subsequent stage of each transceiver 20. The phase detection unit 40 is used to confirm the phase of the trigger pattern output from each transceiver 20, so it can be assembled in the MUX 50 or independently arranged at the previous stage of the MUX 50.

[0052] The schematic diagram of the phase detection unit 40 for one channel is shown in Figure 3 As shown in the figure, the phase detection unit 40 includes, for example, a D flip-flop 41, an EXOR circuit 42, and an averaging circuit 43.

[0053] The D flip-flop 41 includes two input terminals, a D terminal and a CLK terminal, and one output terminal, a Q terminal. A trigger pattern from the corresponding transceiver 20 is input to the D terminal, and a clock selected by the clock selection unit 17 is input to the CLK terminal.

[0054] The EXOR circuit 42 outputs a phase detection signal by taking an exclusive OR of the trigger pattern from the corresponding transceiver 20 and the output signal from the Q terminal of the D flip-flop 41. When a trigger pattern with a period twice that of the clock is input to the D terminal, the phase detection signal becomes a pulse signal having a duty ratio corresponding to the phase of the trigger pattern input to the D terminal.

[0055] The averaging circuit 43 is composed of, for example, a low-pass filter to average the phase detection signal. When a trigger pattern with a period twice that of the clock is input to the D terminal, the averaging circuit 43 outputs a signal of a voltage value corresponding to the duty cycle of the phase detection signal. Thus, the phase of the trigger pattern from the corresponding transceiver 20 can be obtained as a voltage value.

[0056] The amplifier 52 amplifies the signal from the phase detection unit 40 to a voltage level suitable for the ADC 55 at the subsequent stage as necessary.

[0057] ADC55 samples the signal from the phase detection unit 40 amplified by the amplifier 52 at a predetermined sampling rate and converts it into digital data. That is, ADC55 outputs digital data of a voltage value corresponding to the phase difference between the divided clock or external clock selected by the clock selection unit 17 and the trigger pattern. Here, the predetermined sampling rate may be, for example, a value of several hundred ksps to several Msps such as 500 ksps or 1 Msps. Therefore, as ADC55, an ADC having multiple input channels such as a 4-channel ADC may be used.

[0058] The MUX 50 latches the m-bit parallel data output from each transceiver unit 12, selects n bits in a predetermined order in synchronization with the external clock selected by the clock selection unit 17, and outputs n-bit data corresponding to the frequency of the external clock selected by the clock selection unit 17. Here, n is an integer greater than 1 and less than m-1. Figure 1 In the example shown, n=1, m=4. That is, the MUX 50 can multiplex m-bit data from each transceiver unit 12 into n-bit data.

[0059] The DAC 60 is an n×p bit DAC, and outputs an analog signal with a resolution of n×p bits corresponding to the n×p bit data output from all the MUXs 50, that is, a multi-value K PAM signal. Figure 1 In the example shown, n=1 and p=8.

[0060] The operation unit 65 is used to receive the user's operation input, and is composed of, for example, a touch panel with a contact sensor, and the contact sensor is used to detect the contact position based on the contact operation on the input surface corresponding to the display screen of the display device (not shown). Alternatively, the operation unit 65 can also be composed of an input device such as a keyboard or a mouse. The operation input to the operation unit 65 is detected by the control unit 70.

[0061] The control unit 70 is composed of a control device such as a computer including a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA, a ROM (Read Only Memory), a RAM (Random Access Memory), an HDD (Hard Disk Drive), etc., and controls the operation of the above-mentioned parts constituting the signal generating device 1.

[0062] Figure 4 1 is a diagram showing the structure of one channel of the data output unit 10. Each transceiver 20 includes: a FIFO (First-In First-Out) 21 for storing N-bit parallel data among the 32×N-bit parallel data output from the parallel data output unit 11; a PISO (Parallel-In Serial-Out) 22 for converting the N-bit parallel data read from the FIFO 21 according to the read clock signal into 1-bit serial data; a usage determination unit 23 for performing the first and second usage determination processes for determining whether the usage of the FIFO 21 is above the usage threshold; a phase adjustment unit 24 for adjusting the phase of the read clock signal of the FIFO 21 in a manner of decreasing or increasing; frequency dividers 25, 26; and a subtractor 27.

[0063] That is, the transceiver 20 reads out the N-bit parallel data stored in the FIFO 21 , performs parallel / serial conversion on the read parallel data through the PISO 22 , and outputs serial data.

[0064] In the signal generating device 1 of the present embodiment, each transceiver unit 12 can be constituted by a transceiver equipped with a function of adjusting the phase of a read clock signal, such as a TX Phase Interpolator PPM Controller (hereinafter referred to as "TX PI") provided by Xilinx. Furthermore, as an FPGA constituting the data output unit 10, for example, an UltraScale+ having a GTY transceiver manufactured by Xilinx can be preferably used.

[0065] Generally, in multiple transceivers configured on an FPGA, the timings until data is actually output after they are started or reset are not necessarily consistent with each other. Therefore, the usage of FIFO 21 of transceiver 20 is usually different at the timing of starting data output. Moreover, even when focusing on one transceiver 20, the usage when starting to output data may be different each time it is started or reset.

[0066] Below, reference Figure 4 , describing the basic actions of TXPI.

[0067] FIFO 21 acts as a buffer for parallel data output from parallel data output unit 11, and can store N-bit parallel data up to a maximum of M words. FIFO 21 writes or reads N-bit parallel data at the timing of the rising edge of the input write clock signal or read clock signal. The write clock signal and the read clock signal are, for example, signals based on the clock signal generated by the clock generation unit 13.

[0068] The frequency divider 25 divides the read clock signal by the maximum word number M of the FIFO 21 to obtain the read address of the FIFO 21 . On the other hand, the frequency divider 26 divides the write clock signal by the maximum word number M of the FIFO 21 to obtain the write address of the FIFO 21 .

[0069] The subtractor 27 outputs the difference between the read address and the write address respectively outputted from the frequency dividers 25 and 26. The difference outputted from the subtractor 27 reflects the usage of the FIFO 21.

[0070] The usage determination unit 23 performs the first and second usage determination processes as follows: it determines whether the difference output from the subtractor 27 is greater than the usage threshold value at each clock of the operation clock of the FPGA constituting the data output unit 10. The usage determination unit 23 always monitors the difference between the read address and the write address of the FIFO 21 as the usage of the FIFO 21, and outputs 0 when the usage is less than the usage threshold value, and outputs 1 when the usage is greater than the usage threshold value. For example, the usage threshold value is M / 2, that is, 1 / 2 of the maximum number of words M of the FIFO 21. The usage of the FIFO 21 changes as the phase of the read clock signal changes.

[0071] The phase adjustment unit 24 performs a first phase adjustment process for reducing the phase of the read clock signal by a predetermined amount and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount in the usage control process described later. The first phase adjustment process is a process for reducing the usage of the FIFO 21, and the second phase adjustment process is a process for increasing the usage of the FIFO 21.

[0072] The phase adjustment unit 24 can offset the read address value of FIFO21 by adjusting the phase of the read clock signal of FIFO21. As a result, the phase of the parallel data output from FIFO21 is offset. However, the phase adjustment unit 24 cannot adjust the phase of the parallel data output from FIFO21 to an arbitrary value, and the adjustable phase adjustment width or the maximum adjustable amount at one time is also limited. For example, when the output data speed of the transceiver 20 is 32Gbps, the adjustable phase adjustment width of the phase adjustment unit 24 is 1 / 64UI step, and the maximum adjustable amount of the phase adjustment unit 24 is 64UI.

[0073] Below, reference Figure 5 The state transition diagram of the phase synchronization control unit 31 (reference Figure 6 The usage control process performed by the usage control processing unit 31a of FIG. 31 is a process for controlling the usage of the FIFO 21 of each transceiver 20 and is performed independently for each channel, that is, for each transceiver 20.

[0074] like Figure 5 As shown, the usage control processing unit 31a includes eight states S1 to S7, namely, the initial state, the preset state, the BUFCHK1 state, the TXPI_DEC state, the TXPI_INC state, the BUFCHK2 state, and the PHASEADJ state. The arrows between the states indicate transitions and their directions.

[0075] First, the usage control processing unit 31a shifts from the initial state S1 to the preset state S2. The preset state S2 is a state of waiting until each transceiver 20 starts to output serial data. Here, when each transceiver 20 becomes capable of starting to output serial data after startup or reset, it starts to generate a clock in a clock generation circuit (not shown). The usage control processing unit 31a can detect the timing when each transceiver 20 starts to output serial data by detecting the rising edge of the clock.

[0076] When the usage control processing unit 31a detects that each transceiver 20 starts to output serial data, it shifts from the preset state S2 to the BUFCHK1 state S3. The BUFCHK1 state S3 is a state in which the usage control processing unit 31a causes the usage determination unit 23 to execute the first usage determination process.

[0077] The usage control processing unit 31a transitions from the BUFCHK1 state S3 to the TXPI_DEC state S4 when the usage of the FIFO 21 of each transceiver 20 is determined to be greater than the usage threshold value by the first usage determination processing. The TXPI_DEC state S4 is a state in which the usage control processing unit 31a causes the phase adjustment unit 24 to execute the first phase adjustment processing.

[0078] The usage control processing unit 31 a shifts from the TXPI_DEC state S4 to the BUFCHK1 state S3 again on the condition that the phase of the read clock signal of the FIFO 21 of each transceiver 20 is decreased by a predetermined amount by the first phase adjustment processing.

[0079] The usage control processing unit 31a transitions from the BUF CHK1 state S3 to the TXPI_INC state S5 when the number of times that the usage of the FIFO 21 of each transceiver 20 is continuously determined to be less than the usage threshold value by the first usage determination processing reaches the first determination number of times. The TXPI_INC state S5 is a state in which the usage control processing unit 31a causes the phase adjustment unit 24 to execute the second phase adjustment processing.

[0080] The usage control processing unit 31a transitions from the TXPI_INC state S5 to the BUFCHK2 state S6 on the condition that the phase of the read clock signal of the FIFO 21 of each transceiver 20 is increased by a predetermined amount by the second phase adjustment processing. The BUFCHK2 state S6 is a state in which the usage control processing unit 31a causes the usage determination unit 23 to execute the second usage determination processing.

[0081] The usage control processing unit 31 a shifts again from the BUFCHK2 state S6 to the TXPI_INC state S5 on the condition that it is determined in the second usage determination process that the usage of the FIFO 21 of each transceiver 20 is less than the usage threshold.

[0082] The usage control processing unit 31a transfers from the BUFCHK2 state S6 to the PHASEADJ state S7 on the condition that the number of times the usage of the FIFO 21 of each transceiver 20 is continuously determined to be greater than the usage threshold by the second usage determination processing reaches the second determination number. The PHASEADJ state S7 is a state in which the usage control processing unit 31a causes the phase adjustment unit 24 to complete the adjustment of the phase of the read clock signal and waits until a reset signal is input to each transceiver 20.

[0083] The usage control processing unit 31a controls all the transceivers 20 Figure 5 The processing shown can align the usage of FIFO 21 of all channels to half, so that the data delay of all channels can be aligned. The phase of the 32×N bit parallel data output from the parallel data output unit 11 is in phase between all channels, so the phase of the serial data output from all transceivers 20 is also aligned to be approximately in phase.

[0084] according to Figure 5The processing shown can adjust the phase of the serial data output from the transceiver 20 with a calculation accuracy of ±0.008UI (theoretical limit value) when the phase adjustment width by the phase adjustment unit 24 is 1 / 64UI. In addition, the first determination number and the second determination number may be equal or different.

[0085] exist Figure 5 In the process of the usage control processing unit 31a shown in the figure, if the transition from the BUFCHK1 state S3 to the TXPI_DEC state S4, the transition from the BUFCHK2 state S6 to the TXPI_INC state S5, the transition from the BUFCHK1 state S3 to the TXPI_INC state S5, and the transition from the BUFCHK2 state S6 to the PHASEADJ state S7 are performed once when the respective determination conditions are satisfied, the maximum phase difference between the serial data output from all the transceivers 20 after the phase adjustment is completed becomes a value larger than the above-mentioned theoretical limit value. It is considered that this is because the usage of the FIFO 21 always fluctuates due to the jitter components of the write clock signal and the read clock signal, and therefore the determination results of the first and second usage determination processes by the usage determination unit 23 also fluctuate.

[0086] Therefore, the signal generating device 1 of this embodiment has Figure 5 In the processing of the usage control processing unit 31a shown, for the transition from BUFCHK1 state S3 to TXPI_INC state S5 and the transition from BUFCHK2 state S6 to PHASEADJ state S7, the first judgment number and the second judgment number that must continuously satisfy the transition conditions are specified, and the transition is performed only when these numbers continuously meet the transition conditions.

[0087] like Figure 6 As shown, the FPGA control unit 15 includes a phase synchronization control unit 31 , a frequency division ratio setting unit 33 , a rate control unit 34 and a clock selection signal output unit 35 .

[0088] The phase synchronization control unit 31 controls the phase of the toggle pattern, which is 1-bit serial data converted by each transceiver 20 .

[0089] The phase synchronization control unit 31 includes the above-described usage amount control processing unit 31 a , the phase acquisition processing unit 31 b , the phase difference calculation processing unit 31 c , and the phase shift processing unit 31 d .

[0090] The phase acquisition processing unit 31b performs the following phase acquisition processing: while controlling the phase adjustment unit 24 of each transceiver 20 to change the phase of the trigger pattern output from each transceiver 20 from the initial value, it acquires the voltage value measured by the phase detection unit 40. Here, the digital data of the voltage value measured by the phase detection unit 40 is input from the ADC 55 to the phase acquisition processing unit 31b.

[0091] A specific example of the phase acquisition processing by the phase acquisition processing unit 31 b will be described below. Figure 7 The relationship between the trigger pattern output from the transceiver 20 of one channel of the data output unit 10 and the clock is shown.

[0092] First, the phase acquisition processing unit 31b acquires the voltage value measured by the phase detection unit 40 at the start time of the phase acquisition processing. Here, the phase of the trigger pattern at the start time is set to 0UI. In addition, the phase synchronization control unit 31 sets one cycle of the clock at this time to 1UI, and moves the phase of the trigger pattern within the range of -0.75UI to +0.75UI while acquiring the voltage value measured by the phase detection unit 40. For example, Figure 7 As shown by the arrow in , the phase synchronization control unit 31 moves the phase of the trigger pattern from 0UI as the initial value to -0.75UI, then from -0.75UI to +0.75UI, and finally from +0.75UI to 0UI at the start time.

[0093] This means, for example, that every time the phase of the trigger pattern is shifted by about 0.1 UI, the measurement by the phase detection unit 40 is repeated. Figure 8 That result. Figure 8 In the graph, the horizontal axis represents the amount of change [UI] of the phase of the trigger pattern from the initial value, and the vertical axis represents the voltage value [V] measured by the phase detection unit 40.

[0094] Since TXPI adjusts the phase of the serial data from each transceiver 20 according to the usage of FIFO 21, if the usage in the initial state is uneven, it may not be possible to ensure the adjustment width of ±0.75UI. Therefore, the phase synchronization control unit 31 performs the usage control process described above, thereby moving the phase of the trigger pattern within the range of ±0.75UI.

[0095] In the above description, the phase change range of the trigger mode is set to -0.75UI to +0.75UI, but the present invention is not limited thereto. The phase change range of the trigger mode can be at least 1UI, for example, the phase of the trigger mode can also be changed within the range of -0.5UI to +0.5UI.

[0096] The phase difference calculation processing unit 31c performs the following phase difference calculation processing: based on the relationship between the voltage value obtained by the phase acquisition processing unit 31b and the change in the phase of the trigger mode from the initial value, the initial phase difference PC between the divided clock or external clock selected by the clock selection unit 17 and the initial value of the phase of the trigger mode is calculated.

[0097] The phase difference calculation processing unit 31c can use Figure 8 The initial phase difference PC[UI] of the trigger mode at the start of the phase acquisition process is obtained by using the measurement results shown in the figure and the following formula (1). In formula (1), V0 is the voltage value obtained by the phase acquisition processing unit 31b at the start of the phase acquisition process, VH is the maximum value of the voltage value obtained by the phase acquisition processing unit 31b, and VL is the minimum value of the voltage value obtained by the phase acquisition processing unit 31b. Each value in formula (1) may be a value corrected according to the linearity of the relationship between the phase and the voltage, rather than the actual measured value.

[0098] [Formula 1]

[0099]

[0100] The phase synchronization control unit 31 performs the same phase acquisition process and phase difference calculation process on all trigger modes of 32 channels simultaneously or sequentially. As a result, for example, the following can be obtained: Fig. 9 (a)~ Fig. 9 (c) shows the correspondence between the channel number and the initial phase difference PC.

[0101] Here, channel numbers 1 to 4 correspond to the four transceivers 20-0 to 20-3 of the transceiver section 12-1, respectively. Channel numbers 5 to 8 correspond to the four transceivers 20-0 to 20-3 of the transceiver section 12-2, respectively. Channel numbers 9 to 12 correspond to the four transceivers 20-0 to 20-3 of the transceiver section 12-3, respectively. Channel numbers 13 to 16 correspond to the four transceivers 20-0 to 20-3 of the transceiver section 12-4, respectively. Channel numbers 17 to 20 correspond to the four transceivers 20-0 to 20-3 of the transceiver section 12-5, respectively. Channel numbers 21 to 24 correspond to the four transceivers 20-0 to 20-3 of the transceiver section 12-6, respectively. Channel numbers 25 to 28 correspond to the four transceivers 20-0 to 20-3 of the transceiver section 12-7, respectively. Channel numbers 29 to 32 correspond to four transceivers 20 - 0 to 20 - 3 of the transceiver unit 12 - 8 , respectively.

[0102] The phase shift processing unit 31d performs the following phase shift processing: the phase adjustment unit 24 of each transceiver 20 is controlled to shift the phase of the trigger pattern output from each transceiver 20 from the initial value by the amount of the initial phase difference PC so that the phase difference between the divided clock or external clock selected by the clock selection unit 17 and the trigger pattern becomes a value within a predetermined range. Here, the value (phase difference) within the predetermined range refers to a value closest to 0 with the accuracy of the phase adjustment width adjustable by the phase adjustment unit 24.

[0103] Below, reference Fig. 9 (a)~ Fig. 9 (c) of FIG. 1 describes the phase shift processing of the trigger pattern of each channel performed by the phase shift processing unit 31d.

[0104] Fig. 9 (a) in FIG. 1 shows a case where the initial phase difference PC of the trigger pattern output from the transceiver 20 of all channels is positively distributed and its distribution width is less than 0.5UI. In this case, the phase shift processing unit 31d shifts the phase of the trigger pattern of all channels by -PC toward 0. The same is true when the initial phase difference PC of all channels is negatively distributed.

[0105] Fig. 9 (b) in the figure shows the case where the initial phase difference PC of the trigger mode outputted from the transceiver 20 of each channel is distributed in either positive or negative manner and its distribution width is less than 0.5UI. In this case, the phase shift processing unit 31d shifts the phase of the trigger mode with positive distribution toward 0 by -PC, and shifts the phase of the trigger mode with negative distribution toward 0 by -PC.

[0106] Fig. 9 (c) in the figure shows that the initial phase difference PC of the trigger mode output from the transceiver 20 of each channel has a positive or negative distribution and the positive distribution is separated from the negative distribution by more than 0.5UI. In this case, a part of the distribution of the initial phase difference PC that should fall within a width less than 0.5UI is apparently offset by 1UI. Therefore, the phase shift processing unit 31d, for example, shifts the phase of the trigger mode with a positive distribution toward 0 in the positive direction by 1+PC, and shifts the phase of the trigger mode with a negative distribution toward 0 in the positive direction by -PC.

[0107] In addition, from Fig. 9 (a)~ Fig. 9 As can be seen from (c) in FIG. 1 , the four transceivers 20 of the same transceiver unit 12 show the same distribution of the initial phase difference PC. In this case, it is also possible to perform phase acquisition processing and phase difference calculation processing on only one transceiver 20 of each transceiver unit 12, and regard the obtained initial phase difference PC as the common initial phase difference of the four transceivers 20 of each transceiver unit 12.

[0108] The frequency division ratio setting unit 33 sets the frequency division ratio of the frequency division clock based on the external clock to the frequency division clock output unit 14. The phase synchronization control unit 31 repeatedly performs the phase acquisition process, the phase difference calculation process, and the phase shift process while gradually reducing the frequency division ratio through the frequency division ratio setting unit 33. For example, the frequency division ratio is an integer of a power of 2, and the maximum value is 64 and the minimum value is 2. In this case, the frequency division ratio setting unit 33 repeatedly halves the frequency division ratio to change it in the order of 64, 32, 16, 8, 4, and 2.

[0109] Fig.10 This is a diagram showing the amount of phase shift of the trigger pattern based on the phase acquisition process at each frequency division ratio as a proportion of the capacity of FIFO 21 when the phase of the trigger pattern is shifted within the range of -0.75UI to +0.75UI relative to 1UI of the frequency division clock. For example, the capacity of FIFO 21 is equivalent to 128UI when 1 clock of the external clock is set to 1UI, and is equivalent to 2UI (±1UI) in the frequency division clock in which the external clock is divided by a maximum of 64.

[0110] When the frequency division ratio is 64, 75% of the capacity of FIFO 21 is used for shifting the phase of the toggle pattern. Hereinafter, each time the frequency division ratio is halved, the shift amount is also halved, and when the frequency division ratio is 1, the shift amount is 1.17% of the capacity of FIFO 21.

[0111] The rate control section 34 performs control such that a trigger pattern having a frequency half the frequency of the divided clock or the external clock selected by the clock selection section 17 is output from each transceiver 20 as 1-bit serial data output from each transceiver 20. For example, the rate control section 34 outputs N-bit parallel data from the parallel data output section 11 such that the frequency of the trigger pattern output from each transceiver 20 becomes half the frequency of the divided clock or the external clock.

[0112] The clock selection signal output unit 35 outputs a clock selection signal for selecting either the external clock or the divided clock to the clock selection unit 17. Specifically, when the division ratio set by the division ratio setting unit 33 is a predetermined minimum value, the clock selection signal output unit 35 performs phase acquisition processing, phase difference calculation processing, and phase shift processing, and then outputs a clock selection signal for selecting the external clock instead of the divided clock. The minimum value of the division ratio is, for example, 2.

[0113] The following is a signal generation method using the signal generation device 1 of the present embodiment. Fig.11 An example of the processing will be described with reference to the flowchart of FIG. 1. In addition, descriptions overlapping with the description of the structure of the above-mentioned signal generating device 1 will be appropriately omitted.

[0114] If each transceiver unit 12 is activated or reset (step S11: Yes), the phase synchronization control unit 31 performs the usage control process (step S12). For example, when the bit rate of the PAM signal output from the signal generating device 1 is changed by the user's operation input to the operation unit 65, each transceiver unit 12 is reset. Through the usage control process, the usage of the FIFO 21 of each transceiver 20 is aligned to half.

[0115] Fig.12 This is a simplified diagram showing an example of the phase relationship of the trigger pattern output from the transceiver 20 of each channel after the usage control process. The vertical dotted line in the figure represents the timing of the rising edge of the external clock. Each transceiver unit 12 has four channels, namely channel 0 to channel 3. "Ch1 channel 0", "Ch1 channel 2", "Ch4 channel 0", and "Ch7 channel 3" in the figure respectively represent channel 0 of the transceiver unit 12-1, channel 2 of the transceiver unit 12-1, channel 0 of the transceiver unit 12-4, and channel 3 of the transceiver unit 12-7. The data represented by "0" in the trigger mode of each channel is data that should be aligned to be in phase in all channels. The same description is also made in the following figures. After the usage control process, the phase of the trigger pattern of each channel is usually offset from each other compared to 1 clock of the external clock.

[0116] Next, the clock selection unit 17 selects the divided clock (divided clock selection step S13).

[0117] Next, the frequency division ratio setting section 33 sets the frequency division ratio of the frequency division clock in the frequency division clock output section 14 to 64 (frequency division ratio setting step S14). There is a phase difference between the frequency division clock and the external clock at this time, but this need not be considered at this point in time.

[0118] Next, the rate control section 34 outputs a toggle pattern having a frequency half the frequency of the divided clock at the division ratio set in the division ratio setting step S14 from each transceiver 20 (rate control step S15 ).

[0119] Next, the phase acquisition processing unit 31 b executes a phase acquisition process for acquiring the voltage value measured by the phase detection unit 40 while changing the phase of the trigger pattern output from each transceiver 20 from the initial value (phase acquisition process step S16 ).

[0120] Next, the phase difference calculation processing unit 31c performs the following phase difference calculation processing: based on the relationship between the voltage value obtained through the phase acquisition processing step S16 and the change in the phase of the trigger mode from the initial value, the initial phase difference PC between the divided clock selected through the divided clock selection step S13 and the initial value of the phase of the trigger mode is calculated (phase difference calculation processing step S17).

[0121] Fig.13 (a) is a simplified diagram showing the timing of the trigger mode of each channel after the initial phase difference PC is calculated by the phase difference calculation process when the division ratio of the divided clock is 64. At this time, if the maximum phase difference between the trigger modes of each channel is less than 32UI based on the external clock reference, the subsequent phase shift process can be performed without error.

[0122] Next, the phase shift processing unit 31d performs the following phase shift processing: the phase of the trigger pattern is shifted from the initial value by the initial phase difference PC so that the phase difference between the divided clock selected by the divided clock selection step S13 and the trigger pattern becomes a value within a specified range (phase shift processing step S18).

[0123] Fig.13 (b) is a simplified diagram showing the timing of the trigger mode of each channel after the phase is shifted by the phase shift process when the division ratio of the divided clock is 64. At this time, the maximum phase difference between the trigger modes of all channels is adjusted to be less than 0.1UI based on the divided clock reference, that is, it is adjusted to be less than 6.4UI (0.1UI×64 division) based on the external clock reference.

[0124] If the current division ratio is greater than 2 (step S19: No), the division ratio setting unit 33 sets the division ratio of the divided clock in the divided clock output unit 14 to half the current value (division ratio setting step S20). Then, the processing after step S15 is executed again.

[0125] That is, steps S15 to S20 are steps of repeatedly executing the phase acquisition process, the phase difference calculation process, and the phase shift process while the frequency division ratio is gradually reduced in the frequency division ratio setting step S20.

[0126] Fig.14 (a) is a simplified diagram showing the timing of the trigger pattern of each channel after the initial phase difference PC is calculated by the phase difference calculation process when the division ratio of the divided clock is gradually reduced by half to 32, 16, 8 and finally 4 by the division ratio setting unit 33.

[0127] Fig.14 (b) is a simplified diagram showing the timing of the trigger mode of each channel after the phase is shifted by the phase shift process when the division ratio of the divided clock is 4. At this time, the maximum phase difference between the trigger modes of all channels is adjusted to be less than 0.1UI based on the divided clock reference, that is, it is adjusted to be less than 0.4UI (0.1UI×4 division) based on the external clock reference.

[0128] Fig.15(a) is a diagram showing in simplified form the timing of the trigger pattern of each channel after the initial phase difference PC is calculated by the phase difference calculation process when the division ratio of the divided clock reaches 2 by the division ratio setting unit 33 .

[0129] Fig.15 (b) is a simplified diagram showing the timing of the trigger mode of each channel after the phase is shifted by the phase shift process when the division ratio of the divided clock is 2. At this time, the maximum phase difference between the trigger modes of all channels is adjusted to be less than 0.1UI based on the divided clock reference, that is, it is adjusted to be less than 0.2UI (0.1UI×2 division) based on the external clock reference.

[0130] On the other hand, if the current division ratio is 2 (step S19: Yes), the clock selection unit 17 selects an external clock instead of the divided clock (external clock selection step S21). The external clock corresponds to the divided clock with a division ratio of 1, but its phase is inconsistent with the normal divided clock.

[0131] Next, the rate control unit 34 outputs a toggle pattern having a frequency half that of the external clock from each transceiver 20 (rate control step S22 ).

[0132] Next, the phase acquisition processing unit 31 b executes a phase acquisition process for acquiring the voltage value measured by the phase detection unit 40 while changing the phase of the trigger pattern output from each transceiver 20 from the initial value (phase acquisition process step S23 ).

[0133] Next, the phase difference calculation processing unit 31c performs the following phase difference calculation processing: based on the relationship between the voltage value acquired through the phase acquisition processing step S23 and the change in the phase of the trigger mode from the initial value, the initial phase difference PC between the external clock selected through the external clock selection step S21 and the initial value of the phase of the trigger mode is calculated (phase difference calculation processing step S24).

[0134] Fig.16 (a) in FIG. 1 is a diagram showing in simplified form the timing of the trigger pattern of each channel after the initial phase difference PC is calculated by the phase difference calculation process when the external clock is selected by the clock selection unit 17 .

[0135] Next, the phase shift processing unit 31d performs the following phase shift processing: shifting the phase of the trigger pattern from the initial value by the initial phase difference PC so that the phase difference between the external clock selected in the external clock selection step S21 and the trigger pattern becomes a value within a specified range (phase shift processing step S25).

[0136] Fig.16(b) is a simplified diagram showing the timing of the trigger mode of each channel after the phase is shifted by the phase shift processing when the external clock is selected by the clock selection unit 17. At this time, the maximum phase difference between the trigger modes of all channels is adjusted to be less than 0.1UI (0.1UI×1 division) based on the external clock reference.

[0137] Then, the phase synchronization control unit 31 enters a standby state until each transceiver unit 12 is activated or reset again (step S11 ).

[0138] In step S11, the processing after step S12 is automatically executed by starting or resetting each transceiver unit 12, but the present invention is not limited to this. For example, in step S11, the user may press an execution button provided on an operation screen (not shown) of the signal generating device 1 via the operation unit 65, thereby allowing the user to execute the processing after step S12 at any timing.

[0139] In addition, if the phase adjustment of the trigger mode output from each transceiver 20 is completed in step S25, the FPGA control unit 15 continues to automatically transfer to the mode of the PAM signal when normal action occurs, and outputs N bits of parallel data for normal action corresponding to the frequency of the external clock from the parallel data output unit 11.

[0140] In this way, in the signal generating method using the signal generating device 1 of the present embodiment, the phase of the trigger mode of each channel can be coarsely adjusted by a large movement amount using a divided clock with a large division ratio, and finally the phase of the trigger mode of each channel can be finely adjusted by a small movement amount using an external clock with a division ratio equivalent to 1.

[0141] As described above, the signal generating device 1 according to the present embodiment repeatedly executes the phase acquisition process, the phase difference calculation process, and the phase shift process while the division ratio setting unit 33 gradually reduces the division ratio of the divided clock.

[0142] With this configuration, the signal generating device 1 according to the present embodiment can reduce the maximum phase difference between the serial data outputted from the plurality of transceivers 20 to 0.1 UI or less based on the external clock reference.

[0143] Furthermore, the signal generating device 1 according to the present embodiment can significantly increase the maximum adjustable phase difference between the serial data outputted from the plurality of transceivers 20 after startup or reset.

[0144] For example, the signal generating device 1 according to the present embodiment can set the maximum adjustable phase difference between the serial data from each transceiver 20 to 32UI based on the external clock reference. If this value is, for example, 32Gbps, it is equivalent to 1000ps. For example, the phase error in the data sheet of the GTY transceiver of UltraScale+ manufactured by Xilinx is 500ps, so the signal generating device 1 according to the present embodiment can converge the phase error.

[0145] Furthermore, the signal generating device 1 according to the present embodiment does not require an additional mechanism such as a delay circuit outside the FPGA for suppressing the phase difference between serial data before adjustment to within 1UI in advance, and therefore does not require an investigation of parameters applied to the additional mechanism after product manufacturing.

[0146] In addition, the signal generating device 1 involved in this embodiment requires ADC55 in each channel, but their required speed performance is low (hundreds of ksps to several Msps), so it is also possible to use an ADC with multiple input channels, and it is expected that the ADC peripheral circuit can be miniaturized. In addition, the signal generating device 1 involved in this embodiment does not require an external delay circuit, so the circuit scale and substrate size can also be reduced.

[0147] Furthermore, the signal generating device 1 according to the present embodiment performs a usage control process to align the usage of the FIFO 21 of all channels to half before starting the phase acquisition process, the phase difference calculation process, and the phase shift process. Thus, the signal generating device 1 according to the present embodiment can, for example, shift the phase of the trigger pattern to the maximum positive and negative sides within the range of -1UI to +1UI during the phase acquisition process when the usage of the FIFO 21 is equivalent to 2UI of the divided clock with the maximum division ratio.

[0148] Explanation of symbols

[0149] 1-signal generating device, 10-data output unit, 11-parallel data output unit, 12, 12-1 to 12-8-transceiver unit, 13-clock generating unit, 14-frequency division clock output unit, 15-FPGA control unit, 17-clock selecting unit, 20, 20-0 to 20-3-transceiver, 21-FIFO, 22-PISO, 23-usage determination unit, 24-phase adjustment unit, 25, 26-frequency divider, 27-subtractor, 31-phase synchronization control unit, 31a-usage control processing unit, 31b-phase acquisition processing unit, 31c-phase difference calculation processing unit, 31d-phase shift processing unit, 33-division ratio setting unit, 34-rate control unit, 40-phase detection unit, 41-D flip-flop, 42-EXOR circuit, 43-averaging circuit, 50-MUX, 52-amplifier, 55-ADC, 60-DAC, 65-operation unit, 70-control unit.

Claims

1. A signal generating device, comprising: A parallel data output unit (11) outputs multi-bit parallel data; and A plurality of transceivers (20) having a FIFO (21) for storing N-bit parallel data among the multi-bit parallel data output from the parallel data output section, and converting the N-bit parallel data stored in the FIFO into 1-bit serial data, The signal generating device (1) is characterized in that it comprises: A phase synchronization control unit (31) for controlling the phase of the 1-bit serial data converted by each of the transceivers; A frequency-divided clock output unit (14) outputs a frequency-divided clock obtained by dividing the frequency of an external clock; A frequency division ratio setting unit (33) sets the frequency division ratio of the frequency division clock in the frequency division clock output unit, A clock selection unit (17) for selecting any one of the external clock and the divided clock; A rate control unit (34) performs control such that a trigger pattern having a frequency of half the frequency of the divided clock or the external clock selected by the clock selection unit is output from each of the transceivers as the 1-bit serial data; and A phase detection unit (40) measures a voltage value corresponding to a phase difference between the divided clock or the external clock selected by the clock selection unit and the trigger pattern, The phase synchronization control unit comprises: A phase acquisition processing unit (31b) performs a phase acquisition process, wherein the phase acquisition process changes the phase of the trigger mode from an initial value while acquiring the voltage value measured by the phase detection unit; a phase difference calculation processing unit (31c) for performing phase difference calculation processing, wherein the phase difference calculation processing calculates an initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the trigger mode based on a relationship between the voltage value acquired by the phase acquisition processing unit and the amount of change of the phase of the trigger mode from the initial value; and a phase shift processing unit (31d) for performing a phase shift processing, wherein the phase of the trigger pattern is shifted from the initial value by the amount of the initial phase difference so that the phase difference between the divided clock or the external clock selected by the clock selection unit and the trigger pattern becomes a value within a prescribed range, The phase synchronization control unit repeatedly executes the phase acquisition process, the phase difference calculation process, and the phase shift process while gradually reducing the frequency division ratio through the frequency division ratio setting unit. The clock selection section selects the external clock instead of the divided clock after executing the phase acquisition process, the phase difference calculation process, and the phase shift process when the frequency division ratio is a predetermined minimum value.

2. The signal generating device according to claim 1, characterized in that: The frequency division ratio is an integer that is a power of 2, The clock selection section selects the external clock instead of the divided clock after executing the phase acquisition process, the phase difference calculation process, and the phase shift process when the frequency division ratio is 2.

3. The signal generating device according to claim 1, characterized in that: Each of the transceivers has: PISO (22), converting the N-bit parallel data read out from the FIFO according to the read clock signal into the 1-bit serial data; A usage amount determination unit (23) performs first and second usage amount determination processes for determining whether the usage amount of the FIFO is greater than a usage amount threshold value; and A phase adjustment unit (24) performs a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount. The phase synchronization control unit further includes a usage amount control processing unit (31a) that performs usage amount control processing for controlling the usage amount of the FIFO. The usage amount control processing unit causes the usage amount determination unit to execute the first usage amount determination processing under the condition that the serial data starts to be output from each of the transceivers. The usage control processing unit causes the phase adjustment unit to execute the first phase adjustment processing on the condition that the usage of the FIFO of each of the transceivers is determined to be greater than the usage threshold value by the first usage determination processing, The usage control processing unit causes the usage determination unit to execute the second usage determination processing on the condition that the number of times the usage of the FIFO of each of the transceivers is continuously determined to be less than the usage threshold by the first usage determination processing reaches a first determination number, The usage control processing unit causes the phase adjustment unit to execute the second phase adjustment processing on the condition that the usage of the FIFO of each of the transceivers is determined to be less than the usage threshold value by the second usage determination processing, The usage control processing unit causes the phase adjustment unit to end adjustment of the phase of the read clock signal when the number of times the usage of the FIFO of each transceiver is continuously determined to be greater than the usage threshold by the second usage determination processing reaches a second determination number.

4. A signal generating method, which uses a signal generating device (1), wherein the signal generating device (1) comprises: A parallel data output unit (11) outputs multi-bit parallel data; and A plurality of transceivers (20) having a FIFO (21) for storing N-bit parallel data among the multi-bit parallel data output from the parallel data output section, and converting the N-bit parallel data stored in the FIFO into 1-bit serial data, The signal generating method is characterized in that the signal generating device (1) comprises: A frequency-divided clock output unit (14) outputs a frequency-divided clock obtained by dividing the frequency of an external clock; A clock selection unit (17) for selecting any one of the external clock and the divided clock; and A phase detection unit (40) measures a voltage value corresponding to a phase difference between the divided clock or the external clock selected by the clock selection unit and the 1-bit serial data, The signal generating device (1) controls the phase of the 1-bit serial data converted by each of the transceivers, The signal generating method comprises: A frequency division ratio setting step (S14, S20), setting the frequency division ratio of the frequency division clock in the frequency division clock output part; a rate control step (S15, S22), outputting a trigger pattern of half the frequency of the divided clock or the external clock selected by the clock selection unit from each of the transceivers as the 1-bit serial data; a phase acquisition processing step (S16, S23), executing a phase acquisition processing, wherein the phase acquisition processing changes the phase of the trigger pattern from an initial value while acquiring the voltage value measured by the phase detection unit; a phase difference calculation processing step (S17, S24), performing a phase difference calculation processing, the phase difference calculation processing calculating an initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the trigger mode based on the relationship between the voltage value acquired by the phase acquisition processing step and the amount of change of the phase of the trigger mode from the initial value; A phase shift processing step (S18, S25), performing a phase shift processing, wherein the phase of the trigger pattern is shifted from the initial value by the amount of the initial phase difference so that the phase difference between the divided clock or the external clock selected by the clock selection unit and the trigger pattern becomes a value within a prescribed range; Steps (S15 to S20), while gradually reducing the frequency division ratio through the frequency division ratio setting step, repeatedly executing the phase acquisition process, the phase difference calculation process and the phase shift process; and The external clock selection step (S21) selects the external clock instead of the divided clock by the clock selection unit after executing the phase acquisition process, the phase difference calculation process and the phase shift process when the frequency division ratio is a predetermined minimum value.

5. The signal generating method according to claim 4, characterized in that: The frequency division ratio is an integer that is a power of 2, In the external clock selection step, after the phase acquisition process, the phase difference calculation process, and the phase shift process are performed when the frequency division ratio is 2, the external clock is selected instead of the divided clock.

6. The signal generating method according to claim 4, characterized in that: Each of the transceivers has: PISO (22), converting the N-bit parallel data read out from the FIFO according to the read clock signal into the 1-bit serial data; A usage amount determination unit (23) performs first and second usage amount determination processes for determining whether the usage amount of the FIFO is greater than a usage amount threshold value; and A phase adjustment unit (24) performs a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount. The phase synchronization control unit includes a usage amount control processing unit (31a) that performs usage amount control processing for controlling the usage amount of the FIFO. The usage amount control processing unit causes the usage amount determination unit to execute the first usage amount determination processing under the condition that the serial data starts to be output from each of the transceivers. The usage control processing unit causes the phase adjustment unit to execute the first phase adjustment processing on the condition that the usage of the FIFO of each of the transceivers is determined to be greater than the usage threshold value by the first usage determination processing, The usage control processing unit causes the usage determination unit to execute the second usage determination processing on the condition that the number of times the usage of the FIFO of each of the transceivers is continuously determined to be less than the usage threshold by the first usage determination processing reaches a first determination number, The usage control processing unit causes the phase adjustment unit to execute the second phase adjustment processing on the condition that the usage of the FIFO of each of the transceivers is determined to be less than the usage threshold value by the second usage determination processing, The usage control processing unit causes the phase adjustment unit to end adjustment of the phase of the read clock signal when the number of times the usage of the FIFO of each transceiver is continuously determined to be greater than the usage threshold by the second usage determination processing reaches a second determination number.

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