Instruction scheduling method and device, equipment, storage medium and program product

Abstract

The invention relates to an instruction scheduling method and device, equipment, a storage medium and a program product. The method comprises the following steps: acquiring a plurality of instructions in an instruction basic block; reversely traversing each instruction from the penultimate instruction in the instruction basic block, and determining a to-be-scheduled target instruction according to a dependency relationship between adjacent instructions; a scheduling positioning instruction corresponding to the target instruction is determined in the instruction basic block, the scheduling position of the target instruction is determined according to the scheduling positioning instruction, and the scheduling positioning instruction is an instruction which is located behind the target instruction and has a dependency relationship with the target instruction for the first time; and inserting the target instruction into the scheduling position. By adopting the method, the program execution speed can be increased.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction scheduling method, device, equipment, storage medium and program product. Background Art

[0002] A compiler is a software tool that translates high-level programming languages ​​into computer executable code. The compiler converts the source code written by the programmer into binary instructions that the computer can understand and execute, so that the above binary instructions can be packaged into executable files or libraries to run the program on the computer.

[0003] In related technologies, the Low Level Virtual Machine (LLVM) is a comprehensive compiler tool chain that can provide general tools and libraries for developing compilers, optimizers, code generators, etc. The LLVM compiler can convert high-level programming languages ​​into programs to be executed.

[0004] However, because the hardware pipeline is too long, if the execution of the next instruction in the program generated by the LLVM compiler needs to read the write result of the previous instruction, there is a dependency between the next instruction and the previous instruction. At this time, a delay is required between the previous instruction and the next instruction, resulting in slower program execution. Summary of the invention

[0005] Based on this, it is necessary to provide an instruction scheduling method, device, equipment, storage medium and program product that can improve the speed of program execution in response to the above technical problems.

[0006] In a first aspect, the present application provides an instruction scheduling method, comprising:

[0007] Get multiple instructions in an instruction basic block;

[0008] In the instruction basic block, each instruction is traversed backwards starting from the penultimate instruction, and a target instruction to be scheduled is determined according to a dependency relationship between adjacent instructions;

[0009] Determine the scheduling and positioning instruction corresponding to the target instruction in the instruction basic block, and determine the scheduling position of the target instruction according to the scheduling and positioning instruction, wherein the scheduling and positioning instruction is the first instruction that is located after the target instruction and has the dependency relationship with the target instruction;

[0010] The target instruction is inserted into the scheduling position.

[0011] In one embodiment, after obtaining the plurality of instructions in the instruction basic block to be scheduled, the method further comprises:

[0012] Determine whether the number of instructions in the instruction basic block is greater than or equal to a threshold number;

[0013] If the number of instructions in the instruction basic block is greater than the instruction number threshold, the step of reversely traversing each instruction in the instruction basic block to be scheduled is executed to determine the target instruction to be scheduled according to the dependency relationship between adjacent instructions.

[0014] In one embodiment, determining the target instruction to be scheduled according to the dependency relationship between adjacent instructions includes:

[0015] If the adjacent instructions have the dependency relationship and the subsequent instruction among the adjacent instructions has a backward movement attribute, the subsequent instruction is determined to be the target instruction.

[0016] In one embodiment, the method further comprises:

[0017] If the adjacent instructions have the dependency relationship and the subsequent instruction among the adjacent instructions does not have the backward movement attribute, an instruction delay flag is set for the subsequent instruction, and the instruction delay flag is used to indicate that the subsequent instruction has a dependency relationship with the previous instruction.

[0018] In one embodiment, determining the dispatch position of the target instruction according to the dispatch positioning instruction includes:

[0019] If there is a dependency relationship between the first instruction and the second instruction, the position between the first instruction and the second instruction is determined as the scheduling position, the first instruction is the first instruction before the scheduling positioning instruction, and the second instruction is the second instruction before the scheduling positioning instruction;

[0020] If there is no dependency relationship between the first instruction and the second instruction, the scheduling position is determined according to the second instruction and the third instruction, and the third instruction is the third instruction before the scheduling positioning instruction.

[0021] In one embodiment, determining the dispatch position according to the second instruction and the third instruction includes:

[0022] If the second instruction and the third instruction have a dependency relationship, determining the position between the second instruction and the third instruction as the scheduling position;

[0023] If the second instruction and the third instruction do not have a dependency relationship, the position between the first instruction and the second instruction is determined as the scheduling position.

[0024] In one embodiment, after fetching the plurality of instructions in the instruction basic block, the method further comprises:

[0025] If the dependency relationship exists between the penultimate instruction and the penultimate instruction in the instruction basic block, an instruction delay flag is added to the penultimate instruction.

[0026] In one embodiment, the dependency relationship is used to indicate that a source operand of a subsequent instruction comes from a target operand of a preceding instruction.

[0027] In a second aspect, the present application provides an instruction scheduling device, comprising:

[0028] An acquisition module, used for acquiring multiple instructions in an instruction basic block;

[0029] A traversal module, used to traverse each instruction in the instruction basic block in reverse order starting from the penultimate instruction, and determine a target instruction to be scheduled according to a dependency relationship between adjacent instructions;

[0030] A positioning module, used to determine the scheduling positioning instruction corresponding to the target instruction in the instruction basic block, and determine the scheduling position of the target instruction according to the scheduling positioning instruction, wherein the scheduling positioning instruction is the first instruction that is located after the target instruction and has the dependency relationship with the target instruction;

[0031] An insertion module is used to insert the target instruction into the scheduling position.

[0032] In one of the embodiments, the traversal module also includes determining whether the number of instructions in the instruction basic block is greater than or equal to a threshold number; if the number of instructions in the instruction basic block is greater than the threshold number, each instruction in the instruction basic block to be scheduled is traversed in reverse, and the target instruction to be scheduled is determined according to the dependency relationship between adjacent instructions.

[0033] In one of the embodiments, the positioning module is further configured to determine that the subsequent instruction is the target instruction if the adjacent instructions have the dependency relationship and the subsequent instruction among the adjacent instructions has a backward movement attribute.

[0034] In one of the embodiments, the traversal module is also used to set an instruction delay flag for the subsequent instruction if the adjacent instructions have the dependency relationship and the subsequent instruction among the adjacent instructions does not have the backward movement attribute, and the instruction delay flag is used to indicate that the subsequent instruction has a dependency relationship with the previous instruction.

[0035] In one embodiment, the positioning module is also used to determine the position between the first instruction and the second instruction as the scheduling position if there is a dependency relationship between the first instruction and the second instruction, the first instruction is the first instruction before the scheduling positioning instruction, and the second instruction is the second instruction before the scheduling positioning instruction; if there is no dependency relationship between the first instruction and the second instruction, determine the scheduling position according to the second instruction and the third instruction, and the third instruction is the third instruction before the scheduling positioning instruction.

[0036] In one embodiment, the positioning module is further used to determine the position between the second instruction and the third instruction as the scheduling position if there is a dependency relationship between the second instruction and the third instruction; if there is no dependency relationship between the second instruction and the third instruction, determine the position between the first instruction and the second instruction as the scheduling position.

[0037] In one of the embodiments, the traversal module is further configured to add an instruction delay flag to the penultimate instruction if the dependency relationship exists between the penultimate instruction and the penultimate instruction in the instruction basic block.

[0038] In one embodiment, the dependency relationship is used to indicate that a source operand of a subsequent instruction comes from a target operand of a preceding instruction.

[0039] In a third aspect, the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method described in the first aspect when executing the computer program.

[0040] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0041] In a fifth aspect, the present application provides a computer program product, including a computer program, characterized in that when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0042] The above instruction scheduling method, device, equipment, storage medium and program product obtain multiple instructions in the instruction basic block; reversely traverse each instruction from the second to last instruction in the instruction basic block, and determine the target instruction to be scheduled according to the dependency relationship between adjacent instructions; determine the scheduling positioning instruction corresponding to the target instruction in the instruction basic block, and determine the scheduling position of the target instruction according to the scheduling positioning instruction, the scheduling positioning instruction is the first instruction that is located after the target instruction and has a dependency relationship with the target instruction; insert the target instruction into the scheduling position. Since each instruction in the instruction basic block is reversely traversed, and the target instruction to be scheduled is determined according to the dependency relationship between adjacent instructions, adjacent instructions with dependency relationships can be scheduled to the scheduling position, reducing the delay between adjacent instructions, thereby improving the speed of program execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 It is a workflow diagram of the LLVM compiler in the related art;

[0045] Figure 2 A schematic diagram of a module of an intermediate language in the related art;

[0046] Figure 3 A schematic diagram of instruction scheduling optimization in the LLVM compiler in the related art;

[0047] Figure 4 A schematic diagram of a basic block of instructions in the related art;

[0048] Figure 5 A flowchart of an instruction scheduling method provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of instruction scheduling provided in an embodiment of the present application;

[0050] Figure 7 A schematic diagram of an instruction basic block before scheduling provided by an embodiment of the present application;

[0051] Figure 8 A schematic diagram of an instruction basic block after scheduling provided by an embodiment of the present application;

[0052] Fig. 9A flowchart of another instruction scheduling method provided in an embodiment of the present application;

[0053] Fig.10 A flowchart of another instruction scheduling method provided in an embodiment of the present application;

[0054] Fig.11 A structural block diagram of an instruction scheduling device provided in an embodiment of the present application;

[0055] Fig.12 An internal structure diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0057] First, the related technology will be described below.

[0058] A compiler is a software tool that translates high-level programming languages ​​into computer executable code. The compiler converts the source code written by the programmer into binary instructions that the computer can understand and execute, so that the above binary instructions can be packaged into executable files or libraries to run the program on the computer.

[0059] In related technologies, the Low Level Virtual Machine (LLVM) is an open source compiler infrastructure project and a comprehensive compiler tool chain that can provide common tools and libraries for developing compilers, optimizers, code generators, etc. The LLVM compiler can convert high-level programming languages ​​into programs to be executed.

[0060] For example, Figure 1 is a workflow diagram of the LLVM compiler in the related technology, such as Figure 1 As shown, a high-level programming language is input into the LLVM compiler, and the compilation component (e.g., Clang) can first convert the high-level programming language into an intermediate language, and then the intermediate language component (e.g., Pass) can perform a series of optimizations on the intermediate language to generate machine code.

[0061] Among them, high-level programming languages ​​can include C language, C++ language, OpenCL language, etc. Clang is part of the LLVM tool chain, which can convert high-level languages ​​into LLVM's intermediate language. Pass is the LLVM component that processes intermediate languages, which can perform data flow control flow analysis, instruction scheduling, instruction selection, constant propagation folding, redundancy elimination, register allocation and other processing optimizations on the intermediate language. Machine code is the binary instruction code of the hardware. The machine code will be sent to other related modules such as the linker or driver to be processed into information that can be executed on the hardware. The intermediate language can be composed of an instruction part and other information, such as target platform characteristics, global variable function declarations and other information. The intermediate language generated by a program is represented by a module.

[0062] For example, Figure 2 It is a schematic diagram of the module of the intermediate language in the related technology, such as Figure 2 As shown, the intermediate language module includes function blocks (Fucntion), target platform characteristics and global variable function declarations (Target and GlobalVariable Information). A module includes one or more Fucntions, and each Fucntion also includes one or more instruction basic blocks (BasicBlocks). A BasicBlock usually includes one or more instructions. Each BasicBlock includes a unique label (Label) to distinguish different BasicBlocks. The instructions in each BasicBlock can be represented by the instruction opcode name (Inst x) and the instruction operation data (R x). The instruction opcode can include operation opcodes such as addition and logical shift.

[0063] Continue to refer Figure 2 , instruction Inst2 R2, R1, R9, can mean that the operands of instruction Inst2 are R2, R1, R9, where the first operand R2 is the target operand, and the remaining operands R1 and R9 are source operands.

[0064] Figure 3 A schematic diagram of instruction scheduling optimization in the LLVM compiler in the related art, such as Figure 3 As shown, in the LLVM compiler, instruction scheduling is performed both before and after register allocation.

[0065] Regarding instruction scheduling before register allocation, the registers allocated in the current LLVM intermediate language are virtual registers, and the number of registers is not limited. At this time, the constraints on instruction scheduling are minimal, which can greatly improve the parallelism of instructions. However, in the register allocation stage, physical registers are used to replace virtual registers. Due to the limited number of physical registers, the register pressure increases, which may cause register overflow and affect program performance.

[0066] Instruction scheduling is performed after register allocation. In the register allocation stage, register reuse and other situations will increase the dependency between instructions, destroying the instruction scheduling optimization done before register allocation, so instruction scheduling must be performed again after register allocation.

[0067] In the related art, since the hardware pipeline is too long, if the execution of the next instruction in the program converted and generated by the LLVM compiler needs to read the write result of the previous instruction, there is a dependency relationship between the next instruction and the previous instruction. At this time, a delay is required between the previous instruction and the next instruction, resulting in a slower execution speed of the program.

[0068] For example, Figure 4 is a schematic diagram of an instruction basic block in the related art, such as Figure 4 As shown, instruction Inst2 is adjacent to instruction Inst1, and source operand R1 of Inst2 comes from target operand R1 of Inst1. Therefore, there is a dependency relationship between instruction Inst2 and instruction Inst1, and a delay is required during execution.

[0069] To solve the above technical problems, the embodiments of the present application provide an instruction scheduling method, apparatus, device, storage medium and program product, which traverse each instruction in the instruction basic block in reverse and determine the target instruction to be scheduled based on the dependency relationship between adjacent instructions, so that adjacent instructions with dependencies can be scheduled to the scheduling position, reducing the delay between adjacent instructions, thereby improving the speed of program execution.

[0070] It should be noted that the instruction scheduling method provided in the embodiment of the present application is used for optimizing instruction scheduling before register allocation, and the instructions of the instruction scheduling are within the BasicBlock, thereby resolving the delay caused by the dependency between instructions.

[0071] It should be understood that the embodiment of the present application does not limit the application environment of the above instruction scheduling method, and can be applied to any terminal device. Among them, the terminal device can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car devices, projection devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. Head-mounted devices can be virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc.

[0072] In an exemplary embodiment, Figure 5 As shown, an instruction scheduling method is provided, and the method is applied to a terminal device as an example for explanation. The instruction scheduling method includes S201-S204:

[0073] S201, obtaining multiple instructions in an instruction basic block.

[0074] In the present application, after a high-level programming language is input into the LLVM compiler of a terminal device and the LLVM compiler converts the high-level programming language into an intermediate language to generate instruction basic blocks corresponding to the program to be executed, multiple instructions in the instruction basic block can be obtained, thereby scheduling the multiple instructions.

[0075] In some embodiments, the terminal device may also determine whether the number of instructions in the instruction basic block is greater than or equal to the number threshold. If the number of instructions in the instruction basic block is less than the number threshold, the instruction scheduling in the instruction basic block is no longer performed. If the number of instructions in the instruction basic block is greater than the number threshold, the step of reversely traversing each instruction in the instruction basic block to be scheduled is performed to determine the target instruction to be scheduled based on the dependency relationship between adjacent instructions.

[0076] Among them, the above-mentioned number threshold can be specifically set according to actual conditions, and the embodiments of the present application do not limit this. For example, the number threshold can be 2, 3, 4, etc.

[0077] In other embodiments, it may also be determined whether there is a dependency relationship between the penultimate instruction and the penultimate instruction in the instruction basic block. If there is a dependency relationship between the penultimate instruction and the penultimate instruction in the instruction basic block, an instruction delay flag is added to the penultimate instruction.

[0078] The dependency relationship is used to indicate that the source operand of the subsequent instruction comes from the target operand of the previous instruction. For example, if the instruction Inst2 is adjacent to the instruction Inst1, and the source operand R1 of Inst2 comes from the target operand of Inst1, then there is a dependency relationship between the instruction Inst2 and the instruction Inst1.

[0079] The instruction delay flag is used to indicate that the instruction has a dependency relationship with the previous instruction.

[0080] In the present application, when there is a dependency relationship between the penultimate instruction and the penultimate instruction in an instruction basic block, since they are already at the end of the instruction basic block and cannot be scheduled later, only the instruction delay flag needs to be set for the penultimate instruction.

[0081] S202 , traverse each instruction in the instruction basic block in reverse order starting from the penultimate instruction, and determine a target instruction to be scheduled according to a dependency relationship between adjacent instructions.

[0082] In this step, after the terminal device obtains multiple instructions in the instruction basic block, it can reversely traverse each instruction in the instruction basic block starting from the second to last instruction, and determine the target instruction to be scheduled according to the dependency relationship between adjacent instructions.

[0083] Wherein, adjacent instructions may be continuous instructions in the physical space. For example, if the instruction Inst2 is traversed backward from the second-to-last instruction, the instruction Inst1 closest to the instruction Inst2 in the physical space before the instruction Inst2 may form adjacent instructions "Inst2, Inst1" with the instruction Inst2.

[0084] In some embodiments, in the process of traversing each instruction in reverse from the penultimate instruction, if the traversed instruction is a null instruction, the traversal of the instruction basic block may end.

[0085] It should be understood that the embodiments of the present application do not limit how to determine the target instruction to be scheduled based on the dependency relationship between adjacent instructions. In some embodiments, after traversing a certain instruction, the terminal device can first determine whether the instruction has a dependency relationship with the adjacent instructions, and then determine whether the subsequent instruction in the adjacent instructions has the property of moving backward. If there is a dependency relationship between the adjacent instructions and the subsequent instruction in the adjacent instructions has the property of moving backward, the terminal device can determine that the subsequent instruction is the target instruction.

[0086] The dependency relationship is used to indicate that the source operand of the subsequent instruction comes from the target operand of the previous instruction. For example, if the instruction Inst2 is adjacent to the instruction Inst1, and the source operand R1 of Inst2 comes from the target operand of Inst1, then there is a dependency relationship between the instruction Inst2 and the instruction Inst1.

[0087] The backward moving attribute is used to indicate that the instruction can be moved backward. For example, if there is no dependency relationship between an instruction and the subsequent instruction, the instruction has the backward moving attribute.

[0088] In other embodiments, if adjacent instructions have a dependency relationship and the subsequent instruction among the adjacent instructions does not have a backward movement attribute, an instruction delay flag is set for the subsequent instruction, and the instruction delay flag is used to indicate that the subsequent instruction has a dependency relationship with the previous instruction.

[0089] Exemplarily, if there is no dependency between adjacent instructions, they are not processed, and the reverse traversal is returned to obtain the previous instruction. If there is a dependency between adjacent instructions and a backward movement attribute, the subsequent instruction in the adjacent instructions can be determined as the target instruction and scheduled. If there is a dependency between adjacent instructions and no backward movement attribute, an instruction delay flag can be set for the subsequent instruction in the adjacent instructions.

[0090] S203: Determine a scheduling and positioning instruction corresponding to the target instruction in the instruction basic block, and determine a scheduling position of the target instruction according to the scheduling and positioning instruction.

[0091] In this step, after determining the target instruction to be scheduled according to the dependency relationship between adjacent instructions, the scheduling positioning instruction corresponding to the target instruction can be determined in the instruction basic block, and the scheduling position of the target instruction can be determined according to the scheduling positioning instruction.

[0092] The dispatching and locating instruction is the first instruction that is located after the target instruction and has a dependency relationship with the target instruction. For example, if the target instruction is Inst2, the first instruction that uses the target operand of instruction Inst2 after the target instruction is the dispatching and locating instruction (UseInst). If UseInst is not in the identified basic block, it is an empty instruction.

[0093] It should be understood that the embodiments of the present application do not limit how to determine the dispatch position of the target instruction according to the dispatch positioning instruction. In some embodiments, if there is a dependency relationship between the first instruction and the second instruction, the position between the first instruction and the second instruction is determined as the dispatch position. If there is no dependency relationship between the first instruction and the second instruction, the dispatch position is determined according to the second instruction and the third instruction.

[0094] It should be understood that the embodiments of the present application do not limit how to determine the scheduling position according to the second instruction and the third instruction. In some embodiments, if the second instruction and the third instruction have a dependency relationship, the position between the second instruction and the third instruction is determined as the scheduling position. If the second instruction and the third instruction do not have a dependency relationship, the position between the first instruction and the second instruction is determined as the scheduling position.

[0095] Among them, the first instruction is the first instruction before the scheduling and positioning instruction, the second instruction is the second instruction before the scheduling and positioning instruction, and the third instruction is the third instruction before the scheduling and positioning instruction.

[0096] For example, the first instruction before UseInst can be the first instruction (PreInst1), the second instruction before UseInst can be the second instruction (PreInst2), and the third instruction before UseInst can be the third instruction (PreInst3). If UseInst is an empty instruction, PreInst1 is the last instruction of the instruction basic block.

[0097] Exemplarily, the target instruction is ScheInst, and the position of ScheInst is the scheduling position of the target instruction. If there is a dependency relationship between PreInst1 and PreInst2, the position between the first instruction and the second instruction is the position of ScheInst. If there is no dependency relationship between PreInst1 and PreInst2, PreInst3 can be obtained, and the scheduling position of the target instruction can be determined based on whether there is a dependency relationship between PreInst2 and PreInst3. If there is a dependency relationship between PreInst2 and PreInst3, the position between PreInst2 and PreInst3 is the position of ScheInst, and if there is no dependency relationship between PreInst2 and PreInst3, the position between PreInst1 and PreInst2 is the position of ScheInst.

[0098] For example, Figure 6 A schematic diagram of an instruction scheduling provided in an embodiment of the present application, such as Figure 6As shown, the source operand of instruction Inst2 includes R1, and the target operand of instruction Inst1 adjacent to instruction Inst2 is R1, so there is a dependency relationship between Inst2 and Inst1. In addition, the target operand of instruction Inst2 is R2, and the source operand of instruction Inst3 adjacent to instruction Inst2 does not include R2, so there is no dependency relationship between Inst3 and Inst2, and Inst2 has a backward moving attribute. Since there is a dependency relationship between Inst22 and Inst1 and Inst2 has a backward moving attribute, Inst2 can be scheduled backward for the target instruction. In the scheduling process, the first instruction that is located after Inst2 and has a dependency relationship with Inst2 is Inst6, then Inst6 is the scheduling positioning instruction, and accordingly, Inst5 is the first instruction and Inst4 is the second instruction. Since there is a dependency relationship between Inst5 and Inst4, the position between Inst5 and Inst4 can be determined as the scheduling position. Finally, Inst2 can be moved to the scheduling position.

[0099] S204, inserting the target instruction into the scheduling position.

[0100] In this step, after determining the scheduling position of the target instruction, the target instruction can be inserted into the scheduling position to complete the scheduling of the target instruction.

[0101] The following uses the Open Computing Language (OpenCL) program as an example to illustrate the above instruction scheduling method.

[0102] For example, an OpenCL program can define variables gid, val1, val2, then output val1 and val2 to the function uint res = abs(val1) + abs(val2), determine the function calculation result res, and finally output res as the value of gid through the function out[gid] = res. Accordingly, the instruction basic block generated by the OpenCL program can be as follows Figure 7 shown.

[0103] Among them, R1 of Inst1 represents gid, R2 of Inst2 represents val1, and R3 of Inst3 represents val2. Inst4, Inst5, and Inst6 represent abs(val2), and R6 represents the result of abs(val2). Inst7, Inst8, and Inst9 represent abs(val1), and R9 represents the result of abs(val1). R10 of Inst10 represents res, and Inst11 represents out[gid] =res.

[0104] For example, when scheduling the instruction basic blocks generated by the OpenCL program, since Inst11 and Inst10 have a dependency relationship, the instruction delay flags can be set for Inst10 and Inst11 first. Then, starting from Inst10, the reverse traversal is performed. Inst10 and Inst9, Inst9 and Inst8, Inst8 and Inst7 all have dependency relationships, but Inst9, Inst8 and Inst7 do not have the backward movement attribute. Therefore, the instruction delay flags can be set for Inst9, Inst8 and Inst7.

[0105] For example, when traversing backward to Inst6, since Inst6 has the property of moving backward and there is a dependency relationship between Inst6 and its previous instruction Inst5, it is determined that Inst6 can be scheduled. When scheduling Inst6, the instruction Inst10 that uses the result R6 of Inst6 can be found first, and then the instruction Inst9 before Inst10 is obtained. Inst9 has a dependency relationship with its previous instruction Inst8, so Inst6 is scheduled to the front of Inst9.

[0106] For example, when traversing backward to Inst5, since Inst5 has the property of moving backward and there is a dependency relationship between Inst5 and its previous instruction Inst4, it is determined that Inst5 can be scheduled. When scheduling Inst5, the instruction Inst6 that uses the result R5 of Inst5 can be found first, and then the instruction Inst8 before Inst6 can be obtained. Inst8 has a data dependency delay with its previous instruction Inst7, so Inst5 can be scheduled before Inst8.

[0107] For example, traverse backward to Inst4, the instructions after Inst4 are Inst7 and Inst5. If Inst4 is moved in front of Inst5, but there is a dependency relationship between Inst5 and Inst4, then Inst4 does not need to be scheduled. Since there is a dependency relationship between Inst4 and Inst3, an instruction delay flag can be set for Inst4.

[0108] For example, reverse traverse to Inst3, the instruction after Inst3 is Inst4, Inst3 does not have the property of moving backwards, and does not need to be processed. Reverse traverse to Inst2, Inst2 has the property of moving backwards, and there is a dependency relationship between Inst2 and its previous instruction Inst1, so Inst2 can be scheduled. When scheduling Inst2, first find the instruction Inst7 that uses the result R2 of Inst2, and then obtain the instruction Inst4 before Inst7. There is a dependency relationship between Inst4 and its previous instruction Inst3, so Inst2 is scheduled to the front of Inst4. Reverse traverse to Inst1, Inst1 does not have the property of moving backwards, and does not need to be processed.

[0109] Figure 8 A schematic diagram of an instruction basic block after scheduling provided by an embodiment of the present application, such as Figure 7 and 8 As shown in the figure, before scheduling, adjacent instructions Inst1 and Inst2, Inst3 and Inst4, Inst4 and Inst5, Inst5 and Inst6, Inst7 and Inst8, Inst8 and Inst9, Inst9 and Inst10, Inst10 and Inst11 have data dependency delays. After scheduling, adjacent instructions Inst1 and Inst3, Inst9 and Inst10, Inst10 and Inst11 have data dependency delays. Compared with before scheduling, the data dependency delay is greatly reduced after scheduling.

[0110] The instruction scheduling method provided in the embodiment of the present application first obtains multiple instructions in the instruction basic block, and then reversely traverses each instruction in the instruction basic block starting from the penultimate instruction, and determines the target instruction to be scheduled according to the dependency relationship between adjacent instructions. Thirdly, the scheduling positioning instruction corresponding to the target instruction is determined in the instruction basic block, and the scheduling position of the target instruction is determined according to the scheduling positioning instruction. The scheduling positioning instruction is the first instruction that is located after the target instruction and has a dependency relationship with the target instruction. Finally, the target instruction is inserted into the scheduling position. Since each instruction is reversely traversed in the instruction basic block, and the target instruction to be scheduled is determined according to the dependency relationship between adjacent instructions, the adjacent instructions with dependencies can be scheduled to the scheduling position, reducing the delay between adjacent instructions, thereby improving the speed of program execution.

[0111] The following describes how to determine the target instruction to be scheduled based on the dependency relationship between adjacent instructions. Fig. 9 A flowchart of another instruction scheduling method provided in an embodiment of the present application is shown as follows: Fig. 9 As shown, the instruction scheduling method includes S301-S311:

[0112] S301, obtaining multiple instructions in an instruction basic block.

[0113] S302: Determine whether the number of instructions in the instruction basic block is greater than or equal to a threshold number.

[0114] If yes, execute S303, if no, execute S311.

[0115] S303: Add an instruction delay flag to the last instruction.

[0116] S304 , traverse each instruction in the instruction basic block in reverse order starting from the second to last instruction, and determine whether the traversal is completed.

[0117] If yes, execute S311, if no, execute S305.

[0118] S305: Determine whether adjacent instructions have a dependency relationship.

[0119] If yes, execute S306 , if no, execute S304 .

[0120] S306: Determine whether the subsequent instruction among the adjacent instructions has a backward movement attribute.

[0121] If yes, execute S308, if no, execute S307.

[0122] S307 . Set an instruction delay flag for the subsequent instruction, where the instruction delay flag is used to indicate that the subsequent instruction has a dependency relationship with the previous instruction.

[0123] S308: Determine that the subsequent instruction is the target instruction.

[0124] S309. Determine the scheduling and positioning instruction corresponding to the target instruction in the instruction basic block, and determine the scheduling position of the target instruction according to the scheduling and positioning instruction. The scheduling and positioning instruction is the first instruction that is located after the target instruction and has a dependency relationship with the target instruction.

[0125] S310, inserting the target instruction into the scheduling position.

[0126] S304 is executed after S310 .

[0127] S311, end instruction scheduling.

[0128] The following describes how to determine the scheduling position of the target instruction based on the scheduling positioning instruction. Fig.10 A flowchart of another instruction scheduling method provided in an embodiment of the present application is shown as follows: Fig.10 As shown, the instruction scheduling method includes S401-S410:

[0129] S401: Determine whether adjacent instructions have a dependency relationship.

[0130] S402: Determine whether the subsequent instruction among adjacent instructions has a backward movement attribute.

[0131] If yes, execute S404, if no, execute S403.

[0132] S403, setting an instruction delay flag for the subsequent instruction, where the instruction delay flag is used to indicate that the subsequent instruction has a dependency relationship with the previous instruction.

[0133] S404: Determine that the subsequent instruction is the target instruction.

[0134] S405 . Determine a scheduling and locating instruction corresponding to the target instruction in the instruction basic block. The scheduling and locating instruction is the first instruction that is located after the target instruction and has a dependency relationship with the target instruction.

[0135] S406: Determine whether there is a dependency relationship between the first instruction and the second instruction.

[0136] If yes, execute S408, if no, execute S407.

[0137] The first instruction is the first instruction before the scheduling and positioning instruction, and the second instruction is the second instruction before the scheduling and positioning instruction.

[0138] S407: Determine whether there is a dependency relationship between the second instruction and the third instruction.

[0139] If yes, execute S409, if no, execute S408.

[0140] The third instruction is the third instruction before the scheduling and positioning instruction.

[0141] S408. Determine the position between the first instruction and the second instruction as the scheduling position.

[0142] S409: Determine the position between the second instruction and the third instruction as the scheduling position.

[0143] S410, inserting the target instruction into the scheduling position.

[0144] In this application, the intermediate language characteristics generated by LLVM are combined to schedule multiple instructions, thereby solving the delay caused by data dependencies at the instructions that need to be scheduled, and solving the delay caused by data dependencies at the location where the instructions are moved after scheduling. Compared with only focusing on scheduling to solve the data dependency delays of adjacent instructions, the hardware execution efficiency is greatly improved.

[0145] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0146] Based on the same inventive concept, the embodiment of the present application also provides an instruction scheduling device for implementing the instruction scheduling method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the one or instruction scheduling device embodiment provided below can refer to the limitations of the instruction scheduling method above, and will not be repeated here.

[0147] In an exemplary embodiment, Fig.11 As shown, an instruction scheduling device 500 is provided, including: an acquisition module 501, a traversal module 502, a positioning module 503 and an insertion module 504.

[0148] The acquisition module 501 is used to acquire multiple instructions in an instruction basic block.

[0149] The traversal module 502 is used to traverse each instruction in the instruction basic block in reverse order starting from the penultimate instruction, and determine the target instruction to be scheduled according to the dependency relationship between adjacent instructions.

[0150] The positioning module 503 is used to determine the scheduling positioning instruction corresponding to the target instruction in the instruction basic block, and determine the scheduling position of the target instruction according to the scheduling positioning instruction. The scheduling positioning instruction is the first instruction that is located after the target instruction and has a dependency relationship with the target instruction.

[0151] The inserting module 504 is used to insert the target instruction into the scheduling position.

[0152] In one embodiment, the traversal module 502 also includes determining whether the number of instructions in the instruction basic block is greater than or equal to the number threshold; if the number of instructions in the instruction basic block is greater than the number threshold, each instruction in the instruction basic block to be scheduled is traversed in reverse, and the target instruction to be scheduled is determined according to the dependency relationship between adjacent instructions.

[0153] In one embodiment, the positioning module 503 is further configured to determine that the subsequent instruction is the target instruction if there is a dependency relationship between adjacent instructions and the subsequent instruction in the adjacent instructions has a backward movement attribute.

[0154] In one embodiment, the traversal module 502 is also used to set an instruction delay flag for the subsequent instruction if there is a dependency relationship between adjacent instructions and the subsequent instruction in the adjacent instructions does not have a backward movement attribute. The instruction delay flag is used to indicate that the subsequent instruction has a dependency relationship with the previous instruction.

[0155] In one embodiment, the positioning module 503 is also used to determine the position between the first instruction and the second instruction as the scheduling position if there is a dependency relationship between the first instruction and the second instruction, the first instruction is the first instruction before the scheduling positioning instruction, and the second instruction is the second instruction before the scheduling positioning instruction; if there is no dependency relationship between the first instruction and the second instruction, the scheduling position is determined according to the second instruction and the third instruction, and the third instruction is the third instruction before the scheduling positioning instruction.

[0156] In one embodiment, the positioning module 503 is also used to determine the position between the second instruction and the third instruction as the scheduling position if there is a dependency relationship between the second instruction and the third instruction; if there is no dependency relationship between the second instruction and the third instruction, determine the position between the first instruction and the second instruction as the scheduling position.

[0157] In one embodiment, the traversal module 502 is further configured to add an instruction delay flag to the penultimate instruction if there is a dependency relationship between the penultimate instruction and the penultimate instruction in the instruction basic block.

[0158] In one embodiment, the dependency relationship is used to indicate that the source operand of the subsequent instruction is derived from the target operand of the previous instruction.

[0159] The above modules may be embedded in or independent of a processor in a computer device in the form of hardware, or may be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to the above modules.

[0160] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal device, and its internal structure diagram may be as shown in FIG. Fig.12As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an instruction scheduling method is implemented.

[0161] Those skilled in the art will understand that Fig.12 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0162] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above instruction scheduling method when executing the computer program.

[0163] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above instruction scheduling method is implemented.

[0164] In one embodiment, a computer program product is provided, including a computer program, which implements the above instruction scheduling method when executed by a processor.

[0165] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0166] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0167] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. An instruction scheduling method, characterized in that: The method comprises: Get multiple instructions in an instruction basic block; In the instruction basic block, each instruction is traversed backwards starting from the penultimate instruction, and a target instruction to be scheduled is determined according to a dependency relationship between adjacent instructions; Determine the scheduling and positioning instruction corresponding to the target instruction in the instruction basic block, and determine the scheduling position of the target instruction according to the scheduling and positioning instruction, wherein the scheduling and positioning instruction is the first instruction that is located after the target instruction and has the dependency relationship with the target instruction; The target instruction is inserted into the scheduling position.

2. The method according to claim 1, characterized in that After obtaining the plurality of instructions in the instruction basic block to be scheduled, the method further includes: Determine whether the number of instructions in the instruction basic block is greater than or equal to a threshold number; If the number of instructions in the instruction basic block is greater than the instruction number threshold, the step of reversely traversing each instruction in the instruction basic block to be scheduled is executed to determine the target instruction to be scheduled according to the dependency relationship between adjacent instructions.

3. The method according to claim 1, characterized in that The step of determining the target instruction to be scheduled according to the dependency relationship between adjacent instructions includes: If the adjacent instructions have the dependency relationship and the subsequent instruction among the adjacent instructions has a backward movement attribute, the subsequent instruction is determined to be the target instruction.

4. The method according to claim 3, characterized in that The method further comprises: If the adjacent instructions have the dependency relationship and the subsequent instruction among the adjacent instructions does not have the backward movement attribute, an instruction delay flag is set for the subsequent instruction, and the instruction delay flag is used to indicate that the subsequent instruction has a dependency relationship with the previous instruction.

5. The method according to claim 3, characterized in that: Determining the dispatching position of the target instruction according to the dispatching positioning instruction includes: If there is a dependency relationship between the first instruction and the second instruction, the position between the first instruction and the second instruction is determined as the scheduling position, the first instruction is the first instruction before the scheduling positioning instruction, and the second instruction is the second instruction before the scheduling positioning instruction; If there is no dependency relationship between the first instruction and the second instruction, the scheduling position is determined according to the second instruction and the third instruction, and the third instruction is the third instruction before the scheduling positioning instruction.

6. The method according to claim 5, characterized in that The determining the dispatching position according to the second instruction and the third instruction includes: If the second instruction and the third instruction have a dependency relationship, determining the position between the second instruction and the third instruction as the scheduling position; If the second instruction and the third instruction do not have a dependency relationship, the position between the first instruction and the second instruction is determined as the scheduling position.

7. The method according to claim 1, characterized in that After the fetching of the plurality of instructions in the instruction basic block, the method further comprises: If the dependency relationship exists between the penultimate instruction and the penultimate instruction in the instruction basic block, an instruction delay flag is added to the penultimate instruction.

8. The method according to any one of claims 1 to 7, characterized in that: The dependency relationship is used to indicate that the source operand of the subsequent instruction comes from the target operand of the preceding instruction.

9. An instruction scheduling device, characterized in that: The device comprises: An acquisition module, used for acquiring multiple instructions in an instruction basic block; A traversal module, used to traverse each instruction in the instruction basic block in reverse order starting from the penultimate instruction, and determine a target instruction to be scheduled according to a dependency relationship between adjacent instructions; A positioning module, used to determine the scheduling positioning instruction corresponding to the target instruction in the instruction basic block, and determine the scheduling position of the target instruction according to the scheduling positioning instruction, wherein the scheduling positioning instruction is the first instruction that is located after the target instruction and has the dependency relationship with the target instruction; An insertion module is used to insert the target instruction into the scheduling position.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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