Data consistency processing method and device for multi-core CPU and medium

Abstract

The invention relates to a data consistency processing method and device for a multi-core CPU (central processing unit) and a medium, which are used for a safe vehicle-mounted platform and comprise the following steps: receiving data by using the multi-core CPU and checking the validity of the data; periodically acquiring a data total check code of each CPU; comparing the data total check code of each CPU in the same MPU with the data total check code of each CPU in different MPUs, and judging whether the data in the multi-core CPU is consistent or not; if the data in the multi-core CPU are consistent and output data exist in the application core, the application core is used for transmitting the output data to the platform core, the output data in the application core are subjected to output data total check code comparison, and if the output data pass the comparison, the output data are output outwards. Compared with the prior art, the method has the advantages that the CPU of each MPU adopts a 2oo2 architecture to check the input data receiving condition and the total input check code, so that the safety of data consistency check is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-core processor verification, and in particular to a data consistency processing method, device and medium for a multi-core CPU. Background Art

[0002] With the rapid development of modern society, railway transportation, as one of the important modes of transportation, faces increasing challenges in safety and efficiency. Trains need to process a large amount of data during operation, including real-time monitoring, driving control, automatic driving and other functions. The complexity of these functions and the high requirements for safety and real-time performance make it difficult for traditional single-core processor platforms to meet the requirements in terms of processing power and response speed. Therefore, train on-board platforms based on multi-core CPUs have gradually become an important solution to improve train safety and real-time performance.

[0003] Multi-core CPU has parallel processing capability and can execute multiple tasks at the same time, greatly improving the efficiency of data processing. By allocating various functional modules of the train to different processing cores, parallel processing of tasks can be achieved, thereby reducing system response time and enhancing the real-time performance and reliability of the system.

[0004] On-board systems usually need to process a large amount of external communication data, IO data, and various sensor data in real time to ensure safety and performance. In a safe on-board platform based on a multi-core CPU, data consistency between CPUs, between the master and the slave, and between cores becomes increasingly complex. If the input data and output data are inconsistent, it may lead to wrong decisions, especially in autonomous driving and safety-critical applications, which may cause accidents or system failures. Therefore, in a safe train on-board platform based on a multi-core CPU, ensuring data consistency between the master and slave boards, each CPU, and each core is an important issue to ensure system reliability and safety. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a data consistency processing method, device and medium for a multi-core CPU to ensure the consistency of input data and output data between each CPU, between the master and standby MPUs, and between each core.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A data consistency processing method for a multi-core CPU, used in a safety vehicle-mounted platform, the method comprising:

[0008] Utilize the multi-core CPU to receive input data and check the validity of the input data; perform periodic total check code calculation for input data that has passed the validity check to obtain the total check code of the input data of each CPU; compare the total check code of the input data of each CPU in the same MPU with the total check code of the input data of each CPU in different MPUs to determine whether the input data in the multi-core CPU is consistent;

[0009] If the data in the multi-core CPU is consistent and there is output data in the application core, the output data is transmitted to the platform core through inter-core communication using the application core, and the platform core compares the received output data with the total checksum of the output data. If the output data passes the comparison, the output data is output to the outside.

[0010] Furthermore, the MPU is a board equipped with a CPU.

[0011] Furthermore, the input data includes communication messages, speed measurement and positioning messages and IO messages, and the output data includes data output by the application in the application core.

[0012] Furthermore, the process of receiving input data and checking the validity of the input data includes:

[0013] receiving input data from the outside using the first CPU of the main MPU;

[0014] Transmitting all input data of the current cycle to the remaining CPUs of the main MPU and the CPUs of the remaining MPUs by using an input data message through the first CPU of the main MPU;

[0015] Using the first CPU of the main MPU, the validity of each input data is checked one by one according to the communication protocol requirements adopted by each input data, and if the input data fails the validity check, the input data that fails the validity check is discarded;

[0016] Use the remaining CPUs of the main MPU and the CPUs of the remaining MPUs respectively to check the validity of the input data message according to the communication protocol requirements adopted by the input data message. If the input data message in any CPU fails the validity check, the total check code of the input data of the CPU is set to 0;

[0017] If the input data message passes the validity check, the remaining CPUs of the main MPU and the CPUs of the remaining MPUs will be used respectively to check the validity of each input data in the input data message one by one according to the communication protocol requirements adopted by each input data in the input data message. If any input data in the input data message in any CPU fails the validity check, the input data that fails the validity check will be discarded.

[0018] Furthermore, the first CPU is any CPU on the main MPU.

[0019] Furthermore, the process of comparing the total check code of the input data of each CPU in the same MPU includes:

[0020] Exchange total checksum of input data with the CPU of MPU;

[0021] If any CPU in the MPU does not receive the total check code of the input data from other CPUs in the current cycle, the MPU will be transferred to SAFESTATE mode;

[0022] If the total checksum of the input data of each CPU in the MPU is not 0 and is inconsistent, the MPU is switched to SAFESTATE mode;

[0023] If in one cycle, the total check code of input data of only one CPU in the MPU is 0, then the total check code of input data of another CPU in the MPU is set to 0;

[0024] If the total checksum of the input data of any CPU in the MPU is 0 for two consecutive cycles, the MPU will be switched to SAFESTATE mode.

[0025] Furthermore, the CPUs of the same MPU exchange data through serial ports.

[0026] Furthermore, the MPU that enters the SAFESTATE mode stops all current tasks, turns off interrupts, and prohibits external output.

[0027] Furthermore, the process of comparing the total check codes of the input data of each CPU in the different MPUs includes:

[0028] The total checksum of input data is exchanged between CPUs of different MPUs;

[0029] If any CPU in the main MPU does not receive the total check code of the input data of any CPU in the other MPUs or the total check code of the input data received by any CPU in the main MPU is inconsistent with its own total check code of the input data, the MPU of the CPU that did not transmit the total check code or the check code is inconsistent will be transferred to the SAFESTATE mode;

[0030] If any CPU in the remaining MPUs has not received the total check code of the input data of any CPU or the total check code of the input data of any CPU received by any CPU in the remaining MPUs is inconsistent with its own total check code of input data, then when the CPU that has not received the total check code of the input data of any CPU or the total check code of the input data received by any CPU is inconsistent with its own total check code of input data receives any message from the main MPU, the MPU of this CPU will be transferred to SAFESTATE mode.

[0031] Furthermore, the CPUs of different MPUs exchange data via direct network cables or TSN buses.

[0032] Furthermore, the application core is used to execute BIT, realize data interaction with application software and realize data interaction with the platform core, and the platform core is used to execute BIT, process input data, process intermediate key data, process output data, manage master and standby status and realize data interaction with the application core.

[0033] Furthermore, the platform core is any core in the CPU, and the remaining cores in the CPU are the application cores.

[0034] Furthermore, the inter-core communication is data exchange between CPU cores through shared memory.

[0035] Furthermore, the process of comparing the output data check code includes:

[0036] According to the output data, the total check code of the output data is calculated, and the total check code of the output data of each CPU is obtained;

[0037] The total checksum of output data is exchanged between CPUs;

[0038] If any CPU in any MPU does not receive the total check code of the output data of a certain CPU in the current cycle or the validity of the total check code of the received output data does not meet the requirements of the communication protocol adopted by it, the MPU will be transferred to the SAFESTATE mode;

[0039] If any CPU of any MPU detects that the total checksum of the output data of a certain CPU is inconsistent with its own, the MPU will be switched to SAFESTATE mode.

[0040] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the data consistency processing method for a multi-core CPU as described above when executing the computer program.

[0041] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the data consistency processing method for a multi-core CPU as described above.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] 1. The present invention proposes a perfect data consistency processing solution, and designs judgment and error processing flows for input data consistency and output data consistency respectively. The CPU of each MPU adopts a 2oo2 architecture to check the input data reception status and the total input check code, thereby ensuring the security of the data consistency check. The consistency check is performed again for the output data that needs to be output, thereby ensuring the security again.

[0044] 2. The present invention improves reliability by using the dual-media interactive input data reception between the main and standby MPUs through the TSN bus and the direct network cable;

[0045] 3. The present invention adopts a 2×2oo2 multi-core CPU architecture. Through redundant design, on the premise of ensuring the consistency of input and output data, the setting of the check code is used to ensure that when any CPU of the system fails, the remaining CPUs can still ensure the continuity and reliability of data processing and stable operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a schematic diagram of the MPU and CPU structure of the present invention;

[0047] Figure 2 This is a flow chart of input data consistency processing of the present invention;

[0048] Figure 3 This is a flow chart of output data consistency processing of the present invention. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] Example 1

[0051] This embodiment has disclosed a practical application example of a data consistency processing method for a multi-core CPU. This embodiment is applied to a secure vehicle-mounted platform for a multi-core CPU.

[0052] The actual MPU and CPU structures used in this embodiment are as follows: Figure 1 As shown, it includes the following parts:

[0053] MPU (main processing unit) board, the main processing unit board of the safety vehicle platform, the main processing unit of the system, includes CPU1 module and CPU2 module. CPU1 and CPU2 exchange data through the serial port to form a 2oo2 (two by two out of two system). The main board and the standby board of the MPU board form a redundant relationship. The CPU1 and CPU2 of the main and standby boards can communicate through the TSN bus. At the same time, there are direct network cable connections between the CPU1 of the main board of the MPU board and the CPU1 of the standby board, as well as between the CPU2 of the main board and the CPU2 of the standby board;

[0054] CPU1 module mainly includes 1 CPU, which includes 3 cores. Among the 3 cores, 1 platform core is used to run MPU platform software, and 2 application cores are used to run ASW software.

[0055] CPU2 module mainly includes 1 CPU, which includes 3 cores. Among the 3 cores, 1 platform core is used to run MPU platform software, and 2 application cores are used to run ASW software.

[0056] A real-time operating system runs on the Platform Core, and the MPU platform software runs on this operating system. The MPU platform software is mainly used to execute BIT, process input data, process intermediate key data, process output data, manage the master and standby states, and realize data interaction with the application core;

[0057] A real-time operating system runs on ASW Core 1 (application core 1), and vehicle platform software and ASW Core 1 software run on this operating system. The vehicle platform software mainly executes BIT, realizes data interaction with application software and realizes data interaction with platform core. ASW Core 1 software includes ATP software;

[0058] A real-time operating system runs on ASW Core 2 (application core 2), and the vehicle platform software and ASW Core 2 software run on this operating system. The vehicle platform software mainly executes BIT, realizes data interaction with application software and realizes data interaction with the platform core. ASW Core 2 software includes ATO software.

[0059] This embodiment discloses a data consistency processing method for a multi-core CPU, which is used in a safe vehicle-mounted platform. The main method includes two parts. One part is input data consistency processing. The general process is as follows: Figure 2 As shown, the other part is the output data consistency processing, the general process is as follows Figure 3 shown.

[0060] like Figure 2 As shown, the input data consistency processing can be summarized as follows:

[0061] First, a multi-core CPU is used to receive input data and check the validity of the input data.

[0062] Input data includes communication messages, speed measurement and positioning messages, and IO messages.

[0063] When no error is reported, the safety vehicle platform is in NORMAL mode during input data consistency processing and the MPU and CPU operate normally.

[0064] The process of receiving input data and checking its validity includes:

[0065] In NORMAL mode, if Figure 2 As shown, the CPU1 of the main MPU receives input data from the outside;

[0066] Use CPU1 of the main MPU to compile all input data of the current cycle into MSG_C_INMSG message, such as Figure 2 As shown, the MSG_C_INMSG message is transmitted to the CPU2 of the main MPU and the CPU1 and CPU2 of the standby MPU through the TSN bus;

[0067] Using the CPU1 of the main MPU, the validity of each input data is checked one by one according to the communication protocol requirements adopted by each data. If the input data fails the validity check, the input data that fails the validity check is discarded;

[0068] Use CPU2 of the main MPU and CPU1 and CPU2 of the standby MPU respectively to check the validity of the MSG_C_INMSG message according to the communication protocol requirements adopted by the MSG_C_INMSG message. If the MSG_C_INMSG message in any CPU fails the validity check, the total check code of the input data of the corresponding CPU is set to 0;

[0069] If the MSG_C_INMSG message passes the validity check, the CPU2 of the main MPU and the CPU1 and CPU2 of the standby MPU are used to check the validity of each input data in the MSG_C_INMSG message one by one according to the communication protocol requirements adopted by each input data in the MSG_C_INMSG message. If any input data in the MSG_C_INMSG message in any CPU fails the validity check, the input data that fails the validity check will be discarded.

[0070] After checking the validity of the message, a periodic total check code calculation is performed on the input data that has passed the validity check to obtain the total check code of the input data of each CPU. This check code will be updated as the input data obtained in each cycle is different. Figure 2 In the figure, CRC_TOTAL2 refers to the total check code used in this embodiment.

[0071] Subsequently, based on the total check code of the input data of each CPU, the total check code of the input data of each CPU in the same MPU is compared with the total check code of the input data of each CPU in different MPUs to determine whether the input data in the multi-core CPU is consistent.

[0072] The process of comparing the total checksum of the input data of each CPU in the MPU includes:

[0073] Exchange total checksum of input data with the CPU of MPU;

[0074] If any CPU in the MPU does not receive the total check code of the input data from other CPUs in the current cycle, the MPU will be transferred to SAFESTATE mode;

[0075] If the total checksum of the input data of each CPU in the MPU is not 0 and is inconsistent, the MPU is switched to SAFESTATE mode;

[0076] If in one cycle, the total check code of input data of only one CPU in the MPU is 0, then the total check code of input data of another CPU in the MPU is set to 0;

[0077] If the total checksum of the input data of any CPU in the MPU is 0 for two consecutive cycles, the MPU will be switched to SAFESTATE mode.

[0078] The CPUs of the same MPU exchange data through the serial port.

[0079] The MPU that enters SAFESTATE mode enters a shutdown state, stops all current tasks, disables interrupts, and prohibits external output.

[0080] The MPU software in each MPU should check the consistency of the dual MPU input every cycle. If the CRC_TOTAL2 of two CPUs after comparison by the dual MPUs is 0, the MPU software that detects that the CRC_TOTAL2 of two CPUs is 0 shall discard all input data in the current cycle.

[0081] The CPUs of different MPUs exchange data through direct network cables or TSN buses. The process of comparing the total checksums of the data of the CPUs in different MPUs includes:

[0082] The total checksum of input data is exchanged between CPUs of different MPUs;

[0083] If any CPU in the main MPU does not receive the total check code of the input data of any CPU in the other MPUs or the total check code of the input data received by any CPU in the main MPU is inconsistent with its own total check code of the input data, the MPU of the CPU that did not transmit the total check code or the check code is inconsistent will be transferred to the SAFESTATE mode;

[0084] If any CPU in the remaining MPUs has not received the total check code of the input data of any CPU or the total check code of the input data of any CPU received by any CPU in the remaining MPUs is inconsistent with its own total check code of input data, then when the CPU that has not received the total check code of the input data of any CPU or the total check code of the input data received by any CPU is inconsistent with its own total check code of input data receives any message from the main MPU, the MPU of this CPU will be transferred to SAFESTATE mode.

[0085] The output data described in the output data consistency processing is the data output by the application in the application core. The application running in the application core of the CPU will have data that needs to be output. Therefore, it is necessary to ensure the consistency of the input data while also ensuring the consistency of the output data in the application core of the CPU. For example, Figure 3 As shown, the output data consistency processing can be summarized as:

[0086] If the data in the multi-core CPU is consistent and there is data in the application core software that needs to be output, the output data is transmitted to the platform core software through inter-core communication using the application core software, and the platform core software is used to compare the received output data with the total checksum of the output data. If the output data passes the comparison, the output data is output.

[0087] The comparison of the total check code of the output data received here is a 2oo2 comparison based on the total check code of the output data.

[0088] The application core software is the software running in the application core of the CPU, and is used to execute BIT, realize data interaction with the application software, and realize data interaction with the platform core. The platform core software is the software running in the platform core of the CPU, and is used to execute BIT, process input data, process intermediate key data, process output data, manage the master-slave status, and realize data interaction with the application core.

[0089] The CPU includes platform cores and application cores. The platform core is any core in the CPU, and the remaining cores in the CPU are application cores.

[0090] Inter-core communication is the data exchange between CPU cores through shared memory.

[0091] The process of comparing the output data checksum includes:

[0092] According to the output data, calculate the total check code of the output data, and obtain the total check code of the output data of each CPU;

[0093] The total data check code is exchanged between CPUs;

[0094] If any CPU in any MPU does not receive the total check code of the output data of a certain CPU in the current cycle or the validity of the total check code of the received output data does not meet the requirements of the communication protocol adopted by it, the MPU will be transferred to the SAFESTATE mode;

[0095] If any CPU of any MPU detects that the total checksum of the output data of a certain CPU is inconsistent with its own, the MPU will be switched to SAFESTATE mode.

[0096] In this embodiment, the main MPU needs to transmit the check code of the ASW communication data to the standby MPU through the MSG_C_OUTPUT_CHECK message every cycle.

[0097] The standby MPU checks the consistency of the dual MPU outputs every cycle. The dual CPUs of the standby MPU should receive the MSG_C_OUTPUT_CHECK message sent by the main MPU, and the received message should also be valid, and the ASW communication data check code of the two systems should be consistent. Otherwise, as long as the standby MPU receives any message from the main MPU, the standby MPU should switch to SAFESTATE mode.

[0098] Example 2

[0099] Based on Example 1, this embodiment provides an electronic device, including: one or more processors and a memory, wherein the memory stores one or more programs, and the one or more programs include instructions for executing the data consistency processing method for a multi-core CPU as described above.

[0100] At the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and of course may also include hardware required for other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to implement the data consistency processing method for multi-core CPUs. Of course, in addition to the software implementation, the present invention does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc., that is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0101] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0102] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0103] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A data consistency processing method for a multi-core CPU, used in a safety vehicle platform, characterized in that: The method comprises: Utilize the multi-core CPU to receive input data and check the validity of the input data; perform periodic total check code calculation for input data that has passed the validity check to obtain the total check code of the input data of each CPU; compare the total check code of the input data of each CPU in the same MPU with the total check code of the input data of each CPU in different MPUs to determine whether the input data in the multi-core CPU is consistent; If the data in the multi-core CPU is consistent and there is output data in the application core, the output data is transmitted to the platform core through inter-core communication using the application core, and the platform core compares the received output data with the total checksum of the output data. If the output data passes the comparison, the output data is output to the outside.

2. A data consistency processing method for a multi-core CPU according to claim 1, characterized in that: The MPU is a board equipped with a CPU.

3. The data consistency processing method for a multi-core CPU according to claim 1, characterized in that: The input data includes communication messages, speed measurement and positioning messages and IO messages, and the output data includes data output by the application in the application core.

4. The data consistency processing method for a multi-core CPU according to claim 1, characterized in that: The process of receiving input data and checking the validity of the input data includes: receiving input data from the outside using the first CPU of the main MPU; Transmitting all input data of the current cycle to the remaining CPUs of the main MPU and the CPUs of the remaining MPUs by using an input data message through the first CPU of the main MPU; Using the first CPU of the main MPU, the validity of each input data is checked one by one according to the communication protocol requirements adopted by each input data, and if the input data fails the validity check, the input data that fails the validity check is discarded; Use the remaining CPUs of the main MPU and the CPUs of the remaining MPUs respectively to check the validity of the input data message according to the communication protocol requirements adopted by the input data message. If the input data message in any CPU fails the validity check, the total check code of the input data of the CPU is set to 0; If the input data message passes the validity check, the remaining CPUs of the main MPU and the CPUs of the remaining MPUs will be used respectively to check the validity of each input data in the input data message one by one according to the communication protocol requirements adopted by each input data in the input data message. If any input data in the input data message in any CPU fails the validity check, the input data that fails the validity check will be discarded.

5. A data consistency processing method for a multi-core CPU according to claim 4, characterized in that: The first CPU is any CPU on the main MPU.

6. The data consistency processing method for a multi-core CPU according to claim 1, characterized in that: The process of comparing the total check code of the input data of each CPU in the same MPU includes: Exchange total checksum of input data with the CPU of MPU; If any CPU in the MPU does not receive the total check code of the input data from other CPUs in the current cycle, the MPU will be transferred to SAFESTATE mode; If the total checksum of the input data of each CPU in the MPU is not 0 and is inconsistent, the MPU is switched to SAFESTATE mode; If in one cycle, the total check code of input data of only one CPU in the MPU is 0, then the total check code of input data of another CPU in the MPU is set to 0; If the total checksum of the input data of any CPU in the MPU is 0 for two consecutive cycles, the MPU will be switched to SAFESTATE mode.

7. A data consistency processing method for a multi-core CPU according to claim 6, characterized in that: The CPUs of the same MPU exchange data through the serial port.

8. The data consistency processing method for a multi-core CPU according to claim 6, characterized in that: The MPU that enters the SAFESTATE mode stops all current tasks, turns off interrupts, and prohibits external output.

9. The data consistency processing method for a multi-core CPU according to claim 1, characterized in that: The process of comparing the total check codes of the input data of each CPU in the different MPUs includes: The total checksum of input data is exchanged between CPUs of different MPUs; If any CPU in the main MPU does not receive the total check code of the input data of any CPU in the other MPUs or the total check code of the input data received by any CPU in the main MPU is inconsistent with its own total check code of the input data, the MPU of the CPU that did not transmit the total check code or the check code is inconsistent will be transferred to the SAFESTATE mode; If any CPU in the remaining MPUs has not received the total check code of the input data of any CPU or the total check code of the input data of any CPU received by any CPU in the remaining MPUs is inconsistent with its own total check code of input data, then when the CPU that has not received the total check code of the input data of any CPU or the total check code of the input data received by any CPU is inconsistent with its own total check code of input data receives any message from the main MPU, the MPU of this CPU will be transferred to SAFESTATE mode.

10. The data consistency processing method for a multi-core CPU according to claim 1, characterized in that: The CPUs of different MPUs exchange data through direct network cables or TSN buses.

11. The data consistency processing method for a multi-core CPU according to claim 1, characterized in that: The application core is used to execute BIT, realize data interaction with application software and realize data interaction with the platform core. The platform core is used to execute BIT, process input data, process intermediate key data, process output data, manage master-slave status and realize data interaction with the application core.

12. The data consistency processing method for a multi-core CPU according to claim 11, characterized in that: The platform core is any core in the CPU, and the remaining cores in the CPU are the application cores.

13. The data consistency processing method for a multi-core CPU according to claim 1, characterized in that: The inter-core communication is data exchange between CPU cores through shared memory.

14. The data consistency processing method for a multi-core CPU according to claim 1, characterized in that: The process of comparing the output data check code includes: According to the output data, the total check code of the output data is calculated, and the total check code of the output data of each CPU is obtained; The total checksum of output data is exchanged between CPUs; If any CPU in any MPU does not receive the total check code of the output data of a certain CPU in the current cycle or the validity of the total check code of the received output data does not meet the requirements of the communication protocol adopted by it, the MPU will be transferred to the SAFESTATE mode; If any CPU of any MPU detects that the total checksum of the output data of a certain CPU is inconsistent with its own, the MPU will be switched to SAFESTATE mode.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the data consistency processing method for a multi-core CPU are implemented as described in any one of claims 1 to 14.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the data consistency processing method for a multi-core CPU as described in any one of claims 1 to 14 are implemented.

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