Fault processing method and device for high-speed extension link

Abstract

The invention relates to the technical field of computers, in particular to a fault processing method and device for a high-speed extension link. According to the fault processing method for the high-speed extension link, the state machine log is recorded in the training process of the high-speed extension link, whether the high-speed extension link enters the target state or not can be quickly determined after training is completed, time-consuming signal and data packet capture analysis is not needed, and the problem positioning efficiency is improved. And secondly, by analyzing the current bandwidth and rate, whether the degradation condition exists or not can be more accurately judged, so that a more accurate analysis result is provided. And finally, in combination with a predefined target processing strategy, corresponding processing operation can be quickly executed, so that the fault processing time is further shortened, and the stability and reliability of the whole system are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method and device for handling failures of a high-speed extension link. Background Art

[0002] At present, the detection scheme for high-speed expansion devices usually compares the rated bandwidth, rated rate, actual bandwidth, and actual rate to determine whether there is a degradation problem. If such a problem occurs, it is repaired by relying on the information recorded in the log. However, the actual situation is that the fault information obtained from the high-speed expansion device log cannot accurately know which link in the link has a problem. Therefore, once a degradation problem occurs, it is difficult to quickly locate the problem. It can only take a lot of time to use high-frequency oscilloscopes and protocol analyzers to capture signals and data packets to analyze the problem. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a high-speed expansion link fault handling method and device to solve the problem that when facing a degradation problem, the existing high-speed expansion device detection solution is difficult to accurately determine the problem point by relying on the device log, and can only be checked through time-consuming signal and data packet capture and analysis, resulting in inefficient problem positioning.

[0004] In a first aspect, an embodiment of the present invention provides a method for handling a fault of a high-speed extension link, the method comprising:

[0005] When the high-speed extension link enters the training process, recording the state machine log generated by the state machine, and when the high-speed extension link training is completed, determining whether the high-speed extension link enters the target state through the state machine;

[0006] If the high-speed extension link enters the target state, analyzing whether the high-speed extension link is currently degraded based on the current bandwidth and current rate of the high-speed extension link to obtain an analysis result;

[0007] Obtain a target processing strategy corresponding to the analysis result, and execute a processing operation indicated by the target processing strategy.

[0008] Furthermore, the method further comprises:

[0009] If the high-speed extension link does not enter the target state, a device identification abnormality signal and a state machine log generated by the state machine are sent to a baseboard management controller.

[0010] Further, the analyzing whether the high-speed extension link is currently degraded based on the current bandwidth and current rate of the high-speed extension link to obtain the analysis result includes:

[0011] Acquire the rated bandwidth and rated rate corresponding to the high-speed extension link when it is in the target state;

[0012] Comparing the rated bandwidth with the current bandwidth, and comparing the rated rate with the current rate;

[0013] If the current bandwidth is less than the rated bandwidth, it is determined that the current bandwidth of the high-speed extension link is wrong, or, if the current bandwidth is greater than or equal to the rated bandwidth, it is determined that the current bandwidth of the high-speed extension link is correct;

[0014] If the current rate is less than the rated rate, it is determined that the current rate of the high-speed extension link needs to be adjusted; or, if the current rate is greater than or equal to the rated rate, it is determined that the current rate of the high-speed extension link does not need to be adjusted;

[0015] If the current bandwidth is wrong and / or the current rate needs to be adjusted, the analysis result is that the high-speed extension link is degraded; or, if the current bandwidth is correct and the current rate of the high-speed extension link does not need to be adjusted, the analysis result is that the high-speed extension link is not degraded.

[0016] Further, the executing the processing operation indicated by the target processing strategy includes:

[0017] If the analysis result shows that the high-speed extension link is degraded and the degradation is caused by a current bandwidth error, a bandwidth abnormality signal and a state machine log generated by the state machine are sent to a baseboard management controller.

[0018] Further, the executing the processing operation indicated by the target processing strategy includes:

[0019] If the analysis result shows that the high-speed extension link is degraded and the degradation is caused by the need to adjust the current rate, detecting whether both ends of the high-speed extension link support a first rate and detecting whether the register currently supports a bypass balancing function, wherein the first rate is greater than the current rate;

[0020] If both ends of the high-speed extension link support a first rate, and the register currently supports a bypass balancing function, a bypass balancing operation is performed, and the rate in the recovery state of the state machine is set to the first rate;

[0021] detecting whether the first rate is successfully set in the recovery state;

[0022] If the first rate is successfully set in the recovery state, deleting the state machine logs except the start and end of the process of adjusting the rate to the first rate in the recovery state;

[0023] Detecting whether the first rate is the highest public rate, and if the first rate is not the highest public rate, setting the rate in the recovery state to a second rate, wherein the second rate is a lower level rate of the first rate;

[0024] If the second rate is successfully set in the recovery state, deleting the state machine logs except the start and end of the process of adjusting the rate to the second rate in the recovery state;

[0025] detecting whether the second rate is the highest public rate, and if the second rate is the highest public rate, detecting whether the bandwidth of the high-speed extension link is correct when it is at the second rate;

[0026] If the bandwidth of the high-speed extension link at the second rate is correct, all state machine logs are deleted; or if the bandwidth of the high-speed extension link at the second rate is wrong, a bandwidth abnormality signal and the state machine log generated by the state machine are sent to the baseboard management controller.

[0027] Furthermore, the method further comprises:

[0028] If the second rate fails to be set in the recovery state, the rate of the state machine in the recovery state is reset to the first rate, and a speed reduction abnormality signal and a state machine log generated by the state machine are sent to a baseboard management controller.

[0029] Further, the executing the processing operation indicated by the target processing strategy includes:

[0030] If the analysis result shows that the high-speed extension link does not have any degradation, all state machine logs generated by the state machine are deleted.

[0031] In a second aspect, an embodiment of the present invention provides a high-speed extension link fault processing device, the device comprising:

[0032] A determination module, used for recording a state machine log generated by a state machine when the high-speed extension link enters a training process, and determining whether the high-speed extension link enters a target state through the state machine when the high-speed extension link training is completed;

[0033] An analysis module, configured to analyze whether the high-speed extension link is currently degraded based on the current bandwidth and current rate of the high-speed extension link if the high-speed extension link enters the target state, and obtain an analysis result;

[0034] The execution module is used to obtain the target processing strategy corresponding to the analysis result and execute the processing operation indicated by the target processing strategy.

[0035] In a third aspect, an embodiment of the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0036] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the method of the first aspect or any corresponding embodiment thereof.

[0037] The fault handling method for the high-speed extension link provided in the present application first records the state machine log during the high-speed extension link training process, and can quickly determine whether the high-speed extension link has entered the target state after the training is completed, without the need for time-consuming signal and data packet capture and analysis, thereby improving the efficiency of problem location. Secondly, by analyzing the current bandwidth and rate, it is possible to more accurately determine whether there is a degradation situation, thereby providing more accurate analysis results. Finally, combined with the predefined target processing strategy, the corresponding processing operations can be quickly executed, further shortening the fault handling time and improving the stability and reliability of the overall system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 is a flowchart of a method for handling a fault of a high-speed extension link according to some embodiments of the present invention;

[0040] Figure 2 is a schematic diagram of a state machine according to some embodiments of the present invention;

[0041] Figure 3 is a flowchart of another high-speed extension link fault handling method according to some embodiments of the present invention;

[0042] Figure 4 is a structural block diagram of a high-speed extension link fault processing device according to an embodiment of the present invention;

[0043] Figure 5It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0045] According to an embodiment of the present invention, a method and apparatus for handling faults of a high-speed extension link are provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0046] In this embodiment, a method for handling a high-speed extension link failure is provided. Figure 1 FIG. 1 is a flow chart of a method for handling a high-speed extension link failure according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0047] Step S101, when the high-speed extension link enters the training process, the state machine log generated by the state machine is recorded, and when the high-speed extension link training is completed, the state machine is used to determine whether the high-speed extension link enters the target state.

[0048] In an embodiment of the present application, when the high-speed expansion link (PCIe link) starts training, it enters the LTSSM state machine. At this time, the system will start a log recording function to record the state machine log generated by the LTSSM state machine. This log record will capture various state changes of the state machine during the link training process, including but not limited to the signal adjustment stage, the link parameter negotiation process and other information. For example, the state machine is recorded from the initial state to the signal amplitude calibration state, as well as the changes in various intermediate states that may occur later. These records will be stored in a log file or a specific area of ​​memory in a time series or in the logical order of state transitions.

[0049] During the link training process, it is constantly checked whether the first training has been completed and whether the L0 state has been entered for the first time. The check is implemented through the LTSSM state machine. It should be noted that the state machine itself has a series of preset state transition rules and judgment conditions. When the link has completed all the necessary training steps, such as successfully adjusting the amplitude, phase and other parameters of the signal, and negotiating and determining the appropriate link width, rate and other parameters, the state machine determines whether the L0 state has been reached based on this information. If all conditions are met, it is considered that the high-speed extension link has successfully entered the target state (L0 state); if any link in this process has a problem, resulting in the inability to meet the conditions for entering the L0 state, such as the signal quality cannot meet the requirements or the link parameter negotiation fails, then it is determined that the target state has not been entered.

[0050] It should be noted that if Figure 2 As shown in the figure, the state machine is a mathematical model used to describe the behavior of the system. The state machine in the figure shows multiple states and the transition relationship between them. For example, the "Detect" state can be converted to the "Polling", "Hot Reset", "Disabled" and other states, and the "Configuration" state can be converted to the "L2", "L0", "Recovery" and other states. The state machine controls the operation process of the system by defining different states and trigger conditions, ensuring that the system can perform state transitions according to the predetermined logic under different conditions.

[0051] Step S102: if the high-speed extension link enters the target state, then analyzing whether the high-speed extension link is currently degraded based on the current bandwidth and current rate of the high-speed extension link to obtain an analysis result.

[0052] In the embodiment of the present application, analyzing whether the high-speed extension link is currently degraded based on the current bandwidth and current rate of the high-speed extension link to obtain the analysis result includes the following steps A1-A5:

[0053] Step A1, obtaining the rated bandwidth and rated rate corresponding to the high-speed extension link when it is in the target state.

[0054] Specifically, first, the rated bandwidth must be determined based on the standard specifications followed by the high-speed expansion link. For example, for a common PCIe link, if it is configured in accordance with the PCIe4.0 standard and the link width is x8, then the theoretical rated bandwidth value corresponding to the link configuration can be determined by referring to the PCIe4.0-related technical documents and the established calculation formula or the corresponding bandwidth value table specified in the standard. Generally speaking, different PCIe versions (such as PCIe3.0, PCIe4.0, PCIe5.0, etc.) and different link widths (such as x1, x2, x4, etc.) have clear bandwidth standard values.

[0055] At the same time, the maximum bandwidth claimed to be supported by the devices at both ends of the link must also be considered. This is because the rated bandwidth that the link can ultimately achieve is limited by the devices at both ends. For example, if one end of the device supports a maximum bandwidth of PCIe4.0x4 and the other end supports a bandwidth of PCIe4.0x8, then the rated bandwidth of the link will be based on the lower end, that is, the bandwidth value corresponding to PCIe4.0x4 is its rated bandwidth.

[0056] The rated speed is also determined based on the standard that the link follows (such as the PCIe standard). Different PCIe versions correspond to different theoretical transmission rates. For example, PCIe3.0 has a fixed speed specification, and PCIe4.0 has a higher speed. By identifying which PCIe version the link is based on, the corresponding rated speed can be determined.

[0057] In addition, you should also check the supported rates indicated in the product specifications of the devices at both ends of the link, and take the lower rate as the rated rate of the link to ensure that the link operating rate is adaptable to the devices at both ends to avoid the problem of not being able to achieve the expected rate due to device incompatibility.

[0058] Step A2, comparing the rated bandwidth with the current bandwidth, and comparing the rated rate with the current rate.

[0059] Specifically, the current bandwidth value obtained is compared with the previously determined rated bandwidth value. The current rate obtained is compared with the rated rate, and the relationship between the current rate and the rated rate is clarified by using the numerical comparison method.

[0060] Step A3: if the current bandwidth is less than the rated bandwidth, it is determined that the current bandwidth of the high-speed extension link is wrong; or, if the current bandwidth is greater than or equal to the rated bandwidth, it is determined that the current bandwidth of the high-speed extension link is correct.

[0061] Specifically, when the current bandwidth value is found to be less than the rated bandwidth through comparison, it means that the actual data transmission capability of the link does not meet the expected standard. This may be due to physical damage to the link (such as line aging, poor contact, etc.), equipment failure (such as a problem with the sending or receiving module at one end), or external interference (such as electromagnetic interference affecting signal quality), which makes it impossible to achieve data transmission under the rated bandwidth, so the current bandwidth is determined to be incorrect.

[0062] If the current bandwidth is greater than or equal to the rated bandwidth, it means that the link has at least reached the expected transmission capacity standard in actual operation. From the perspective of bandwidth, the link is working normally, so the current bandwidth is correct.

[0063] Step A4: if the current rate is less than the rated rate, it is determined that the current rate of the high-speed extension link needs to be adjusted; or if the current rate is greater than or equal to the rated rate, it is determined that the current rate of the high-speed extension link does not need to be adjusted.

[0064] Specifically, when it is detected that the current rate is less than the rated rate, it indicates that the link is not running at its optimal rate. This may be because certain configuration parameters of the devices at both ends of the link do not match, the signal attenuation during transmission is too great, so the rate needs to be reduced to ensure the accuracy of data transmission, or software-level factors such as the device driver limit the rate increase. Therefore, in this case, it is determined that the current rate of the high-speed extension link needs to be adjusted in the hope of reaching the rated rate or better transmission efficiency.

[0065] If the current rate is greater than or equal to the rated rate, it means that the link is already able to transmit data at a rate not lower than the expected rate. From the rate perspective, the link performance meets the requirements. At this time, it is determined that the current rate of the high-speed extension link does not need to be adjusted.

[0066] Step A5, if the current bandwidth is wrong and / or the current rate needs to be adjusted, the analysis result is that the high-speed extension link is degraded; or, if the current bandwidth is correct and the current rate of the high-speed extension link does not need to be adjusted, the analysis result is that the high-speed extension link is not degraded.

[0067] Specifically, if the current bandwidth error occurs, it means that the data transmission capacity of the link has not met expectations, that is, the link performance has declined; or the current rate needs to be adjusted, which also means that the link cannot run at the ideal rate, which also reflects the degradation of link performance. As long as one or both of these two situations are met, it can be analyzed that the high-speed extension link is degraded, that is, the overall performance of the link has deteriorated compared to its rated state.

[0068] If the current bandwidth is correct, it means that the bandwidth of the link is in line with expectations, and the current rate of the high-speed extension link does not need to be adjusted, which means that the rate is also normal. If these two conditions are met at the same time, it can be determined that there is no degradation in the high-speed extension link, that is, the link as a whole is in a normal working state that meets the rated requirements in terms of key indicators such as bandwidth and rate.

[0069] In an embodiment of the present application, the method further includes: if the high-speed extension link does not enter the target state, sending a device identification abnormality signal and a state machine log generated by the state machine to the baseboard management controller.

[0070] Specifically, it is determined that the link has not entered the target state, and a signal specifically used to indicate device identification abnormality is generated. This signal has a specific format and encoding rules, which is used to clearly inform the baseboard management controller (BMC) that the current device has an abnormality in identification. Its specific encoding format and signal content may be defined according to the communication protocol standard followed by the entire system, so that the BMC can accurately identify and parse this signal about a problem with device identification.

[0071] At the same time, it is necessary to obtain the state machine logs generated by the state machine during the link training process. The state machine logs are stored in a specific storage area, which may be a specific location in the device's memory or a dedicated log storage module. According to certain reading rules, the state machine logs that record detailed information such as state changes and parameter adjustments at each stage of link training are completely extracted from the storage area. For example, the initial state records entered by the state machine when the link training starts, the intermediate state changes when various parameter adjustments are tried during the training process, and the relevant records of the last moment before the target state is finally failed are extracted to ensure that the log information is complete and can be used for subsequent fault analysis.

[0072] In order to send the device identification abnormality signal and state machine log to the baseboard management controller (BMC), a communication connection between the two needs to be established first. After the communication connection is successfully established, the prepared device identification abnormality signal is sent to the BMC in accordance with the established communication protocol format to let the BMC know that the device identification abnormality has occurred. Then, the extracted state machine log data is sent through the same communication channel. The data may be sent in batches and packaged according to a certain data packet size to ensure that the data can be accurately and completely received by the BMC. During the sending process, there will also be a corresponding error checking mechanism (such as CRC check, etc.) to check whether an error occurs during the data transmission process. If an error occurs, retransmission and other operations will be performed until the BMC successfully receives a complete and accurate device identification abnormality signal and state machine log.

[0073] Step S103, obtaining the target processing strategy corresponding to the analysis result, and executing the processing operation indicated by the target processing strategy.

[0074] In an embodiment of the present application, the processing operation indicated by the target processing strategy is executed, including: if the analysis result is that the high-speed extension link is degraded and the degradation is caused by the current bandwidth error, a bandwidth exception signal and a state machine log generated by the state machine are sent to the baseboard management controller.

[0075] Specifically, first, determine whether there is a degradation based on the results of the previous comparative analysis of the rated bandwidth and the current bandwidth, and the rated rate and the current rate. According to the established logic, if the current bandwidth is less than the rated bandwidth, and / or the current rate needs to be adjusted, it is determined that the high-speed extension link is degraded. On this basis, further investigate the specific reasons for the degradation and carefully check the results of the bandwidth comparison. If it is determined that the current bandwidth is wrong (that is, the current bandwidth is less than the rated bandwidth), and it can be confirmed that this bandwidth error is the cause of the degradation of the entire link, then the prerequisites for subsequent operations are met.

[0076] When it is determined that the link is degraded due to bandwidth errors, a bandwidth anomaly signal is generated. The bandwidth anomaly signal contains some key information, such as a specific code that may be used to identify the anomaly as a bandwidth anomaly, and may also be accompanied by relevant parameters indicating the degree of bandwidth error (for example, how much lower the current bandwidth is than the rated bandwidth, etc.). These contents are generated according to the communication protocol and signal definition rules agreed upon within the entire system to ensure that the BMC can accurately interpret the bandwidth problem.

[0077] Next, it is necessary to extract the state machine logs generated by the state machine during the link operation process. These logs record in detail the various state changes, link parameter adjustments, and related events that the state machine has experienced from the beginning of the link operation to the current degradation situation. They are generally stored in a specific memory area of ​​the device or a dedicated log storage module. Through the corresponding reading interface and access rules, these log data are extracted in order and in full.

[0078] Then, according to the established communication protocol and data transmission rules, the generated bandwidth anomaly signal is first sent to the BMC. This sending process must ensure that the signal is transmitted accurately in the specified format, and the BMC can correctly parse the relevant information of the bandwidth anomaly after receiving it. Subsequently, the extracted state machine log data is sent to the BMC through the same communication link. Since the amount of state machine log data may be large, it is often transmitted in a block and packaged manner, and each time a data block is sent, the corresponding verification information (such as CRC check code, etc.) will be attached to verify the integrity of the data at the BMC receiving end. If a verification error occurs during the transmission process, the sending end will retransmit the operation according to the feedback until the BMC receives the bandwidth anomaly signal and all state machine logs completely and accurately, so that the BMC can further analyze the specific cause of the bandwidth anomaly based on this information and take corresponding treatment measures.

[0079] By sending bandwidth anomaly signals and state machine logs to the baseboard management controller, the management control unit can be notified promptly and effectively about the specific situation of the high-speed expansion link degradation, thereby achieving the following purposes: first, quickly locate the cause of the fault so that engineers can quickly take repair measures; second, record detailed status information, which is helpful for subsequent fault analysis and system optimization; third, improve system stability and ensure that the link can be handled in a timely manner when bandwidth errors occur, reducing the risk of data loss and business interruption.

[0080] In the embodiment of the present application, executing the processing operation indicated by the target processing strategy includes the following steps B1-B8:

[0081] Step B1, if the analysis result shows that the high-speed extension link is degraded and the degradation is caused by the need to adjust the current rate, then detect whether both ends of the high-speed extension link support the first rate, and detect whether the register currently supports the bypass balancing function, wherein the first rate is greater than the current rate.

[0082] Specifically, first, determine whether there is degradation based on the results of the previous comparative analysis of the rated bandwidth and the current bandwidth, and the rated rate and the current rate. According to the established rules, if the current bandwidth is less than the rated bandwidth, and / or the current rate needs to be adjusted, it is determined that the high-speed extension link is degraded. On this basis, further investigate the cause. If it is determined that the current rate needs to be adjusted, which causes the link degradation, then enter the subsequent detection stage.

[0083] By querying the hardware specifications of the devices at both ends of the link or reading the specific configuration register information inside the device, it is determined whether the devices at both ends support the first rate. When these devices are designed and manufactured, the rate parameters they support will be recorded in the corresponding identification area or configuration register. The system obtains this information through the corresponding access interface to determine whether the rate list supported by the devices at both ends contains the specified first rate (here the first rate is greater than the current rate, for example, if the current rate is GEN3, the first rate may be GEN4, etc.).

[0084] Similarly, access the specific link-related registers in the device, and check the settings of the corresponding register bits representing the bypass equalization function according to the established register bit definition and function mapping rules to determine whether the current register sets the bypass equalization function to a support state. For example, if the binary value of certain bits of a register is a specific code, it means that the bypass equalization function is supported.

[0085] Step B2: If both ends of the high-speed extension link support the first rate and the register currently supports the bypass balancing function, a bypass balancing operation is performed and the rate in the recovery state of the state machine is set to the first rate.

[0086] Specifically, when it is determined that both ends of the high-speed extension link support the first rate and the register currently supports the bypass equalization function, it means that the preconditions for performing the bypass equalization operation are met. The bypass equalization operation usually involves adjusting the link signal transmission path, signal processing method, etc. to meet the requirements of bypass equalization. The specific implementation will be carried out according to the technical standards and hardware design followed by the link, such as changing the signal equalization compensation method, adjusting certain electrical parameters of signal transmission, etc., so that the link has the conditions for high-speed transmission in a new way.

[0087] While performing the bypass balancing operation, the link state machine (such as the LTSSM state machine) is interacted with and an instruction is sent to it to set the rate parameter in the recovery state of the state machine to the first rate. The state machine has corresponding variables or registers for storing and managing rate information. Through a legal write operation, the value representing the first rate (for example, different rate levels are represented by specific codes, GEN4 corresponds to a certain code value, etc.) is written to the corresponding storage location, so that the state machine knows that the link should be configured according to the first rate in the recovery state.

[0088] Step B3, detecting whether the first rate is set successfully in the recovery state.

[0089] Specifically, after the rate in the recovery state is set to the first rate, a detection mechanism is started to confirm whether the first rate is actually set successfully. This detection may involve multiple levels of inspection.

[0090] By using professional test instruments (such as high-frequency oscilloscopes, etc.) to connect to the key signal nodes of the link, observe whether the signal's frequency, amplitude, phase and other parameters meet the standard requirements corresponding to the first rate. For example, at different rate levels, the clock frequency of the signal is clearly specified. Check whether the actual signal's clock frequency reaches the theoretical clock frequency value corresponding to the first rate. If the deviation is within the allowable range, it can be preliminarily determined that the rate setting at the signal level is successful.

[0091] At the same time, the devices at both ends of the link also have a certain rate monitoring and feedback mechanism. By reading the rate status information fed back by the device (for example, the status register inside the device will update the current working rate and other information in real time, and the corresponding values ​​are obtained by accessing these registers), check whether the current rate reported by it has been updated to the first rate. If the rate fed back by the device is consistent with the set first rate, then on the whole, it can be determined that the first rate is set successfully in the recovery state.

[0092] Step B4: If the first rate is set successfully in the recovery state, delete the state machine logs except the start and end of the process of adjusting the rate to the first rate in the recovery state.

[0093] First, locate the log storage area in the state machine that records the process of adjusting the rate to the first rate in the recovery state. This part of the log may record the key nodes, parameter changes and other detailed information in the entire adjustment process in chronological order or operation order, and is stored in a specific location in the device's memory or a dedicated log storage module. Then, according to the rules, filter out the intermediate process logs except the start and end logs. The start log usually records the timestamp of the start of the rate adjustment operation, the initial state and other information, and the end log records the timestamp of the completion of the adjustment, the final state and other key information, while the intermediate process log contains relatively detailed process records such as temporary parameter values ​​and intermediate state transitions during the adjustment process.

[0094] Call the corresponding log management function or execute the deletion instruction to delete the filtered intermediate process logs from the storage area to release storage space. At the same time, only the start and end logs are retained for subsequent possible viewing of changes in key link status.

[0095] Step B5, detecting whether the first rate is the highest public rate, if the first rate is not the highest public rate, setting the rate in the recovery state to the second rate, wherein the second rate is a lower level rate of the first rate.

[0096] Specifically, determine whether the first rate is the highest public rate. The determination needs to comprehensively consider the highest rate supported by the devices at both ends of the link, similar to the previous method of determining the support of a certain rate by the device. The hardware specifications of the devices at both ends and the corresponding configuration register information are queried again to obtain all the rate levels that the devices at both ends can support, and then find out the highest rate value they all support, and compare it with the current first rate.

[0097] If the comparison finds that the first rate is not the highest public rate, it means that there is still room for the link to further improve the rate to achieve optimal performance. Then it is necessary to perform the next rate adjustment operation and set the rate in the recovery state to the second rate. The second rate here is the next level rate of the first rate (for example, the first rate is GEN4, the second rate is GEN5, etc., which is determined by the rate level sequence supported by the link) to prepare for the subsequent optimization of link performance.

[0098] Step B6: If the second rate is set successfully in the recovery state, delete the state machine logs except the start and end of the process of adjusting the rate to the second rate in the recovery state.

[0099] Specifically, when it is determined that the rate in the recovery state is to be set to the second rate, the value representing the second rate is written to the corresponding rate parameter storage location in the state machine by interacting with the link state machine to complete the rate setting operation, and then the detection mechanism is immediately started to confirm whether the second rate is successfully set in the recovery state.

[0100] Use a test instrument to detect whether the relevant parameters of the link signal meet the standard requirements corresponding to the second rate. At the same time, read the rate status information fed back by the device to check whether the current rate reported by it has been updated to the second rate. If the test results of both aspects indicate that the rate has been successfully updated to the second rate, it is determined that the second rate is successfully set in the recovery state.

[0101] If it is determined that the second rate is set successfully, locate the log storage area of ​​the state machine that records the process of adjusting the rate to the second rate in the recovery state, filter out the intermediate process logs except the start and end logs, and perform deletion operations, retaining only the key start and end logs to complete the log management work.

[0102] Step B7, detecting whether the second rate is the highest public rate, and if the second rate is the highest public rate, detecting whether the bandwidth of the high-speed extension link is correct when it is at the second rate.

[0103] Specifically, to determine whether the second rate is the highest public rate, the detection method is still to check the highest rate supported by the devices at both ends of the link, and compare it with the current second rate to determine whether the second rate has reached the optimal rate state supported by both ends of the link.

[0104] If the comparison result shows that the second rate is the highest public rate, it means that the link has reached the optimal configuration from the rate perspective. At this time, it is necessary to further detect whether the bandwidth of the link at the second rate is correct, so as to comprehensively evaluate the performance status of the link. Even if the rate reaches the optimal level, if there is a problem with the bandwidth, the link still cannot work normally and efficiently, so enter the next step of bandwidth detection.

[0105] Step B8, if the bandwidth of the high-speed extension link at the second rate is correct, then delete all state machine logs. Or, if the bandwidth of the high-speed extension link at the second rate is wrong, then send a bandwidth abnormality signal and the state machine log generated by the state machine to the baseboard management controller.

[0106] Specifically, if the comparison finds that the actual bandwidth is equal to the rated bandwidth or is within a reasonable error range, it means that the link is in normal state in terms of both rate and bandwidth. At this time, the log management module is called to delete all state machine logs to release storage space. Because the link is working normally, these logs are no longer necessary to be retained.

[0107] If the actual bandwidth does not match the rated bandwidth, that is, the bandwidth is abnormal, then it is necessary to send a bandwidth abnormality signal and the state machine log generated by the state machine to the baseboard management controller (BMC). The method of generating the bandwidth abnormality signal is similar to that mentioned above. According to the specific format and encoding rules, the BMC is informed of the bandwidth problem. At the same time, the complete state machine log (including the previously retained key start and end logs and other log information related to the link status) is extracted and sent to the BMC through the established communication link, so that the BMC can perform troubleshooting and further processing based on this information.

[0108] In an embodiment of the present application, the method also includes: if the second rate fails to be set in the recovery state, resetting the rate in the recovery state of the state machine to the first rate, and sending a speed reduction abnormal signal and a state machine log generated by the state machine to the baseboard management controller.

[0109] Specifically, the function module that feeds back the abnormal situation to the baseboard management controller (BMC) starts to operate and generates a speed reduction abnormal signal. This signal follows specific format and coding requirements, which covers key details such as indicating that this is a speed reduction abnormality and involving adjustment from the first rate to the second rate but failure, so that the BMC can accurately parse the abnormal situation according to the communication protocol agreed by the system. Then, the state machine log generated by the state machine during the entire link rate adjustment process is extracted from the storage device, and the log content containing the details of each stage from the initial attempt to adjust the rate, setting the second rate to the failure of the setting is completely obtained according to the corresponding reading rules. After that, through the established communication link, in accordance with the established communication protocol and data transmission rules, the generated speed reduction abnormal signal is first sent to the BMC to inform the abnormal situation, and then the extracted state machine log data is packaged and transmitted in batches. Each batch of data is accompanied by verification information (such as CRC check code). Once a verification error occurs in the transmission, a retransmission operation is performed until the BMC receives the speed reduction abnormal signal and all state machine logs completely and accurately.

[0110] In this way, by detecting the rate support at both ends of the high-speed extension link and the register bypass balancing function, the link degradation problem can be effectively dealt with. After confirming that a higher rate is supported and the register allows bypass balancing, the link rate is adjusted to the highest public rate or the next level rate, and the state machine log is optimized to improve the stability and efficiency of the link. At the same time, the correctness of the bandwidth is detected to ensure the accuracy of the bandwidth adjustment, reduce the risk of bandwidth anomalies, and thus improve the overall performance and reliability of the network.

[0111] In addition, obtain the results of all rate conversion operations in history, including conversion from the first rate to other rates, and conversion from other rates back to the first rate. For each operation, record whether it is successfully completed. Count the success rate of similar second rate conversion operations (i.e., conversion from the current state to the second rate). For example, if there were 10 similar operation attempts before, 7 of which succeeded and 3 failed, then the success rate of this type of operation is 70%.

[0112] At the same time, the link aging degree can also be detected, and a link aging model can be established based on the link usage time, historical data of signal attenuation, etc. For example, after a certain period of use, or when the signal attenuation exceeds a certain threshold, the link aging degree is considered to have increased by a certain level.

[0113] Risk assessment is performed based on the above historical data. If the success rate of similar rate conversion operations in the past is low, such as less than 50%, then this operation has a higher risk of failure based on historical experience. When the link aging degree is high, for example, the link signal attenuation is close to the critical value that affects the success of the rate conversion, this will also increase the risk of this operation. According to the comprehensive weight of these factors, the risk probability of this second rate setting operation is calculated. For example, the weight of the historical success rate is 0.6, and the weight of the link aging degree is 0.4. The risk value is calculated through the corresponding quantitative indicators. When the pre-check module assesses that this operation has a high risk of failure (for example, the risk probability exceeds 70%), it will immediately generate an early warning signal. The early warning signal will contain an identifier indicating that it is a risk warning about the second rate setting operation. At the same time, the early warning signal will also be accompanied by a timestamp to record the time when the warning was generated.

[0114] In the embodiment of the present application, executing the processing operation indicated by the target processing strategy includes: if the analysis result is that there is no degradation of the high-speed extension link, deleting all state machine logs generated by the state machine.

[0115] Specifically, when the comparison and analysis of the high-speed extension link related parameters (such as rated bandwidth and current bandwidth, rated rate and current rate, etc.) shows that there is no degradation, first locate the relevant area for storing state machine logs. These logs are usually stored in a specific location of the device's memory or a dedicated log storage module. They record in detail the various state changes, parameter adjustments, and other information of the state machine during link operation and training. Then, call the corresponding log management function or execute a specific deletion instruction to delete all state machine logs generated by the state machine in the area, thereby releasing the storage space occupied by the storage logs.

[0116] The fault handling method for the high-speed extension link provided in the present application first records the state machine log during the high-speed extension link training process, and can quickly determine whether the high-speed extension link has entered the target state after the training is completed, without the need for time-consuming signal and data packet capture and analysis, thereby improving the efficiency of problem location. Secondly, by analyzing the current bandwidth and rate, it is possible to more accurately determine whether there is a degradation situation, thereby providing more accurate analysis results. Finally, combined with the predefined target processing strategy, the corresponding processing operations can be quickly executed, further shortening the fault handling time and improving the stability and reliability of the overall system.

[0117] The following is a complete high-speed expansion link troubleshooting process. Figure 3 As shown:

[0118] ① The PCIe link starts training and enters the LTSSM state machine. At the same time, the operation of recording the state machine log is started to record various state changes and related parameter information during the link training process.

[0119] ② Check whether the first training is completed and the L0 state is entered for the first time.

[0120] If the L0 state cannot be successfully entered for the first time: an alarm of device recognition abnormality is sent to the BMC, and the LTSSM state machine log is sent. Then, the LTSSM state machine log in the memory is deleted, and the whole process ends.

[0121] If you successfully enter the L0 state for the first time: Go to the next step to further determine whether the actual bandwidth is correct.

[0122] ③ Check the actual bandwidth and determine whether it is correct.

[0123] If the bandwidth is incorrect: Send an alarm about the abnormal device bandwidth to the BMC, send the LTSSM state machine log, and proceed to the next step.

[0124] If the bandwidth is correct: Go to the next step to determine whether you need to enter the recovery state to further adjust the PCIe link rate.

[0125] ④ Regardless of whether the bandwidth is correct, it is necessary to determine whether it is necessary to enter the recovery state to adjust the PCIe link rate.

[0126] If rate adjustment is not required: Delete all LTSSM state machine logs and end the process.

[0127] If the rate needs to be adjusted: then determine whether the BypassingEqualization function needs to be executed (this requires that both ends of the link support GEN5 and higher rates, and the register is set to support this function).

[0128] ⑤Judge the execution of Bypassing Equalization:

[0129] If you need to execute the BypassingEqualization function: set it directly according to the GEN5 rate in the recovery state, and then check whether it is successfully configured as the GEN5 rate.

[0130] If the GEN5 rate is successfully configured: delete the recovery process log of the current rate, keep only the start and end logs, and proceed to the next step to determine whether the current rate is the maximum rate supported by the link.

[0131] If BypassingEqualization fails or cannot be executed: execute the recovery state machine to adjust the PCIe link rate to the GEN2 rate, and then determine whether the recovery state machine is successfully completed and adjusted to the GEN2 rate.

[0132] If the BypassingEqualization function does not need to be executed: the recovery state machine is also executed to adjust the PCIe link rate to the GEN2 rate, and then it is determined whether the recovery state machine is successfully completed and adjusted to the GEN2 rate.

[0133] ⑥ Determine the GEN2 rate adjustment situation:

[0134] If the rate adjustment to GEN2 fails, the PCIe link working rate is reduced to GEN1, and the corresponding device speed reduction exception and LTSSM state machine log are sent to the BMC. The LTSSM state machine log in the memory is deleted, and the process ends.

[0135] If the GEN2 rate is successfully entered: Go to the next step to determine whether the current rate is the highest public rate of the link.

[0136] ⑦ Determine whether the current rate is the highest public rate of the link:

[0137] Check whether the current rate is the highest public rate of the link.

[0138] If it is not the highest public rate: adjust the rate to the next level rate (such as GEN2 to GEN3, GEN3 to GEN4, GEN4 to GEN5, etc.) in the recovery state, and then determine whether the rate increase is successful.

[0139] If successful: Delete the recovery process log of the current rate, retain only the start and end logs, and return to the step of determining whether the current rate is the maximum rate supported by the link.

[0140] If not: roll back to the previous rate (such as GEN3 to GEN2, GEN4 to GEN3, GEN5 to GEN4, etc.), send the corresponding device speed reduction exception and LTSSM state machine log to the BMC, and then end the process.

[0141] If it is the highest public rate: Go to the next step to further determine whether the PCIe link bandwidth is correct.

[0142] ⑧ Determine again whether the PCIe link bandwidth is correct:

[0143] Check the PCIe link bandwidth to determine whether it is correct.

[0144] If the bandwidth is incorrect: send the corresponding device bandwidth exception and LTSSM state machine log to the BMC, delete the LTSSM state machine log in the memory, and end the process.

[0145] If there are no abnormalities during the process: delete all PCIeLTSSM state machine logs and exit this process.

[0146] In the present embodiment, a high-speed extension link fault handling device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0147] This embodiment provides a high-speed extension link fault processing device, such as Figure 4 As shown, including:

[0148] The determination module 401 is used to record the state machine log generated by the state machine when the high-speed extension link enters the training process, and determine whether the high-speed extension link enters the target state through the state machine when the high-speed extension link training is completed;

[0149] The analysis module 402 is used to analyze whether the high-speed extension link is currently degraded based on the current bandwidth and current rate of the high-speed extension link if the high-speed extension link enters the target state, and obtain an analysis result;

[0150] The execution module 403 is used to obtain the target processing strategy corresponding to the analysis result and execute the processing operation indicated by the target processing strategy.

[0151] In an embodiment of the present application, the device further includes: a sending module, which is used to send a device identification abnormality signal and a state machine log generated by the state machine to the baseboard management controller if the high-speed extension link does not enter the target state.

[0152] In the embodiment of the present application, the analysis module 402 is used to obtain the rated bandwidth and the rated rate corresponding to the high-speed extension link when the high-speed extension link is in the target state; compare the rated bandwidth with the current bandwidth, and compare the rated rate with the current rate; if the current bandwidth is less than the rated bandwidth, it is determined that the current bandwidth of the high-speed extension link is wrong, or, if the current bandwidth is greater than or equal to the rated bandwidth, it is determined that the current bandwidth of the high-speed extension link is correct; if the current rate is less than the rated rate, it is determined that the current rate of the high-speed extension link needs to be adjusted, or, if the current rate is greater than or equal to the rated rate, it is determined that the current rate of the high-speed extension link does not need to be adjusted; if the current bandwidth is wrong, and / or the current rate needs to be adjusted, the analysis result is that the high-speed extension link is degraded; or, if the current bandwidth is correct and the current rate of the high-speed extension link does not need to be adjusted, the analysis result is that the high-speed extension link is not degraded.

[0153] In the embodiment of the present application, the execution module 403 is used to send a bandwidth abnormality signal and a state machine log generated by the state machine to the baseboard management controller if the analysis result shows that the high-speed extension link is degraded and the degradation is caused by the current bandwidth error.

[0154] In an embodiment of the present application, the execution module 403 is used to detect whether both ends of the high-speed extension link support the first rate, and detect whether the register currently supports the bypass balancing function if the analysis result shows that the high-speed extension link is degraded and the degradation is caused by the need to adjust the current rate, wherein the first rate is greater than the current rate; if both ends of the high-speed extension link support the first rate and the register currently supports the bypass balancing function, then perform the bypass balancing operation and set the rate in the recovery state of the state machine to the first rate; detect whether the first rate is set successfully in the recovery state; if the first rate is set successfully in the recovery state, delete the state machine log except the start and end of the process of adjusting the rate to the first rate in the recovery state; detect the first rate Whether the rate is the highest public rate, if the first rate is not the highest public rate, the rate in the recovery state is set to the second rate, wherein the second rate is the next level rate of the first rate; if the second rate is successfully set in the recovery state, the state machine logs except the start and end of the process of adjusting the rate to the second rate in the recovery state are deleted; whether the second rate is the highest public rate is detected, if the second rate is the highest public rate, whether the bandwidth of the high-speed extension link is correct when it is at the second rate is detected; if the bandwidth of the high-speed extension link is correct when it is at the second rate, all state machine logs are deleted; or, if the bandwidth of the high-speed extension link is wrong when it is at the second rate, a bandwidth abnormality signal and the state machine log generated by the state machine are sent to the baseboard management controller.

[0155] In an embodiment of the present application, the sending module is also used to reset the rate in the recovery state of the state machine to the first rate if the second rate fails to be set in the recovery state, and send a speed reduction exception signal and a state machine log generated by the state machine to the baseboard management controller.

[0156] In the embodiment of the present application, the execution module 403 is used to delete all state machine logs generated by the state machine if the analysis result shows that there is no degradation of the high-speed extension link.

[0157] See also Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0158] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0159] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0160] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of a computer device based on the presentation of a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0161] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0162] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0163] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0164] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for handling a high-speed extension link failure, characterized in that: The method comprises: When the high-speed extension link enters the training process, recording the state machine log generated by the state machine, and when the high-speed extension link training is completed, determining whether the high-speed extension link enters the target state through the state machine; If the high-speed extension link enters the target state, analyzing whether the high-speed extension link is currently degraded based on the current bandwidth and current rate of the high-speed extension link to obtain an analysis result; Obtain a target processing strategy corresponding to the analysis result, and execute a processing operation indicated by the target processing strategy.

2. The method according to claim 1, characterized in that The method further comprises: If the high-speed extension link does not enter the target state, a device identification abnormality signal and a state machine log generated by the state machine are sent to a baseboard management controller.

3. The method according to claim 1, characterized in that The analyzing whether the high-speed extension link is currently degraded based on the current bandwidth and current rate of the high-speed extension link to obtain the analysis result includes: Acquire the rated bandwidth and rated rate corresponding to the high-speed extension link when it is in the target state; Comparing the rated bandwidth with the current bandwidth, and comparing the rated rate with the current rate; If the current bandwidth is less than the rated bandwidth, it is determined that the current bandwidth of the high-speed extension link is wrong, or, if the current bandwidth is greater than or equal to the rated bandwidth, it is determined that the current bandwidth of the high-speed extension link is correct; If the current rate is less than the rated rate, it is determined that the current rate of the high-speed extension link needs to be adjusted; or, if the current rate is greater than or equal to the rated rate, it is determined that the current rate of the high-speed extension link does not need to be adjusted; If the current bandwidth is wrong and / or the current rate needs to be adjusted, the analysis result is that the high-speed extension link is degraded; or, if the current bandwidth is correct and the current rate of the high-speed extension link does not need to be adjusted, the analysis result is that the high-speed extension link is not degraded.

4. The method according to claim 3, characterized in that The executing the processing operation indicated by the target processing strategy includes: If the analysis result shows that the high-speed extension link is degraded and the degradation is caused by a current bandwidth error, a bandwidth abnormality signal and a state machine log generated by the state machine are sent to a baseboard management controller.

5. The method according to claim 3, characterized in that: The executing the processing operation indicated by the target processing strategy includes: If the analysis result shows that the high-speed extension link is degraded and the degradation is caused by the need to adjust the current rate, detecting whether both ends of the high-speed extension link support a first rate, and detecting whether the register currently supports a bypass balancing function, wherein the first rate is greater than the current rate; If both ends of the high-speed extension link support a first rate, and the register currently supports a bypass balancing function, a bypass balancing operation is performed, and the rate in the recovery state of the state machine is set to the first rate; detecting whether the first rate is successfully set in the recovery state; If the first rate is successfully set in the recovery state, deleting the state machine logs except the start and end of the process of adjusting the rate to the first rate in the recovery state; Detecting whether the first rate is the highest public rate, and if the first rate is not the highest public rate, setting the rate in the recovery state to a second rate, wherein the second rate is a lower level rate of the first rate; If the second rate is successfully set in the recovery state, deleting the state machine logs except the start and end of the process of adjusting the rate to the second rate in the recovery state; detecting whether the second rate is the highest public rate, and if the second rate is the highest public rate, detecting whether the bandwidth of the high-speed extension link is correct when it is at the second rate; If the bandwidth of the high-speed extension link at the second rate is correct, all state machine logs are deleted; or if the bandwidth of the high-speed extension link at the second rate is wrong, a bandwidth abnormality signal and the state machine log generated by the state machine are sent to the baseboard management controller.

6. The method according to claim 5, characterized in that The method further comprises: If the second rate fails to be set in the recovery state, the rate of the state machine in the recovery state is reset to the first rate, and a speed reduction abnormality signal and a state machine log generated by the state machine are sent to a baseboard management controller.

7. The method according to claim 2, characterized in that The executing the processing operation indicated by the target processing strategy includes: If the analysis result shows that the high-speed extension link does not have any degradation, all state machine logs generated by the state machine are deleted.

8. A high-speed extension link fault handling device, characterized in that: The device comprises: A determination module, used for recording a state machine log generated by a state machine when the high-speed extension link enters a training process, and determining whether the high-speed extension link enters a target state through the state machine when the high-speed extension link training is completed; An analysis module, configured to analyze whether the high-speed extension link is currently degraded based on the current bandwidth and current rate of the high-speed extension link if the high-speed extension link enters the target state, and obtain an analysis result; The execution module is used to obtain the target processing strategy corresponding to the analysis result and execute the processing operation indicated by the target processing strategy.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 7.

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