Prefetch parameter configuration and cache prefetch method, device and storage medium

Abstract

Embodiments of the present application provide a prefetch parameter configuration and cache prefetch method, device and storage medium. In the embodiments of the present application, for a processor running an application, a plurality of prefetch parameter combinations supported by the processor are grouped, and each parameter space obtained by grouping is taken as a granularity for optimization processing based on a performance distribution model of the application, so that the search efficiency of the prefetch parameter combination is improved, the search complexity is reduced, and the calculation cost is saved; the value of the hardware module for prefetch control in the processor is configured based on the optimized prefetch parameter combination, so that the processor performs the prefetch operation more reasonably with the optimized prefetch parameter combination, and the performance of the CPU in performing the prefetch operation is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of cloud storage, and particularly relates to a prefetch parameter configuration and cache prefetch method, device and storage medium. BACKGROUND

[0002] Prefetching is a technology used by a central processing unit (CPU), which can be divided into software prefetching and hardware prefetching. Hardware prefetching is implemented by a dedicated hardware module (referred to as a prefetcher) in the CPU. The prefetcher in the CPU can extract instructions or data from a slower storage medium (such as a memory) to a faster storage medium (such as a cache) before the instructions or data are actually needed, thereby improving the execution performance of the CPU.

[0003] If the prefetching strategy is not good, it is possible to cause the execution performance of the CPU to decrease. Because the cache resources are limited, if the prefetching is wrong, useless data is prefetched, which can cause useful data to be evicted from the cache, thereby increasing the power consumption of the system and reducing the execution performance of the CPU. Therefore, how to make the CPU use a more reasonable prefetching strategy is a problem to be solved in the current prefetching mechanism. SUMMARY

[0004] Aspects of the present application provide a prefetch parameter configuration and cache prefetch method, device and storage medium, which are used to configure a prefetch parameter combination for a CPU and improve the performance of the CPU in performing a prefetch operation.

[0005] The present application provides a prefetch parameter configuration method, which includes determining a target application and a target processor responsible for running the target application, the target processor including a plurality of hardware modules for prefetching control, and a value combination between the plurality of hardware modules forming a plurality of prefetch parameter combinations; grouping the plurality of prefetch parameter combinations according to the number of a plurality of prefetching algorithms supported by the target processor to obtain a plurality of parameter spaces; performing optimization processing of the prefetch parameter combinations on the plurality of parameter spaces according to a performance distribution model of the target application to obtain a target prefetch parameter combination; and configuring values of the plurality of hardware modules according to the target prefetch parameter combination, so that the target processor performs a prefetch operation according to the target prefetch parameter combination.

[0006] The embodiment of the present application further provides a cache prefetch method, which is applied to a target processor running a target application, the target processor comprises a plurality of hardware modules for prefetch control, and values of the plurality of hardware modules are configured according to the prefetch parameter configuration method provided by the embodiment of the present application; the method comprises the following steps: reading the values of the plurality of hardware modules, the values of the plurality of hardware modules are combined to form a target prefetch parameter combination for prefetch control; and performing a prefetch operation based on the target prefetch parameter combination in the process of running the target application.

[0007] The embodiment of the present application further provides an electronic device, which comprises a memory and a processor; the memory is used for storing a computer program; the processor is coupled with the memory and is used for executing the computer program to realize each step in the prefetch parameter configuration method provided by the embodiment of the present application.

[0008] The embodiment of the present application further provides a processor, which is responsible for running a target application, and the processor comprises a plurality of hardware modules for prefetch control, values of the plurality of hardware modules are configured according to the prefetch parameter configuration method provided by the embodiment of the present application, and the processor is used for realizing steps in the cache prefetch method provided by the embodiment of the present application.

[0009] The embodiment of the present application further provides a computer readable storage medium storing a computer program, when the computer program is executed by a processor, the processor realizes each step in the prefetch parameter configuration method or the cache prefetch method provided by the embodiment of the present application.

[0010] In the embodiment of the present application, for a processor running an application, a plurality of prefetch parameter combinations supported by the processor are grouped, and each parameter space obtained by grouping is taken as a granularity for optimization processing based on a performance distribution model of the application, so that the search efficiency of the prefetch parameter combination is improved, the search complexity is reduced, and the calculation cost is saved; values of hardware modules for prefetch control in the processor are configured based on the optimized prefetch parameter combination, so that the processor performs the prefetch operation more reasonably with the optimized prefetch parameter combination, and the performance of the CPU in performing the prefetch operation is improved. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the present application, constitute a part of the present application and illustrate the illustrative embodiments of the present application and their description serve to explain the present application, and do not constitute improper limitations on the present application. In the drawings:

[0012] Figure 1a A schematic diagram of an instruction pipeline of a processor core is provided for the exemplary embodiment of the present application;

[0013] Figure 1b A schematic diagram of a prefetch register and a prefetch parameter thereof is provided for the exemplary embodiment of the present application;

[0014] Figure 1c A schematic diagram of a cache prefetch process provided for an exemplary embodiment of the present application;

[0015] Figure 2a A flowchart of a prefetch parameter configuration method provided for an exemplary embodiment of the present application;

[0016] Figure 2b A state diagram of a task configuration interface provided for an exemplary embodiment of the present application;

[0017] Figure 2c A flowchart of an optimization process of prefetch parameter combination for any parameter space provided for an exemplary embodiment of the present application;

[0018] Figure 3 A flowchart of a cache prefetch method provided for an exemplary embodiment of the present application;

[0019] Figure 4 A structural diagram of a prefetch parameter configuration device provided for an exemplary embodiment of the present application;

[0020] Figure 5 A structural diagram of a cache prefetch device provided for an exemplary embodiment of the present application;

[0021] Figure 6 A structural diagram of an electronic device provided for an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described below in conjunction with specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0023] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0024] On some traditional physical servers, multiple applications are usually run, and CPU resources of the physical server are shared by the multiple applications. The access memory mode and read-write regularity of the applications are different, and different prefetch strategies will have different performance impacts on the applications. However, in the case of running multiple applications on a physical server, only one prefetch strategy can be configured for the CPU, which will lose both sides, and one prefetch strategy cannot bring performance advantages to all applications.

[0025] With the development of virtualization technology and cloud computing technology, various cloud computing scenarios appear, such as public cloud, private cloud, and hybrid cloud. In the cloud computing scenario, users can purchase or deploy virtualization instances, such as virtual machines, containers, cloud hosts, Elastic Compute Service (ECS), etc. In some application scenarios, the virtualization instance can be allocated an independent physical running environment and independent physical resources, such as the virtualization instance having independent computing resources, storage resources, and network resources, etc. In some application scenarios, the computing resources independently possessed by the virtualization instance include one or more CPU resources. This provides conditions for controlling the cache prefetch algorithm from the dimension of the virtualization instance.

[0026] Further, considering that in the cloud computing scenario, the virtualization instance is usually scheduled in the cluster dimension, that is, the scheduled virtualization instance usually deploys the same application, and various resources allocated to the virtualization instance are mainly for the same application, such as the CPU allocated to the virtualization instance is responsible for running an application. On this basis, the cache prefetch control of the CPU can be personalized from the application dimension in the virtualization instance, so that the CPU can more reasonably perform prefetch operations in the application running process, and pre-read data and / or instructions from the memory to the cache, or from the three-level cache to the two-level cache, or from the two-level cache to the one-level cache, to solve various problems encountered in the memory in the running process of some applications, such as low cache hit rate, insufficient memory bandwidth resources, and memory contention.

[0027] In the embodiment, the number of applications deployed in the virtualization instance is not limited, and can be one or more. No matter how many applications are carried in the virtualization instance, the scheme provided by the embodiment can be used to configure the pre-fetch parameter of the processor to which the application capable of being allocated to the independent processor. In addition, it should be noted that in some application scenarios, the application is carried in the virtualization instance, which can ensure that the application has relatively independent physical resources (including independent processor resources) to a certain extent, but the virtualization instance is not the only technical means that can ensure that the application has independent processor resources. Any application scenario in which the application exclusively occupies the processor resources is applicable to the embodiment, and the way of carrying the application in the virtualization instance to make the application exclusively occupy the processor resources is only one application scenario of the embodiment. Specifically, in the embodiment, the target application can be determined, and the target processor responsible for running the target application can be determined. The target processor refers to the processor exclusively occupied by the target application, and then based on this, the target processor is configured with a more appropriate pre-fetch strategy from the dimension of the target application. It should be noted that the target application can be allocated to one or more processors, and each processor can be used as the target processor in the embodiment when it is exclusively occupied by the target application.

[0028] In the embodiment, the cache system of the target processor core is a multi-level system divided according to tasks. In addition, the implementation structure of the core cache system of the processor of different architectures, different models and different manufacturers will be different, which is not limited in the embodiment. The processors of various architectures, various models and various manufacturers are applicable to the embodiment as long as they support the hardware pre-fetch scheme and need to perform pre-fetch control. An exemplary target processor core is shown below, as shown in the figure, the instruction pipeline of the target processor core includes but is not limited to the following stages: fetch and decode (Fetch&Decode) stage, execution (Execution) stage and commit and exit (Commit&Retire) stage. Figure 1a

[0029] ​The Fetch & Decode stage corresponds to an In-Order Front End module, which includes, but is not limited to, the following hardware units: a Branch Prediction Unit, a Decode, Rename & Dispatch Unit, a Level 1 Instruction-Cache (L1 I-Cache) Unit, and a Level 1 Instruction Translation Lookaside Buffer (L1-I-TLB) Unit. The L1 I-Cache is used to store instructions; the L1 D-Cache is used to store Level 1 cache data. The L1-I-TLB is used to cache page table entries to determine the physical address of a L1 instruction.

[0030] The Execution stage corresponds to an Out-Of-Order Back End module, which includes, but is not limited to, the following hardware units: an Issue Queue, Execution Units, a Load Store Unit, a Level 1 Data-TLB (L1 D-TLB) Unit, a Level 2 TLB Unit, and a Level 1 Data-Cache (L1 D-Cache) Unit. The L2 TLB is used to cache page table entries to determine the physical address of a L1 cache.

[0031] The Commit & Retire stage corresponds to an In-Order Instruction Retire module, which includes, but is not limited to, the following hardware units: a Commit & Retire Unit.

[0032] The Fetch & Decode stage and the Execution stage also correspond to a Core-Clure Interface module, which includes a Level 2 Cache Unit. The Level 2 Cache Unit is used to cache page table entries to determine the physical address of a L1 cache. Figure 1a The Last Level Cache (LLC), also known as the Level 3 Cache, is not shown for the target processor. The LLC is optional for some target processors.

[0033] Among them, the branch prediction unit is used to predict the address of the next instruction, for example, to predict the address of the CPU to prefetch instructions; the decoding, renaming and scheduling unit is mainly used to obtain instructions from the L1 I-Cache according to the address predicted by the branch prediction unit, identify the type of the instructions, and perform renaming of the instructions, and write the renamed instructions in the order into the launch queue. The execution unit is used to execute the instructions in the launch queue, and the load and store unit provides the data required by the instructions in the launch queue. The submission and exit unit is used to submit the execution results and exit.

[0034] In order to improve the running performance of the target application, cache prefetching operations will be involved in the above instruction pipeline process, as shown in Figure 1c The cache prefetching can be summarized as the following two kinds: one is to read data from the low-end storage in advance and write it into the high-end cache, which is referred to as cache read data, mainly including L2 Cache->L1 I-Cache / L1 D-Cache, indicating reading instructions from L2 Cache into L1 I-Cache or reading data from L2 Cache into L1 D-Cache, and L2 TLB->L1 I-TLB / L1 D-TLB, indicating reading instruction mapping information from L2 TLB into L1 I-TLB or reading data mapping information from L2 TLB into L1 D-TLB; the other is to write dirty pages in the high-end storage back to the low-end storage in advance, which is referred to as dirty page write back, mainly including L1 D-Cache->L2 Cache, indicating writing dirty pages in L1 D-Cache back to L2 Cache in advance, and L1 I-TLB / L1 D-TLB->L2 TLB, indicating writing instruction mapping information in L1 I-TLB back to L2 TLB in advance or writing data mapping information in L1 D-TLB back to L2 TLB in advance. In the embodiments of the present application, the cache read data is mainly concerned, that is, the case of reading data from the low-end storage in advance and writing it into the high-end cache.

[0035] In actual applications, there are two kinds of prefetching methods, software and hardware. Software prefetching can insert prefetch instructions in the program, use prefetch instructions to perform prefetching during coding, or use optimized compilation options during compilation to use prefetch instructions to improve the execution efficiency of the program. Hardware prefetching is implemented by a dedicated hardware prefetching module (such as a prefetcher) inside the target processor. The prefetcher is mainly used for data and / or instruction prefetching, that is, to place data that may be used in advance in the relevant cache to wait to be used in the relevant cache. In the embodiments of the present application, the hardware prefetching method is mainly concerned.

[0036] The target processor supports multiple hardware prefetch algorithms, and different hardware prefetch algorithms are implemented by different prefetchers. Which hardware prefetch algorithm (or prefetcher) is used by the target processor and how data and / or instructions are prefetched by the hardware prefetch algorithm (or prefetcher) can be controlled by multiple hardware modules in the target processor for prefetch control. That is, in the present embodiment, in addition to the prefetcher, the target processor also includes multiple hardware modules for cache prefetch control. In an optional implementation, the multiple hardware modules for prefetch control can be implemented as multiple prefetch registers, and of course, can also be other hardware structures other than prefetch registers, which are not limited. In the following embodiments of the present application, the multiple hardware modules for prefetch control in the target processor will be described by way of example with the multiple hardware modules for prefetch control being implemented as multiple prefetch registers.

[0037] The multiple prefetch registers in the present embodiment refer to registers for cache prefetch control of the target processor, and it should be noted that the target processor also includes other registers, which are not limited in the embodiments of the present application. Each prefetch register is used to control a prefetch parameter, and different prefetch registers represent different prefetch parameters, that is, each prefetch register corresponds to a prefetch parameter, and a prefetch parameter has at least two values. For example, if the prefetch parameter corresponding to the prefetch register is represented by 1 bit (bit), the values of the prefetch register are two, which are 0 and 1; if the prefetch parameter of the prefetch register is represented by 2 bits, the values of the prefetch register are four, which are 00, 01, 10 and 11. For the same prefetch register, different values are mutually exclusive, indicating that at the same time, the value of the prefetch register can only be one of them. The value combination of the multiple prefetch registers forms multiple prefetch parameter combinations, and each prefetch parameter combination represents a prefetch strategy. For example, the prefetch parameter combination can include but is not limited to: which prefetch algorithm is used by the target processor, which data is prefetched, when to start prefetching, and where to store the prefetched data, etc., and these information can be given by the values of different prefetch registers.

[0038] Optionally, the multiple prefetch registers included in the target processor can be classified according to the prefetch parameters they represent. Specifically, the multiple prefetch registers can be divided into two types: one type represents prefetch algorithm selection parameters, mainly used to select whether to use a certain prefetch algorithm (i.e., prefetcher). Here, it should be noted that the prefetch algorithm mentioned in the embodiments of this application mainly refers to the hardware prefetch algorithm, that is, the prefetch algorithm implemented by the prefetcher; the other type represents prefetch operation execution control parameters, mainly used to control how the selected prefetcher executes the prefetch process. There are multiple such prefetch registers, used to provide different prefetch operation execution control parameters for the prefetcher, such as determining which piece of data the prefetcher prefetches, when to start prefetching data, the amount of data to be prefetched, the prefetch location, and the storage location of the prefetched data. Among them, the number of prefetch registers representing prefetch algorithm selection parameters can be one, and the number of prefetch registers representing prefetch operation execution control parameters can be multiple, such as two, three, or ten. Correspondingly, a prefetch parameter combination, which is a combination of values ​​of multiple prefetch registers, includes prefetch algorithm selection parameters and prefetch operation execution control parameters.

[0039] For example, in Figure 1b The diagram illustrates some of the prefetch registers included in the target processor. The CMC_MIN_WAY register represents the prefetch algorithm selection parameters, indicating whether to select the Correlated Miss Caching (CMC) algorithm. The CMC algorithm is a hardware prefetch algorithm, a type of time prefetcher, that utilizes a portion of the L2 cache space to store historical miss information and uses this miss information as metadata for data prefetching. When prefetching data from memory to the L2 cache, the number of bits reserved for data and instructions in the L2 cache is controlled by the L2_DATA_PART and L2_INST_PART registers, respectively. The L2 cache data portion (L2_DATA_PART) register and the L2 cache instruction portion (L2_INST_PART) register represent prefetch operation execution control parameters. The values ​​of the L2_DATA_PART and L2_INST_PART registers can have various values. Figure 1bIn the embodiment, it is assumed that the parameters of the L2_DATA_PART register and the L2_INST_PART register are represented by 3 bits, and each has 8 values; if the value of the L2_DATA_PART register is 000, it indicates that 0 bits in the L2 cache are reserved for data, which is a reset value; if the value of the L2_DATA_PART register is 001, it indicates that 1 bit in the L2 cache is reserved for data; if the value of the L2_INST_PART register is 111, it indicates that 7 bits in the L2 cache are reserved for instructions; if the value of the L2_INST_PART register is 101, it indicates that 5 bits in the L2 cache are reserved for instructions. Different combinations of values of the L2_DATA_PART register and the L2_INST_PART register form different prefetching schemes, and different prefetching schemes produce different performance data of the target application during running of the target application.

[0040] In the embodiment, each prefetching register has at least two values, and the combinations of values among the plurality of prefetching registers are very large, which can be represented as 2 n n represents the number of bits involved in the plurality of prefetching registers. In the embodiment, one combination of values of the plurality of prefetching registers is referred to as one combination of prefetching parameters, and how to select a more suitable combination of prefetching parameters from the many combinations of prefetching parameters and configure the combination of prefetching parameters to the prefetching registers so as to implement prefetching control of the target processor is a problem that needs to be solved in the embodiment. That is, the main target of the embodiment is to select a more suitable combination of prefetching parameters from the many combinations of prefetching parameters, configure the selected more suitable combination of prefetching parameters to the plurality of prefetching registers included in the target processor, so that the target processor performs cache prefetching operation according to the more suitable combination of prefetching parameters for the target application, so as to improve the performance data of the running target application.

[0041] The performance improvement of the target application caused by the prefetch operation of the target processor under the control of different prefetch parameter combinations is not the same. In the embodiments of the present application, the performance of the target application caused by the prefetch parameter combination can be evaluated from two dimensions of coverage and accuracy. For example, in the case of coverage, without using the prefetch parameter configuration algorithm, 100 cache miss situations occur, and in the case of using the prefetch parameter configuration method to determine the prefetch parameter combination Z, the cache miss situation is reduced to 30 times, which means that the prefetch parameter combination Z successfully avoids 70 cache miss situations, i.e. the coverage is 70 / 100=70%. For example, for accuracy, consider the number of times of the prefetch data executed by the prefetch parameter combination, the prefetch parameter combination Z executes 140 prefetch operations, of which 70 are valid, so the accuracy is 70 / 140=50%. In the embodiments of the present application, the prefetch parameter combination that can bring better performance improvement to the target application can be selected from a plurality of prefetch parameter combinations, which is referred to as selecting a better prefetch parameter combination from a plurality of prefetch parameter combinations.

[0042] A simple method for selecting a better prefetch parameter combination is that for each prefetch parameter combination, the values in the prefetch parameter combination are respectively configured as the values of the plurality of prefetch registers of the target processor, so that the target processor can execute the prefetch operation in the process of running the target application under the control of the prefetch parameter combination, and obtain the performance data of the target application caused by the prefetch operation. Thus, by running each prefetch parameter combination once, the performance data of each prefetch parameter combination brought to the target application can be obtained, and then a prefetch parameter combination with better performance data is selected as the prefetch parameter combination used by the target processor for cache prefetching. However, there are many types of prefetch parameter combinations, for example, the target processor executes the prefetch operation in the processes A, B and C above involves 35 groups of prefetch registers, and there are 2^56 prefetch parameter combinations between the 35 groups of prefetch registers, the search space is very large, and it takes time to run each time for the prefetch parameter combination. Therefore, it will take a lot of time to run all the prefetch parameter combinations in 2^56 once, and it is obvious that a better solution cannot be obtained by directly traversing a plurality of prefetch parameter combinations.

[0043] In order to improve the search efficiency of the prefetch parameter combination, in the embodiments of the present application, the plurality of prefetch parameter combinations are grouped from the dimension of the plurality of prefetch algorithms supported by the target processor, and the optimization processing of the prefetch parameter combination is performed according to the grouping, and a better prefetch parameter combination is selected, the search space of the prefetch parameter combination is reduced by grouping, the configuration efficiency of the prefetch parameter is improved, and the configuration cost is saved.

[0044] The technical solutions provided by the embodiments of the present application will be described in detail below with reference to the drawings.

[0045] Figure 2a A flowchart of a pre-fetch parameter configuration method provided for an exemplary embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the method comprises the following steps. Figure 2a

[0046] 101, determining a target application and a target processor responsible for running the target application, the target processor comprising a plurality of hardware modules for pre-fetch control, and a value combination of the plurality of hardware modules forming a plurality of pre-fetch parameter combinations;

[0047] 102, grouping the plurality of pre-fetch parameter combinations according to a number of pre-fetch algorithms supported by the target processor, to obtain a plurality of parameter spaces;

[0048] 103, performing optimization processing of the pre-fetch parameter combinations on the plurality of parameter spaces according to a performance distribution model of the target application, to obtain a target pre-fetch parameter combination;

[0049] 104, configuring values of the plurality of hardware modules for pre-fetch control according to the target pre-fetch parameter combination, so that the target processor performs a pre-fetch operation according to the target pre-fetch parameter combination.

[0050] The method provided in the embodiment is used for configuring a pre-fetch parameter combination of a CPU from the perspective of an application, so that the CPU can perform a pre-fetch operation more reasonably according to the configured pre-fetch parameter combination, the performance of the CPU in performing the pre-fetch operation during running of the target application is improved, and the running performance of the target application is improved.

[0051] In the embodiment, the target application is not limited, and can be any application that needs to be run by the target processor, for example, a video application, an online shopping application, an instant messaging application, a novel application, a mail service application, a taxi-hailing application, a map application, a game application, etc. The embodiment of the present application does not limit the model, specification and manufacturer of the target processor, and any processor supporting a hardware pre-fetch scheme and needing pre-fetch control is applicable to the embodiment of the present application.

[0052] In the embodiment of the present application, the implementation of determining the target application and the target processor responsible for running the target application is not limited, and is exemplarily described as follows.

[0053] Example A1: ​In this example, the personnel responsible for pre-fetch parameter configuration (e.g., a tenant corresponding to the target application, a relevant personnel of a cloud computing scenario, etc.) is allowed to send a pre-fetch parameter configuration task through a terminal device used by the personnel, and carries description information of the target application and description information of the target processor in the pre-fetch parameter configuration task. The description information of the target application can include but is not limited to: type information, name information, function information, etc. of the target application; and the type information of the target application can be live, social, learning, shopping, or game, etc. The description information of the target processor can include but is not limited to: model, version, manufacturer, device identifier, internal architecture, pre-fetch capability, etc. Accordingly, the execution subject of the embodiments of the present application can be various electronic devices, which can receive the pre-fetch parameter configuration task, determine the target application according to the description information of the target application, and determine the target processor responsible for running the target application according to the description information of the target processor.

[0054] Example A2: In this example, a task configuration interface can be displayed to the personnel responsible for pre-fetch parameter configuration, as shown in Figure 2b The task configuration interface includes application configuration options and processor configuration options; the personnel responsible for pre-fetch parameter configuration can perform configuration operations on the application configuration options and the processor configuration options. For example, the application configuration options include: a first option name and a first option value list or an input box corresponding to the first option name, the first option name indicates configuration of the application, if it is a first option value list, the list includes multiple information items for describing the application, which can be selected; if it is an input box, it allows input of information for describing the application; configuration of the application configuration options can be implemented as: the personnel responsible for pre-fetch parameter configuration selects one or more information items from the first option value list for describing the target application, or inputs multiple information in the input box for describing the target application. Similarly, the processor configuration options include: a second option name and a second option value list or an input box corresponding to the second option name, the second option name indicates configuration of the processor, if it is a second option value list, the list includes multiple information items for describing the processor, which can be selected; if it is an input box, it allows input of information for describing the processor; configuration of the application configuration options can be implemented as: the personnel responsible for pre-fetch parameter configuration selects one or more information items from the second option value list for describing the target processor, or inputs multiple information in the input box for describing the target processor. Accordingly, in response to the configuration operations on the application configuration options and the processor configuration options, the description information of the target application and the target processor can be obtained, and then the target application and the target processor are determined according to the description information of the target application and the target processor, respectively. The task configuration interface can be a remote command interface, a web page, or an application page, which is not limited. In addition,Figure 2b The style of the task configuration interface shown is only an example and is not limited thereto.

[0055] In the case of determining the target application and the target processor, the number of the plurality of prefetch algorithms supported by the target processor and the plurality of prefetch parameter combinations formed by the value combinations between the plurality of hardware modules included in the target processor for performing prefetch control are determined. For ease of description and understanding, in the subsequent content of the embodiment, a plurality of hardware modules are taken as an example to be implemented as a plurality of prefetch registers for description. In order to more quickly select a more suitable target prefetch parameter combination from the plurality of prefetch parameter combinations, in the embodiment of the present application, according to the number of the plurality of prefetch algorithms supported by the target processor, the plurality of prefetch parameter combinations are grouped to obtain a plurality of parameter spaces, each parameter space includes part of the prefetch parameter combinations. The parameter space obtained by grouping in the embodiment is taken as a granularity, and the plurality of parameter spaces are subjected to optimization processing of the prefetch parameter combinations, thereby obtaining the target prefetch parameter combination. Wherein, grouping the plurality of prefetch parameter combinations mainly refers to selecting some prefetch parameter combinations related to each prefetch algorithm from the plurality of prefetch parameter combinations, and taking the some prefetch parameter combinations related to the prefetch algorithm as the parameter space of the prefetch algorithm. The parameter space of the prefetch algorithm does not include the prefetch parameter combinations irrelevant to the prefetch algorithm, so as to reduce the search space of the parameter space and improve the optimization efficiency of the prefetch parameter.

[0056] In the embodiment of the present application, the grouping of the plurality of prefetch parameter combinations according to the number of the plurality of prefetch algorithms supported by the target processor is not limited. In an optional embodiment, considering that the prefetch operation execution control parameters required by each prefetch algorithm are not completely the same, that is, the prefetch registers required by different prefetch algorithms are not completely the same. In view of this, for each prefetch algorithm, the plurality of prefetch registers can be divided into two categories, that is, a first group of prefetch registers affecting the prefetch algorithm and a second group of prefetch registers not affecting the prefetch algorithm. The first group of prefetch registers can include one or more prefetch registers; the second group of prefetch registers can include one or more prefetch registers. In the embodiment of the present application, how to determine which prefetch register is related to which or which several prefetch algorithms and which prefetch register is irrelevant to which or which several prefetch algorithms is not limited.

[0057] In an optional embodiment, the pre-fetch operation execution control parameters associated with a pre-fetch algorithm can be determined in the process of designing the pre-fetch algorithm, the pre-fetch registers associated with the pre-fetch operation execution control parameters are determined as the pre-fetch registers associated with the pre-fetch algorithm, and the other pre-fetch registers are determined as the pre-fetch registers not associated with the pre-fetch algorithm, i.e. whether the values of the pre-fetch registers will affect a certain pre-fetch algorithm is known and is set when the target processor is manufactured. In another optional embodiment, which pre-fetch registers are associated with a pre-fetch algorithm and which pre-fetch registers are not associated with the pre-fetch algorithm can be determined through online testing. Specifically, for a certain pre-fetch algorithm, whether the pre-fetch register Y affects the pre-fetch algorithm can be determined by setting Y as valid or invalid respectively, keeping the values of the other pre-fetch registers unchanged, obtaining the pre-fetch parameter combination H1 and the pre-fetch parameter combination H2 corresponding to the pre-fetch register Y being valid and invalid respectively, configuring the values of the pre-fetch registers of the target processor according to the pre-fetch parameter combination H1 and the pre-fetch parameter combination H2 respectively, making the target processor run the target application, and obtaining the performance data J1 and the performance data J2 respectively. If the performance difference between the performance data J1 and the performance data J2 is less than a set performance difference threshold, it is considered that the pre-fetch register Y does not affect the pre-fetch algorithm, and if the performance difference between the performance data J1 and the performance data J2 is greater than or equal to the set performance difference threshold, it is considered that the pre-fetch register Y affects the pre-fetch algorithm. In this way, whether each pre-fetch register affects the pre-fetch algorithm is determined in turn, and finally the pre-fetch registers associated with the pre-fetch algorithm and the pre-fetch registers not associated with the pre-fetch algorithm are obtained.

[0058] For any pre-fetch register, the values of the pre-fetch register can be divided into valid and invalid according to whether the pre-fetch register will affect a certain pre-fetch algorithm from the perspective of the pre-fetch algorithm, i.e. if the pre-fetch register affects the pre-fetch algorithm, the values of the pre-fetch register are valid for the pre-fetch algorithm, and if the pre-fetch register does not affect the pre-fetch algorithm, a value can be set for the pre-fetch register to represent that the pre-fetch register is invalid for the pre-fetch algorithm, and this value is referred to as an invalid value. For example, if the value of the pre-fetch register is 1 bit, when the pre-fetch register does not affect a certain pre-fetch algorithm, the value of the pre-fetch register can be set to 0 or 1 for the pre-fetch algorithm, and 0 or 1 is an invalid value. If the value of the pre-fetch register is 2 bits, when the pre-fetch register does not affect a certain pre-fetch algorithm, the value of the pre-fetch register can be set to one of the four values, e.g. 00 or 01, and 00 or 01 is an invalid value. For each pre-fetch register, the invalid value of the pre-fetch register for a certain pre-fetch algorithm can be pre-set when the target processor is manufactured, and the specific value representing that the pre-fetch register is invalid for a certain pre-fetch algorithm is not limited.

[0059] Based on the above analysis, an embodiment of grouping a plurality of prefetch parameter combinations according to the number of a plurality of prefetch algorithms supported by a target processor to obtain a plurality of parameter spaces includes: for any prefetch algorithm, determining a first group of prefetch registers that will affect the prefetch algorithm and a second group of prefetch registers that will not affect the prefetch algorithm among a plurality of prefetch registers; from a plurality of prefetch parameter combinations, selecting a part of the expected parameter combinations in which the values of the first group of prefetch registers are valid and the values of the second group of prefetch registers are invalid, as the parameter space corresponding to the prefetch algorithm. For example, the target processor involves 3 prefetch registers for cache prefetch, denoted as registers R1-R3, the prefetch algorithm M1 is related to 2 prefetch registers, denoted as registers R1 and R2, assuming that both registers are 1 bit, and the values are 0 or 1, and is not related to the other 1 prefetch register, denoted as register R3, assuming that this 1 register is 2 bits, and the values can be 00, 01, 10 or 11, then the 2 registers related to the prefetch algorithm M1 can be divided into the first group of prefetch registers, that is, including registers R1 and R2, and the 1 prefetch register not related to the prefetch algorithm M1 can be divided into the second group of prefetch registers, that is, including register R3; for the prefetch algorithm M1, each prefetch register in the first group of prefetch registers has a valid value of 0 or 1 for the prefetch algorithm M1, and each prefetch register in the second group of prefetch registers has an invalid value indicating that it does not affect the prefetch algorithm M1, assuming that the value indicating that register R3 is invalid for the prefetch algorithm M1 is 00; based on this, the 3 prefetch registers form 16 prefetch parameter combinations including: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111, so from the 16 prefetch parameter combinations, the prefetch parameter combination corresponding to the values of the first group of prefetch registers all being valid and the values of the second group of prefetch registers all being invalid values, that is, 0000, 0100, 1000, 1100, can be selected as the parameter space corresponding to the prefetch algorithm M1. It is explained here that in the above embodiment, 3 prefetch registers are taken as an example to illustrate how to obtain the parameter space corresponding to the prefetch algorithm based on the prefetch algorithm, and in actual application, the number of prefetch registers is not limited to 3, and the prefetch registers related and unrelated to the prefetch algorithm can be many, for example, the prefetch algorithm M1 can be related to 25 prefetch registers and unrelated to the other 10 prefetch registers, but no matter how many prefetch registers there are, the principle is the same.

[0060] After obtaining the parameter space corresponding to each prefetch algorithm, the optimization processing of the prefetch parameter combination can be performed on the plurality of parameter spaces according to the performance distribution model of the target application, with the parameter space corresponding to each prefetch algorithm as the granularity, to obtain the target prefetch parameter combination. In this embodiment, the performance distribution model of the target application can reflect the performance distribution of the target application when actually running under various prefetch parameter combinations, and can achieve the effect of simulating the running of the target application to a certain extent. The optimization processing of the prefetch parameter combination on the plurality of parameter spaces according to the performance distribution model refers to the process of selecting, for each parameter space, the relatively optimal partial prefetch parameter combination from the parameter space according to the performance distribution of the target application when actually running under various prefetch parameter combinations reflected by the performance distribution model, and finally selecting the target prefetch parameter combination from the relatively optimal partial prefetch parameter combinations selected from each parameter space.

[0061] In this embodiment, in order to select the target prefetch parameter combination, each prefetch parameter combination can be taken as an independent variable X, the running performance data of the target application in the actual running environment according to each prefetch parameter combination can be taken as a dependent variable Y, the actual running environment of the target application can be regarded as a black box system composed of the target application, the operating system and the hardware system, and a target function is used for representation. Wherein, X can be input into the target function to obtain Y, and the target of the embodiment of the present application is to find the value of X when Y is relatively optimal. Since the relationship between X and Y is relatively complex, the target function is not necessarily a convex function, and the traditional gradient descent method can no longer be applicable. Therefore, in this embodiment, the performance distribution model of the target application is constructed, the prior distribution of the target function is assumed by using the performance distribution model, that is, the performance distribution model is used to replace the target function, and then the optimization processing of the prefetch parameter combination on the plurality of parameter spaces is performed according to the performance distribution model of the target application, to obtain the target prefetch parameter combination.

[0062] In the embodiments of the present application, the performance distribution model is not limited, and is a distribution function that can reflect the performance distribution of the target application under various combinations of prefetch parameters. In an optional embodiment, the combinations of prefetch parameters and the performance data of the target application are sampled, and the performance distribution model is constructed based on the sampled data. Specifically, a plurality of combinations of prefetch parameters are initially sampled to obtain at least one initial combination of prefetch parameters. For example, the initial sampling can be random sampling or quantitative sampling, such as setting the number of samples, which can be 10, 100, or 500, etc. Then, the at least one initial combination of prefetch parameters is respectively configured to a plurality of prefetch registers of the target processor, and the target processor is controlled to run the target application based on the values in the plurality of prefetch registers to obtain at least one initial performance data caused by the prefetch operation of the target processor to the target application during the running of the target application according to the initial combinations of prefetch parameters; and a distribution function representing the performance data of the target application with respect to the combinations of prefetch parameters is constructed as the performance distribution model based on the at least one initial combination of prefetch parameters and the at least one initial performance data.

[0063] Exemplarily, taking 3 prefetch registers R1-R3 as an example, and assuming that register R1 and R2 adopt 1 bit, and register R3 adopts 2 bits, the 3 prefetch registers form 16 prefetch parameter combinations including: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111; the 16 prefetch parameter combinations can be initially sampled, for example, assuming that 4 initial prefetch parameter combinations, i.e., 0000, 0110, 1010 and 1110, are selected, and each initial prefetch parameter combination represents a prefetch strategy, which includes selecting a prefetch algorithm to be used and some control parameters required by the prefetch algorithm to perform a prefetch operation, such as when to perform a prefetch operation, how much data to prefetch, where to store the prefetched data in the cache, and the like; then, the 4 initial prefetch parameter combinations are sequentially configured to the 3 prefetch registers R1-R3 in the target processor, for example, the initial prefetch parameter combination 0000 is configured to the 3 prefetch registers R1-R3, then the value of R1 in the 3 prefetch registers is 0, the value of R2 is 0, and the value of R3 is 00, assuming that the value of R1 being 0 represents selecting the prefetch algorithm M0, the value of R2 being 0 represents performing a prefetch operation at time t, and the value of R3 being 00 represents prefetching data amount d0 from the memory to the L1-cache; after the initial prefetch parameter combination 0000 is configured to the 3 prefetch registers R1-R3, the target application can be started, at this time the target processor runs the target application, and in the process of running the target application, the target processor preferentially reads instructions or data from the L1 I-Cache / L1 D-Cache, in this process, according to the values of the 3 prefetch registers R1-R3, it can be determined to use the prefetch algorithm M0, to perform a prefetch operation at time t, and specifically to read data amount d0 from the memory and write the read data into the L1 D-cache; the prefetch operation under the control of the initial prefetch parameter combination 0000 will affect the cache hit rate of the target processor, and further affect the running efficiency of the target processor, and indirectly affect the running performance of the target application, such as the response speed of the target application, whether the target application crashes due to insufficient memory, and the like, therefore, the performance data of the target application under the initial prefetch parameter combination 0000 can be obtained. By analogy, the initial prefetch parameter combinations 0110, 1010 and 1110 can be sequentially configured to the 3 prefetch registers R1-R3, and the target processor is sequentially controlled to run the target application under different initial parameter combinations, and the performance data of the target application under the initial prefetch parameter combinations 0110, 1010 and 1110 is sequentially obtained.After obtaining the performance data of the target application under the initial prefetch parameter combinations 0000, 0110, 1010 and 1110, statistical analysis of the probability distribution can be performed according to the initial prefetch parameter combinations 0000, 0110, 1010 and 1110 and the performance data of the target application under the initial prefetch parameter combinations 0110, 1010 and 1110, to obtain.

[0064] If the initial prefetch parameter combination 0000 is an optimal combination, the data prefetched into the L1 D-cache is probably required by the target processor, and can be prefetched into the L1 D-cache before the target processor reads it, which can improve the running efficiency of the target processor, so that the target application has good running performance, and the distribution function of the performance data of the target application with respect to the prefetch parameter combination can be obtained. Alternatively, in an embodiment of the present application, it is considered that the performance data of the target application with respect to the prefetch parameter combination conforms to a Gaussian distribution, that is, the Gaussian distribution function can be used as the performance distribution model in the embodiment, that is, the prefetch parameter combination and the performance data of the target application caused by the prefetch operation of the target processor during running the target application according to the prefetch parameter combination are subject to a Gaussian distribution.

[0065] In an optional embodiment, in the case of obtaining the performance distribution model, the performance distribution model can be used in the process of optimizing the prefetch parameter combination in the plurality of parameter spaces. The number of iterations T of the optimization process can be set, T is a positive integer, that is, the prefetch parameter combination in each parameter space is optimized for T rounds, and T is less than the number of prefetch parameter combinations in the parameter space, which is beneficial to reduce the number of prefetch parameter combinations that need to be processed in the optimization process, save resources and improve efficiency. The value of T can be flexibly set according to the accuracy requirement of the optimization process. See Figure 2c As shown in FIG. 13, a method of optimizing the prefetch parameter combination in a plurality of parameter spaces according to a performance distribution model to obtain a target prefetch parameter combination includes: for any parameter space, optimizing the prefetch parameter combination in the parameter space for T rounds according to the performance distribution model to obtain T kinds of prefetch parameter combinations and T target performance data generated by the target processor running the target application using the T kinds of prefetch parameter combinations; and selecting the target prefetch parameter combination from the T kinds of prefetch parameter combinations according to the T target performance data. The performance distribution model can be updated according to the prefetch parameter combination and the target performance data obtained after each round of optimization, so that the performance distribution model is continuously updated in the T rounds of optimization. In the optimization process, the quality of the prefetch parameter combination selected based on the performance distribution model can be improved through continuous updating of the performance distribution model.

[0066] Alternatively, see Figure 2cFor any round of optimization processing, an acquisition function can be used to sample, in combination with the performance distribution model of the last round, the prefetch parameter combinations in the parameter space to obtain the prefetch parameter combinations of the current round; the target processor can be controlled to run the target application according to the prefetch parameter combinations of the current round to obtain the target performance data of the current round, specifically, each value in the prefetch parameter combinations of the current round is configured as the value of the corresponding prefetch register in the target processor, and the target processor is controlled to run the target application, and the prefetch operation is performed according to the values of the plurality of prefetch registers (i.e., the prefetch parameter combinations of the current round) in the process of running the target application, and then the performance data brought by the prefetch operation to the target application is obtained as the target performance data of the current round; then, the performance distribution model of the last round is updated according to the prefetch parameter combinations of the current round and the target performance data of the current round to obtain the performance distribution model of the current round. For the first round of optimization processing, the acquisition function is used to sample, in combination with the initial performance distribution model created for the target application, the prefetch parameter combinations in the parameter space to obtain the prefetch parameter combinations of the current round; the prefetch parameter combinations of the current round are configured to the plurality of prefetch registers of the target processor, and the target processor is controlled to run the target application based on the values in the plurality of prefetch registers to obtain the target performance data of the current round; the performance distribution model created for the target application is updated according to the prefetch parameter combinations of the current round and the target performance data of the current round to obtain the performance distribution model of the current round. After obtaining the performance distribution model of the current round, it further includes adding 1 to the iteration round, and judging whether the iteration round has reached T times, if not, the next round of iteration is continued; if T times are reached, the iteration process is ended.

[0067] In the sampling function, exploitation and exploration are balanced in the selection process. The sampling function can balance exploitation and exploration based on the mean and variance of the performance distribution model to find the sampling point (i.e., the prefetch parameter combination) for the next round of optimization processing. Exploitation means that, based on the performance distribution information, more prefetch parameter combinations are sampled as close as possible to the currently known prefetch parameter combination. Sampling in the area with a higher mean in the performance distribution information can obtain a local optimal solution, i.e., a prefetch parameter combination with optimal performance data. Exploration means that more unknown prefetch parameter combinations are obtained, such as sampling in the area with a higher variance in the performance distribution information, which is more likely to find a prefetch parameter combination with globally optimal performance data. The sampling function can include but is not limited to Upper Confidence Bound (UCB), Expected Improvement (EI), and Probability of Improvement (PI) models.

[0068] Further optionally, for any round of optimization processing, the performance distribution information that the prefetch parameter combination of the current round needs to meet is obtained in combination with the performance distribution model of the last round. For example, according to the prefetch parameter combination and the corresponding performance data of the last round, the given variance of the performance distribution model of the last round, and the kernel function, the performance distribution information that the prefetch parameter combination of the current round needs to meet can be obtained. The performance distribution information can be represented by the variance and mean of the performance distribution model of the last round. According to the sampling function and the performance distribution information, a group of prefetch parameter combinations with performance loss satisfying a preset condition are selected as the prefetch parameter combination of the current round. The sampling function can determine multiple candidate prefetch parameter combinations according to the performance distribution information and estimate the performance loss of the multiple candidate prefetch parameter combinations. The preset condition is not limited, for example, the prefetch parameter combination with the minimum performance loss can be selected as the prefetch parameter combination of the current round; for another example, the candidate prefetch parameter combination with a performance loss less than a first performance loss threshold can be determined, and a prefetch parameter combination is randomly selected from the candidate prefetch parameter combination with a performance loss less than the first performance loss threshold as the prefetch parameter combination of the current round.

[0069] Optionally, the implementation of selecting the target prefetch parameter combination from the T prefetch parameter combinations according to the T target performance data is not limited. For example, according to the T target performance data corresponding to the T prefetch parameter combinations obtained by optimization, a prefetch parameter combination with optimal target performance data is selected from the T prefetch parameter combinations as the target prefetch parameter combination. For another example, according to the T target performance data corresponding to the T prefetch parameter combinations obtained by optimization, a preliminary selected prefetch parameter combination with a performance loss less than a set second performance loss threshold is determined from the T prefetch parameter combinations, and a prefetch parameter combination is randomly selected from the preliminary selected prefetch parameter combination as the target prefetch parameter combination. For another example, according to the T target performance data corresponding to the T prefetch parameter combinations obtained by optimization, a prefetch parameter combination with target performance data within a set range interval is selected from the T prefetch parameter combinations as the target prefetch parameter combination. For another example, according to the T target performance data corresponding to the T prefetch parameter combinations obtained by optimization, a prefetch parameter combination with target performance data greater than a set performance threshold is selected from the T prefetch parameter combinations as the target prefetch parameter combination.

[0070] After obtaining the target prefetch parameter combination, the values of the plurality of prefetch registers can be configured according to the target prefetch parameter combination, so that the target processor can perform prefetch operations according to the target prefetch parameter combination during the running of the target application. Specifically, each value in the target prefetch parameter combination is configured as the value of the corresponding prefetch register in the plurality of prefetch registers, so that the target processor can perform prefetch operations according to the values of the prefetch registers and according to the target prefetch parameter combination corresponding to the values during the running of the target application.

[0071] In this embodiment, the performance distribution of the target application when actually running under various prefetch parameter combinations is reflected by the performance distribution model, and the optimization of the prefetch parameter combination in the plurality of parameter spaces is performed to obtain the optimized partial prefetch parameter combination. Instead of directly expressing the complex function relationship between the prefetch parameter combination and the performance data, the performance distribution is used, which has the advantages of simple implementation and high efficiency. Furthermore, the actual running environment is used, that is, the selected partial prefetch parameter combination is actually run by the target processor to obtain the target performance data corresponding to the target application. The actual running environment can be the actual production environment of the target application or a test environment built for prefetch parameter tuning, which is not limited. Compared with the above-mentioned way of running each prefetch parameter combination, the method provided in this embodiment only needs to actually run a small part of the optimized prefetch parameter combinations, has high efficiency, can quickly select a prefetch parameter combination with better performance from the small part of the optimized prefetch parameter combinations, and can be used in the online application in time. Moreover, the target application can have good cache prefetch performance in the initial stage of going online, and the prefetch parameter combination can be continuously updated offline to continuously optimize the performance data of the target application.

[0072] In an optional embodiment, considering Figure 1b The performance of the A / B / C three-part prefetch register in the flow of L1-L2-LLC-Memory affects each other, and the performance is continuous, so the objective function can be considered as continuous differentiable. Based on this, in this embodiment, any optimization algorithm that can realize the prefetch parameter configuration method is suitable for the present application. The following provides an example of an optimization algorithm: a method for searching for a CPU cache prefetch parameter combination in a parameter space for a target application is designed based on a sequential model-based global optimization (SMBO) algorithm, which is called an optimized SMBO (OSMBO) algorithm.

[0073] Principle of OSMBO algorithm: the parameters (f, M, T, S) involved in the OSMBO algorithm, f represents the objective function, M is the performance distribution model created by the target application, T represents the maximum number of iterations, the real-time iteration number is represented by t, S is the sampling function, H[n]=(x 1：k , f(x 1：k )) is the performance data of the target application, and x is the prefetch parameter combination.

[0074] Step 1: group the multiple prefetch parameter combinations according to the number N of the multiple prefetch algorithms supported by the target processor, obtain N parameter spaces, and search for the optimal prefetch parameter combination in each parameter space.

[0075] Step 2: for each parameter space, update the performance distribution model M according to the performance data function H[n]=(x 1：k , f(x 1：k )) of the target application that has been obtained so far; at this time, the performance data of k prefetch parameter combinations is recorded in H[n].

[0076] Step 3: determine the next prefetch parameter combination x k+1 by the sampling function S and the updated performance distribution model M;

[0077] Step 4: use the objective function to obtain the performance data f(x k+1 ) of the new prefetch parameter combination x k+1 , and add the performance data (x k+1 , f(x k+1 )) of the new prefetch parameter combination to H[n];

[0078] Step 5: repeat steps 2-4 until the real-time iteration number t of each parameter space reaches T;

[0079] Step 6: After the iteration of all parameter spaces is completed, the optimal prefetch parameter combination is selected from the selected prefetch parameter combinations in the iteration process as the target prefetch parameter combination and is output.

[0080] Step 7: The values of the corresponding prefetch registers of the target processor are configured according to the target prefetch parameter combination, so that the processor performs the prefetch operation according to the values of the plurality of prefetch registers.

[0081] In the embodiment, the prefetch parameter configuration can be personalized for the target application, the performance problem of a single application can be well solved, and the negative influence of other software and hardware caused by the prefetch parameter configuration for the target application is more controllable. In addition, in the prefetch parameter configuration process for the target application, the OSMBO algorithm is used for tuning, and the prefetch parameter combinations are grouped, so that the dimension of the parameter search space can be reduced, for example, from 35 dimensions to 20 dimensions or less, the search complexity and search cost are reduced, and the effect is better and the automation degree is higher compared with the traditional manual experience tuning method, and the cost can be saved.

[0082] In addition to the method shown in the above embodiments, the application also provides a cache prefetch method. Figure 2a In addition to the method shown in the above embodiments, the application also provides a cache prefetch method.

[0083] As shown in the above embodiments, the method comprises the following steps. Figure 3

[0084] 301, read the values of the plurality of hardware modules, and the combination of the values of the plurality of hardware modules forms a target prefetch parameter combination for prefetch control;

[0085] 302, in the process of running the target application, performing a prefetch operation based on the target prefetch parameter combination.

[0086] The plurality of hardware modules can be implemented as prefetch registers, and in the following description of the embodiment, the prefetch registers will be described as an example, but are not limited to the prefetch registers, and can also be other hardware structures.

[0087] ​The pre-fetch parameter configuration method provided in the embodiments of the present application can obtain a target pre-fetch parameter combination for pre-fetch control, and configure corresponding pre-fetch register values of a target processor based on the target pre-fetch parameter combination. In the cache pre-fetch process, the target processor reads the values of a plurality of pre-fetch registers included in the target processor. In the process of running the target application, data pre-fetch operations can be performed based on the target pre-fetch parameter combination, or instruction pre-fetch operations can be performed based on the target pre-fetch parameter combination, or both data pre-fetch operations and instruction pre-fetch operations can be performed based on the target pre-fetch parameter combination.

[0088] In an optional embodiment, the target pre-fetch parameter combination includes a set of values corresponding to the pre-fetch algorithm selection parameter and the pre-fetch operation execution control parameter; the target processor includes a plurality of pre-fetchers for performing data and / or instruction pre-fetching, and the pre-fetchers are configured to perform pre-fetch operations, which can be specifically referred to the foregoing. Based on this, an embodiment of performing data and / or instruction pre-fetch operations based on the target pre-fetch parameter combination during the process of running the target application includes: during the process of running the target application, selecting a target pre-fetcher from the plurality of pre-fetchers supported by the target processor according to the value of the pre-fetch algorithm selection parameter; and controlling the target pre-fetcher to perform data pre-fetch operations or instruction pre-fetch operations, or controlling the target pre-fetcher to perform both data pre-fetch operations and instruction pre-fetch operations according to the value of the pre-fetch operation execution control parameter.

[0089] Optionally, the pre-fetch operation execution control parameters comprise at least: a pre-fetch time control parameter, a pre-fetch data amount control parameter, a pre-fetch location control parameter, and a storage location control parameter. The pre-fetch time control parameter can be how long in advance the data needs to be pre-fetched for the task to be executed, for example, it can be 1 ms or 1 um, etc.; the pre-fetch data amount control parameter can include but is not limited to: the pre-fetch data amount of the L1 cache, the pre-fetch data amount of the L2 cache, the pre-fetch data amount of the LLC, and the cache data amount of the memory, etc.; the pre-fetch location control parameter refers to which storage location to obtain the data from, for example, a hard disk or a magnetic disk, etc.; the storage location control parameter can include but is not limited to: the L1 cache, the L2 cache, the LLC, and the memory, etc. One embodiment of controlling the target pre-fetcher to execute the data and / or instruction pre-fetch operation according to the pre-fetch operation execution control parameters comprises: according to the pre-fetch time control parameter and the pre-fetch data amount control parameter, controlling the target pre-fetcher to read the data from a first storage location pointed to by the pre-fetch location control parameter, and write the read data into a second storage location pointed to by the storage location control parameter. The read / write speed of the second storage location is greater than that of the first storage location; for example, the first storage location can be the L1 cache, and the second storage location can be the L2 cache; for another example, the first storage location can be the L2 cache, and the second storage location can be the LLC cache. Alternatively, according to the pre-fetch time control parameter and the pre-fetch data amount control parameter, the target pre-fetcher reads the instruction from the first storage location pointed to by the pre-fetch location control parameter, and writes the read instruction into the second storage location pointed to by the storage location control parameter. Alternatively, according to the pre-fetch time control parameter and the pre-fetch data amount control parameter, the target pre-fetcher reads the data and the instruction from the first storage location pointed to by the pre-fetch location control parameter, and writes the read data and the instruction into the second storage location pointed to by the storage location control parameter.

[0090] It is explained that, according to the different pre-fetchers supported by the target processor, the pre-fetch process and the pre-fetch operation control parameters required in the pre-fetch process will also be different, and accordingly, the process of executing the pre-fetch operation according to the values of the plurality of pre-fetch registers will also be different, which is easy to be thought and flexibly implemented by those skilled in the art on the basis of the disclosed content of the embodiments, therefore, any scheme capable of performing the pre-fetch control of the pre-fetcher in the target processor through the values of the plurality of pre-fetch registers by configuring the values of the plurality of pre-fetch registers is within the protection scope of the embodiments.

[0091] It is to be noted that the execution subject of each step of the method provided in the above embodiments can be the same device, or the method can also be executed by different devices as the execution subject. For example, the execution subject of steps 101 to 103 can be device A; for another example, the execution subject of steps 101 and 102 can be device A, and the execution subject of step 103 can be device B; etc.

[0092] In addition, in some of the processes described in the above embodiments and the accompanying drawings, a plurality of operations are included in a specific order, but it should be clear that these operations can be executed in the order in which they appear in this document or in parallel, and the serial numbers of the operations, such as 101, 102, etc., are only used to distinguish different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes can include more or fewer operations, and these operations can be executed in sequence or in parallel. It should be noted that the "first", "second", etc. described herein are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do "first" and "second" represent different types.

[0093] Figure 4 A structure diagram of a pre-fetch parameter configuration device provided for an example embodiment of the present application is shown in FIG. 1, which includes a determination module 41, a grouping module 43, an optimization module 44, and a configuration module 45. Figure 4

[0094] The determination module 41 is configured to determine a target application and a target processor responsible for running the target application, the target processor including a plurality of hardware modules for pre-fetch control, and the value combinations between the plurality of hardware modules forming a plurality of pre-fetch parameter combinations.

[0095] The grouping module 43 is configured to group the plurality of pre-fetch parameter combinations according to the number of pre-fetch algorithms supported by the target processor, to obtain a plurality of parameter spaces.

[0096] The optimization module 44 is configured to perform optimization processing of the pre-fetch parameter combinations on the plurality of parameter spaces according to a performance distribution model of the target application, to obtain a target pre-fetch parameter combination.

[0097] The configuration module 45 is configured to configure the values of the plurality of hardware modules according to the target pre-fetch parameter combination, so that the target processor performs a pre-fetch operation according to the target pre-fetch parameter combination.

[0098] In an optional embodiment, different hardware modules in the plurality of hardware modules represent different pre-fetch parameters, and the plurality of hardware modules include a hardware module representing a pre-fetch algorithm selection parameter and a hardware module representing a pre-fetch operation execution control parameter; wherein a pre-fetch parameter has at least two hardware module values, and the different hardware module values are mutually exclusive; and a pre-fetch parameter combination includes a pre-fetch algorithm selection parameter and a pre-fetch operation execution control parameter.

[0099] ​In an optional embodiment, the determining module 41 is specifically configured to: receive a pre-fetch parameter configuration task, the pre-fetch parameter configuration task including description information of the target application and description information of the target processor; determine the target application and the target processor according to the description information of the target application and the description information of the target processor respectively; or display a task configuration interface, the task configuration interface including an application configuration option and a processor configuration option; and determine the target application and the target processor in response to a configuration operation on the application configuration option and the processor configuration option.

[0100] In an optional embodiment, as shown in Figure 4 the apparatus further includes a constructing module 42 configured to construct a performance distribution model for the target application, the performance distribution model being used to reflect a performance distribution of the target application when actually running under various pre-fetch parameter combinations.

[0101] Further, the constructing module 42 is specifically configured to: perform initial sampling on the plurality of pre-fetch parameter combinations to obtain at least one initial pre-fetch parameter combination; control the target processor to run the target application based on the at least one initial pre-fetch parameter combination to obtain at least one initial performance data; and construct a distribution function of performance data of the target application with respect to the pre-fetch parameter combination as the performance distribution model according to the at least one initial pre-fetch parameter combination and the at least one initial performance data.

[0102] In an optional embodiment, the grouping module 43 is specifically configured to: for any pre-fetch algorithm, determine a first group of hardware modules that will affect the pre-fetch algorithm and a second group of hardware modules that will not affect the pre-fetch algorithm in the plurality of hardware modules; and select, from the plurality of pre-fetch parameter combinations, a part of pre-fetch parameter combinations in which the values of the first group of hardware modules are effective and the values of the second group of hardware modules are ineffective, as a parameter space corresponding to the pre-fetch algorithm.

[0103] In an optional embodiment, the optimizing module 44 is specifically configured to: for any parameter space, perform T rounds of optimization processing on the pre-fetch parameter combinations in the parameter space according to the performance distribution model to obtain T pre-fetch parameter combinations and T target performance data generated by the target processor running the target application using the T pre-fetch parameter combinations; and select a target pre-fetch parameter combination from the T pre-fetch parameter combinations according to the T target performance data; wherein the performance distribution model is continuously updated in the T rounds of optimization processing, T is a positive integer, and T is less than the number of pre-fetch parameter combinations in the parameter space.

[0104] Optionally, the optimization module 44 is specifically configured to: for any round of optimization processing, using a sampling function, in combination with a performance distribution model of a previous round, sampling a prefetch parameter combination in the parameter space in the current round to obtain a prefetch parameter combination in the current round; controlling the target processor to run the target application based on the prefetch parameter combination in the current round to obtain target performance data in the current round; and updating the performance distribution model of the previous round according to the prefetch parameter combination in the current round and the target performance data in the current round to obtain a performance distribution model in the current round.

[0105] Further optionally, the optimization module 44 is specifically configured to: for any round of optimization processing, in combination with a performance distribution model of a previous round, obtaining performance distribution information that needs to be met by a prefetch parameter combination in the current round; and according to the sampling function and the performance distribution information, selecting a group of prefetch parameter combinations that meet a preset condition in performance loss as the prefetch parameter combination in the current round.

[0106] In an optional embodiment, the target application is carried in a virtualized instance, and the virtualized instance exclusively occupies the target processor.

[0107] Figure 5 A structural schematic diagram of a cache prefetching device provided by an exemplary embodiment of the present application is provided, which can be applied to a target processor responsible for running a target application, and the target processor includes a plurality of hardware modules for prefetching control, and values of the plurality of hardware modules are configured according to a prefetch parameter configuration method provided by the present application. As shown in the figure, the device includes a reading module 51 and a prefetching module 52. Figure 5 The reading module 51 is configured to read values of the plurality of hardware modules, and a combination of the values of the plurality of hardware modules forms a target prefetch parameter combination for prefetching control.

[0108] The reading module 51 is configured to read values of the plurality of hardware modules, and a combination of the values of the plurality of hardware modules forms a target prefetch parameter combination for prefetching control.

[0109] The prefetching module 52 is configured to perform a prefetching operation based on the target prefetch parameter combination in a process of running the target application.

[0110] In an optional embodiment, the target prefetch parameter combination includes a prefetch algorithm selection parameter and a prefetch operation execution control parameter; and the prefetching module is specifically configured to: in the process of running the target application, according to a value of the prefetch algorithm selection parameter, selecting a target prefetcher from a plurality of prefetchers supported by the target processor; and according to a value of the prefetch operation execution control parameter, controlling the target prefetcher to perform the prefetching operation.

[0111] Optionally, the pre-fetch operation execution control parameter comprises at least: a pre-fetch time control parameter, a pre-fetch data volume control parameter, a pre-fetch location control parameter and a storage location control parameter; and the pre-fetch module is specifically configured to: according to the pre-fetch time control parameter and the pre-fetch data volume control parameter, control the target pre-fetcher to read data and / or instructions from a first storage location pointed to by the pre-fetch location control parameter, and write the read data and / or instructions to a second storage location pointed to by the storage location control parameter; and wherein the read / write speed of the second storage location is greater than that of the first storage location.

[0112] With regard to the embodiments provided by the present application Figures 4-5 The detailed implementation and beneficial effects of each step of the device are described in detail in the foregoing embodiments, and will not be described in detail here.

[0113] Figure 6 A structural schematic diagram of an electronic device is provided for the exemplary embodiments of the present application. As shown in the figure, Figure 6 The device includes a memory 64 and a processor 65.

[0114] The memory 64 is used to store computer programs and can be configured to store various other data to support operations on the electronic device. Examples of these data include instructions for any application or method operating on the electronic device.

[0115] The memory 64 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0116] The processor 65 is coupled to the memory 64 and is used to execute the computer programs in the memory 64, for: determining a target application and a target processor responsible for running the target application, the target processor including a plurality of hardware modules for pre-fetch control, and the value combinations between the plurality of hardware modules forming a plurality of pre-fetch parameter combinations; grouping the plurality of pre-fetch parameter combinations according to the number of a plurality of pre-fetch algorithms supported by the target processor, to obtain a plurality of parameter spaces; performing optimization processing of the pre-fetch parameter combinations on the plurality of parameter spaces according to a performance distribution model of the target application, to obtain a target pre-fetch parameter combination; and configuring the values of the plurality of hardware modules according to the target pre-fetch parameter combination, so that the target processor performs a pre-fetch operation according to the target pre-fetch parameter combination.

[0117] In an optional embodiment, different hardware modules in the plurality of hardware modules represent different prefetch parameters, the plurality of hardware modules comprising a hardware module representing a prefetch algorithm selection parameter and a hardware module representing a prefetch operation execution control parameter; wherein one prefetch parameter has at least two hardware module values, and the different hardware module values are mutually exclusive; and one prefetch parameter combination comprises the prefetch algorithm selection parameter and the prefetch operation execution control parameter.

[0118] In an optional embodiment, the processor 65, when determining the target application carried in the virtualization instance and the target processor responsible for running the target application, is specifically configured to: receive a prefetch parameter configuration task, the prefetch parameter configuration task comprising description information of the target application and description information of the target processor; determine the target application and the target processor according to the description information of the target application and the description information of the target processor, respectively; or display a task configuration interface, the task configuration interface comprising an application configuration option and a processor configuration option; and determine the target application and the target processor in response to a configuration operation on the application configuration option and the processor configuration option.

[0119] In an optional embodiment, the processor 65, when constructing a performance distribution model for the target application, is specifically configured to: perform initial sampling on a plurality of prefetch parameter combinations to obtain at least one initial prefetch parameter combination; control the target processor to run the target application based on the at least one initial prefetch parameter combination to obtain at least one initial performance data; and construct a distribution function of performance data of the target application with respect to the prefetch parameter combination as the performance distribution model according to the at least one initial prefetch parameter combination and the at least one initial performance data.

[0120] In an optional embodiment, the processor 65, when grouping a plurality of prefetch parameter combinations according to the number of a plurality of prefetch algorithms supported by the target processor to obtain a plurality of parameter spaces, is specifically configured to: for any one prefetch algorithm, determine a first group of hardware modules that will affect the prefetch algorithm and a second group of hardware modules that will not affect the prefetch algorithm in the plurality of hardware modules; and select, from the plurality of prefetch parameter combinations, a part of prefetch parameter combinations in which the values of the first group of hardware modules are valid and the values of the second group of hardware modules are invalid, as a parameter space corresponding to the prefetch algorithm.

[0121] In an optional embodiment, when the processor 65 performs the optimization processing on the plurality of parameter spaces according to the performance distribution model to obtain the target prefetch parameter combination, specifically, for any parameter space, the processor 65 performs T rounds of optimization processing on the prefetch parameter combinations in the parameter space according to the performance distribution model to obtain T kinds of prefetch parameter combinations and T pieces of target performance data generated by the target processor running the target application using the T kinds of prefetch parameter combinations; and the processor 65 selects the target prefetch parameter combination from the T kinds of prefetch parameter combinations according to the T pieces of target performance data; wherein the performance distribution model is updated in the T rounds of optimization processing, T is a positive integer, and T is less than the number of prefetch parameter combinations in the parameter space.

[0122] Optionally, when the processor 65 performs T rounds of iterative optimization processing on the prefetch parameter combinations in the parameter space according to the performance distribution model to obtain T kinds of prefetch parameter combinations and T pieces of target performance data generated by the target processor running the target application using the T kinds of prefetch parameter combinations, specifically, for any round of optimization processing, the processor 65 uses a sampling function to sample the prefetch parameter combinations in the parameter space in the current round in combination with the performance distribution model of the last round to obtain the prefetch parameter combinations in the current round; the processor 65 controls the target processor to run the target application based on the prefetch parameter combinations in the current round to obtain the target performance data in the current round; and the processor 65 updates the performance distribution model of the last round according to the prefetch parameter combinations in the current round and the target performance data in the current round to obtain the performance distribution model in the current round.

[0123] Further optionally, when the processor 65 uses a sampling function to sample the prefetch parameter combinations in the parameter space in the current round in combination with the performance distribution model of the last round to obtain the prefetch parameter combinations in the current round for any round of optimization processing, specifically, for any round of optimization processing, the processor 65 obtains the performance distribution information that needs to be met by the prefetch parameter combinations in the current round in combination with the performance distribution model of the last round; and the processor 65 selects a group of prefetch parameter combinations that meet a preset condition in performance loss from the performance distribution information as the prefetch parameter combinations in the current round according to the sampling function and the performance distribution information.

[0124] In an optional embodiment, the target application is carried in a virtualized instance, and the virtualized instance exclusively occupies the target processor.

[0125] The detailed implementation and beneficial effects of each step of the device shown in the embodiments provided by the present application have been described in detail in the foregoing embodiments, and will not be described in detail here. Figure 6 The detailed implementation and beneficial effects of each step of the device shown in the embodiments provided by the present application have been described in detail in the foregoing embodiments, and will not be described in detail here.

[0126] Further, as shown in the device shown in the embodiments provided by the present application, Figure 6 The electronic device further includes a communication component 66, a display 67, a power supply component 68, an audio component 69, and other components. Figure 6The diagram only shows some components and does not mean that the electronic device includes only these components. Figure 6 The components shown. Additionally... Figure 6 The components within the dashed box are optional, not mandatory, and their specific requirements depend on the product form of the electronic device. The electronic device in this embodiment can be a terminal device such as a desktop computer, laptop computer, smartphone, or IoT device, or a server-side device such as a conventional server, cloud server, or server array. If the electronic device in this embodiment is a terminal device such as a desktop computer, laptop computer, or smartphone, it may include... Figure 6 The components within the dashed box; if the electronic device in this embodiment is implemented as a conventional server, cloud server, or server array, etc., it may be omitted. Figure 6 The component within the dashed box.

[0127] This application embodiment also provides a processor responsible for running a target application. The processor includes: multiple hardware modules for prefetch control, the values ​​of the multiple hardware modules being configured according to the prefetch parameter configuration method provided in this application embodiment. The processor is used to: read the values ​​of the multiple hardware modules, combine the values ​​of the multiple hardware modules to form a target prefetch parameter combination for prefetch control; and perform a prefetch operation based on the target prefetch parameter combination during the running of the target application.

[0128] In an optional embodiment, the target prefetch parameter combination includes: prefetch algorithm selection parameters and prefetch operation execution control parameters; when the processor performs a prefetch operation based on the target prefetch parameter combination during the execution of the target application, it is specifically used to: select a target prefetcher from a variety of prefetchers supported by the target processor according to the value of the prefetch algorithm selection parameters during the execution of the target application; and control the target prefetcher to perform a prefetch operation according to the value of the prefetch operation execution control parameters.

[0129] Optionally, the prefetch operation execution control parameters include at least: prefetch time control parameters, prefetch data volume control parameters, prefetch location control parameters, and storage location control parameters; when the processor controls the target prefetcher to perform a prefetch operation according to the prefetch operation execution control parameters, it is specifically used to: control the target prefetcher to read data and / or instructions from the first storage location pointed to by the prefetch location control parameters according to the prefetch time control parameters and the prefetch data volume control parameters, and write the read data and / or instructions to the second storage location pointed to by the storage location control parameters; wherein, the read / write speed of the second storage location is greater than the read / write speed of the first storage location.

[0130] Accordingly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed, can perform the above-described functions. Figure 2a and Figure 3The steps in the illustrated method embodiment.

[0131] The memory described above can be implemented by any type of volatile or nonvolatile storage devices or a combination thereof, such as Static Random-Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic or optical disk.

[0132] The communication component described above is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as a WiFi, 2G, 3G, 4G / LTE, 5G, or other mobile communication network, or a combination thereof. In an example embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication component further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Blue Tooth (BT) technology, and other technologies.

[0133] The display described above includes a screen, which can include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensor can not only sense a boundary of a touch or a slide action, but also detect a duration and a pressure associated with a touch or a slide operation.

[0134] The power component provides power to various components of the device in which the power component is located. The power component can include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power to the device in which the power component is located.

[0135] The audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC) that is configured to receive an external audio signal when the device in which the audio component is located is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in a memory or transmitted via the communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.

[0136] Those skilled in the art will understand that embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-readable storage media (including, but not limited to, disk memory, Compact Disc Read-Only Memory (CD-ROM), optical memory, and the like) embodying computer usable program code.

[0137] The present application is described in reference to the flowchart illustrations and / or block diagrams according to the embodiments of the application. It should be understood that each flow and / or block in the flowchart illustrations and / or block diagrams, and a combination of flows and / or blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, a special purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams one or more flows and / or blocks in the flowchart illustrations and / or block diagrams.

[0138] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means that implement the function specified in the flowchart illustrations and / or block diagrams one or more flows and / or blocks in the flowchart illustrations and / or block diagrams.

[0139] These computer program instructions can also be loaded into a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart and / or block diagram block or blocks.

[0140] In one typical arrangement, the computing device includes one or more processors (Central Processing Units, CPUs), input / output interfaces, network interfaces, and memory.

[0141] The memory can include non-persistent memory and / or volatile memory, such as random access memory (RAM) and / or cache memory, and / or non-volatile memory, such as read-only memory (ROM), EPROM, and / or flash memory. The memory is an example of computer readable media.

[0142] Computer readable media includes permanent and non-permanent, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital video disc (DVD), or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer readable media does not include transitory media, such as modulated data signals and carrier waves.

[0143] It should also be noted that the terms "comprising", "comprises" or other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0144] The above embodiments are only used to illustrate the present application, but not to limit it. Instead of the above, various modifications and changes can be made to the application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall fall into the scope of the claims of the application.

Claims

1. A method for configuring prefetch parameters, characterized in that, include: The target application and the target processor responsible for running the target application are determined. The target processor includes multiple hardware modules for prefetch control, and the value combinations among the multiple hardware modules form multiple prefetch parameter combinations. Based on the number of prefetching algorithms supported by the target processor, the various prefetching parameter combinations are grouped to obtain multiple parameter spaces; one prefetching algorithm corresponds to one parameter space, and the parameter space includes a portion of prefetching parameter combinations where the values ​​of the first group of hardware modules are valid and the values ​​of the second group of hardware modules are invalid, where the first group of hardware modules and the second group of hardware modules are hardware modules that affect and do not affect the prefetching algorithm, respectively. Based on the performance distribution model of the target application, the multiple parameter spaces are optimized by prefetching parameter combinations to obtain the target prefetched parameter combination; The values ​​of the plurality of hardware modules are configured according to the target prefetch parameter combination, so that the target processor performs a prefetch operation according to the target prefetch parameter combination.

2. The method according to claim 1, characterized in that, Different hardware modules in the plurality of hardware modules represent different prefetch parameters. The plurality of hardware modules include hardware modules representing prefetch algorithm selection parameters and hardware modules representing prefetch operation execution control parameters. One of the prefetch parameters has at least two possible values, and the different values ​​are mutually exclusive; a combination of prefetch parameters includes prefetch algorithm selection parameters and prefetch operation execution control parameters.

3. The method according to claim 1, characterized in that, Identifying the target application and the target processor responsible for running the target application includes: Receive a prefetch parameter configuration task, the prefetch parameter configuration task including description information of the target application and description information of the target processor; determine the target application and the target processor respectively based on the description information of the target application and the description information of the target processor; or Display a task configuration interface, which includes application configuration options and processor configuration options; respond to configuration operations on the application configuration options and processor configuration options, and determine the target application and target processor.

4. The method according to claim 1, characterized in that, Also includes: Initial sampling is performed on the multiple prefetch parameter combinations to obtain at least one initial prefetch parameter combination; The target processor is controlled to run the target application based on the at least one initial prefetch parameter combination to obtain at least one initial performance data. Based on the at least one initial prefetch parameter combination and the at least one initial performance data, a distribution function characterizing the performance data of the target application with respect to the prefetch parameter combination is constructed as the performance distribution model.

5. The method according to claim 1, characterized in that, Based on the number of prefetch algorithms supported by the target processor, the various prefetch parameters are grouped to obtain multiple parameter spaces, including: For any prefetch algorithm, determine the first group of hardware modules that will affect the prefetch algorithm and the second group of hardware modules that will not affect the prefetch algorithm from among the plurality of hardware modules; From the various prefetch parameter combinations, select the partial prefetch parameter combinations where the values ​​of the first group of hardware modules are valid and the values ​​of the second group of hardware modules are invalid, and use these combinations as the parameter space corresponding to the prefetch algorithm.

6. The method according to claim 1, characterized in that, Based on the performance distribution model of the target application, the multiple parameter spaces are optimized by prefetching parameter combinations to obtain the target prefetched parameter combination, including: For any parameter space, according to the performance distribution model, the prefetched parameter combinations in the parameter space are optimized in T rounds to obtain T prefetched parameter combinations and T target performance data generated by the target processor running the target application using the T prefetched parameter combinations; Based on the T target performance data, a target prefetch parameter combination is selected from the T prefetch parameter combinations; wherein, the performance distribution model is continuously updated in T rounds of optimization processing, T is a positive integer, and T is less than the number of prefetch parameter combinations in the parameter space.

7. The method according to claim 6, characterized in that, Based on the performance distribution model, T rounds of iterative optimization are performed on the prefetched parameter combinations in the parameter space to obtain T prefetched parameter combinations and T target performance data generated by the target processor running the target application using the T prefetched parameter combinations, including: For any round of optimization, a sampling function is used, combined with the performance distribution model of the previous round, to sample the pre-fetched parameter combination in the parameter space for this round, thus obtaining the pre-fetched parameter combination for this round. Based on the prefetched parameter combination of this round, the target processor is controlled to run the target application in order to obtain the target performance data of this round; Based on the pre-fetched parameter combination and the target performance data of this round, the performance distribution model of the previous round is updated to obtain the performance distribution model of this round.

8. The method according to claim 7, characterized in that, For any round of optimization, a sampling function is used, combined with the performance distribution model of the previous round, to sample the prefetched parameter combinations in the parameter space for this round, resulting in the prefetched parameter combinations for this round, including: For any round of optimization, the performance distribution information that the pre-fetched parameter combination needs to satisfy is obtained by combining the performance distribution model of the previous round. Based on the sampling function and the performance distribution information, a set of prefetched parameter combinations that satisfy preset conditions for performance loss is selected as the prefetched parameter combination for this round.

9. The method according to any one of claims 1-8, characterized in that, The target application is hosted in a virtualized instance, and the virtualized instance exclusively uses the target processor.

10. A cache prefetching method, characterized in that, A target processor for running a target application, the target processor including multiple hardware modules for prefetch control, the values ​​of the multiple hardware modules being configured according to the method according to any one of claims 1-9; the method including: The values ​​of the plurality of hardware modules are read, and the values ​​of the plurality of hardware modules are combined to form a target prefetch parameter combination for prefetch control; During the execution of the target application, a prefetch operation is performed based on the target prefetch parameter combination.

11. The method according to claim 10, characterized in that, The target prefetch parameter combination includes: prefetch algorithm selection parameters and prefetch operation execution control parameters; During the execution of the target application, a prefetching operation is performed based on the target prefetching parameter combination, including: During the execution of the target application, the target prefetcher is selected from a variety of prefetchers supported by the target processor based on the value of the prefetch algorithm selection parameter. The target prefetcher is controlled to perform a prefetch operation based on the value of the prefetch operation execution control parameter.

12. The method according to claim 11, characterized in that, The prefetch operation execution control parameters include at least: prefetch time control parameters, prefetch data volume control parameters, prefetch location control parameters, and storage location control parameters; Controlling the target prefetcher to perform a prefetch operation according to the prefetch operation execution control parameters includes: Based on the prefetch time control parameter and the prefetch data volume control parameter, the target prefetcher is controlled to read data and / or instructions from the first storage location pointed to by the prefetch location control parameter, and write the read data and / or instructions to the second storage location pointed to by the storage location control parameter; wherein, the read / write speed of the second storage location is greater than the read / write speed of the first storage location.

13. An electronic device, characterized in that, include: Memory and processor; The memory is used for a computer program; the processor, coupled to the memory, is used to execute the computer program to implement the steps of the method according to any one of claims 1-9.

14. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it causes the processor to perform the steps of the method according to any one of claims 1-9 and 10-12.

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