Multi-chip package link

Abstract

A system on chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. In one embodiment, p hard IP blocks are used, where each block provides n data paths, all h = n * p hard IP data paths are provided. Wherein the system design requires all k data paths, possibly k is not equal to h, so that the [k / n] hard IP block provides h = n * p available hard IP data paths. In this case, the h-k lanes may be disabled. In the event of a lane inversion, e.g., between a hard IP and a soft IP, bow-tie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

Description

[0001] This application is a divisional application of application number 202011344684.9 filed on February 22, 2016 and named 'Multi-chip package link'.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of and priority to U.S. Non-Provisional Patent Application No. 14 / 669,975, filed on March 26, 2015, and entitled “MULTICHIP PACKAGE LINK,” the entire contents of which are incorporated herein by reference. Technical Field

[0004] The present disclosure relates to computing systems and, in particular, but not exclusively, to point-to-point interconnects. Background Art

[0005] Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic that may be present on an integrated circuit device. As a corollary, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on separate integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically includes a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, etc.

[0006] Smaller computing devices are becoming more and more popular due to the greater ability to supply more processing power in a smaller package. Smart phones, tablet computers, ultra-thin notebook computers and other user devices have grown exponentially. However, these smaller devices rely on servers that are used for both data storage and complex processing that exceeds the form factor. Therefore, the demand for the high-performance computing market (i.e., server space) is still increasing. For example, in modern servers, there is usually not only a single processor with multiple cores, but also multiple physical processors (also referred to as multiple sockets) for increasing computing power. But when processing power increases with the increase in the number of devices in the computing system, the communication between the socket and other devices becomes more critical.

[0007] In fact, interconnects have evolved from more traditional multi-drop buses that primarily handled electrical communications to fully scaled interconnect architectures that facilitate fast communications. Unfortunately, as the demand for future processors to consume at even higher rates increases, the corresponding demand is within the capabilities of existing interconnect architectures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An embodiment of a computing system including an interconnect architecture is shown.

[0009] Figure 2 An embodiment of an interconnect architecture including a layered stack is shown.

[0010] Figure 3 Embodiments of requests or packets to be generated or received within an interconnect fabric are shown.

[0011] Figure 4 An embodiment of a transmitter and receiver pair for an interconnect architecture is shown.

[0012] Figure 5 An embodiment of a multi-chip package is shown.

[0013] Figure 6 is a simplified block diagram of a multi-chip package link (MCPL).

[0014] Figure 7 is a representation of exemplary signaling on an exemplary MCPL.

[0015] Figure 8 is a simplified block diagram showing the data path in an exemplary MCPL.

[0016] Fig. 9 is a simplified block diagram illustrating an exemplary crosstalk cancellation technique in an embodiment of MCPL.

[0017] Fig.10 is a simplified circuit diagram illustrating exemplary crosstalk cancellation components in an embodiment of the MCPL.

[0018] Fig.11 is a simplified block diagram of MCPL.

[0019] Fig.12 is a simplified block diagram of the MCPL using a logical PHY interface (LPIF) to interface with upper layer logic of multiple protocols.

[0020] Fig.13 is a representation of exemplary signaling on an exemplary MCPL associated with restoration of a link.

[0021] Figures 14A-14C is an exemplary bit map of data on the lanes of an exemplary MCPL.

[0022] Fig.15 is a representation of a portion of an exemplary link state machine.

[0023] Fig.16 is a representation of the process associated with exemplary centering of a link.

[0024] Fig.17 is a representation of an exemplary link state machine.

[0025] Fig.18 Is an indication of signaling used to enter a low power state.

[0026] Fig.19 An embodiment of a block diagram for a computing system including a multi-core processor is shown.

[0027] Fig. 20 Another embodiment of a block diagram for a computing system including a multi-core processor is shown.

[0028] Fig.21 An embodiment of a block diagram for a processor is shown.

[0029] Fig. 22 Another embodiment of a block diagram for a computing system including a processor is shown.

[0030] Fig.23 Embodiments of blocks are shown for a computing system including multiple processors.

[0031] Fig.24 An exemplary system implemented as a system on a chip (SoC) is shown.

[0032] Fig.25 An example of signal transmission in the embodiment is shown.

[0033] Fig.26 is an exemplary flow chart of a method for encoding data for which no explicit STREAM paths exist.

[0034] Fig. 27 is an example flow chart of a method for encoding data for which no explicit STREAM paths exist.

[0035] Fig.28 is an exemplary flow chart of a method for performing centering of a reference voltage.

[0036] Fig.29A and 29B is an example of a crosstalk pattern.

[0037] Fig.30 is an exemplary illustration of eye centering.

[0038] Fig.31 is an exemplary flow chart of a method for eye centering.

[0039] Fig.32 is an exemplary block diagram of a system including hard IP and soft IP.

[0040] Fig.33 is an exemplary block diagram of the interface between hard IP blocks and soft IP blocks.

[0041] Fig.34is an example of a system with a multiplexer-like programmable switch for handling path reversal.

[0042] Like reference numbers and numerals in the various drawings indicate like elements. DETAILED DESCRIPTION

[0043] In the following description, many specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / heights, specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details are not required for practicing the present invention. In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits / code for the described algorithms, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific computer system power-off and gate control techniques / logic, and other specific operational details of computer systems, are not described in detail to avoid unnecessarily obscuring the present invention.

[0044] Although the following embodiments may be described with reference to energy conservation and energy efficiency in a particular integrated circuit, such as a computing platform or microprocessor, other embodiments may be applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks. TM . They may also be used in other devices, such as handheld devices, tablet computers, other thin laptops, system-on-chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), system-on-chips, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. In addition, the apparatus, methods, and systems described herein are not limited to physical computing devices, but may also involve software optimization for energy conservation and efficiency. As will become apparent in the following description, embodiments of the methods, apparatus, and systems described herein (whether with reference to hardware, firmware, software, or a combination thereof) are critical to a "green technology" future balanced with performance considerations.

[0045] As computing systems advance, the components therein become more complex. As a result, the interconnect architectures that couple and communicate between components are also increasing in complexity to ensure that bandwidth requirements for optimal component operation are met. In addition, different market segments require different aspects of the interconnect architecture to adapt to the needs of the market. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance to save power. However, the single purpose of most architectures is to provide the highest possible performance with maximum power savings. A number of interconnects are discussed below that will likely benefit from the various aspects of the invention described herein.

[0046] An interconnect structure architecture includes a Peripheral Component Interconnect Express (PCI) (PCIe) architecture. The main goal of PCIe is to enable components and devices from different suppliers to interoperate in an open architecture and span multiple market areas; clients (desktop and mobile), servers (standard and enterprise), and embedded and communication devices. PCI Express (Peripheral Component Interconnect Express) is a high-performance, general-purpose I / O interconnect defined for various future computing and communication platforms. Some PCI attributes (e.g., its usage model, load-store architecture, and software interface) have been maintained through its amendments, and the previous parallel bus implementation has been replaced by a highly scalable, fully serial interface. The updated version of PCI Express utilizes point-to-point interconnects, switch-based technology, and encapsulated protocols to deliver new levels of performance and functionality. Power management, quality of service (QoS), hot-plug / hot-plug support, data integrity, and error handling are among some of the advanced features supported by PCI Express.

[0047] refer to Figure 1 , shows an embodiment of a structure including a point-to-point link interconnecting a set of components. System 100 includes a processor 105 and a system memory 110 coupled to a controller hub 115. Processor 105 includes any processing element such as a microprocessor, a host processor, an embedded processor, a coprocessor, or other processor. Processor 105 is coupled to controller hub 115 via a front side bus (FSB) 106. In one embodiment, FSB 106 is a serial point-to-point interconnect as described below. In another embodiment, link 106 includes a serial, differential interconnect architecture that conforms to different interconnect standards.

[0048] System memory 110 includes any memory device, such as random access memory (RAM), nonvolatile (NV) memory, or other memory accessible by devices in system 100. System memory 110 is coupled to controller hub 115 via memory interface 116. Examples of memory interfaces include double data rate (DDR) memory interfaces, dual channel DDR memory interfaces, and dynamic RAM (DRAM) memory interfaces.

[0049] In one embodiment, controller hub 115 is a root hub, root complex or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnection hierarchy. Examples of controller hub 115 include chipsets, memory controller hubs (MCHs), north bridges, interconnect controller hubs (ICHs), south bridges and root controllers / centers. Typically, the term chipset refers to two physically separate controller hubs, i.e., a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). It should be noted that current systems typically include an MCH integrated with processor 105, and controller 115 is used to communicate with I / O devices in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported by root complex 115.

[0050] Here, controller hub 115 is coupled to switch / bridge 120 via serial link 119. Input / output modules 117 and 121 (also referred to as interfaces / ports 117 and 121) include / implement a layered protocol stack to provide communication between controller hub 115 and switch 120. In one embodiment, multiple devices can be coupled to switch 120.

[0051] The switch / bridge 120 routes packets / messages from the device 125 upstream (i.e., toward the level of the root complex) to the controller hub 115 and routes packets / messages from the processor 105 or the system memory 110 downstream (i.e., leaving the level of the root controller downward) to the device 125. In one embodiment, the switch 120 is referred to as a logical component of multiple virtual PCI to PCI bridge devices. The device 125 includes any internal or external device or component to be coupled to the electronic system, such as an I / O device, a network interface controller (NIC), an insert card, an audio processor, a network processor, a hard drive, a storage device, a CD / DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a FireWire device, a Universal Serial Bus (USB) device, a scanner, and other input / output devices. Typically, in PCIe terminology, for example, a device is referred to as an endpoint. Although not specifically shown, the device 125 may include a PCIe to PCI / PCI-X bridge to support traditional or other versions of PCI devices. Endpoint devices in PCIe are generally classified as traditional, PCIe, or root complexes of integrated endpoints.

[0052] The graphics accelerator 130 is also coupled to the controller hub 115 via a serial link 132. In one embodiment, the graphics accelerator 130 is coupled to the MCH, which is coupled to the ICH. The switch 120 and corresponding I / O devices 125 are then coupled to the ICH. The I / O modules 131 and 118 are also used to implement a layered protocol stack to communicate between the graphics accelerator 130 and the controller hub 115. Similar to the above discussion of the MCH, the graphics controller or graphics accelerator 130 itself can be integrated into the processor 105.

[0053] Go to Figure 2 , which shows an embodiment of a layered protocol stack. The layered protocol stack 200 includes any form of layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCie stack, a next generation high performance computing interconnect stack, or other layered stack. Although the following reference Figure 1-4 The discussion is related to the PCIe stack, but the same concepts can be applied to other interconnect stacks. In one embodiment, the protocol stack 200 is a PCIe protocol stack including a transaction layer 205, a link layer 210, and a physical layer 220. Figure 1 Interfaces such as interfaces 117, 118, 121, 122, 126, and 131 in may be represented as a communication protocol stack 200. A representation as a communication protocol stack may also be referred to as a module or interface that implements / includes the protocol stack.

[0054] PCI Express uses packets to transfer information between components. Packets are formed in the transaction layer 205 and the data link layer 210 to transport information from the transmitting component to the receiving component. As the transmitted packets flow through other layers, they are expanded with additional information required for the packets processed in those layers. On the receiving side, the reverse process occurs and the packet is transformed from its physical layer 220 representation to the data link layer 210 representation and finally (transaction layer packet) into a form that can be processed by the transaction layer 205 of the receiving device.

[0055] Transaction Processing Layer

[0056] In one embodiment, transaction layer 205 is used to provide an interface between the processing core of the device and the interconnect architecture (such as data link layer 210 and physical layer 220). In this regard, the primary responsibility of transaction layer 205 is the assembly and disassembly of packets (i.e., transaction layer packets or TLPs). Transaction layer 205 typically manages credit-based flow control of TLPs. PCIe implements split transactions, i.e., transactions with requests and responses separated by time, allowing the link to carry other traffic while the target device collects data for the response.

[0057] In addition, PCIe utilizes credit-based flow control. In this scheme, a device notifies each of the receive buffers in the transaction layer 205 of an initial amount of credits. An external device at the opposite end of the link (e.g., Figure 1 The controller center 115 in the Controller Center counts the number of credits consumed by each TLP. If the transaction does not exceed the credit limit, the transaction can be transmitted. When a response is received, the total number of credits will be restored. The advantage of the credit scheme is that if no credit limit is encountered, the delay in credit return does not affect performance.

[0058] In one embodiment, the four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions include one or more of read requests and write requests for transferring data to / from a memory mapped location. In one embodiment, memory space transactions can use two different address formats, for example, a short address format such as a 32-bit address, or a long address format such as a 64-bit address. Configuration space transactions are used to access the configuration space of a PCIe device. Transactions to the configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

[0059] Thus, in one embodiment, transaction layer 205 assembles packet header / payload 206. The format for the current packet header / payload can be found in the PCIe specification at the PCIe specification website.

[0060] Quick Reference Figure 3 , which shows an embodiment of a PCIe transaction descriptor. In one embodiment, a transaction descriptor 300 is a mechanism for conveying transaction information. In this regard, the transaction descriptor 300 supports the identification of transactions in the system. Other potential uses include tracking modifications to the default transaction ordering and the association of transactions with channels.

[0061] Transaction descriptor 300 includes a global identifier field 302, an attribute field 304, and a channel identifier field 306. In the illustrated example, global identifier field 302 is depicted as including a local transaction identifier field 308 and a source identifier field 310. In one embodiment, global transaction identifier 302 is unique for all pending requests.

[0062] According to one embodiment, the local transaction identifier field 308 is a field generated by the requesting agent and is unique to all outstanding requests that require completion by the requesting agent. In addition, in this example, the source identifier 310 uniquely identifies the requester agent within the PCIe hierarchy. Therefore, together with the source ID 310, the local transaction identifier 308 field provides a global identification of transactions within the hierarchy domain.

[0063] Attribute field 304 specifies the characteristics and relationships of transaction processing. In this regard, attribute field 304 may be used to provide additional information that allows the default processing of transaction processing to be modified. In one embodiment, attribute field 304 includes priority field 312, reserved field 314, sort field 316 and no snooping field 318. Here, priority subfield 312 can be modified by the initiator to assign priority to transaction processing. Reserved attribute field 314 is reserved for future or vendor-defined use. Possible use models using priority or security attributes can be implemented using reserved attribute fields.

[0064] In this example, the sort attribute field 316 is used to provide optional information that conveys the sort type that can modify the default sort rule. According to an exemplary embodiment, a sort attribute of "0" indicates the default sort rule for the application, wherein a sort attribute of "1" indicates a loose sort, wherein writes can pass writes in the same direction, and read completions can pass writes in the same direction. Snoop attribute field 318 is used to determine whether a transaction is snooped. As shown, channel ID field 306 identifies the channel with which the transaction is associated.

[0065] Link Layer

[0066] The link layer 210 (also referred to as the data link layer 210) acts as an intermediate stage between the transaction layer 205 and the physical layer 220. In one embodiment, the responsibility of the data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components in the link. One side of the data link layer 210 accepts the TLPs assembled by the transaction layer 205, applies a packet sequence identifier 211 (i.e., an identification number or packet number), calculates and applies an error detection code (i.e., CRC 212), and submits the modified TLP to the physical layer 220 for transmission across the physical layer to an external device.

[0067] Physical Layer

[0068] In one embodiment, the physical layer 220 includes a logical sub-block 221 and an electrical sub-block 222 to physically transmit packets to an external device. Here, the logical sub-block 221 is responsible for the "digital" functions of the physical layer 221. In this regard, the logical sub-block includes a transmission section that prepares outgoing information sent by the physical sub-block 222, and a receiver section that identifies and prepares received information before passing it to the link layer 210.

[0069] Physical block 222 includes a transmitter and a receiver. The transmitter is provided by a logical sub-block 221 with symbols, which the transmitter serializes and transmits to an external device. The receiver is supplied with serialized symbols from an external device, and the receiver converts the received signal into a bit stream. The bit stream is deserialized and supplied to logical sub-block 221. In one embodiment, an 8b / 10b transmission code is used, in which ten-bit symbols are transmitted / received. Here, special symbols are used to frame packets with frames 223. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

[0070] As described above, although the transaction layer 205, link layer 210, and physical layer 220 are described with reference to a specific embodiment of the PCIe protocol stack, the layered protocol stack is not so limited. In fact, any layered protocol may be included / implemented. As an example, a port / interface represented as a layered protocol includes: (1) a first layer for assembling packets, i.e., a transaction layer; a second layer for serializing packets, i.e., a link layer; and a third layer for transmitting packets, i.e., a physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.

[0071] Next reference Figure 4 , which shows an embodiment of a PCIe serial point-to-point structure. Although an embodiment of a PCIe serial point-to-point link is shown, the serial point-to-point link is not limited thereto because it includes any transmission path for transmitting serial data. In the illustrated embodiment, the basic PCIe link includes two low voltage differential drive signal pairs: a transmission pair 406 / 411 and a reception pair 412 / 407. Therefore, device 405 includes a transmission logic 406 for transmitting data to device 410 and a reception logic 407 for receiving data from device 410. In other words, two transmission paths (i.e., paths 416 and 417), and two reception paths (i.e., paths 418 and 419) are included in the PCIe link.

[0072] A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices (e.g., device 405 and device 410) is referred to as a link (e.g., link 415). A link can support one path - each path represents a set of differential signal pairs (one pair for transmission and one pair for reception). In order to scale bandwidth, a link can aggregate multiple paths indicated by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0073] A differential pair refers to two transmission paths (e.g., lines 416 and 417) for transmitting differential signals. As an example, when line 416 switches from a low voltage level to a high voltage level (i.e., a rising edge), line 417 drives from a high logic level to a low logic level (i.e., a falling edge). Differential signals may show better electrical characteristics, such as better signal integrity (i.e., cross-coupling, voltage overshoot / undershoot, ringing, etc.). This allows for better timing windows, which enables faster transmission frequencies.

[0074] Figure 5 5 is a simplified block diagram 500 illustrating an exemplary multi-chip package 505 including two or more chips, or dies (eg, 510, 515) communicatively connected using an exemplary multi-chip package link (MCPL) 520. Figure 5 An example of two (or more) dies is shown, where the two (or more) dies are interconnected using an exemplary MCPL520, but it should be understood that the principles and features of the MCPL embodiments described herein can be applied to any interconnect or link connecting a die (e.g., 510) and other components, including connecting two or more dies (e.g., 510, 515), connecting a die (or chip) to another component outside the die, connecting a die to another device or die outside the package (e.g., 505), connecting a die to a BGA package, and embodiments of a patch (POINT) on an interposer, among other potential other examples.

[0075] Typically, a multi-chip package (e.g., 505) can be an electronic package in which multiple integrated circuits (ICs), semiconductor dies, or other discrete components (e.g., 510, 515) are packaged onto a unified substrate (e.g., silicon or other semiconductor substrate) to facilitate use as a combined component of a single component (e.g., like a larger IC). In some instances, the larger component (e.g., die 510, 515) itself can be an IC system, such as a system on a chip (SoC), a multi-processor chip, or other component that includes multiple components (e.g., 525-530 and 540-545) on a device (e.g., on a single die (e.g., 510, 515)). Multi-chip package 505 can provide the flexibility to build complex and varied systems from potentially multiple discrete components and systems. For example, each of die 510, 515 can be manufactured using a silicon substrate of package 505 provided by a third entity or otherwise provided by two different entities, among many other examples. In addition, the die and other components within the multi-chip package 505 themselves may include interconnects or other communication structures (e.g., 535, 550) that provide an infrastructure for communication between components (e.g., 525-530 and 540-545) within the device (e.g., 510, 515, respectively). The various components and interconnects (e.g., 535, 550) may potentially support or use a variety of different protocols. In addition, communication between the die (e.g., 510, 515) may potentially include transactions between various components on the die via a variety of different protocols. Designing mechanisms to provide communication between chips (or die) on a multi-chip package can be challenging, with conventional solutions employing highly specialized, expensive, and package-specific solutions based on the specific combination of components (and required transactions) that are attempted to be interconnected.

[0076] The examples, systems, algorithms, devices, logic, and features described in this specification can solve at least some of the problems identified above, including potentially many other problems not explicitly mentioned herein. For example, in some embodiments, a high bandwidth, low power, low latency interface can be provided to connect a host device (e.g., a CPU) or other device to a companion chip in the same package as the host. Such a multi-chip package link (MCPL) can support multiple packaging options, multiple I / O protocols, and reliability, availability, and serviceability (RAS) features. In addition, the physical layer (PHY) can include an electrical layer and a logical layer, and can support longer channel lengths, including channel lengths of up to about 45 mm and in some cases exceeding about 45 mm. In some embodiments, the exemplary MCPL can operate at high data rates (including data rates exceeding 8-10 Gb / sec).

[0077] In an exemplary embodiment of the MCPL, the PHY electrical layer can improve upon conventional multi-channel interconnect solutions (e.g., multi-channel DRAM I / O), extending data rates and channel configurations, for example, through a number of features (including, for example, regulated mid-rail termination, low power efficient crosstalk cancellation, circuit redundancy, per-bit duty cycle correction and deskew, line coding, and transmitter equalization, among other potential examples).

[0078] In an exemplary embodiment of the MCPL, a PHY logic layer may be implemented that may also facilitate (e.g., electrical layer features) scaling of data rates and channel configurations while also enabling the interconnect to route multiple protocols across the electrical layer. Such an embodiment may provide and define a modular common physical layer that is protocol agnostic and designed for potentially any existing or future interconnect protocol.

[0079] Go to Figure 6 , a simplified block diagram 600 is shown representing at least a portion of a system that includes an exemplary implementation of a multi-chip package link (MCPL). The MCPL can be implemented using physical electrical connections (e.g., wires implemented as pathways) to connect a first device 605 (e.g., a first die including one or more subcomponents) to a second device 610 (e.g., a second die including one or more other subcomponents). In the specific example shown in the high-level representation of diagram 600, all signals (in channels 615, 620) can be unidirectional, and pathways can be provided for data signals to have both upstream data transfer and downstream data transfer. Although Figure 6 Block diagram 600 refers to the first component 605 as the upstream component and the second component 610 as the downstream component, and refers to the physical path of the MCPL used to send data as the downstream channel 615 and the path used to receive data (from component 610) as the upstream channel 620, but it should be understood that the MCPL between devices 605, 610 can be used by each device to both send and receive data between the devices.

[0080] In an exemplary embodiment, the MCPL may provide a physical layer (PHY) including electrical MCPL PHYs 625a, 625b (or, collectively, 625) and executable logic implementing MCPL logical PHYs 630a, 630b (or, collectively, 630). The electrical or physical PHY 625 may provide a physical connection over which data is transmitted between devices 605, 610. Signal conditioning components and logic may be implemented in association with the physical PHY 625 to establish the high data rate and channel configuration capabilities of the link, which in some applications may involve closely clustered physical connections at lengths of about 45 mm or more. The logical PHY 630 may include logic for facilitating timing, link state management (e.g., for link layers 635a, 635b), and protocol multiplexing between potentially multiple different protocols for communicating on the MCPL.

[0081] In an exemplary embodiment, the physical PHY 625 may include a set of data paths for each channel (e.g., 615, 620) over which in-band data may be sent. In this particular example, 50 data paths are provided in the upstream channel 620 and the downstream channel 615, but any number of paths may be used as permitted by layout and power constraints, desired applications, device constraints, etc. Each channel may also include one or more dedicated paths for gating, or clock, signals for the channel, one or more dedicated paths for valid signals for the channel, one or more dedicated paths for flow signals, and one or more dedicated paths for link state machine management or sideband signals. The physical PHY may also include a sideband link 640, wherein, in some examples, among other examples, the sideband link 640 may be a bidirectional lower frequency control signal link for coordinating state transitions and other attributes of the MCPL of the connected devices 605, 610.

[0082] As described above, multiple protocols can be supported using the implementation of MCPL. In fact, multiple independent transaction layers 650a, 650b can be provided in each device 605, 610. For example, each device 605, 610 can support and utilize two or more protocols, such as PCI, PCIe, QPI, Intel intra-die interconnect (IDI), etc. IDI is a consistency protocol for communicating between cores, last level cache (LLC), memory, graphics, and IO controllers on the die. Other protocols (including Ethernet protocol, Infiniband protocol, and other PCIe structures based on the protocol) can also be supported. In other examples, the combination of logical PHY and physical PHY can also be used as a die to die interconnect, which is used to connect a SerDes PHY (PCIe, Ethernet, Infiniband or other high-speed SerDes) on a die to its upper layer implemented on another die.

[0083] The logical PHY 630 can support multiplexing between these multiple protocols on the MCPL. For example, a dedicated flow path can be used to assert an encoded flow signal that identifies which protocol applies to data sent substantially simultaneously on the data path of the channel. In addition, the logical PHY 630 can be used to negotiate various types of link state transitions that various protocols can support or request. In some instances, the LSM_SB signal sent through the dedicated LSM_SB path of the channel can be used in conjunction with the sideband link 640 to transmit and negotiate link state transitions between devices 605, 610. In addition, link training, error detection, skew detection, de-skew, and other functions of traditional interconnects can be replaced or managed in part using the logical PHY 630. For example, valid signals sent through one or more dedicated valid signal paths in each channel can be used to signal link activity, detect skew, link errors, and implement other features, among other instances. In Figure 6 In a specific example of, multiple valid paths are provided in each channel. For example, data paths within a channel can be bundled or clustered (physically and / or logically), and valid paths can be provided for each cluster. In addition, among other examples, multiple strobe paths can be provided, and in some cases, dedicated strobe signals are provided for each cluster of multiple data path clusters in the channel.

[0084] As described above, the logical PHY 630 can be used to negotiate and manage link control signals sent between devices connected by MCPL. In some embodiments, the logical PHY 630 may include a link layer packet (LLP) generation logic 660 that can be used to send link layer control messages through MCPL (i.e., in-band). Among other examples, such messages can be sent using a flow path through a data path of a channel, and the flow path identification data (e.g., link control data) is link layer to link layer message delivery. In addition to other link layer features between the link layers 635a, 635b of devices 605, 610, the link layer messages implemented using the LLP module 660 can respectively facilitate the negotiation and execution of link layer state transitions, power management, loopback, disabling, re-centering, and scrambling.

[0085] Go to Figure 7 , a diagram 700 is shown representing an exemplary signaling of a set of paths (e.g., 615, 620) in a particular channel using an exemplary MCPL. Figure 7 In the example of , two clusters with twenty-five (25) data paths are provided for fifty (50) total data paths in the channel. A portion of the paths are shown, while other paths (e.g., DATA[4-46] and a second strobe signal path (STRB)) are omitted (e.g., as redundant signals) for ease of illustration of the specific example. When the physical layer is in an active state (e.g., not powered off or in a low power mode (e.g., L1 state)), a synchronous clock signal can be provided for the strobe path (STRB). In some embodiments, data can be sent on both the rising and falling edges of the strobe. Each edge (or half clock cycle) can be divided into a unit time interval (UI). Therefore, in this example, one bit (e.g., 705) can be sent on each path, allowing one byte to be sent every 8UI. The byte time period 710 can be defined as 8UI, or as the time for sending one byte on a single data path in a data path (e.g., DATA[0-49]).

[0086] In some embodiments, a valid signal (e.g., VALID 0, VALID 1) sent on one or more dedicated valid signal channels can be used as a dominant indicator for a receiving device or receiver when asserted (high) to identify that data is being sent from a transmitting device or source on a data path (e.g., DATA[0-49]) during the following time period (e.g., byte time period 710). Alternatively, when the valid signal is low, the source indicates that the receiver will not send data on the data path during the following time period. Therefore, when the receiver logic PHY detects (e.g., on paths VALID 0 and VALID 1) that the valid signal is not asserted, the receiver can ignore any data detected on the data path (e.g., DATA[0-49]) during the following time period. For example, in fact, when the source does not send any data, crosstalk noise or other bits can appear on one or more of the data paths in the data path. Due to the low or non-asserted valid signal during the previous time period (e.g., the previous byte time period), the receiver can determine that the data path will be ignored during the following time period.

[0087] The data sent on each path in the path of MCPL can be strictly aligned to the selection signal. Time periods (e.g., byte time periods) can be defined based on the selection, and each of these periods can correspond to a defined window in which signals are to be sent on the data path (e.g., DATA[0-49]), the valid path (e.g., VALID1, VALID2), and the flow path (e.g., STREAM). Therefore, the alignment of these signals can achieve the identification of the valid signal in the previous time period window applied to the data in the next time period window, and the identification of the stream signal applied to the data in the same time period window. The stream signal can be an encoded signal (e.g., 1 byte of data for a byte time period window) that is encoded to identify the protocol applied to the data sent during the same time period window.

[0088] To illustrate, in Figure 7In the specific example of , byte time cycle windows are defined. Valid is asserted in time cycle window n (715) before any data is injected on the data path DATA[0-49]. At the next time cycle window n+1 (720), data is sent on at least some of the data paths. In this case, data is sent on all fifty data paths during n+1 (720). Because valid was asserted for the duration of the previous time cycle window n (715), the receiver device can verify the data received on the data path DATA[0-49] during time cycle window n+1 (720). In addition, the dominant nature of the valid signal during time cycle window n (715) allows the receiving device to prepare for the incoming data. Continued Figure 7 In the example of , the valid signal remains asserted (on VALID1 and VALID2) during time period window n+1 (720), so that the receiver device expects data to be sent via data path DATA[0-49] during time period window n+2 (725). If the valid signal is to remain asserted during time period window n+2 (725), the receiver device may also expect to receive (and process) additional data sent during the immediately following time period window n+3 (730). However, Figure 7 In the example of , the valid signal is de-asserted for the duration of time cycle window n+2 (725), thereby indicating to the receiver device that no data will be sent during time cycle window n+3 (730) and that any bits detected on the data path DATA[0-49] during time cycle window n+3 (730) should be ignored.

[0089] As described above, multiple active paths and strobe paths can be maintained in each channel. Among other advantages, this can help maintain circuit simplicity and synchronization in clusters of relatively long physical paths connecting two devices. In some embodiments, a data path group can be divided into clusters of data paths. For example, in Figure 7 In the example of , data path DATA[0-49] can be divided into two clusters of twenty-five paths and each cluster can have dedicated valid and enable paths. For example, valid path VALID 1 can be associated with data path DATA[0-24], and valid path VALID 2 can be associated with data path DATA[25-49]. The signals on each "copy" path of the valid and enable paths for each cluster can be the same. VALID paths and STREAM paths can also be different between clusters, allowing them to be operated as independent ports in the structure or as reduced width ports to save power.

[0090] As described above, the data on the stream path STREAM can be used to indicate the receiving logic PHY to apply the protocol to the corresponding data sent on the data path DATA[0-49]. Figure 7 In the example of , during the same time period window as the data on the data path DATA[0-49], the stream signal is sent on STREAM to indicate the protocol of the data on the data path. In alternative embodiments, the stream signal (e.g., along with the corresponding valid signal, in addition to other potential modifications) may be sent during the previous time period window. However, continuing to Figure 7 In the example of, during time period window n+2 (725), stream signal 735 is sent, the stream signal 735 being encoded to indicate a protocol (e.g., PCIe, PCI, IDIQPI, etc.) that is applied to bits sent via data path DATA[0-49] during time period window n+2 (725). Similarly, another stream signal 740 may be sent during a subsequent time period window n+2 (725) to indicate a protocol that is applied to bits sent via data path DATA[0-49] during time period window n+2 (725), and so on. In some cases, for example, Figure 7 In the example of (where both stream signals 735, 740 have the same encoding, binary FF), the data in sequential time period windows (e.g., n+1 (720) and n+2 (725)) may belong to the same protocol. However, in other cases, the data in sequential time period windows (e.g., n+1 (720) and n+2 (725)) may come from different transactions applied by different protocols, and, among other examples, the stream signals (e.g., 735, 740) may be encoded to identify different protocols applied to sequential bits of data on a data path (e.g., DATA[0-49]).

[0091] In some embodiments, a low power state or idle state can be defined for the MCPL. For example, when no device is sending data on the MCPL, the physical layer (electrical and logical) of the MCPL can enter an idle state or a low power state. Figure 7In the example of , during time cycle window n-2 (745), the MCPL is in a quiet state or idle state and the gating is disabled to save power. The MCPL can be switched out of the low power mode or idle mode and wake up the gating during time cycle window n-1 (e.g., 705). The gating can be completed by sending a preamble (e.g., to help wake up and synchronize each channel and receiver device in the channel), starting the gating signal before any other signal is sent on other non-gated channels. After this time cycle window n-1 (705), the valid signal can be asserted in time cycle window n (715) to notify the receiver that data appears in the next time cycle window n+1 (720) discussed above.

[0092] The MCPL may re-enter a low power state or idle state (e.g., L1 state) based on detection of idle conditions for other paths, data paths, and / or MCPL channels. For example, no signal transmission may be detected starting at time cycle window n+3 (730) and onward. In addition to other examples and principles (including those discussed later in this document), logic on the source or sink device may initiate a transition back to a low power state, thereby again generating (e.g., time cycle window n+5 (755)) a strobe to enter idle in power save mode.

[0093] The electrical characteristics of the physical PHY may include one or more of the following: single-ended signaling, half-rate forwarding timing, matching between interconnect channels and on-chip transmission delays of transmitters (sources) and receivers (sinks), optimized electrostatic discharge (ESD) protection, pad capacitance, and other features. In addition, MCPL may be implemented to achieve higher data rates (e.g., approaching 16Gb / sec) and energy efficiency characteristics than traditional packaged I / O solutions.

[0094] Figure 8 A portion of a simplified block diagram 800 representing a portion of an exemplary MCPL is shown. Figure 8 The diagram 800 includes a representation of an exemplary path 805 (eg, a data path, a valid path, or a flow path) and clock generation logic 810. Figure 8 As shown in the example of , in some embodiments, the clock generation logic 810 can be implemented as a clock tree that is used to distribute the generated clock signal to each block of each path (e.g., data path 805) that implements the exemplary MCPL. In addition, a clock recovery circuit 815 can be provided. In some embodiments, as is customary in at least some conventional interconnect I / O architectures, a separate clock recovery circuit can be provided for a cluster of multiple paths, rather than providing a separate clock recovery circuit for each path, where the clock signal is distributed in each path. In fact, when applied to Figure 6 and 7 In the exemplary configuration, a separate gating path and accompanying clock recovery circuitry may be provided for each cluster of twenty-five data paths.

[0095] Continue to Figure 8 In some embodiments, at least the data path, the flow path, and the valid path can terminate at the middle rail at a regulated voltage greater than zero (ground). In some embodiments, the middle rail voltage can be regulated to V CC / 2. In some embodiments, a separate voltage regulator 825 may be provided in each cluster of paths. For example, among other potential examples, when applied to Figure 6 and 7 In the example of, the first voltage regulator can be provided to the first cluster of twenty-five data paths and the second voltage regulator can be provided to the remaining cluster of twenty-five data paths. In some cases, the exemplary voltage regulator 825 can be implemented as a linear regulator, a switched capacitor circuit, among other examples. In some embodiments, an analog feedback loop or a digital feedback loop can be provided for the linear regulator, among other examples.

[0096] In some implementations, crosstalk cancellation circuitry may also be provided to the exemplary MCPL. In some cases, the tight nature of the long MCPL wires may introduce crosstalk interference between the paths. Crosstalk cancellation logic may be implemented to address these and other issues. For example, in Figure 9-10 In one example shown, crosstalk can be significantly reduced using low power active circuits as shown in Figures 900 and 1000. For example, in Fig. 9 In the example of , a weighted high pass filtered "aggressor" signal can be added to the "victim" signal (i.e., the signal that is experiencing crosstalk interference from the aggressor). Each signal can be considered a victim of crosstalk to each other's signals in the link, and can itself be an aggressor to another signal as long as it is a source of crosstalk interference. Due to the derivative nature of crosstalk on a link, such a signal can be generated and reduce the crosstalk on the victim path by more than 50%. In Fig. 9 In the example of , a low pass filtered aggressor signal may be generated by a high pass RC filter (eg, implemented by C and R1) that produces a filtered signal to be added using a summing circuit 905 (eg, an RX sense-amplifier).

[0097] When the circuit implementation can be realized with relatively low overhead, as illustrated in Fig. 9 An exemplary transistor-level circuit diagram of the circuits shown and described in the examples of Fig.10 As shown in the figure, similar to Fig. 9The implementation described in the example of may be a particularly convenient solution for applications (e.g., MCLP). It should be understood that Fig. 9 and 10 The representation in is a simplified representation and the actual implementation will be included in Fig. 9 and 10 Multiple copies of the circuit shown in FIG. 1 are provided to accommodate a network with crosstalk interference within and between the paths of the link. As an example, in a three-path link (e.g., paths 0-2), a circuit similar to Fig. 9 and 10 The circuits described in the example of the circuits described in other examples can be provided from via 0 to via 1, from via 0 to via 2, from via 1 to via 0, from via 1 to via 2, from via 2 to via 0, from via 2 to via 1, and so on based on the geometric layout of the vias.

[0098] Additional features may be implemented at the physical PHY level of the exemplary MCPL. For example, in some cases, receiver offsets may introduce significant errors and limit I / O voltage tolerances. Circuit redundancy may be used to improve receiver sensitivity. In some embodiments, circuit redundancy may be optimized to account for standard deviation offsets of data samplers used in the MCPL. For example, an exemplary data sampler may be provided that is designed to a three (3) standard deviation offset specification. Figure 6 and 7 In the example of , for example, two (2) data samplers would be used for each receiver (e.g., for each channel) and one hundred (100) samplers would be used for a fifty (50) channel MCPL. In this example, the probability that one of the receiver (RX) channels will not meet the three standard deviation offset specification is 24%. If another of the other data samplers is found to be out of bounds, a chip reference voltage generator may be provided to set the upper offset bound and move on to the next data sampler on the receiver. However, with each receiver using four (4) data samplers (i.e., instead of two in this example), the receiver will only fail if three out of the four samplers fail. For a fifty channel MCPL, as in Figure 6 and 7 In the example of FIG. 5 , adding this additional circuit redundancy can significantly reduce the failure rate from 24% to less than 0.01%.

[0099] In other examples, at very high data rates, per-bit duty cycle correction (DCC) and tilt correction can be used to increase the baseline of each cluster DCC and tilt correction to improve link margins. Instead of correcting for all cases (as in traditional solutions), in some embodiments, low-power digital implementations can be used to sense and correct outliers where I / O lines fail. For example, global adjustments of pathways can be performed to identify problem pathways within a cluster. These problem pathways can then be used as per-path adjustments to achieve the goal of high data rates supported by MCPL.

[0100] Additional features may also optionally be implemented in some instances of MCPL to improve the performance characteristics of the physical link. For example, line coding may be provided. Although the intermediate rail termination as described above may allow the DC data bus inversion (DBI) to be omitted, the AC DBI may still be used to reduce dynamic power. In addition to other example benefits, more complex encoding may also be used to eliminate the worst-case differences between 1 and 0 to reduce, for example, driver requirements for the intermediate rail regulator, and to limit I / O switching noise. In addition, transmitter equalization may also be optionally implemented. For example, at very high data rates, insertion losses may be significant for in-package channels. In some cases, two-tap weight transmitter equalization (e.g., performed during the initial power-up sequence) may be sufficient to alleviate some of these problems, and so on.

[0101] Go to Fig.11 , simplified block diagram 1001 shows an example logical PHY illustrating an example MCPL. Physical PHY 1105 can be connected to a die including logical PHY 1110 and additional logic to support the link layer of the MCPL. In this example, the die can also include logic for supporting multiple different protocols on the MCPL. For example, in Fig.11 In the example of, PCIe logic 1115 and IDI logic 1120 can be provided so that the die can communicate using PCIe or IDI on the same MCPL connecting two dies, in potentially many other examples, including where more than two protocols are supported by the MCPL or protocols other than PCIe and IDI are supported by the MCPL. The various protocols supported between the dies can provide varying levels of services and features.

[0102] The logical PHY 1110 may include logic for negotiating link state transitions associated with requests from upper layer logic of the die (e.g., received via PCIe or IDI). In some embodiments, the logical PHY 1110 may also include link test and debug logic (e.g., 1130). As described above, the exemplary MCPL may support control signals that are sent between die via the MCPL to facilitate the protocol agnostic, high performance, and (among other example features) power efficiency features of the MCPL. For example, as described in the above examples, the logical PHY 1110 may support the generation, transmission, and reception of valid signals, flow signals, and LSM sideband signals associated with sending and receiving data via a dedicated data path.

[0103] In some embodiments, multiplexing logic (e.g., 1135) and demultiplexing logic (e.g., 1140) may be included in the logical PHY 1110 or otherwise accessible to the logical PHY 1110. For example, the multiplexing logic (e.g., 1135) may be used to identify data (e.g., specifically packets, messages, etc.) that will be sent to the MCPL. The multiplexing logic 1135 may identify the protocol that manages the data and generate a stream signal encoded to identify the protocol. For example, in an exemplary embodiment, the stream signal may be encoded as a byte of two hexadecimal symbols (e.g., IDI: FFh; PCIe: F0h; LLP: AAh; sideband: 55h, etc.) and may be sent during the same window (e.g., byte time period window) of the data managed by the identified protocol. Similarly, the demultiplexing logic 1140 may be used to interpret the incoming stream signal to decode the stream signal and identify the protocol to be applied to the data received simultaneously with the stream signal on the data path. The demultiplexing logic 1140 may then apply (or ensure) link layer processing for the particular protocol and cause the data to be processed by the corresponding protocol logic (eg, PCIe logic 1115 or IDI logic 1120 ).

[0104] The logical PHY 1110 may also include a link layer packet logic 1150 that may be used to handle various link control functions, including power management tasks, loopback, disabling, re-centering, scrambling, etc. Among other functions, the LLP logic 1150 may facilitate link layer to link layer messages through MCLP. Data corresponding to LLP signaling may also be identified by a stream signal sent on a dedicated stream signal path, which is encoded to identify data path LLP data. Multiplexing logic and demultiplexing logic (e.g., 1135, 1140) may also be used to generate and interpret stream signals corresponding to LLP services, and to enable such services to be processed by appropriate die logic (e.g., LLP logic 1150). Similarly, in other examples, some embodiments as MCLP may include dedicated sidebands (e.g., sidebands 1155 and supporting logic), such as asynchronous and / or lower frequency sideband channels.

[0105] The logical PHY logic 1110 may also include state machine management logic that can generate and receive (and use) link state management messages through a dedicated LSM sideband path. For example, in other potential examples, the LSM sideband path can be used to perform feedback checks (handshaking) to advance the link training state and exit from a power management state (e.g., L1 state). In other examples, the LSM sideband signal can be an asynchronous signal because it is not aligned with the data, valid flow signal of the link, but corresponds to a signal transmission state transition and alignment of a link state machine between two tube cores or chips connected by the link. In some examples, among other example benefits, providing a dedicated LSM sideband path can allow the detection circuitry of the reception of the traditional squelch and analog front end (AFE) to be eliminated.

[0106] Go to Fig.12 , a simplified block diagram 1200 shows another representation of the logic used to implement the MCPL. For example, a defined logical PHY interface (LPIF) 1205 is provided for the logical PHY 1110 through any of a plurality of different protocols (e.g., PCIe, IDI, QPI, etc.) 1210, 1215, 1220, 1225, and a signaling mode (e.g., sideband) can be interfaced with the physical layer of the exemplary MCPL. In some embodiments, multiplexing and arbitration logic 1230 can also be provided as a layer separate from the logical PHY 1110. In one example, the LPIF 1205 can be provided as an interface on either side of the MuxArb layer 1230. The logical PHY 1110 can be interfaced with the physical PHY (e.g., the analog front end (AFE) 1105 of the MCPL PHY) through another interface.

[0107] The LPIF can extract the PHY (logic and electrical / analog) from the upper layers (e.g., 1210, 1215, 1220, 1225) so that completely different PHYs can be implemented transparently to the upper layers under the LPIF. In other examples, this can help promote modularity and reuse in the design, such as when the underlying signal transmission technology PHY is updated, the upper layer can remain intact. In addition, the LPIF can define multiple signals that implement multiplexing / demultiplexing, LSM management, error detection and handling, and other functions of the logical PHY. For example, Table 1 summarizes at least a portion of the signals that can be defined for an exemplary LPIF:

[0108] Table 1:

[0109]

[0110]

[0111] Table 1

[0112] As shown in Table 1, in some embodiments, an alignment mechanism can be provided by AlignReq / AlignAck feedback checks. For example, when the physical layer enters recovery, some protocols may lose packet framing. For example, in order to ensure the correct framing identification through the link layer, the alignment of the packet can be corrected. In addition, Fig.13 As shown, when the physical layer enters recovery, the physical layer can assert the StallReq signal so that when a new aligned packet is ready to be transmitted, the link layer asserts the stall signal. The physical layer logic can sample both stall and valid to determine whether the packet is aligned. For example, the physical layer can continue to drive trdy to discharge link layer packets until the sampled stall and valid are asserted. Other potential implementations include using other valid alternative implementations for assisting packet alignment.

[0113] Various fault tolerances can be defined for signals on the MCPL. For example, fault tolerances can be defined for valid, stream, LSM sideband, low frequency sideband, link layer packets, and other types of signals. Fault tolerance for packets, messages, and other data sent through the dedicated data path of the MCPL can be based on a specific protocol for managing data. In some embodiments, in addition to other potential examples, error detection and handling mechanisms can be set, such as, cyclic redundancy check (CRC), retry buffer. As an example, for PCIe packets sent through the MCPL, a 32-bit CRC can be used for PCIe transaction layer packets (TLPs) with guaranteed delivery (e.g., through a replay mechanism) and a 16-bit CRC can be used for PCIe link layer packets (which can be constructed to be lossy (e.g., where replay is applied)). In addition, in addition to other examples, for PCIe framing tokens, a specific Hamming distance (e.g., a Hamming distance of four (4)) can be defined for token identifiers; parity and 4-bit CRC can also be utilized. On the other hand, for IDI packets, a 16-bit CRC can be utilized.

[0114] In some embodiments, fault tolerance may be defined for a link layer packet (LLP) that includes a requirement for a valid signal to transition from low to high (i.e., 0 to 1) (e.g., to assist in ensuring bit and symbol lock). Additionally, in one example, among other defined characteristics that may be used as a basis for determining a fault in LLP data on the MCPL, a particular number of consecutive, identical LLPs may be defined to be sent, with a requester retry after a response timeout, and a response may be expected for each request. In a further example, fault tolerance may be provided for a valid signal, for example, by extending the valid signal, or symbol, over a time period window (e.g., by maintaining the valid signal high for eight UIs). Additionally, among other examples, errors or faults in a stream signal may be prevented by maintaining a Hamming distance for the encoding values ​​of the stream signal.

[0115] Implementations of the logical PHY may include error detection, error reporting, and error handling logic. In some implementations, the logical PHY of the exemplary MCPL may include logic for detecting PHY layer deframing errors (e.g., on valid and streaming paths), sideband errors (e.g., regarding LSM state transitions), errors in the LLP (e.g., critical to LSM state transitions), among other examples. Some error detection / resolution may be sent to upper layer logic, such as PCIe logic adapted to detect specific PCIe errors, among other examples.

[0116] In the case of a deframing error, in some embodiments, one or more mechanisms may be provided by error handling logic. Deframing errors may be handled based on the protocols involved. For example, in some embodiments, the link layer may be notified of the error, thereby triggering a retry. Deframing may also cause realignment of the logical PHY deframing. In addition, among other techniques, re-centering of the logical PHY may be performed and the symbol / window lock may be reacquired. In some examples, centering may include a PHY that moves the receiver clock phase to an optimal point to detect incoming data. In this context, "optimal" may refer to where it has the maximum tolerance for noise and clock jitter. Among other examples, re-centering may include a simplified centering function, for example, the simplified centering function is performed when the PHY wakes up from a low power state.

[0117] Other types of errors may involve other error handling techniques. For example, an error detected in the sideband can be captured by a timeout mechanism of the corresponding state (e.g., of the LSM). The error can be logged and then the link state machine can be switched to reset. The LSM can remain in the reset state until a restart command is received from software. In another example, an LLP error (e.g., a link control packet error) can be handled using a timeout mechanism that can restart the LLP sequence if an acknowledgement of the LLP sequence is not received.

[0118] Figures 14A-14C A representation of an exemplary bitmap on the data paths of an exemplary MCPL for various types of data is shown. For example, the exemplary MCPL may include fifty data paths. Fig.14A A first bitmap of an exemplary 16-byte slot in a first protocol (such as an IDI) is shown, which may be sent via a data path within an 8UI symbol or window. For example, within a defined 8UI window, three 16-byte slots (including the header slot) may be sent. In this example, two bytes of data remain, and these remaining two bytes may be utilized as CRC bits (e.g., DATA

[48] and DATA

[49] on the path).

[0119] In another example, Fig. 14B A second exemplary bitmap for PCIe packet data sent through fifty data lanes of an exemplary MCPL is shown. Fig. 14BIn an example of PCIe, 16-byte packets (e.g., transaction layer (TLP) or data link layer (DLLP) PCIe packets) can be sent over the MCPL. In an 8UI window, three packets can be sent using the remaining two bytes within the window leaving unused bandwidth. Framing tokens can be included within these symbols and used to locate the start and end of each packet. In an example of PCIe, Fig. 14B The framing used in the example may be the same as those tokens implemented with PCIe at 8GT / sec.

[0120] In another example, Fig. 14C As shown, an exemplary bit map of a link-to-link packet (e.g., packet LLP) sent via an exemplary MCPL is shown. The LLP can be every 4 bytes, and each LLP (e.g., LLP0, LLP1, LLP2, etc.) can be sent four times in a row according to fault tolerance and error detection within the exemplary embodiment. For example, failure to receive four consecutive identical LLPs can indicate an error. In addition, when there are other data types, failure to receive a VALID in a travel time window or codeword can also indicate an error. In some cases, the LLP can have a fixed slot. In addition, in this example, in addition to other examples, unused, or "spare" bits in a byte time period can result in a logical 0 being transmitted through two of the fifty paths (e.g., DATA[48-49]).

[0121] Go to Fig.15 , a simplified link state machine transition diagram 1400 is shown along with the sideband feedback check exchanges utilized between state transitions. For example, the Reset.Idle state (e.g., where a phase-locked loop (PLL) lock calibration is performed) can be transitioned to the Reset.Cal state (e.g., where the link is further calibrated) via a sideband feedback check. Reset.Cal can be transitioned to the Reset.ClockDCC state (e.g., where duty cycle correction (DCC) and delay locked loop (DLL) locking can be performed) via a sideband feedback check. Additional feedback checks can be performed to transition from the Reset.ClockDCC to the Reset.Quiet state (e.g., to deassert a valid signal). To assist in alignment of signaling on a path of the MCPL, the path can be centered via the Center.Pattern state.

[0122] In some embodiments, as in Fig.16As shown in the example of , during the Center.Pattern state, the transmitter can generate a training pattern or other data. The receiver can adjust its receiver circuit to receive such a training pattern, for example, by setting the phase interpolator position and the vref position and setting the comparator. The receiver can continuously compare the received pattern with the expected pattern and save the result in a register. After a set of patterns is completed, the receiver can increase the phase interpolator setting to keep vref the same. The test pattern generation and comparison process can continue and the new comparison results can be stored in the register using a process that repeats the stepping through all phase interpolator values ​​and through all values ​​of vref. When the pattern generation and comparison process is complete, the Center.Quiet state can be entered. The following is centered through the Center.Pattern and Center Quiet link states, and the sideband feedback check (which can, for example, use the LSM band signal through the dedicated LSM sideband path of the link) facilitates the transition to the Link.Init state to initialize the MCPL and enable data to be sent on the data MCPL.

[0123] Temporarily return to Fig.15 As discussed above, the sideband feedback check can be used to facilitate the link state machine transition between the die or chips in the multi-chip package. For example, the signal on the LSM sideband path of the MCPL can be used to synchronize the state machine transition in the entire die. For example, when the conditions for exiting the state (e.g., Reset.Idle) are met, the edge that meets these conditions can assert the LSM sideband signal on its outbound LSM_SB path and wait for other remote die to reach the same conditions and assert the LSM sideband signal on its LSM_SB path. When both LSM_SB signals are asserted, the link state machine of each corresponding die can be converted to the next state (e.g., Reset.Cal state). A minimum overlap time can be defined, during which both LSM_SB signals should remain asserted before the transition state. In addition, after LSM_SB is de-asserted, a minimum static time can be defined to allow accurate turn detection. In some embodiments, each link state machine transition can be regulated on this LSM_SB feedback check and promoted by this LSM_SB feedback check.

[0124] Fig.17 1700 is a more detailed link state machine diagram illustrating at least some of the additional link states and link state transitions that may be included in the exemplary MCPL. Fig.17Among other states and state transitions shown, the exemplary link state machine may include a "guided loopback" transition that may be provided to place the path of the MCPL in a digital loopback. For example, after the clock recovery circuit, the receiver path of the MCPL may be looped back to the transmitter path. An "LBRecenter" state may also be provided, which may be used to align digital symbols in some cases. In addition, as Fig.15 As shown, MCPL may support multiple link states, including an active L0 state and low power states (eg, an L1 idle state, and an L2 sleep state), among potential other examples.

[0125] Fig.18 1800 is a simplified block diagram illustrating an exemplary process for transitioning between an active state (e.g., L0) and a low power, or idle state (e.g., L1). In this particular example, a first device 1805 and a second device 1810 are communicatively coupled using MCPL. When in the active state, data is transmitted through a path (e.g., DATA, VALID, STREAM, etc.) of the MCPL. Link layer packets (LLPs) may be transmitted through a path (e.g., a data path having a stream signal indicating that the data is LLP data) to assist in facilitating link state transitions. For example, an LLP may be sent between the first device 1805 and the second device 1810 to negotiate entry from L0 to L1. For example, an upper layer protocol supported by the MCPL may communicate the need to enter L1 (or another state) and the upper layer protocol may cause the LLP to be sent through the MCPL to facilitate link layer feedback verification so that the physical layer enters L1. For example, Fig.18At least a portion of the transmitted LLP is shown to include an "enter L1" request LLP sent from the second (upstream) device 1810 to the first (downstream) device 1805. In some embodiments, and in the upper layer protocol, the downstream port does not initiate entry into L1. Among other examples, the receiving first device 1805 may send a "change to L1" request LLP in response, where the second device 1810 may acknowledge the confirmation (ACK) LLP by "changing to L1". Upon detecting that the feedback check is complete, the logical PHY may cause the sideband link to be asserted on the dedicated sideband link to confirm that the ACK is received and the device (e.g., 1805) is ready and expects to enter L1. For example, the first device 1805 may assert a sideband signal 1815 sent to the second device 1810 to confirm that the last ACK is received in the link layer feedback check. In addition, the second device 1810 may also assert a sideband signal in response to the sideband signal 1815 to notify the first device 1805 of the sideband ACK 1805 of the first device. With the link layer control and sideband feedback checks completed, the MCPL PHY can be transitioned to the L1 state so that all lanes of the MCPL are placed in an idle power saving mode, including the MCPL strobes 1820, 1825 of the corresponding devices 1805, 1810. L1 can be exited after the upper layer logic of one of the first device 1805 and the second device 1810 requests to re-enter L0 (e.g., in response to detecting that data is to be sent to the other device through the MCPL).

[0126] As described above, in some embodiments, the MCPL can facilitate communication between two devices that support potentially multiple different protocols, and the MCPL can facilitate communication based on potentially any one of multiple protocols over the MCPL's path. However, facilitating multiple protocols can replicate entry and re-entry into at least some link states. For example, while some conventional interconnects have a single upper layer protocol that assumes a host role in state transitions, an embodiment of the MCPL with multiple different protocols effectively involves multiple hosts. As an example, if Fig.18 As shown, each of PCIe and IDI can be supported by an implementation of MCPL between two devices 1805, 1810. For example, placing the physical layer into an idle or low power state can be regulated based on first obtaining permission from each of the supported protocols (e.g., PCIe and IDI).

[0127] In some cases, entry into L1 (or another state) may be requested by supporting only one of a plurality of supported protocols for an implementation of the MCPL. Although there may be a possibility (e.g., based on identifying similar conditions on the MCPL (e.g., little or no traffic)) that other protocols will similarly request entry into the same state, the logical PHY may wait until permission or instructions are received from each upper layer protocol before actually facilitating the state transition. The logical PHY may track which upper layer protocols have requested state changes (e.g., perform corresponding feedback checks), and upon identifying that each of the protocols has requested a particular state change, trigger a state transition (e.g., a transition from L0 to L1 or another transition that will affect or interfere with communications of other protocols). In some embodiments, protocols may be blind to other protocols in the system on which they at least partially depend. In addition, in some cases, protocols may expect a response to a request (e.g., from the PHY) to enter a particular state, such as a confirmation or rejection of the requested state transition. Thus, in this case, while waiting for permission from other supported protocols to enter the idle link state, the logical PHY can generate a synthetic response to a request to enter the idle state to "trick" the requesting upper layer protocol into believing that a particular state has been entered (when in fact, the path is still active, at least until the other protocol also requests to enter the idle state). Among other potential advantages, this can simplify coordinating entry into low power states between multiple protocols in other examples.

[0128] It should be noted that the above-described apparatus, method, and system can be implemented in any electronic device or system as described above. As a specific illustration, the following figures provide exemplary systems for utilizing the present invention described herein. As the following system is described in more detail, multiple interconnections different from the above discussion are disclosed, described, and re-discussed. And it is apparent that the above-described advances can be applied to one or more of these interconnections, structures, or architectures.

[0129] refer to Fig.19 , depicts an embodiment of a block diagram for a computing system including a multi-core processor. Processor 1900 includes any processor or processing device for executing code, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SOC), or other device. In one embodiment, processor 1900 includes at least two cores, core 1901 and core 1902, which may include an asymmetric core or a symmetric core (as shown in the embodiment). However, processor 1900 may include any number of processing elements that may be symmetric or asymmetric.

[0130] In one embodiment, a processing element refers to hardware or logic for supporting software threads. Examples of hardware processing elements include: thread units, thread slots, threads, processing units, contexts, context units, logical processors, hardware threads, cores, and / or any other elements that can maintain a state (e.g., execution state or architecture state) for a processor. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with a code (e.g., a software thread, an operating system, an application, or other code). A physical processor (or processor socket) generally refers to an integrated circuit, which may include any number of other processing elements (e.g., cores or hardware threads).

[0131] A core generally refers to logic located on an integrated circuit that is capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to a core, a hardware thread generally refers to any logic located on an integrated circuit that is capable of maintaining an independent architectural state, where the independently maintained architectural states share access to execution resources. It can be seen that when some resources are shared and other resources are dedicated to an architectural state, the naming of hardware threads and the lines between cores overlap. However, typically, cores and hardware threads are viewed by the operating system as independent logical processors, where the operating system can independently schedule operations on each logical processor.

[0132] like Fig.19 As shown, the physical processor 1900 includes two cores, core 1901 and core 1902. Here, core 1901 and core 1902 are considered to be symmetric cores, that is, cores with the same configuration, functional units and / or logic. In another embodiment, core 1901 includes an out-of-order processor core, and core 1902 includes an in-order processor core. However, core 1901 and core 1902 can be selected separately from any type of core (e.g., a native core, a software-managed core, a core suitable for executing a native instruction set architecture (ISA), a core suitable for executing an instruction set architecture (ISA) of a translation, a co-designed core, or other known cores). In a heterogeneous core environment (i.e., an asymmetric core), some form of conversion (e.g., binary conversion) can be utilized to schedule or execute code on one or two cores. For further discussion, when the units in core 1902 operate in a similar manner in the described embodiments, the functional units shown in core 1901 are described in more detail below.

[0133] As shown, core 1901 includes two hardware threads 1901a and 1901b, which may also be referred to as hardware thread slots 1901a and 1901b. Therefore, in one embodiment, a software entity such as an operating system potentially regards processor 1900 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads simultaneously. As described above, the first thread is associated with architecture state register 1901a, the second thread is associated with architecture state register 1901b, the third thread may be associated with architecture state register 1902a, and the fourth thread may be associated with architecture state register 1902b. Here, as described above, each of architecture state registers (1901a, 1901b, 1902a and 1902b) may be referred to as a processing element, thread slot or thread unit. As shown, architecture state register 1901a is copied in architecture state register 1901b, so that independent architecture state / context can be stored for logical processor 1901a and logical processor 1901b. In core 1901, other smaller resources (e.g., instruction pointers and renaming logic in allocator and renamer block 1930) may also be replicated for threads 1901a and 1901b. Some resources (e.g., reorder buffers, ILTB 1920, load / store buffers, and queues in reorder / retirement unit 1935) may be shared through partitioning. Other resources (e.g., general internal registers, page table base register(s), low-level data cache and data-TLB 1915, execution unit(s) 1940, and portions of out-of-order unit 1935) may be fully shared.

[0134] Processor 1900 typically includes other resources that may be fully shared, shared through partitioning, or dedicated by / to processing elements. Fig.19 , an embodiment of a purely exemplary processor with illustrative logical units / resources of a processor is shown. It should be noted that the processor may include or omit one or more of these functional units, and include any other known functional units, logic, or firmware not depicted. As shown, core 1901 includes a simplified, representative out-of-order (OOO) processor core. However, sequential processors may be utilized in different embodiments. The OOO core includes a branch target buffer 1920 for predicting branches to be executed / adopted, and an instruction translation buffer (I-TLB) 1920 for storing address translation entries for instructions.

[0135] The core 1901 also includes a decoding module 1925 coupled to the extraction unit 1920 to decode the extracted elements. In one embodiment, the extraction logic includes an independent sequencer associated with the thread slots 1901a, 1901b, respectively. Typically, the core 1901 is associated with a first ISA, which defines / specifies instructions executable on the processor 1900. Typically, a machine code instruction as part of the first ISA typically includes a portion of the instruction (called an opcode) that references / specifies the instruction or operation to be performed. The decoding logic 1925 includes circuits that recognize these instructions from the opcode of the instruction and pass the decoded instructions in the pipeline to be processed as defined by the first ISA. For example, as discussed in more detail below, in one embodiment, the decoder 1925 includes logic designed or adapted to recognize specific instructions such as transactional instructions. Due to the decoder 1925 recognition, the architecture or core 1901 takes specific, predefined actions to perform tasks associated with the appropriate instructions. It is important to note that one or more of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of these instructions may be new or old instructions. In one embodiment, it should be noted that decoder 1926 recognizes the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoder 1926 recognizes a second ISA (a subset of the first ISA or a different ISA).

[0136] In one example, the allocator and renamer block 1930 includes an allocator for reserving resources (e.g., a register file for storing instruction processing results). However, threads 1901a and 1901b may be capable of out-of-order execution, where the allocator and renamer block 1930 also reserves other resources, such as a reorder buffer for tracking instruction results. Unit 1930 may also include a register renamer that is used to rename program / instruction reference registers to other registers located inside processor 1900. Reorder / retirement unit 1935 includes components for supporting out-of-order execution and later in-order retirement of instructions executed out of order, such as the reorder buffer, load buffer, and store buffer mentioned above.

[0137] In one embodiment, the (one or more) scheduler and execution unit block 1940 includes a scheduler unit for scheduling instructions / operations on execution units. For example, a floating point instruction is scheduled on a port of an execution unit with an available floating point execution unit. A register file associated with the execution unit is also included to store information instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

[0138] A lower level data cache and data translation buffer (D-TLB) 1950 is coupled to the execution unit(s) 1940. The data cache is used to store recently used / operated elements, e.g., data operands, which may be kept in a memory consistency state. The D-TLB is used to store recent virtual / linear to physical address translations. As a specific example, the processor may include a page table structure for decomposing physical memory into multiple virtual pages.

[0139] Here, core 1901 and core 1902 share access to a higher level or further-out cache, such as a second level cache associated with on-chip interface 1910. It should be noted that higher level or further-out refers to cache levels increasing or further-out from the execution unit(s). In one embodiment, the higher level cache is a last level data cache - the last cache in the memory hierarchy on processor 1900. However, the higher level cache is not limited to this and may be associated with or include an instruction cache. A trace cache - an instruction cache - may instead be coupled after decoder 1925 to store recently decoded traces. Here, an instruction may refer to a macroinstruction (i.e., a general instruction recognized by a decoder), which may be decoded into multiple microinstructions (micro-operations).

[0140] In the configuration depicted, the processor 1900 also includes an on-chip interface module 1910. Historically, memory controllers, described in more detail below, have been included in computing systems external to the processor 1900. In this case, the on-chip interface 1910 is used to communicate with devices external to the processor 1900, such as system memory 1975, a chipset (typically including a memory controller hub for connecting to the memory 1975 and an I / O controller hub for connecting to peripheral devices), a memory controller hub, a north bridge, or other integrated circuits. And in this case, the bus 1905 may include any known interconnect, such as a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

[0141] Memory 1975 may be dedicated to processor 1900 or shared with other devices in the system. Examples of common types of memory 1975 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. It should be noted that device 1980 may include a graphics accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I / O controller hub, a wireless transceiver, a flash memory device, an audio controller, a network controller, or other known devices.

[0142] However, recently, as more logic and devices are integrated on separate dies such as SOCs, each of these devices can be incorporated into the processor 1900. For example, in one embodiment, a memory controller hub is on the same package and / or on a die with the processor 1900. Here, a portion 1910 of the core (on-core portion) includes one or more controllers for interfacing with other devices (e.g., memory 1975 or graphics device 1980). A configuration including an interconnect and a controller for interfacing with such devices is generally referred to as an on-core (or un-core configuration). As an example, the on-chip interface 1910 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 1905 for off-chip communication. However, in a SOC environment, even more devices such as a network interface, a coprocessor, memory 1975, a graphics processor 1980, and any other known computer devices / interfaces can be integrated on a separate die or integrated circuit to provide a small form factor with high functionality and low power consumption.

[0143] In one embodiment, processor 1900 can execute compiler, optimization and / or converter code 1977 to compile, convert and / or optimize application code 1976 to support the device and method described herein or interface with it. Compiler generally includes a program or assembly that converts source text / source code into target text / target code. Usually, compiler compiler / application code is completed in multiple stages and multi-pass (pass) to convert high-level programming language code into low-level machine or assembly language code. However, single-pass compiler can still be used for simple compilation. Compiler can utilize any known compilation technology and perform any known compiler operation, for example, lexical analysis, preprocessing, parsing, semantic analysis, code generation, code conversion and code optimization.

[0144] Larger compilers typically include multiple phases, but most often these phases are included in two general phases: (1) the front end, i.e., where syntactic processing, semantic processing, and some transformations / optimizations may typically occur, and (2) the back end, i.e., where analysis, conversion, optimization, and code generation typically occur. Some compilers refer to the middle stage, which illustrates the ambiguity between the front end and back end of the compiler. Thus, references to the insertion, association, generation, or other operations of the compiler may occur in any of the above phases or passes, as well as any other known phases or passes of the compiler. As an illustrative example, the compiler may insert operations, calls, functions, etc., in one or more phases of compilation, for example, inserting calls / operations in the front end phase of compilation, and then converting the calls / operations to lower level code during the conversion phase. It should be noted that during dynamic compilation, compiler code or dynamic optimization code may insert such operations / calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (compiled code) may be dynamically optimized during runtime. Here, program code may include dynamic optimization code, binary code, or a combination thereof.

[0145] Similar to compilers, translators such as binary translators statically or dynamically translate code to optimize and / or convert code. Thus, references to the execution of code, application code, program code, or other software environment may refer to: (1) the execution of a compiler(s), an optimizing code optimizer, or a translator for dynamically or statically compiling program code, maintaining software structure, performing other operations, optimizing code, or converting code; (2) the execution of a main program code including operations / calls, such as application code that has been optimized / compiled; (3) the execution of other program code (e.g., a library) associated with the main program code to maintain software structure, to perform operations related to other software, or to optimize code; or (4) a combination of the above.

[0146] Reference now Fig. 20 , shows a block diagram of an embodiment of a multi-core processor. Fig. 20 As shown in the embodiment of FIG. 2 , the processor 2000 includes multiple domains. Specifically, the core domain 2030 includes multiple cores 2030A- 2030N, the graphics domain 2060 includes one or more graphics engines with a media engine 2065 , and the system agent domain 2010 .

[0147] In various embodiments, system agent domain 2010 handles power control events and power management so that independent units (e.g., cores and / or graphics engines) of domains 2030 and 2060 are independently controllable to dynamically operate in appropriate power modes / levels (e.g., active, turbo, sleep, hibernate, deep sleep or other advanced configuration power interface states) based on the activity (or inactivity) occurring in a given unit. Each of domains 2030 and 2060 can operate at different voltages and / or powers, and in addition, independent units within a domain may all operate at independent frequencies and voltages. It should be noted that although only three domains are shown, it should be understood that the scope of the present invention is not limited thereto, and additional domains may be present in other embodiments.

[0148] As shown, in addition to the various execution units and additional processing elements, each core 2030 also includes a low-level cache. Here, the various cores are coupled to each other and to a shared cache memory formed by multiple units or fragments of the last level cache (LLC) 2040A-2040N; these LLCs typically include storage and cache controller functions, and these LLCs are shared between cores and possibly between graphics engines.

[0149] As shown, a ring interconnect 2050 couples the cores together and provides interconnections between the core domain 2030, the graphics domain 2060, and the system agent circuitry 2010 via a plurality of ring stops 2052A-2052N, each of which is located between a core and an LLC segment. Fig. 20 As shown, interconnect 2050 is used to carry various information, including address information, data information, confirmation information, and snoop / invalidation information. Although a ring interconnect is shown, any known on-die interconnect or structure can be utilized. As illustrative examples, some of the structures discussed above (e.g., another on-die interconnect, a system-on-chip structure (OSF), an advanced microcontroller bus architecture (AMBA) interconnect, a multi-dimensional mesh structure, or other known interconnect architectures) can be utilized in a similar manner.

[0150] As further depicted, the system agent domain 2010 includes a display engine 2012 for providing control and interface to an associated display. The system agent domain 2010 may include other units, such as: an integrated memory controller 2020 for providing an interface to system memory (e.g., DRAM implemented through multiple DIMMs); ​​consistency logic 2022 for performing memory consistency operations. There may be multiple interfaces to enable interconnection between the processor and other circuits. For example, in one embodiment, at least one direct media interface (DMI) 2016 interface and one or more PCIeTM Interface 2014. The display engine and these interfaces are usually connected via PCIe TM The bridge 2018 is coupled to the memory. Additionally, one or more other interfaces may be provided to provide communications between other agents (such as additional processors or other circuits).

[0151] Reference now Fig.21 , shows a block diagram of a representative core; in particular, the logic blocks of the back end of the core, such as Fig. 20 of core 2030. Usually, Fig.21 The illustrated architecture includes an out-of-order processor having a front end unit 2170 for fetching incoming instructions, performing various processing (e.g., caching, decoding, branch prediction, etc.) and passing the instructions / operations along an out-of-order (OOO) engine 2180. The OOO engine 2180 performs further processing on the decoded instructions.

[0152] Specifically, in Fig.21 In an embodiment of the invention, the out-of-order engine 2180 includes an allocation unit 2182 for receiving decoded instructions from the front end unit 2170, which may be in the form of one or more micro-instructions or micro-instructions, and allocating them to appropriate resources, such as registers, etc. Next, the instructions are provided to a reservation station 2184, which reserves resources and schedules them to be executed on one of a plurality of execution units 2186A-2186N. There may be various types of execution units, including, for example, an arithmetic logic unit (ALU), a load and store unit, a vector processing unit (VPU), a floating point execution unit, etc. The results from these different execution units are provided to a re-order buffer (ROB) 2188, which takes the out-of-order results and returns them to correct the program order.

[0153] Still reference Fig.21 , it should be noted that both the front end unit 2170 and the out-of-order engine 2180 are coupled to different levels of the memory hierarchy. Specifically shown is the instruction level cache 2172, which is in turn coupled to the mid-level cache 2176, which is in turn coupled to the final level cache 2195. In one embodiment, the final level cache 2195 is implemented in an on-chip (sometimes referred to as an uncore) unit 2190. As an example, the unit 2190 is similar to Fig. 20As described above, the uncore 2190 communicates with the system memory 2199, which in the illustrated embodiment is implemented via ED RAM. It should also be noted that the various execution units 2186 within the out-of-order engine 2180 communicate with the first level cache 2174, which also communicates with the mid-level cache 2176. It should also be noted that additional cores 2130N-2-2130N may be coupled to the LLC 2195. Although shown at a high level, Fig.21 It should be understood that there may be various changes and additional components.

[0154] Go to Fig. 22 , a block diagram of an exemplary computer system formed using a processor including an execution unit for executing instructions, wherein one or more of the interconnections for implementing one or more features according to one embodiment of the present invention are shown. According to the present invention, for example, in the embodiments described herein, the system 2200 includes a component such as a processor 2202, which is used to use an execution unit including logic for executing an algorithm for processing data. The system 2200 represents an example of a computer system based on PENTIUM III. TM 、PENTIUM 4 TM , Xeon TM , Itanium, XScale TM and / or StrongARM TM The sample system 2200 may be used with a processing system based on a microprocessor, but other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In one embodiment, the sample system 2200 executes WINDOWS 1000 available from Microsoft Corporation of Redmond, Washington. TM The operating system may be a version of the system, but other operating systems (eg, UNIX and Linux), embedded software and / or graphical user interfaces may also be used. Thus, embodiments of the present invention are not limited to any specific combination of hardware circuitry and software.

[0155] Embodiments are not limited to computer systems. Alternative embodiments of the present invention may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include microcontrollers, digital signal processors (DSPs), systems on chips, network computers (NetPCs), set-top boxes, network centers, wide area network (WAN) switches, or any other system that may execute one or more instructions according to at least one embodiment.

[0156] In the illustrated embodiment, the processor 2202 includes one or more execution units 2208 to implement an algorithm for executing at least one instruction. An embodiment can be described in the context of a separate processor desktop or server system, but an alternative embodiment can be included in a multi-processor system. System 2200 is an example of a "center" system architecture. Computer system 2200 includes a processor 2202 for processing data signals. As an illustrative example, processor 2202 includes a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor that implements a combination of instruction sets, or any other processor device (e.g., a digital signal processor). Processor 2202 is coupled to a processor bus 2210, which transmits data signals between processor 2202 and other components in system 2200. Elements of system 2200 (e.g., graphics accelerator 2212, memory controller hub 2216, memory 2220, I / O controller hub 2224, wireless transceiver 2226, flash BIOS 2228, network controller 2234, audio controller 2236, serial expansion port 2238, I / O controller 2240, etc.) perform conventional functions well known to those skilled in the art.

[0157] In one embodiment, the processor 2202 includes a level 1 (L1) internal cache memory 2204. Depending on the architecture, the processor 2202 may have a single internal cache or multiple levels of internal cache. Other embodiments include a combination of both internal and external caches depending on the specific implementation and needs. Register file 2206 is used to store different types of data in various registers (including integer registers, floating point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers).

[0158] An execution unit 2208 including logic for performing integer and floating point operations also resides in the processor 2202. In one embodiment, the processor 2202 includes a microcode (ucode) ROM for storing microcode, which, when executed, is used to execute algorithms for some macroinstructions or handle complex scenarios. Here, the microcode may be updateable to handle logic errors / repairs for the processor 2202. For one embodiment, the execution unit 2208 includes logic for processing a compressed instruction set 2209. By including the compressed instruction set 2209 in the instruction set of the general-purpose processor 2202 and the associated circuits for executing instructions, operations used by multiple multimedia applications can be performed using compressed data in the general-purpose processor 2202. Therefore, multiple multimedia applications are accelerated and executed more efficiently by using the full width of the processor data bus to perform operations on compressed data. This may eliminate the need for smaller units of data to be transmitted across the data bus of the processor to perform one or more operations (one data element at a time).

[0159] Alternative embodiments of execution unit 2208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 2200 includes memory 2220. Memory 2220 includes a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or other storage device. Memory 2220 stores instructions and / or data represented by data signals to be executed by processor 2202.

[0160] It should be noted that one or more of the above-mentioned features or aspects of the present invention can be utilized in Fig. 222202, implements one or more aspects of the present invention as described above. Alternatively, the present invention is associated with a processor bus 2210 (e.g., other known high-performance computing interconnects), a high-bandwidth memory path 2218 to a memory 2220, a point-to-point link to a graphics accelerator 2212 (e.g., a Peripheral Component Interconnect Express (PCIe) conforming to the architecture), a controller hub interconnect 2222, an I / O or other interconnect (e.g., USB, PCI, PCIe) to couple other components shown. Some examples of these components include an audio controller 2236, a firmware hub (flash BIOS) 2228, a wireless transceiver 2226, a data storage 2224, a conventional I / O controller 2210 including a user input and keyboard interface 2242, a serial expansion port 2238 (e.g., a universal serial bus (USB)), and a network controller 2234. The data storage device 2224 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0161] Reference now Fig.23 , shows a block diagram of a second system 2300 according to an embodiment of the present invention. Fig.23 As shown, multiprocessor system 2300 is a point-to-point interconnect system and includes a first processor 2370 and a second processor 2380 coupled via a point-to-point interconnect 2350. Each of processor 2370 and processor 2380 can be a certain version of a processor. In one embodiment, 2352 and 2354 are part of a serial, point-to-point coherent interconnect structure, such as a high-performance architecture. Therefore, the present invention can be implemented within a QPI architecture.

[0162] Although only two processors 2370, 2380 are shown, it should be understood that the scope of the present invention is not limited in this regard. In other embodiments, one or more additional processors may be present in a given processor.

[0163] Processor 2370 and processor 2380 are shown to include integrated memory controller unit 2372 and integrated memory controller unit 2382, respectively. Processor 2370 also includes point-to-point (PP) interface 2376 and point-to-point (PP) interface 2378 as part of its bus controller unit; similarly, second processor 2380 includes PP interface 2386 and PP interface 2388. Processors 2370 and 2380 can exchange information via point-to-point (PP) interface 2350 using PP interface circuit 2378 and PP interface circuit 2388. Fig.23As shown, IMC 2372 and IMC 2382 couple the processors to respective memories, namely, memory 2332 and memory 2334, which may be portions of main memory locally attached to the respective processors.

[0164] Processor 2370 and processor 2380 exchange information with chipset 2390 via separate PP interfaces 2352 and 2354 using point-to-point interface circuit 2376, point-to-point interface circuit 2394, point-to-point interface circuit 2386, and point-to-point interface circuit 2398, respectively. Chipset 2390 also exchanges information with high-performance graphics circuit 2338 via interface circuit 2392 and along high-performance graphics interconnect 2339.

[0165] A shared cache (not shown) may be included in either processor or external to both processors; but still connected to the processors via the PP interconnect so that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0166] Chipset 2390 may be coupled to first bus 2316 via interface 2396. In one embodiment, first bus 2316 may be a peripheral component interconnect (PCI) bus, or a bus such as a PCI Express bus or other third generation I / O interconnect bus, but the scope of the present invention is not so limited.

[0167] like Fig.23 As shown, various I / O devices 2314 are coupled to first bus 2316 and a bus bridge 2318 that couples first bus 2316 to a second bus 2320. In one embodiment, second bus 2320 comprises a low pin count (LPC) bus. In one embodiment, various devices are coupled to second bus 2320 including, for example, a keyboard and / or mouse 2322, communication devices 2327, and a storage unit 2328 (e.g., a disk drive or other mass storage device that typically includes instructions / code and data 2330). Additionally, audio I / O 2324 is shown as being coupled to second bus 2320. It should be noted that other architectures are possible, in which the components and interconnect architectures involved vary. For example, instead of Fig.23 Instead of a point-to-point architecture, the system can implement a multi-point bus or other such architecture.

[0168] Next go to Fig.24, depicts an embodiment of a system on chip (SOC) design according to the invention. As a specific illustrative example, the SOC 2400 is included in a user equipment (UE). In one embodiment, UE refers to any device used by an end user for communication, such as a handheld phone, a smart phone, a tablet computer, an ultra-thin notebook, a notebook with a broadband adapter, or any other similar communication device. Typically, a UE is connected to a base station or node, which may correspond in nature to a mobile station (MS) in a GSM network.

[0169] Here, SOC 2400 includes two cores - 2406 and 2407. Similar to the discussion above, core 2406 and core 2407 may conform to an instruction set architecture (e.g., based on Architecture Core TM , Advanced Micro Devices (AMD) processors, MLP-based processors, ARM-based processor designs, or their customers), and their licensors or users. Core 2406 and core 2407 are coupled to a cache control 2408 associated with a bus interface unit 2409 and an L2 cache 2411 for communicating with other parts of the system 2400. Interconnect 2410 includes an on-chip interconnect (such as IOSF, AMBA, or other interconnects discussed above), which may implement one or more aspects described herein.

[0170] The interface 2410 provides communication channels to other components, such as a subscriber identity module (SIM) 2430 for interfacing with a SIM card, a boot ROM 2435 for holding boot code for execution by the cores 2406 and 2407 to initialize and boot the SOC 2400, an SDRAM controller 2440 for interfacing with an external memory (e.g., DRAM 2460), a flash controller 2445 for interfacing with a non-volatile memory (e.g., flash memory 2465), a peripheral control 2450 (e.g., a serial peripheral interface) for interfacing with peripheral devices, a video codec 2420 and a video interface 2425 for displaying and receiving input (e.g., touch-enabled input), a GPU 2415 for performing graphics-related calculations, etc. One or more of these interfaces may be combined with aspects of the invention described herein.

[0171] In addition, the system shows peripheral devices for communication, such as Bluetooth module 2470, 3G modem 2475, GPS 2485, and WiFi 2485. As described above, the UE includes a radio for communication. Therefore, not all of these peripheral communication modules are required. However, in some forms of the UE, a radio for external communication will be included.

[0172] Figure 25-27 An example of data encoding without a dedicated STREAM path is disclosed. In embodiments of the interface described herein, a "STREAM" path may be provided to distinguish Intra-chip interconnect (IDI) business and On-chip system framework (IOSF) services, both are provided at the link layer. Link control packets (LCPs) at the PHY layer may also need to be marked. In one embodiment, one flow path is provided in each cluster of 20 data paths.

[0173] However, in some embodiments, an interface may be provided without a dedicated STREAM path. For example, to provide equivalent functionality, STREAM path data may be provided within the data path during idle cycles. Because one stream path may be provided in every 20 data paths, the elimination of the stream path saves approximately 5% of area.

[0174] In one embodiment, during the pre-data time, 20 data lanes from the middle rail may be driven high to represent one data type and the same 20 data lanes may be driven low to represent a second data type (e.g., On-Chip System Architecture (IOSF). To represent additional data types such as Link Control Packets (LCPs), the lanes may be divided into two or more groups and a separate bit may be encoded into each group. LCPs may also be encoded into post-data time, for example, by stopping microchip traffic and controlling the "VALID" lane from the mid-rail to 0 or 1.

[0175] There are a number of ways to accomplish this. Fig.25 In FIG. 2 , arrow 2510 marks an example pre-data symbol time, and arrow 2520 marks an example post-data symbol time. Fig.25 In the example of FIG. 1 , in addition to the data paths (which may be provided in groups of n paths each (where n=20 in one example)), a "STROBE" path may be provided, and each group may include a "VALID" path. The "STREAM" path is also disclosed by way of example to illustrate that signaling may be required in the absence of the teachings of this specification. Fig.26 and 27 The method can eliminate the STREAM path, providing approximately 5% space savings in one embodiment.

[0176] During the pre-data period, for example, the data paths of the middle rail in a tridata scheme remain idle. However, they can be driven to 0 or 1 without loss of electrical integrity. Therefore, the idle data paths are useful for encoding streaming data without a separate streaming path.

[0177] In one embodiment, it is only necessary to distinguish IOSF from IDI in the pre-data period. Therefore, all paths can be driven high or low to indicate one of the two possibilities. However, the present specification is not limited to this. It is also possible to provide k bits of stream data by dividing the data stream into k groups and driving a value onto each group to indicate 2 k These groups can be of uniform size, but this is not required. If no paths are needed, they may be idle in the mid-rail state.

[0178] It is also possible to use only k paths instead of grouping. However, the use of grouping provides redundancy which is beneficial to embodiments where reliability is superior to various other embodiments.

[0179] Post data may also be provided for encoding LCP packets. This is useful because in situations where the link layer provides only two types of packets (e.g., IOSF and IDI), the data path can receive uniform values, while the LCP is encoded separately. Encoding post LCP data is possible because, in some embodiments, LCP always takes precedence over microslices. When an agent needs to send LCP on the PHY, it can terminate microslice traffic by providing back pressure on the link layer.

[0180] Similar to the manner in which multiple link layer types can be provided as described above, different types of LCPs can be encoded onto the paths during the symbol time of the post-data period. For example, "00" on paths 0 and 1 can be requested to enter hardware re-centering. This situation may occur when cyclic redundancy check (CRC) errors are encountered at a higher than expected rate, causing one of the agents to determine that the link needs to be retrained so that the clock can be properly "centered". In the example, "01" can be the ACK for the request. These are provided by way of non-limiting examples only, and it should be noted that many different LCP requests and responses can be usefully encoded in the scheme. In addition, as described above, encoding the same value on multiple paths can help reduce errors. In an embodiment, keeping the path at the middle rail indicates that no LCP is sent.

[0181] Furthermore, in some embodiments, it may be desirable to send an LCP in the quiet time after the post-data period. To this end, for example, the VALID path may be pulled to 0 just before the LCP is sent. During the quiet period, the VALID path may remain at the mid-rail elsewhere.

[0182] In some embodiments, STROBE, VALID and STREAMID of all clusters can be driven identically to each other. In other embodiments, they can be driven separately to provide enhanced capabilities, for example, re-centering only a separate cluster, while other clusters continue to receive normal business.

[0183] Fig.26 26 is a flow chart illustrating a method 2600 of providing embedded flow path data. Fig.26 In the example, pre-data encoding is used.

[0184] In block 2610, a flow channel encoder encodes a flow channel identifier or a category identifier to identify the category of data to be tracked.

[0185] In block 2620, still in Fig.25 During the pre-data time shown, the channel driver drives the encoded category identifier onto the data channel. In some embodiments, where multiple bits of flow channel identifiers are required, this can include dividing the data channel into an appropriate number of groups. For example, if there are 20 channels and four bits are required to represent up to 16 data categories, the data channel can be divided into four groups of five channels per group. In each group, all five channels will be driven to the same state. In the case of an extra channel that cannot receive a value, the extra channel may be left at the middle rail.

[0186] The pre-data period expires in block 2630. The data path must now be freed for substantive data use.

[0187] In block 2640, the lane driver drives the substantive data onto the data lane.

[0188] In box 2690, the method is completed.

[0189] Fig. 27 is a flow chart illustrating a method 2700 of providing additional post-data stream information (eg, LCP signal).

[0190] In block 2710, a flow channel encoder encodes a flow channel identifier or a category identifier to identify the category of data to be tracked.

[0191] In block 2720, still in Fig.25During the pre-data time shown, the channel driver drives the encoded category identifier onto the data channel. In some embodiments, where multiple bits of flow channel identifiers are required, this can include dividing the data channel into an appropriate number of groups. For example, if there are 20 channels and four bits are required to represent up to 16 data categories, the data channel can be divided into four groups of five channels per group. In each group, all five channels will be driven to the same state. In the case of an extra channel that cannot receive a value, the extra channel may be left at the middle rail.

[0192] The pre-data period expires in block 2730. The data path must now be freed for substantive data use.

[0193] In block 2740, the lane driver drives the substantive data onto the data lane.

[0194] The data cycle ends in block 2750. The data path can now be used again as a stream identifier.

[0195] In block 2760, for example, agent A determines that it is required to provide LCP. Therefore, agent A stops sending flits.

[0196] In block 2770, the stream encoder encodes the LCP. For example, code for application "RECENTER" may be provided, and code for agent B ( Figure 3 ) to provide an "ACK" to the request. Additional LCP codes are also available.

[0197] The path driver drives the LCP code onto the datapath in block 2780. Both agents then perform the requested actions.

[0198] In box 2790, the method is completed.

[0199] Figure 28-30 Shown as Fig.17 One embodiment of a centered state is shown. In this embodiment, when the interface is brought up from a powered down state, the link must be "trained" to operate at full speed. Training is necessary because values ​​can "drift" over time and between different conditions (such as temperature). Especially with high speed links like PCIe, it is necessary to properly center the signal in both the time domain (horizontal) and the voltage domain (vertical) to avoid bit errors that can be caused by parameter drift.

[0200] Training can include "centering" or "re-centering" the clock signal to ensure that the signal is properly centered in both the time and voltage domains. At any given speed, the clock has a window in which samples of the data path will produce the correct value. Sampling outside the window may produce bit errors. The faster the clock, the smaller the window. In increasing complexity, there are separate windows for vertical Vref centering and horizontal phase centering. Therefore, in one example, and particularly in high-speed interconnects with narrow windows, an important aspect of training is adjusting both the Vref and the phase of the clock so that the data is sampled at or near the center of the window to minimize bit errors.

[0201] In one example, training includes supplying a known value such as a PRBS to the interface and then sampling the return bit pattern. After sampling, the clock can be shifted vertically in the voltage domain (Vref) or horizontally in the time domain (phase). The interface detects when bit errors begin to occur, thereby constructing a two-dimensional "eye", which can be substantially diamond-shaped. In simple terms, values ​​within the eye cause no (or acceptably few) bit errors, while values ​​outside the eye cause an unacceptable number of bit errors.

[0202] Centering can include a combination of both hardware and software. In some embodiments, software centering can be run from a basic input-output system (BIOS) chip. In one example, hardware is provided for basic or initial centering operations, which can provide a rough centering solution. Software can then be used to supplement and improve the initial centering. Software centering provides additional flexibility and, in some cases, greater programmability of logic than hardware centering. This can solve problems such as, for example, hardware centering finding that it thinks content is "near center" for the eye, when in fact a closer center can be obtained via additional steps / processes.

[0203] In one example, the hardware includes 32 quantized delay settings for phase adjustment, but any number of quantized delay settings may be provided. re f Settings can be quantized similarly.

[0204] In the first (hardware only) stage, centering may include a sweep of the quantized phase settings across each path at a nominal voltage V (e.g., original value or last calculated value). After each sweep, the error detector lists the number of errors (if any) encountered in each step / pass.

[0205] The error detection in this embodiment is an example of transmitter (Tx) adaptation, i.e., the Tx value is adjusted based on the remote receiver (Rx) metrics available to Tx on the reverse channel. Software running on a core on the upstream die can use sideband (see Figure 6 ) accesses the local die and the remote die, which serves as the reverse channel. In HPI, since the reverse channel is not on the same wire as the link layer, this adaptation occurs in both directions simultaneously.

[0206] In an embodiment, each scan is aggregated. Therefore, rather than scoring the number of errors on any one path, the scan scores the number of errors across all paths. This means that in some cases, the best settings for an individual path may not be the best for the interconnect as a whole. This phase scan can be performed in hardware at initial startup and can be used to perform a rough centering, where an approximate center phase is selected. In an embodiment, the phase scan is performed at full speed so that The value of is suitable for full speed operation. In other embodiments, the initial hardware scan may be performed first at a partial speed (eg, at half speed) and then improved at full speed.

[0207] After the phase scan is complete, the interface is placed at full speed (if necessary) and software instructions can be loaded from the BIOS to continue improving the centering in software. In this second phase (performed in software in one example), the voltage (V ref ) values ​​are similarly swept across the quantization settings. Each sweep can be In other words, each path utilizes the voltage The phase setting at V ref Sweep to determine the optimum V ref The offset σ is then incremented (e.g., by 1) and on either side (e.g. ) ref If the eye is not yet fully defined, σ can be increased again, and the process can be repeated until the eye is fully defined (see Fig.30 ), which occurs when V max ≈V min (Wherein, V max For the selected The maximum phase with an acceptable error rate is at V min is in the selected In one embodiment, the minimum phase with an acceptable error rate is selected.

[0208] As with the phase sweep, each voltage sweep results in zero or more errors, and at each V ref The results at the values ​​are aggregated across all paths. In an embodiment, V is executed at an operational speed (in one example, 8Ghz). ref Scan to ensure the results are valid for actionable speeds.

[0209] In the third stage, the software can construct a two-dimensional "eye" including a center point based on the values ​​identified in the first two stages. The eye can be a diamond or other suitable shape. It may be meaningful to determine the best center of the eye because the eye opening may be asymmetric around the major inflection point, non-monotonic, and somewhat time-varying. Therefore, eye centering can be performed in the software. In one example, centering includes finding and The value of and the midpoint between these two, and V max and V min The software can calculate the recommended center based on the midpoint.

[0210] The software can then select four inflection points along the edge of the diamond and generate a grid at the inflection points and along the four vertices of the diamond (located at V max 、V min , and If the eye has been built and properly centered, then these eight points should all fall exactly within the eye and should therefore have an acceptable error rate. If one or more of the eight points result in an unacceptable error rate, then the eye may need to be adjusted to improve performance. For example, if the inflection point fails, then the boundaries of the eye may need to be adjusted inwards by one quantum on one or both axes. The new value would then need to be similarly tested to ensure that it passes. When the points are adjusted accordingly, the center Can also be adjusted accordingly.

[0211] By providing Fig.29A and 29BThe crosstalk pattern shown is used to enhance the error detection described in one or more of the above stages. In this example, it can be seen that the test of a path includes: selecting the tested path as the "victim" path. A test pattern (including, for example, PRBS) can be driven on this path. The adjacent path and up to l paths in the distance (in this example, l=4) are "aggressor" paths. These paths receive the crosstalk pattern, which in this case is the logical inversion of the test pattern, thereby approximating the "worst case" scenario. The remaining paths are neutral parties. This test pattern is particularly helpful in centering the eye, because at this stage it is important to detect edge cases and ensure that they are reasonably within the eye.

[0212] Fig.28 A centering flow chart as described in this specification is provided.

[0213] In block 2810, the interconnect wakes up, for example, to start up after the machine has been shut down.

[0214] In block 2820, the interconnect performs initial voltage centering as described above. This may include performing a voltage scan in hardware and selecting the setting that results in the fewest total bit errors.

[0215] In block 2840, once the coarse voltage centering is completed in hardware (if voltage centering was done at a reduced speed (eg, at half speed)), the interface may be placed at its full speed.

[0216] In block 2850, phase centering is performed (e.g., in software). In some examples, the software may also improve voltage centering as described herein. As described above, phase centering in one embodiment includes scanning each voltage V 0 ±σ phase In other words, a voltage is selected and the phase is swept at that voltage.

[0217] In box 2870, the eye is built in software.

[0218] In block 2880, eye centering is performed. As described above, in one embodiment, this includes selecting four vertices and four inflection points, and stress testing each point to determine if it passes. If a point fails, the vertex or inflection point can be adjusted inward and tested again. Eye Center Can also be adjusted accordingly.

[0219] Fig.29A and 29BAn example victim / aggressor test pattern as described above is shown. In this example, up to four paths above or below the victim (tested) path are filled with the aggressor pattern. The remaining paths are neutral. In an embodiment, the aggressor pattern is the exact bitwise inversion of the PRBS test pattern on the victim path.

[0220] Fig.30 is an illustration of an example of an eye 3000. In this illustration, the eye 3000 is a suitable rhombus shape for the sake of illustrating some important features. However, the features of the eye 3000 need not, and generally will not, be normal or monotonous. The rhombus defined by the eye 3000 may be tilted left, right, up, or down, and the edges need not consist of perfectly collinear straight lines. This is particularly true once the eye 3000 is centered.

[0221] In this example, the eye 3000 initially scans each V across multiple phase quanta. ref Select 3010 to define to identify the V ref Select the two phase endpoints 3020. The sweep can be from V 0 3034 starts and proceeds in the above and below quantization steps until V max 3030 and V min 3032 is identified. In this example, 3042 and 3040 all appear in V 0 line, but in reality one or both may appear on some other line and need not appear on the same line.

[0222] Inflection point 3050 is also selected. In this example, V 0 To V max An odd number of quanta is included so that inflection points 3050-1 and 3050-2 can be chosen at a "real" center point between the two. However, V 0 To V min An even number of quanta is included so that the inflection points 3050-3 and 3050-4 must be chosen off center. These can be chosen by a floor function, a ceiling function, or can be chosen on either side of the interval depending on design choice.

[0223] You can also select the initial center Again, since these values ​​are quantized, this may not be the geometric center, but may be offset from the center by one or more quanta in any direction. During centering, V max 3030, V min 3032, 3042, 3040, and inflection point 3050 are used as test points. As a result of the test, one or more of these points may be adjusted up or down, left or right by one or more quanta to make the shape of eye 3000 more irregular. When the test points are adjusted, the center Adjustments can be made as needed. Once centering is complete, all paths are set to phase and voltage values ​​to ensure optimal operation.

[0224] Fig.31 is a flow chart of an eye centering method 3100 according to one or more examples of the present specification. Some embodiments of the method 3100 may be performed in software, but the method may also be performed in hardware, or in a combination of hardware and software.

[0225] In block 3110, the software selects test points, e.g., Fig.30 V max 3030, V min 3032, 3042, 3040 and turning point 3050.

[0226] In block 3120, the software uses Fig.29A and 29B The victim / aggressor pathways are pressure tested at each test point on each pathway.

[0227] In decision block 3130, if all points pass, then in block 3150, the phase and voltage at the center of the eye may be used. to set up all pathways.

[0228] In block 3140, if not all points pass, the failed points can be adjusted inward. Control then passes to block 3120 to test (one or more) new points. This continues iterating until all points have passed and the data path has been properly configured in block 3150.

[0229] In box 3190, the method is completed.

[0230] In some examples, an operation known as "re-centering" may also occur as needed. For example, re-centering may be required when an unacceptable number of errors occur during operation. In one example, the unacceptable error rate is more than about 10 12 A cyclic redundancy check (CRC) error in one of the bits. When this occurs, the microchip stops and the phits take over the interconnect to perform the phase scan in hardware (the software may not be available because the machine is running, so the BIOS cannot be loaded).

[0231] Recentering may take several microseconds, which is unacceptably slow for periodic recentering in high-speed interconnects. Therefore, in one embodiment, recentering occurs only when an error tracker in the interface link layer detects that the number of CRC errors received in a time span is greater than a threshold. For example, every 10 12 Bit-one CRC errors may be acceptable. But more may be indicative of a true error. Therefore, the receiving agent can send a sideband message to inform the transmitting agent that a re-centering is required. When this occurs, the sending agent acknowledges the message, and the two agents enter into a re-centering.

[0232] The message on the sideband may be a link control packet (LCP), which is a special class of packets sent on the interface sideband. The sideband may operate at a speed orders of magnitude slower than the link layer. For example, the interface sideband may operate at 100 to 400 MHz.

[0233] Some interface designs may choose to perform low frequency or continuous CDR tracking using signaling on the data path, which consists of flits / packets scrambled with PRBS 23. During quiet periods, when there are not enough packets on the data path, the PHY inserts dummy LCPs so that this tracking can be maintained.

[0234] Now go to Figure 32-34 In some embodiments, it may be beneficial to design a system in stages by first designing low-order blocks and then aggregating the low-order blocks into functional elements. An intellectual property (IP) block (or "computational block") may refer to a reusable unit of logic, circuitry, or chip layout. For example, a SoC may include multiple IP blocks, including multiple instances of the same IP block. In some instances, an IP block may support multiple functions, which in some cases are implemented by one or more devices included in the IP block. A system may be designed by defining a collection of IP blocks to implement the system. For example, a team may design a low-level functional block and make the block available to other teams, which serves as a drop-in component for subsequent designs. In this type of multi-layer design process, it is beneficial to provide some functions as "hard IP blocks" or "hard IP" (meaning that the IP block has a fixed route that may not change during a higher-level design). Hard IP blocks may include, for example, analog components that are sensitive to routing changes. For some analog components, rerouting may result in changes in impedance or capacitance, which may affect the functionality of some sensitive analog components. Therefore, the development team responsible for designing the hard IP block can optimize these parameters and ensure that each of the components operates within acceptable parameters. Once the routing is fixed, it should not be changed by downstream designers.

[0235] Other IP blocks may be provided as "soft IP". Soft IP may include, for example, digital components that are less sensitive to routing changes. Thus, soft IP blocks may have fixed logical functionality, but may be arranged according to the design requirements of a particular design. For example, a PHY layer may have a physical PHY implemented in a hard IP, and a logical PHY implemented in a soft IP.

[0236] Although it is advantageous to provide some types of functional blocks in hard IP, the limitations of hard IP are that the block is inflexible by design and definition. Thus, in one example, a SOC designer may require 50 data paths. The designer may be working with a hard IP block that provides 20 data paths per unit. Because the routing of the hard IP blocks is fixed at design time, the SOC designer must use an integer number of hard IP blocks. Specifically, using p hard IP blocks, each of which provides n data paths, a total of h=n*p total hard IP data paths are provided. In the case where the system design requires a total of k data paths, k≠h may be encountered. For example, when k=50 and n=20, p=[k / n]=3 hard IP blocks require h=n*p=60 available hard IP data paths. This result is acceptable as long as h≥k, or in other words, as long as p hard IP blocks provide at least enough data paths. During layout of the final SOC, the optimization software will not connect the extra 10 data paths to any power supplies or logic gates, so that the only cost associated with having the extra data paths is a certain amount of extra space on the silicon wafer. Because hard IP blocks tend to be small compared to the entire wafer, the wasted space is not excessive. To facilitate the use of hard IP blocks, each data path can have a separate enable so that unused data paths can be ignored. Also note that other combinations of paths from the cluster can be used depending on the situation (for example, unused paths can be distributed in the middle of the cluster to reduce crosstalk).

[0237] Fig.32 A block diagram of an example die is disclosed, showing that a logical PHY can be implemented in a soft IP (SIP) and a physical PHY can be implemented in a hard IP (HIP). An internal standard interface (OPIS, on-package interface (OPI) PHY interface specification) is defined in this example to facilitate partitioning. A link PHY interface (LP I) is also provided.

[0238] This partitioning allows configuration aspects such as lane reversal to be moved to the soft IP. The HIP (detailed in the dashed box) is built as a cluster that allows flexibility (eg, port width) without sacrificing performance (eg, speed).

[0239] Fig.33is an illustrative example of placement of hard IP and soft IP according to one or more examples of the present specification. Fig.33 In the example, the upper layer 3310 provides higher-level logic and can be implemented in any suitable form. The soft IP 3320 provides a logical PHY. Several hard IP blocks 3330 are also provided. Specifically, hard IP blocks 3330-1, 3330-2, and 3330-3 each have 20 data paths (n=20) and have necessary supporting paths. In this embodiment, the PHY has a total of 50 paths (k=50). Therefore, three hard IP blocks 3330 are used because of the total 60 available paths in the hard IP (h=60). Because the hard IP blocks are fixed, 10 additional paths are included. In this example, each hard IP block 3330 can provide a separate enable for each data path. Therefore, paths 10-19 on hard IP block 3330-3 are disabled. During layout, they will receive no routing, no power, no clock, and no other signals. Paths 10-19 are shown as disabled by example only. In other embodiments, depending on design requirements, any 10 paths may be disabled to achieve the same effect.

[0240] Fig.34 A problem (i.e., path reversal) that may arise using hard IP blocks and soft IP blocks is shown. This can be illustrated using an example PHY package that provides both a transmitter and a receiver. In this example, the transmitter and receiver can each be provided on a separate SOC die and then integrated into a single package. Each die can include, for example, a physical PHY provided in the hard IP, and a logical PHY provided in the soft IP. Because the hard IP, soft IP, and / or die can be provided by different groups within the same vendor or by different vendors, in some cases, the data paths of one group can be reversed from the data paths of another group. In the case of a SOC designer, the designer may not know in advance how the OEM intends to implement the design and whether the paths are reversed.

[0241] Therefore, path reversal can be encountered at various interfaces. In one case, path reversal may occur between hard IP and soft IP. In other cases, path reversal may occur between two dies on the same package.

[0242] To handle this path reversal, "bowties" can be used to route the data paths to each other. However, since these data paths must cross each other, at least 2 additional layers are required to route the bowties (either on the die or on the package). This introduces additional design complexity.

[0243] Fig.34Three packages 3410 are included. For example only, each package 3410 includes a hard IP 3330, a soft IP 3320, and upper layer logic 3310. As previously described, the hard IP 3330 provides physical PHY, the soft IP 3320 provides logical PHY functions, and the upper layer 3310 provides additional upper layer logic.

[0244] For example, in package 3410-1, Die 1 (Tx) is the PHY transmitter and Die 2 (Rx) is the PHY receiver. As shown in this example, the data path of Die 1 is the reversed path from the data path of Die 2. Therefore, if bow ties are used, additional layers may be required so that the connections can cross each other. This increases the complexity of the design.

[0245] In package 3410-2, there is a via reversal between the hard IP 3330 and the soft IP 3320 of Die 1. In this case, a bow tie connection must be formed on Die 1. Again, the bow tie will require an additional layer on Die 1 so that the vias can be properly matched. As previously described, this leads to additional design complexity.

[0246] However, in the example of package 3410-3, the path inversion can be fixed and the paths are properly aligned without the need for bow tie connections and the additional complexity associated therewith. Specifically, in package 3410-3, soft IP 3320 includes a multiplexer-like programmable switch 3480. Switch 3480 may not be a traditional multiplexer with a selection signal for selecting between inputs, but switch 3480 may be similar to a multiplexer in internal structure, with the number of inputs being the same as the number of outputs in this example having a different case.

[0247] The programmable aspects of switch 3480 include a switch that includes at least two modes, namely, one mode for routing directly through the path, and another mode for routing the path in reverse order. Other programmed options may also be provided as needed. To this end, the data path may have a virtual fuse feature. At startup, a fuse pull device may determine whether the path is to be reversed on package 3410-3. If the path is to be reversed, programmable switch 3480 will be blown to perform the path reversal. If the path is not to be reversed, the fuse puller blows multiplexer 3420 so as not to reverse the path. In the case where the direction is known at design time, the designer of package 3410-3 can program the fuse puller to provide the correct direction.

[0248] Advantageously, the architecture takes into account the fact that the direction of the path may not be known in advance by the designer of the soft IP 3320. For example, the package 3410-3 may be provided to an original equipment manufacturer (OEM), which may determine the direction of the package 3410-3 according to its own design requirements. In this case, the OEM may know the direction and can manually set the fuse puller to correctly determine the direction of the switch 3480. In another example, at startup, the package 3410-3 may perform a training sequence to determine whether the data path is a straight through route or a crossover route. Based on the results of the training sequence, the software can then program the fuse puller to provide the appropriate direction for the switch 3480.

[0249] While the present invention has been described with reference to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this specification.

[0250] A design may go through various stages, from creation to simulation to manufacturing. Data representing a design may represent the design in a variety of ways. First, as used in simulation, hardware may be represented using a hardware description language or other functional description language. In addition, at some stages of the design process, a circuit-level model with logic and / or transistor gates may be generated. In addition, at some stage, most designs reach a data level that represents the physical layout of various devices in a hardware model. In the case of conventional semiconductor manufacturing techniques, the data representing the hardware model may be data that specifies the presence or absence of various features on different mask layers of a mask used to produce an integrated circuit. In any representation of a design, data may be stored in any form of machine-readable medium. A memory or magnetic or optical storage (e.g., a disk) may be a machine-readable medium for storing information transmitted via light or electric wave modulation or otherwise generated to transmit such information. When an electrical carrier indicating or carrying a code or design is transmitted, a new version is generated in terms of performing a copy, buffering, or retransmission of the electrical signal. Therefore, a communication provider or network provider may store, at least temporarily, a copy of information encoded into a carrier on a tangible machine-readable medium, embodying the technology of an embodiment of the present specification.

[0251] As used herein, module refers to any combination of hardware, software and / or firmware. As an example, a module includes hardware such as a microcontroller, which is associated with a non-transitory medium to store a code suitable for execution by the microcontroller. Therefore, in one embodiment, with reference to a module, refers to hardware, which is specially configured to identify and / or execute a code for being kept on a non-transitory medium. In addition, in another embodiment, the use of a module refers to a non-transitory medium including a code, which is particularly suitable for being implemented by a microcontroller to perform a predetermined operation. And it can be inferred from this that in yet another embodiment, the term module (in this example) can refer to a combination of a microcontroller and a non-transitory medium. Typically, the module boundaries shown as separate usually vary and may overlap. For example, a first module and a second module can share hardware, software, firmware, or a combination thereof, while possibly retaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, such as a transistor, a register, or other hardware (e.g., a programmable logic device).

[0252] In one embodiment, the phrase "configured to" is used to refer to arranging, putting together, manufacturing, offering for sale, importing and / or designing a device, hardware, logic or element to perform a specified or determined task. In this example, the device or element is still "configured to" perform the specified task when it is not working if it is designed, coupled, and / or interconnected to perform the specified task. As a purely illustrative example, a logic gate can provide a 0 or 1 during operation. However, the logic gate is "configured to" provide an enable signal to the clock, which does not include every possible logic gate that can provide a 1 or 0. Instead, a logic gate is a logic gate that is coupled in some way during operation, and a 1 or 0 output is used to enable the clock. It is important to note again that the use of the term "configured to" does not require operation, but rather focuses on the latent state of the device, hardware, and / or element, where when the device, hardware or element is operating, the latent state of the device, hardware and / or element is designed to perform a specific task.

[0253] Additionally, in one embodiment, the use of the phrases "for," "capable of / capable of," and or "capable of being operable for," refers to some device, logic, hardware, and / or element being in such a manner to enable the use of the device, logic, hardware, and / or element in a particular manner. In one embodiment, note that the use of "for," "capable of being," or "capable of being operable for," as described above, refers to a latent state of a device, logic, hardware, and / or element, wherein the device, logic, hardware, and / or element is not operational but is designed in such a manner to enable the use of a device in a particular manner.

[0254] As used herein, value includes any known representation of a number, state, logic state, or binary logic state. Typically, the use of logic levels, logic values, or logic values ​​is also referred to as 1 and 0, which represent only binary logic states. For example, 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage unit such as a transistor or a flash memory unit may be able to maintain a separate logic value or multiple logic values. However, other representations of values ​​have been used in computer systems. For example, the decimal number ten may also be represented as a binary value 1010 and the hexadecimal letter A. Therefore, value includes any representation of information that can be maintained in a computer system.

[0255] In addition, a state can be represented by a value or multiple parts of a value. As an example, a first value, such as a logical one, can represent a default or initial state, while a second value, such as a logical zero, can represent a non-default state. In addition, in one embodiment, the terms reset and set refer to default and updated values ​​or states, respectively. For example, a default value may include a high logic value (i.e., reset), while an updated value may include a low logic value (i.e., set). It should be noted that any combination of values ​​can be used to represent any number of states.

[0256] Embodiments of the above methods, hardware, software, firmware or code, etc. may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that is executable by a processing element. Non-transitory machine-accessible / readable media include any mechanism, such as a computer or electronic system, that provides (i.e., stores and / or transmits) information in a machine-readable form. For example, non-transitory machine-accessible media include: random access memory (RAM) (e.g., static RAM (SRAM) or dynamic RAM (DRAM)); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for holding information received from a transient (propagating) signal (e.g., a carrier wave, an infrared signal, a digital signal); etc., all of which are used to distinguish from non-transitory media from which information can be received.

[0257] Instructions for programming logic to perform embodiments of the present invention may be stored in a memory in the system, such as DRAM, cache, flash memory or other storage. In addition, instructions may be distributed via a network or by other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, a floppy disk, an optical disk, a compact disk (CD-ROM), a read-only memory, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, a flash memory, or a tangible, machine-readable storage used in information transmission via an electrical, optical, acoustic or other form of propagation signal (e.g., a carrier wave, an infrared signal, a digital signal, etc.) through the Internet. Therefore, a computer-readable medium includes any type of tangible, machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0258] The following embodiments relate to embodiments according to the present specification. One or more embodiments may provide an apparatus, system, machine-readable storage, machine-readable medium, hardware-based and / or software-based logic, and method for providing a hard intellectual property (IP) subcomponent and a soft IP component having at least one soft IP block, wherein the hard intellectual property (IP) subcomponent includes p hard IP blocks, wherein each hard IP block is used to provide n data paths and has fixed routing, and wherein the p hard IP blocks are used to provide h=n*p available hard IP paths; the soft IP component having at least one soft IP block includes logic capable of routing and provides k data paths, wherein k≠h.

[0259] In one or more embodiments, the data paths have individual enables, and kh paths are to be disabled.

[0260] In one or more embodiments, the soft IP block further includes a programmable switch for selectively mapping the data path according to a switch mode.

[0261] In one or more embodiments, the switching modes include at least: a direct path mapping mode, in which the paths are mapped in numerical order; and a cross-mapping mode, in which the paths are mapped in reverse numerical order.

[0262] In one or more embodiments, the switching pattern is programmable via a fuse puller.

[0263] In one or more embodiments, the switching pattern is programmable via a training sequence.

[0264] In one or more embodiments, the fuses are programmable via a read-only memory.

[0265] In one or more embodiments, each path is used to receive a non-correlated pseudo-random bit sequence for centering.

[0266] In one or more embodiments, at least some of the hard IP blocks are configured to receive separate VALID signals.

[0267] In one or more embodiments, at least some of the hard IP blocks are configured to receive separate STREAM_IDs.

[0268] In one or more embodiments, an interconnected system includes: a first agent; a second agent; and an interconnect, the interconnect being used to communicatively couple the first agent to the second agent, the interconnect including: a hard intellectual property (IP) subcomponent including P hard IP modules and a soft IP component having at least one soft IP block; wherein each hard IP block is used to provide n data paths and has a fixed route, and wherein the p hard IP blocks are used to provide h=n*p available hard IP paths; the soft IP component having at least one soft IP block includes logic capable of routing and provides k data paths, wherein k≠h.

[0269] In one or more embodiments, a method for providing interconnection is also disclosed, including: placing a hard intellectual property (IP) subcomponent including p hard IP blocks, placing a soft IP component having at least one soft IP block; wherein each hard IP block is used to provide n data paths and has a fixed routing, and wherein the p hard IP blocks are used to provide h=n*p available hard IP paths; the soft IP component having at least one soft IP block includes routable logic and provides k data paths, wherein k≠h.

[0270] In one or more embodiments, the method further comprises disabling kh paths.

[0271] In one or more embodiments, the method further includes selectively mapping the data paths according to the switching pattern.

[0272] In one or more embodiments, data paths are selectively mapped according to a switch pattern, including a direct path mapping pattern in numerical order.

[0273] In one or more embodiments, selectively mapping the data paths according to the switching pattern includes: cross-mapping the paths in reverse digital order.

[0274] In one or more embodiments, the method further comprises providing a pseudo-random bit sequence for centering for each lane.

[0275] In one or more embodiments, an interconnect device includes: a clock generator for generating a clock signal; a phase shifter for phase-shifting the clock signal through a test phase; an error rate detector for measuring an error rate of the test phase; and an operable phase selector for selecting an operable phase of the clock signal based at least in part on the error rate of the test phase.

[0276] In one or more embodiments, an interconnect device includes: a flow path encoder for encoding a category identifier for a data packet; and a path driver for driving the category identifier onto at least one data path of n data paths during a non-data time of the data packet.

[0277] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification does not necessarily all refer to the same embodiment. In addition, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0278] In the above description, specific embodiments have been given with reference to specific exemplary embodiments. However, it is apparent that various modifications and variations may be set forth in the appended claims without departing from the broader spirit and scope of the present invention. Therefore, the description and drawings are shown in an illustrative manner and not in a restrictive manner. In addition, the foregoing use of embodiments and other exemplary language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as possibly the same embodiments.

Claims

1. An integrated circuit die, comprising: a hard IP (HIP) subassembly including a plurality of hard logic blocks, wherein the hard logic blocks are associated with a plurality of data paths; a plurality of protocol-specific logic blocks for communicating data in accordance with a corresponding plurality of data communications protocols; and A soft IP (SIP) component is used to selectively map the plurality of data channels.

2. An interconnection device, comprising: A clock generator, which is used to generate a clock signal; A phase shifter, used for shifting the phase of the clock signal to a test phase; an error rate detector for measuring an error rate of the test phase; and an operable phase selector for selecting an operable phase of the clock signal based at least in part on the error rate of the test phase.

3. An interconnection device, comprising: a stream channel encoder for encoding a category identifier for a data packet; as well as A lane driver is configured to drive the category identifier onto at least one of the n data lanes during a non-data time of the data packet.

Images