Link signal optimization device and method based on retimer and link matching

Abstract

The invention provides a link signal optimization device and method based on a retimer and link matching, the device comprises a first link device, a retimer, a controller and a second link device, the first link device or the second link device sends a signal to the retimer; the retimer analyzes the received signal sent by the first link device and sends the analyzed signal to the second link device or the first link device; wherein the retimer is obtained by the controller after parameter adjustment based on an optimal retimer parameter matched with the first link section information, the second link section information and the link equipment information which are obtained in advance. According to the invention, the optimal retimer parameter is matched by combining the first link section and the second link section with the link equipment information, so that adjustment is carried out for different link sections and equipment, the compatibility and adaptability of the system are improved, and targeted signal optimization is realized.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a link signal optimization device and method based on a retimer and link matching. Background Art

[0002] With the development of science and technology, the high-speed serial computer expansion bus standard peripheral component interconnect express (PCIe) 5.0 protocol has been widely used in servers for high-speed interconnection with PCIe devices such as the central processing unit (CPU), network card, hard disk and graphics processing unit (GPU). Compared with PCIe4.0, its speed has doubled, which has greatly improved the performance of the server, but the increase in speed also brings signal integrity issues.

[0003] However, in the PCIe link, printed circuit board (PCB) routing, connectors, cables, etc. may introduce loss to the link. At the same time, impedance discontinuity and compatibility between the CPU and PCIe devices will also cause the PCIe signal quality to deteriorate, thereby causing link problems. Summary of the invention

[0004] The present invention provides a link signal optimization device and method based on a retimer and link matching, which are used to solve the defect of PCB routing, connectors and cables in the prior art that the link introduces loss, realize segmented identification and management of PCIe links, and facilitate PCIe signal optimization of complex systems under various configurations.

[0005] The present invention provides a link signal optimization device based on a retimer and link matching, comprising a first link device, a retimer, a controller and a second link device, wherein: the retimer receives a signal sent by the first link device or the second link device; the retimer parses the received signal sent by the first link device and sends the parsed signal to the second link device, or parses the received signal sent by the second link device and sends the parsed signal to the first link device; wherein the retimer is obtained by the controller after adjusting the parameters of the optimal retimer based on the first link segment information, the second link segment information and the link device information matching obtained in advance, the first link segment is used to characterize the link composed of the first link device and the retimer as link nodes, the second link segment is used to characterize the link composed of the retimer and an extension module with the second link device built in as link nodes, and the link device information includes the second link device information.

[0006] According to the present invention, a link signal optimization device based on a retimer and link matching is provided. Before the retimer parses the received signal, the device includes: a controller, which obtains first link segment information, second link segment information and link device information; the controller determines the matching optimal retimer parameters according to the first link segment information, the second link segment information and the link device information in combination with parameter tuning information; wherein the parameter tuning information includes multiple link information and the optimal retimer parameters corresponding to each link, the path of the link is composed of the first link segment and the second link segment, and the paths of different links are not exactly the same, and the optimal retimer parameters are obtained based on the corresponding link tuning verification; the controller uses the matching optimal retimer parameters to adjust the retimer.

[0007] According to a link signal optimization device based on a retimer and link matching provided by the present invention, the first link device includes at least two serial interfaces, the first link segment also includes an adapter card and at least two first connectors, the adapter card includes at least two second connectors, the serial interface, the first connector and the second connector are connected one-to-one, and the second connector is connected one-to-one with the retimer; the second link segment also includes a third connector, and the third connector is used to connect the retimer and the expansion module one-to-one; the controller obtains the first link segment information, the second link segment information and the link device information, including: based on the adapter card and the retimer, the controller reads the first connector address to obtain the first link segment information; based on the adapter card, the second connector, the retimer and the third connector, the controller reads the expansion module identifier to obtain the second link segment information; based on the adapter card, the second connector, the retimer and the third connector, the controller reads the second link device information in the expansion module to obtain the link device information.

[0008] According to a link signal optimization device based on a retimer and link matching provided by the present invention, the first connector address is an address identifier corresponding to the first connector configured based on an address configuration module in advance, and the number of address identifier bits n and the number of serial interfaces m of the first link device satisfy 2 n ≥m.

[0009] According to a link signal optimization device based on a retimer and link matching provided by the present invention, the adapter card also includes a first sideband signal connector, the device also includes a second sideband connector, and the third connector includes a first connection end and a second connection end, and the first connection end and the second connection end are connected by a cable; based on the adapter card, the second connector, the retimer and the third connector, the controller reads the expansion module identification, including: based on the second sideband signal connector, the first sideband signal connector, the second connector correspondingly connected to the first sideband signal connector, the gold finger connected to the second connector, the retimer connected to the gold finger, the first connection end correspondingly plugged into the retimer, and the cable correspondingly connecting the first connection end and the second connection end plugged into the expansion module, the controller reads the identification information of the expansion module stored in the field replaceable unit chip connected to the corresponding cable to obtain the expansion module identification.

[0010] According to a link signal optimization device based on a retimer and link matching provided by the present invention, based on an adapter card and a retimer, a controller reads the address of the first connector, including: based on the second sideband signal connector, the first sideband signal connector, the second connector corresponding to the first sideband signal connector, and a gold finger connected to the second connector, the controller reads the address information of the first connector stored in the input and output expansion chip connected to the corresponding gold finger to obtain the first connector address.

[0011] According to a link signal optimization device based on a retimer and link matching provided by the present invention, based on an adapter card, a second connector, a retimer and a third connector, a controller reads the second link device information in an extension module, including: based on a second sideband signal connector, a first sideband signal connector, a second connector correspondingly connected to the first sideband signal connector, a gold finger connected to the second connector, a retimer connected to the gold finger, a third connector correspondingly connected to the retimer and an extension module correspondingly connected to the third connector, the controller reads the second link device information in the corresponding extension module.

[0012] According to a link signal optimization device based on a retimer and link matching provided by the present invention, a controller uses the matched optimal retimer parameters to adjust the parameters of the retimer, including: the controller generates an integrated circuit bus signal according to the matched optimal retimer parameters, and sends the integrated circuit bus signal to the second sideband signal connector based on the corresponding integrated circuit bus channel; the second sideband signal connector receives the integrated circuit bus signal and sends the received integrated circuit bus signal to the first sideband signal connector through the corresponding channel of the cable; the first sideband signal connector sends the received integrated circuit bus signal to the corresponding second connector based on the printed circuit board routing connected to the corresponding second connector; the second connector sends the integrated circuit bus signal to the retimer based on the gold finger, and adjusts the parameters of the retimer.

[0013] According to a link signal optimization device based on a retimer and link matching provided by the present invention, before the retimer receives a signal sent by a first link device or a second link device, the device includes: the first link device sends a signal to a first connector corresponding to the serial interface through a serial interface; the first connector receives the signal and sends the received signal to the retimer through a second connector corresponding to an adapter card; or the second link device sends a signal to the retimer through a third connector.

[0014] The present invention also provides a link signal optimization method based on a retimer and link matching, comprising: receiving a signal sent by a first link device or a second link device; parsing the received signal sent by the first link device, and sending the parsed signal to the second link device, or parsing the received signal sent by the second link device, and sending the parsed signal to the first link device; wherein the retimer is obtained by a controller after adjusting parameters based on the optimal retimer parameters matched based on the first link segment information, the second link segment information and the link device information obtained previously, the first link segment is used to characterize a link composed of the first link device and the retimer as link nodes, the second link segment is used to characterize a link composed of the retimer and an extension module with a built-in second link device as link nodes, and the link device information includes the second link device information.

[0015] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the link signal optimization method based on a retimer and link matching as described in any one of the above is implemented.

[0016] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the link signal optimization method based on a retimer and link matching as described in any one of the above is implemented.

[0017] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned link signal optimization methods based on a retimer and link matching.

[0018] The link signal optimization device and method based on retimer and link matching provided by the present invention analyze the specific first link segment and the second link segment, and match the optimal retimer parameters in combination with the link device information to adjust the parameters for different link segments and devices, thereby finding the most suitable retimer settings through parameter matching, improving the compatibility and adaptability of the entire system, effectively enhancing signal strength, reducing noise, ensuring the stability and reliability of data transmission, and achieving targeted signal optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 It is one of the structural schematic diagrams of the link signal optimization device based on the retimer and link matching provided by the present invention; Figure 2 This is the second structural schematic diagram of the link signal optimization device based on the retimer and link matching provided by the present invention; Figure 3 is a cable schematic diagram of a third connector provided by the present invention; Figure 4 is a schematic diagram of a board frame of a retimer provided by the present invention; Figure 5 It is a flow chart of a link signal optimization method based on a retimer and link matching provided by the present invention; Figure 6 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Figure 1 A schematic structural diagram of a link signal optimization device based on a retimer and link matching is shown, the device comprising a first link device, a retimer, a controller and a second link device, wherein: A retimer (Retimer), receiving a signal sent by the first link device or the second link device; The retimer parses a received signal sent by the first link device and sends the parsed signal to the second link device, or parses a received signal sent by the second link device and sends the parsed signal to the first link device; wherein the retimer is obtained by the controller after adjusting parameters based on the optimal retimer parameters matched based on the first link segment information, the second link segment information and the link device information obtained previously, the first link segment is used to characterize a link composed of the first link device and the retimer as link nodes, the second link segment is used to characterize a link composed of the retimer and an extension module with the second link device built in as link nodes, and the link device information includes the second link device information.

[0023] Specifically, the Retimer parses the received signal and sends the parsed signal to the second-link device or the first-link device, including: if the Retimer receives a signal sent by the first-link device, the Retimer parses the signal and sends it to the second-link device; if the Retimer receives a signal sent by the second-link device, the Retimer parses the signal and sends it to the first-link device, thereby optimizing the signal by using the Retimer to make the signal reach the optimal state and improve system performance.

[0024] In this embodiment, reference Figure 2 The first link device includes at least two serial interfaces, the first link segment also includes an adapter card and at least two first connectors, the adapter card includes at least two second connectors, the serial interface, the first connector and the second connector are connected one-to-one, and the second connector is connected one-to-one with the Retimer; the second link segment also includes a third connector, and the third connector is used to connect the Retimer and the expansion module one-to-one.

[0025] It is worth noting that the number of serial interfaces of the first link device, the number of first connectors, the number of third connectors, the number of Retimers, the number of second connectors and the number of expansion modules 4 match the settings.

[0026] In an optional embodiment, the first link device and the second link device may adopt high-speed serial computer expansion bus standard (Peripheral Component Interconnect express, referred to as PCIe) devices, the first link device may adopt a central processing unit (Central Processing Unit, referred to as CPU), the serial interface may adopt a high-speed peripheral component interconnect port (PCIe Port), the second link device may adopt a graphics processing unit (Graphics Processing Unit, referred to as GPU), the first connector may adopt a motherboard connection input / output connector (Motherboard Connection Input / Output, referred to as MCIO), the second connector may adopt a GENZ (Generation Z) connector, the third connector may adopt a common design form factor pluggable module (Common Design Form Factor Pluggable, referred to as CDFP), the extension module may adopt a GPU box extension box or an external graphics card box, etc., which may be determined here according to the actual links involved without further limitation.

[0027] Accordingly, before the retimer receives the signal sent by the first link device or the second link device, it includes: the first link device sends the signal to the first connector corresponding to the serial interface through the serial interface; the first connector receives the signal and sends the received signal to the retimer through the second connector corresponding to the adapter card; or the second link device sends the signal to the retimer through the third connector.

[0028] Furthermore, the adapter card also includes a first sideband signal connector, the device also includes a second sideband connector, the first sideband signal connector is connected to the controller through the second sideband connector, the first sideband signal connector is connected to each second connector one by one, and the second connector is connected to the Retimer through a Golden Finger (GF); the first link device, the first connector, the controller and the second sideband signal connector are arranged on the mainboard; the third connector includes a first connection end and a second connection end, the first connection end and the second connection end are connected through a cable, the first connection end is plugged into the Retimer, and the second connection end is plugged into the expansion module.

[0029] In an optional embodiment, the controller adopts a baseboard management controller (Baseboard Management Controller, referred to as BMC).

[0030] It should be added that the second sideband signal connector is connected to the integrated circuit bus (Inter-Integrated Circuit, I 2 C) The channels are connected one-to-one, the second sideband signal connector is connected to the first sideband signal connector through a cable, and the first sideband signal connector is connected to each second connector one-to-one through a plurality of PCB traces.

[0031] Correspondingly, the second link device sends the signal to the retimer through the third connector, including: the second link device sends the signal to the retimer through the second connection end plugged into the expansion module, the cable connected to the second connection end and the first connection end correspondingly plugged into the retimer.

[0032] In an optional embodiment, before the retimer Retimer parses the received signal, it includes: a controller, obtaining first link segment information, second link segment information and link device information; the controller, based on the first link segment information, the second link segment information and the link device information, combined with parameter tuning information, determines matching optimal retimer parameters; wherein the parameter tuning information includes multiple link information and optimal retimer parameters corresponding to each link, the path of the link is composed of the first link segment and the second link segment, and the paths of different links are not exactly the same, and the optimal retimer parameters are obtained based on the corresponding link tuning verification; the controller uses the matching optimal retimer parameters to adjust the parameters of the retimer Retimer.

[0033] Specifically, the controller obtains the first link segment information, the second link segment information and the link device information, including: based on the adapter card and the retimer, the controller reads the first connector address to obtain the first link segment information; based on the adapter card, the second connector, the retimer and the third connector, the controller reads the expansion module identifier to obtain the second link segment information; based on the adapter card, the second connector, the retimer and the third connector, the controller reads the second link device information in the expansion module to obtain the link device information.

[0034] It should be noted that the first connector address is an address identifier corresponding to the first connector configured based on the address configuration module in advance, and the number of address identifier bits n and the number of serial interfaces m of the first link device satisfy 2 n ≥m.

[0035] In an optional embodiment, after configuring the address identifier corresponding to the first connector based on the address configuration module, it also includes: uploading the configured address identifier to the input and output (IO) expansion chip based on the address configuration module or the first connector, so as to facilitate subsequent address reading based on the IO expansion chip.

[0036] Furthermore, reference Figure 3 , based on the adapter card, the second connector, the retimer and the third connector, the controller reads the expansion module identification, including: based on the second sideband signal connector, the first sideband signal connector, the second connector corresponding to the first sideband signal connector, the GF connected to the second connector, the Retimer connected to the GF, the first connection end correspondingly plugged into the Retimer, and the cable correspondingly connecting the first connection end and the second connection end plugged into the expansion module, the controller reads the identification information of the expansion module stored in the field replaceable unit (Field Replace Unit, FRU for short) chip connected to the corresponding cable to obtain the expansion module identification.

[0037] It should be noted that by reading the field replaceable unit (FRU) chip through the above-mentioned specific signal path, the identification information of the expansion module can be accurately obtained to ensure that the system can clearly identify different expansion modules, providing an accurate basis for subsequent management and configuration, and improving the maintenance efficiency and reliability of the system. In addition, by making full use of existing connectors and components, such as the second sideband signal connector, the first sideband signal connector, the second connector, GF, Retimer, and cables, etc., new hardware components can be avoided to reduce costs and system complexity.

[0038] In an optional embodiment, based on the adapter card, the second connector, the retimer and the third connector, the controller reads the expansion module identification, and also includes: using a preset wireless reading method or a preset interface to read the expansion module identification, so as to switch to the backup path in time when the reading path based on the third connector fails, thereby ensuring the availability of the identification information.

[0039] In an optional embodiment, after the controller reads the expansion module identifier based on the adapter card, the second connector, the retimer and the third connector, it also includes: encrypting the expansion module identifier; and before the controller obtains the first link segment information, the second link segment information and the link device information, it also includes: performing security verification on the controller or the user to ensure that only authorized devices or users can read and use the expansion module identifier, thereby achieving encrypted transmission of data, preventing unauthorized access and tampering, and ensuring the security and stability of the system.

[0040] In addition, refer to Figure 4 Based on the adapter card and the retimer, the controller reads the address of the first connector, including: based on the second sideband signal connector, the first sideband signal connector, the second connector corresponding to the first sideband signal connector, and the GF connected to the second connector, the controller reads the address information of the first connector stored in the input and output IO expansion chip connected to the corresponding GF to obtain the first connector address.

[0041] In an optional embodiment, after the controller reads the first connector address based on the adapter card and the retimer, it includes: comparing the read first connector address with the preset address information to ensure that the read address is valid and correct; or, verifying the read first connector address based on a preset verification algorithm.

[0042] Accordingly, after determining that the address is abnormal, it also includes: triggering an alarm or other preset error correction program, which can be set according to actual design requirements to improve the stability and reliability of the system.

[0043] Similarly, based on the adapter card and the retimer, after the controller reads the first connector address, the first connector address can also be encrypted to encrypt the first connector address for transmission, and before the controller obtains the first link segment information, the second link segment information and the link device information, the controller or user can be securely verified to prevent the address information from being illegally obtained or tampered with.

[0044] Continue to refer Figure 4 , based on the adapter card, the second connector, the retimer and the third connector, the controller reads the second link device information in the expansion module, including: based on the second sideband signal connector, the first sideband signal connector, the second connector correspondingly connected to the first sideband signal connector, the GF connected to the second connector, the Retimer connected to the GF, the third connector correspondingly connected to the Retimer and the expansion module correspondingly connected to the third connector, the controller reads the second link device information in the corresponding expansion module. Similarly, after reading the second link device information, the second link device information can be encrypted. Here, refer to the above method for encrypting the expansion module identifier, which will not be repeated here. In addition, the second link device information includes the second link device identifier.

[0045] In an optional embodiment, based on the first link segment information, the second link segment information and the link device information, combined with the parameter tuning information, the matching optimal retimer parameters are determined, including: inputting the first link segment information, the second link segment information and the link device information into a parameter prediction model to predict the retimer parameters in combination with the parameter tuning information to obtain the optimal retimer parameters; wherein the parameter prediction model is trained based on training data and parameter labels corresponding to the training data.

[0046] It should be noted that the parameter prediction model can use an existing machine learning algorithm or a specified algorithm, which is not further limited here. The machine learning algorithm is used to automatically learn and predict the retimer parameters, thereby learning the optimal parameter setting mode under different link conditions to achieve more efficient parameter matching and signal optimization.

[0047] Furthermore, the link device information can also report the device's operating temperature, power stability, and age, to more comprehensively consider factors that may affect the link signal quality and achieve more comprehensive parameter matching and optimization.

[0048] In an alternative embodiment, continue to refer to Figure 4 The controller uses the matched optimal retimer parameters to adjust the parameters of the retimer Retimer, including: the controller generates an integrated circuit bus (Inter-Integrated Circuit, referred to as I 2 C) signal, and based on the corresponding I 2 C channel, I 2 C signal is sent to the second sideband signal connector; the second sideband signal connector receives I 2 C signal, and transmits the received I 2 C signal is sent to the first sideband signal connector; the first sideband signal connector receives the I 2 C signal is sent to the corresponding second connector; the second connector sends I 2 The C signal is sent to the Retimer to adjust the parameters of the Retimer.

[0049] It should be noted that by adjusting the parameters of the matching optimal retimer, it is possible to ensure that the Retimer works in the state that is most suitable for the current link, thereby optimizing the link signal quality to the greatest extent and improving the stability and reliability of data transmission.

[0050] In an optional embodiment, after the controller adjusts the Retimer using the matching optimal retimer parameters, the Retimer feeds back its own status information or adjustment results to the controller, so that the controller further adjusts the parameters according to the feedback information to achieve more accurate optimization.

[0051] In an optional embodiment, after the controller uses the matched optimal retimer parameters to adjust the Retimer parameters, it also includes: using preset monitoring software or sensors to monitor the link status in real time, and dynamically adjusting the retimer parameters according to the link performance indicators obtained by monitoring, so that the system can more intelligently adapt to the changing link environment and further improve the effect of signal optimization. It should be added that the link performance indicators include bit error rate, signal strength and transmission delay.

[0052] In an optional embodiment, in the same link, multiple Retimers are used to work together, that is, Retimers are deployed at multiple preset nodes of the link, and the Retimers work together through a communication protocol, so that different Retimers are responsible for different link segments, and different aspects of the signal are optimized, so as to jointly ensure the signal quality of the entire link and achieve better link signal optimization effect.

[0053] In summary, the embodiment of the present invention analyzes the specific first link segment and the second link segment, and matches the optimal retimer parameters in combination with the link device information to adjust the parameters for different link segments and devices, thereby finding the most suitable retimer settings through parameter matching, improving the compatibility and adaptability of the entire system, effectively enhancing signal strength, reducing noise, ensuring the stability and reliability of data transmission, and achieving targeted signal optimization.

[0054] The link signal optimization method based on the retimer and link matching provided by the present invention is described below. The link signal optimization method based on the retimer and link matching described below and the link signal optimization device based on the retimer and link matching described above can refer to each other.

[0055] Figure 5 is a flow chart of a link signal optimization method based on a retimer and link matching provided by the present invention, such as Figure 5 As shown, the execution subject of the method is a retimer Retimer, including: S51, receiving a signal sent by a first link device or a second link device; S52, parsing a received signal sent by the first link device, and sending the parsed signal to the second link device, or parsing a received signal sent by the second link device, and sending the parsed signal to the first link device; wherein the retimer is obtained by the controller after adjusting parameters based on the first link segment information, the second link segment information and the link device information obtained previously, the first link segment is used to characterize a link composed of the first link device and the retimer as link nodes, the second link segment is used to characterize a link composed of the retimer and an extension module with the second link device built in as link nodes, and the link device information includes the second link device information.

[0056] Specifically, the received signal is parsed, and the parsed signal is sent to the second link device or the first link device, including: if the Retimer receives a signal sent by the first link device, the Retimer parses the signal and sends it to the second link device; if the Retimer receives a signal sent by the second link device, the Retimer parses the signal and sends it to the first link device, thereby optimizing the signal by using the Retimer, so that the signal reaches the best state and improves system performance.

[0057] In this embodiment, the first link device includes at least two serial interfaces, the first link segment also includes an adapter card and at least two first connectors, the adapter card includes at least two second connectors, and accordingly, receiving the signal sent by the first link device includes: receiving the signal sent by the first link device based on the first connector connected to the serial interface of the first link device and the second connector corresponding to the adapter card connected to the first connector.

[0058] Furthermore, the adapter card further includes a first sideband signal connector, and the device further includes a second sideband connector, and receiving a signal sent by the second link device includes: receiving a signal sent by the second link device based on the third connector. Specifically, receiving a signal sent by the second link device based on the third connector includes: receiving the signal sent by the second link device through a second connection end plugged into the second link device, a cable connected to the second connection end, and a first connection end correspondingly plugged into the Retimer.

[0059] In an optional embodiment, before parsing the received signal, the method includes: using a controller to obtain first link segment information, second link segment information and link device information; using the controller to determine matching optimal Retimer parameters based on the first link segment information, the second link segment information and the link device information in combination with parameter tuning information; wherein the parameter tuning information includes multiple link information and the optimal Retimer parameters corresponding to each link, the path of the link is composed of the first link segment and the second link segment, and the paths of different links are not exactly the same, and the optimal Retimer parameters are obtained based on the corresponding link tuning verification; based on the controller, the Retimer is adjusted using the matching optimal Retimer parameters.

[0060] Specifically, the controller is used to obtain the first link segment information, the second link segment information and the link device information, including: based on the adapter card and the retimer, the controller is used to read the first connector address to obtain the first link segment information; based on the adapter card, the second connector, the retimer and the third connector, the controller is used to read the expansion module identifier to obtain the second link segment information; based on the adapter card, the second connector, the retimer and the third connector, the controller is used to read the second link device information in the expansion module to obtain the link device information.

[0061] It should be noted that before the controller is used to read the address of the first connector based on the adapter card and the retimer, the following steps are included: the address identifier corresponding to the first connector is configured based on the address configuration module, and the number of address identifier bits n and the number of serial interfaces m of the first link device meet 2 n ≥m.

[0062] In an optional embodiment, after configuring the address identifier corresponding to the first connector based on the address configuration module, it also includes: using the address configuration module or the first connector to upload the configured address identifier to the input and output IO expansion chip, so as to facilitate subsequent address reading based on the IO expansion chip.

[0063] Furthermore, based on the adapter card, the second connector, the retimer and the third connector, the expansion module identification is read by using a controller, including: based on the second sideband signal connector, the first sideband signal connector, the second connector correspondingly connected to the first sideband signal connector, the GF connected to the second connector, the Retimer connected to the GF, the first connection end correspondingly plugged into the Retimer, and the cable correspondingly connecting the first connection end and the second connection end plugged into the expansion module, the controller is used to read the identification information of the expansion module stored in the field replaceable unit (Field Replace Unit, FRU for short) chip connected to the corresponding cable to obtain the expansion module identification.

[0064] In an optional embodiment, based on the adapter card, the second connector, the retimer and the third connector, the expansion module identification is read by the controller, and it also includes: the controller uses a preset wireless reading method or a preset interface to read the expansion module identification, so that when the reading path based on the third connector fails, it can switch to the backup path in time, thereby ensuring the availability of the identification information.

[0065] In an optional embodiment, after using the controller to read the expansion module identifier based on the adapter card, the second connector, the retimer and the third connector, it also includes: encrypting the expansion module identifier; and before using the controller to obtain the first link segment information, the second link segment information and the link device information, it also includes: performing security verification on the controller or the user to ensure that only authorized devices or users can read and use the expansion module identifier, thereby achieving encrypted transmission of data, preventing unauthorized access and tampering, and ensuring the security and stability of the system.

[0066] In addition, based on the adapter card and the retimer, the controller is used to read the address of the first connector, including: based on the second sideband signal connector, the first sideband signal connector, the second connector corresponding to the first sideband signal connector, and the GF connected to the second connector, the controller is used to read the address information of the first connector stored in the input and output IO expansion chip connected to the corresponding GF to obtain the first connector address.

[0067] In an optional embodiment, after reading the first connector address using a controller based on an adapter card and a retimer, it includes: comparing the read first connector address with the preset address information to ensure that the read address is valid and correct; or, verifying the read first connector address based on a preset verification algorithm.

[0068] Accordingly, after determining that the address is abnormal, it also includes: triggering an alarm or other preset error correction program, which can be set according to actual design requirements to improve the stability and reliability of the system.

[0069] Similarly, after the controller reads the first connector address based on the adapter card and the retimer, the first connector address can also be encrypted to encrypt the first connector address for transmission, and before the controller obtains the first link segment information, the second link segment information and the link device information, the controller or user can be securely verified to prevent the address information from being illegally obtained or tampered with.

[0070] Based on the adapter card, the second connector, the retimer and the third connector, the second link device information in the expansion module is read by the controller, including: based on the second sideband signal connector, the first sideband signal connector, the second connector corresponding to the first sideband signal connector, the GF connected to the second connector, the Retimer connected to the GF, the third connector corresponding to the Retimer and the expansion module corresponding to the third connector, the second link device information in the corresponding expansion module is read by the controller. Similarly, after reading the second link device information, the second link device information can be encrypted. Here, refer to the above method of encrypting the expansion module identifier, and no repetition is made here.

[0071] In an optional embodiment, based on the first link segment information, the second link segment information and the link device information, combined with the parameter tuning information, the matching optimal retimer parameters are determined, including: inputting the first link segment information, the second link segment information and the link device information into a parameter prediction model to predict the retimer parameters in combination with the parameter tuning information to obtain the optimal retimer parameters; wherein the parameter prediction model is trained based on training data and parameter labels corresponding to the training data.

[0072] Furthermore, the link device information may also include the operating temperature, power stability, and service life of the device, so as to more comprehensively consider factors that may affect the link signal quality and achieve more comprehensive parameter matching and optimization.

[0073] In an optional embodiment, based on the controller, the retimer Retimer is adjusted using the matched optimal retimer parameters, including: based on the controller, generating an integrated circuit bus (Inter-Integrated Circuit, referred to as I 2 C) signal, and based on the corresponding I 2 C channel, I 2 C signal is sent to the second sideband signal connector; based on the second sideband signal connector, receiving I 2 C signal, and transmits the received I 2 C signal is sent to the first sideband signal connector; based on the first sideband signal connector and the corresponding PCB trace, the received I 2 C signal is sent to the corresponding second connector; based on the second connector, I 2 The C signal is sent to the Retimer to adjust the parameters of the Retimer.

[0074] In an optional embodiment, after adjusting the Retimer parameters based on the controller using the matching optimal Retimer parameters, it includes: using the Retimer to feed back its own state information or adjustment results to the controller, so that the controller can further adjust the parameters according to the feedback information to achieve more accurate optimization.

[0075] In an optional embodiment, after adjusting the Retimer parameters based on the controller using the matched optimal Retimer parameters, it also includes: using preset monitoring software or sensors to monitor the link status in real time, and dynamically adjusting the Retimer parameters according to the link performance indicators obtained by monitoring, so that the system can more intelligently adapt to the changing link environment and further improve the effect of signal optimization. It should be added that the link performance indicators include bit error rate, signal strength and transmission delay, etc.

[0076] In an optional embodiment, in the same link, multiple Retimers are used to work together, that is, Retimers are deployed at multiple preset nodes of the link, and the Retimers work together through a communication protocol, so that different Retimers are responsible for different link segments, and different aspects of the signal are optimized, so as to jointly ensure the signal quality of the entire link and achieve better link signal optimization effect.

[0077] In summary, the embodiment of the present invention analyzes the specific first link segment and the second link segment, and matches the optimal retimer parameters in combination with the link device information to adjust the parameters for different link segments and devices, thereby finding the most suitable retimer settings through parameter matching, improving the compatibility and adaptability of the entire system, effectively enhancing signal strength, reducing noise, ensuring the stability and reliability of data transmission, and achieving targeted signal optimization.

[0078] Figure 6 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 6 As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630 and a communication bus 640, wherein the processor 610, the communication interface 620 and the memory 630 communicate with each other through the communication bus 640. The processor 610 may call the logic instructions in the memory 630 to execute a link signal optimization method based on a retimer and link matching, the method comprising: receiving a signal sent by a first link device or a second link device; parsing the received signal sent by the first link device and sending the parsed signal to the second link device, or parsing the received signal sent by the second link device and sending the parsed signal to the first link device; wherein the retimer is obtained by the controller after adjusting the parameters of the optimal retimer based on the first link segment information, the second link segment information and the link device information matching obtained previously, the first link segment is used to characterize the link formed by the first link device and the retimer as the link node, the second link segment is used to characterize the link formed by the retimer and the extension module with the second link device built in as the link node, and the link device information includes the second link device information.

[0079] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0080] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the link signal optimization method based on retimer and link matching provided by the above methods, the method including: receiving a signal sent by a first link device or a second link device; parsing the received signal sent by the first link device, and sending the parsed signal to the second link device, or parsing the received signal sent by the second link device, and sending the parsed signal to the first link device; wherein the retimer is obtained by the controller after adjusting the parameters of the optimal retimer based on the first link segment information, the second link segment information and the link device information matching obtained previously, the first link segment is used to characterize the link composed of the first link device and the retimer as link nodes, the second link segment is used to characterize the link composed of the retimer and the expansion module with the second link device built in as link nodes, and the link device information includes the second link device information.

[0081] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the processor executes the link signal optimization method based on retimer and link matching provided by the above methods, the method comprising: receiving a signal sent by a first link device or a second link device; parsing the received signal sent by the first link device, and sending the parsed signal to the second link device, or parsing the received signal sent by the second link device, and sending the parsed signal to the first link device; wherein the retimer is obtained by the controller after adjusting the parameters of the optimal retimer based on the first link segment information, the second link segment information and the link device information matching obtained previously, the first link segment is used to characterize the link composed of the first link device and the retimer as link nodes, the second link segment is used to characterize the link composed of the retimer and the expansion module with the second link device built in as link nodes, and the link device information includes the second link device information.

[0082] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0083] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A link signal optimization device based on a retimer and link matching, characterized in that: The invention comprises a first link device, a retimer, a controller and a second link device, wherein: The retimer receives a signal sent by the first link device or the second link device; The retimer parses a received signal sent by the first link device and sends the parsed signal to the second link device, or parses a received signal sent by the second link device and sends the parsed signal to the first link device; wherein the retimer is obtained by the controller after adjusting parameters based on the optimal retimer parameters matched based on the first link segment information, the second link segment information and the link device information obtained previously, the first link segment is used to characterize a link formed by the first link device and the retimer as link nodes, the second link segment is used to characterize a link formed by the retimer and an extension module with the second link device built in as link nodes, and the link device information includes the second link device information.

2. The link signal optimization device based on retimer and link matching according to claim 1, characterized in that: Before the retimer analyzes the received signal, it includes: The controller obtains first link segment information, second link segment information and link device information; The controller determines, according to the first link segment information, the second link segment information and the link device information, in combination with parameter tuning information, matching optimal retimer parameters; wherein the parameter tuning information includes multiple link information and optimal retimer parameters corresponding to each of the links, the path of the link is composed of the first link segment and the second link segment, and the paths of different links are not completely the same, and the optimal retimer parameters are obtained after verification based on corresponding link tuning; The controller adjusts the retimer using the matched optimal retimer parameters.

3. The link signal optimization device based on retimer and link matching according to claim 2, characterized in that: The first link device includes at least two serial interfaces, the first link segment also includes an adapter card and at least two first connectors, the adapter card includes at least two second connectors, the serial interfaces, the first connectors and the second connectors are connected in a one-to-one correspondence, and the second connectors are connected in a one-to-one correspondence with the retimer; The second link segment further includes a third connector, the third connector being used to connect the retimer and the expansion module in a one-to-one correspondence; The controller obtains first link segment information, second link segment information, and link device information, including: Based on the adapter card and the retimer, the controller reads a first connector address to obtain first link segment information; Based on the adapter card, the second connector, the retimer and the third connector, the controller reads the expansion module identifier to obtain second link segment information; Based on the adapter card, the second connector, the retimer and the third connector, the controller reads the second link device information in the expansion module to obtain link device information.

4. The link signal optimization device based on retimer and link matching according to claim 3, characterized in that: The first connector address is an address identifier corresponding to the first connector configured based on the address configuration module, and the number of address identifier bits n and the number of serial interfaces m of the first link device satisfy 2 n ≥m.

5. The link signal optimization device based on retimer and link matching according to claim 3, characterized in that: The adapter card further includes a first sideband signal connector, the device further includes a second sideband connector, the third connector includes a first connection end and a second connection end, the first connection end and the second connection end are connected via a cable; Based on the riser card, the second connector, the retimer, and the third connector, the controller reads the expansion module identification, including: Based on the second sideband signal connector, the first sideband signal connector, the second connector correspondingly connected to the first sideband signal connector, the gold finger connected to the second connector, the retimer connected to the gold finger, the first connection end correspondingly plugged into the retimer, and the cable correspondingly connected to the first connection end and the second connection end plugged into the expansion module, the controller reads the identification information of the expansion module stored in the field replaceable unit chip connected to the corresponding cable to obtain the expansion module identification.

6. The link signal optimization device based on retimer and link matching according to claim 5, characterized in that: Based on the riser card and the retimer, the controller reads a first connector address, including: Based on the second sideband signal connector, the first sideband signal connector, the second connector corresponding to the first sideband signal connector, and the gold finger connected to the second connector, the controller reads the address information of the first connector stored in the input and output expansion chip connected to the corresponding gold finger to obtain the first connector address.

7. The link signal optimization device based on retimer and link matching according to claim 5, characterized in that: Based on the riser card, the second connector, the retimer, and the third connector, the controller reads second link device information in the expansion module, including: Based on the second sideband signal connector, the first sideband signal connector, the second connector correspondingly connected to the first sideband signal connector, the gold finger connected to the second connector, the retimer connected to the gold finger, the third connector correspondingly connected to the retimer, and the expansion module correspondingly connected to the third connector, the controller reads the second link device information in the corresponding expansion module.

8. The link signal optimization device based on retimer and link matching according to claim 5, characterized in that: The controller adjusts the retimer using the matched optimal retimer parameters, including: The controller generates an integrated circuit bus signal according to the matched optimal retimer parameter, and sends the integrated circuit bus signal to the second sideband signal connector based on the corresponding integrated circuit bus channel; The second sideband signal connector receives the integrated circuit bus signal and sends the received integrated circuit bus signal to the first sideband signal connector through a corresponding channel of the cable; The first sideband signal connector sends the received integrated circuit bus signal to the corresponding second connector based on the printed circuit board trace connected to the corresponding second connector; The second connector sends the integrated circuit bus signal to the retimer based on the gold finger to adjust the parameters of the retimer.

9. The link signal optimization device based on retimer and link matching according to claim 3, characterized in that: Before the retimer receives the signal sent by the first link device or the second link device, the method includes: The first link device sends a signal to a first connector corresponding to the serial interface through the serial interface; The first connector receives the signal, and sends the received signal to the retimer through a second connector corresponding to the adapter card; or, The second-link device sends a signal to the retimer through the third connector.

10. A link signal optimization method based on retimer and link matching, characterized in that: include: receiving a signal sent by the first link device or the second link device; Parse the received signal sent by the first link device and send the parsed signal to the second link device, or parse the received signal sent by the second link device and send the parsed signal to the first link device; wherein the retimer is obtained by the controller after adjusting the parameters of the optimal retimer based on the first link segment information, the second link segment information and the link device information obtained previously, the first link segment is used to characterize the link composed of the first link device and the retimer as link nodes, the second link segment is used to characterize the link composed of the retimer and the expansion module with the second link device built in as link nodes, and the link device information includes the second link device information.

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