Storage and calculation integrated chip architecture based on MRAM (Magnetic Random Access Memory)

Abstract

The invention provides a storage and calculation integrated chip architecture based on an MRAM (Magnetic Random Access Memory), which comprises an in-storage calculation circuit and further comprises an in-storage calculation array formed based on MRAM units and used for realizing in-storage multiply-accumulate operation, states of every two rows of word lines of the in-storage calculation array are complementary, and the states of every two rows of word lines jointly represent input of the multiply-accumulate operation; the states of every two rows of MTJs of the in-memory calculation array are complementary, and the states of every two rows of MTJs jointly represent the weight of a multiply-accumulate operation; the first current mirror circuit is connected with bit lines of all columns of the in-memory computing array and used for copying a relatively constant current to all the columns of the in-memory computing array so as to obtain an output voltage on each column, and the output voltage of each column is used for representing a multiply-accumulate computing result of each column.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a storage-computing integrated chip architecture based on MRAM. Background Art

[0002] Currently, artificial intelligence technology is booming. For example, the highly artificial intelligence language model Chatgpt has been born, and artificial intelligence has penetrated into all aspects of society. For artificial intelligence computing, the increase in functions means the increase in computing power, and traditional devices can no longer meet the growing demand for computing power. Especially on mobile and offline terminal devices, it is impossible to borrow the computing power of cloud servers at all times. In order to save power consumption and reduce latency, the demand for storage and computing integrated chips has become increasingly obvious.

[0003] Among various types of integrated storage and computing chips, magnetic random access memory (MRAM) has the advantages of non-volatility, high-speed reading and writing, low power consumption, and unlimited erasing and writing. Its high temperature resistance and radiation resistance can be used for reasoning in extreme environments. Therefore, it is necessary to propose an integrated storage and computing chip architecture based on MRAM. Summary of the invention

[0004] In view of this, the present invention provides a memory-computation integrated chip architecture based on MRAM, which can realize multiplication and accumulation operations in memory.

[0005] The present invention provides a memory-computing integrated chip architecture based on MRAM, including: an in-memory computing circuit, wherein the in-memory computing circuit includes:

[0006] An in-memory computing array based on MRAM cells is used to implement in-memory multiplication and accumulation operations. The states of every two rows of word lines in the in-memory computing array are complementary, and the states of every two rows of word lines jointly represent the input of a multiplication and accumulation operation. When the input is +1, the first row of the two rows of word lines is a high level, and the second row is a low level; when the input is -1, the first row of the two rows of word lines is a low level, and the second row is a high level; the states of every two rows of MTJs in the in-memory computing array are complementary, and the states of every two rows of MTJs jointly represent the weight of a multiplication and accumulation operation. When the weight is +1, the first row of the two rows of MTJs is in a high resistance state, and the second row is in a low resistance state; when the weight is -1, the first row of the two rows of MTJs is in a low resistance state, and the second row is in a high resistance state;

[0007] The first current mirror circuit is connected to the bit lines of each column of the in-memory computing array and is used to replicate a relatively constant current to each column of the in-memory computing array so as to obtain an output voltage on each column. The output voltage of each column is used to represent the multiplication and accumulation calculation results of each column.

[0008] Optionally, it also includes:

[0009] A first read / write circuit, used for performing read / write operations on the in-memory computing array;

[0010] The central control module is used to control the read and write operations of the first read and write circuit, and when the weights stored in the in-memory computing array are updated, the new weights are written into the in-memory computing array.

[0011] Optionally, it also includes:

[0012] An output cache circuit, comprising an output cache array based on MRAM cells and a second read-write circuit in its periphery, wherein the output cache array is used to cache the multiplication and accumulation calculation results of each column of the in-memory calculation array, the source lines of each column of the output cache array are connected to a fixed voltage, the bit lines of each column of the output cache array are grounded through a controllable switch, and the second read-write circuit is used to perform read and write operations on the output cache array;

[0013] A conversion circuit, connected between the in-memory computing array and the output cache array, for converting the output voltage of each column of the in-memory computing array into a write current of each column of the output cache array;

[0014] The central control module is also used to determine whether the multiplication-accumulation calculation results cached in the output cache array need to be continued to be calculated. If continued calculation is required, the second reading circuit is controlled to read the multiplication-accumulation calculation results cached in the output cache array for continued calculation; if continued calculation is not required, the multiplication-accumulation calculation results cached in the output cache array are read and output.

[0015] Optionally, the conversion circuit includes:

[0016] A plurality of conversion branches having the same number as the number of columns of the in-memory computing array, each conversion branch comprising a MOSFET switch, an input NMOS transistor and a second current mirror circuit,

[0017] The MOSFET switch includes an NMOS tube and a PMOS tube connected in parallel, and a gate-end signal inverter, wherein the gate end of the NMOS tube is connected to the gate end of the PMOS tube through the gate-end signal inverter, serving as a control end of the MOSFET switch; the source end of the NMOS tube is connected to the source end of the PMOS tube, serving as a first connection end of the MOSFET switch; the drain end of the NMOS tube is connected to the drain end of the PMOS tube, serving as a second connection end of the MOSFET switch;

[0018] A first control signal of high or low level is input to the control end of the MOSFET switch, the first control signal is provided by the central control module, a first connection end of the MOSFET switch is connected to a bit line of a column of the in-memory computing array, a second connection end of the MOSFET switch is connected to the gate end of the input NMOS tube, and a source end of the input NMOS tube is grounded;

[0019] The second current mirror circuit includes two PMOS tubes with a common gate and a common source, the source ends of the two PMOS tubes are connected to the power supply end, the gate ends of the two PMOS tubes are connected to the drain end of the input NMOS tube, the drain end of one of the PMOS tubes is connected to the drain end of the input NMOS tube, and the drain end of the other PMOS tube is connected to the bit line of a column of the output cache array.

[0020] Optionally, it also includes:

[0021] A first calculation signal control circuit, connected between the central control module and the in-memory calculation array, for controlling the state of each row word line of the in-memory calculation array according to a second control signal of high and low levels, so as to provide input to the in-memory calculation array;

[0022] The central control module is also used to convert the 0 / 1 data that can be input into the in-memory computing array in real time into the second control signal through voltage coding.

[0023] Optionally, the first calculation signal control circuit includes:

[0024] MOSFET switches having the same number of rows as the in-memory computing array, each MOSFET switch comprising an NMOS tube and a PMOS tube connected in parallel, and a gate-end signal inverter, the gate end of the NMOS tube being connected to the gate end of the PMOS tube via the gate-end signal inverter, serving as a control end of the MOSFET switch; the source end of the NMOS tube being connected to the source end of the PMOS tube, serving as a first connection end of the MOSFET switch; the drain end of the NMOS tube being connected to the drain end of the PMOS tube, serving as a second connection end of the MOSFET switch;

[0025] The control end of each MOSFET switch inputs the second control signal, the first connection end of each MOSFET switch is respectively connected to a high level end, and the second connection end of each MOSFET switch is respectively connected to a row of word lines of the in-memory computing array.

[0026] Optionally, it also includes:

[0027] An input cache circuit, comprising an input cache array based on MRAM cells and a third read-write circuit in its periphery, wherein the input cache array is used to cache 0 / 1 data that cannot be input into the in-memory computing array in real time, and the third read-write circuit is used to perform read and write operations on the input cache array;

[0028] A second calculation signal control circuit is connected between the input cache array and the in-memory calculation array, and is used to control the state of each row word line of the in-memory calculation array according to a third control signal of a high or low level generated after the cached 0 / 1 data is read, so as to provide input to the in-memory calculation array;

[0029] The central control module is also used to control the read and write operations of the third read and write circuit, write the 0 / 1 data that cannot be input into the in-memory computing array in real time into the input cache array, and read out the 0 / 1 data cached in the input cache array when the in-memory computing array is idle.

[0030] Optionally, the second calculation signal control circuit includes:

[0031] The number of MOSFET switches is the same as the number of rows of the in-memory computing array;

[0032] and, a cache data inverter connected one-to-one with each MOSFET switch;

[0033] The third control signal is input to the input end of each cache data inverter, and the output end of each cache data inverter is connected to the control end of the MOSFET switch; the first connection end of each MOSFET switch is respectively connected to a high level end, and the second connection end of each MOSFET switch is respectively connected to a row of word lines of the in-memory computing array.

[0034] Optionally, it also includes:

[0035] A weight storage array based on MRAM cells, used to store the spare weights of the in-memory computing array;

[0036] The weight storage array and the input cache array share the third read-write circuit. When the weight of the in-memory computing array needs to be updated, the weight is read from the weight storage array and written into the in-memory computing array.

[0037] Optionally, the central control module is a microcontroller or FPGA.

[0038] The MRAM-based integrated memory and computing chip architecture provided by the present invention uses an in-memory computing array to implement multiplication and accumulation operations in memory. Furthermore, by adding an output cache array and an input cache array, real-time caching of output data and input data is achieved, reducing bus pressure, power consumption and latency, and is suitable for application scenarios of multi-target detection and multi-layer reasoning. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic diagram of the structure of a storage-computing integrated chip based on MRAM according to an embodiment of the present invention;

[0040] Figure 2 It is a schematic diagram of the structure of a MOSFET switch;

[0041] Figure 3 It is a schematic diagram of transient simulation circuit verification of output buffer circuit;

[0042] Figure 4 It is a schematic diagram of data down-sampling reading;

[0043] Figure 5 This is a schematic diagram of the structure of a storage-computing integrated chip based on MRAM according to an embodiment of the present invention;

[0044] Figure 6 This is an overall block diagram of a storage-computing integrated chip architecture based on MRAM according to an embodiment of the present invention;

[0045] Figure 7 The present invention is an application example and a schematic diagram of a data processing flow thereof. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0049] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0050] An embodiment of the present invention provides a memory-computing integrated chip architecture based on MRAM, the memory-computing integrated chip architecture includes an in-memory computing circuit 20, such as Figure 1 As shown, the in-memory computing circuit 20 includes:

[0051] The in-memory computing array formed based on MRAM cells is used to realize in-memory multiplication and accumulation operations. The states of every two rows of word lines in the in-memory computing array are complementary, and the states of every two rows of word lines jointly represent the input of a multiplication and accumulation operation. When the input is +1, the first row of the two rows of word lines is high level, and the second row is low level; when the input is -1, the first row of the two rows of word lines is low level, and the second row is high level; the states of every two rows of MTJs in the in-memory computing array are complementary, and the states of every two rows of MTJs jointly represent the weight of a multiplication and accumulation operation. When the weight is +1, the first row of the two rows of MTJs is in a high resistance state, and the second row is in a low resistance state; when the weight is -1, the first row of the two rows of MTJs is in a low resistance state, and the second row is in a high resistance state;

[0052] The first current mirror circuit is connected to the bit lines of each column of the in-memory computing array and is used to replicate a relatively constant current to each column of the in-memory computing array so as to obtain an output voltage on each column. The output voltage of each column is used to represent the multiplication and accumulation calculation results of each column.

[0053] Figure 1 An optional circuit structure of the first current mirror circuit is shown. The in-memory computing array has n+1 bit lines BL0-BLn, the first current mirror circuit includes n+1 PMOS tubes and 1 NMOS tube, the source end of the NMOS tube is grounded, the drain end of the NMOS tube is connected to the drain end of one of the PMOS tubes, the drain ends of the other n PMOS tubes are respectively connected to a bit line of the in-memory computing array, the gate ends of the n+1 PMOS tubes are connected together and connected to the drain end of the NMOS tube, and the source ends of the n+1 PMOS tubes are connected together and connected to the power supply end VDD.

[0054] Furthermore, the in-memory computing array periphery has a first read-write circuit ( Figure 1 (not shown), the first read / write circuit is used to perform read / write operations on the in-memory computing array;

[0055] The integrated storage and computing chip architecture also includes a central control module 10, which is used to control the read and write operations of the first read and write circuit, and when the weights stored in the in-memory computing array are updated, the new weights are written into the in-memory computing array.

[0056] It can be understood that the first read / write circuit includes a row decoder, a column decoder and a sense amplifier, and the sense amplifier is a voltage sensing or current sensing type.

[0057] Further, in one embodiment, continue to refer to Figure 1 The storage-computing integrated chip architecture further includes: an output buffer circuit 30 and a conversion circuit 40,

[0058] The output buffer circuit 30 includes an output buffer array based on MRAM cells and a second read / write circuit around it. The output buffer array is used to buffer the multiplication and accumulation calculation results of each column of the internal calculation array. The source lines of each column of the output buffer array are connected to a fixed voltage V B (determined by the maximum number of rows opened during caching and the size of the transistors of the second current mirror circuit), the bit lines of each column of the output cache array are grounded through a controllable switch, and the second read-write circuit is used to perform read and write operations on the output cache array;

[0059] The conversion circuit 40 is connected between the in-memory calculation array and the output cache array, and is used to convert the output voltage of each column of the in-memory calculation array into the write current of each column of the output cache array;

[0060] The central control module 10 is also used to determine whether the multiplication-accumulation calculation results cached in the output cache array need to be continued to be calculated. If continued calculation is required, the second reading circuit is controlled to read the multiplication-accumulation calculation results cached in the output cache array for continued calculation; if continued calculation is not required, the multiplication-accumulation calculation results cached in the output cache array are read and output.

[0061] It can be understood that the second read / write circuit includes a row decoder, a column decoder and a sense amplifier, and the sense amplifier is a voltage sensing or current sensing type. Figure 1 Only the sense amplifier of the second read / write circuit is shown.

[0062] Figure 1 An optional circuit structure of the conversion circuit 40 is shown. The conversion circuit 40 includes:

[0063] Multiple conversion branches with the same number of columns as the in-memory computation array, Figure 1 n+1 conversion branches are shown, each of which includes a MOSFET switch, an input NMOS transistor and a second current mirror circuit.

[0064] The structure of the MOSFET switch can be referred to Figure 2 , the MOSFET switch includes an NMOS tube and a PMOS tube connected in parallel, and a gate-end signal inverter. The gate end of the NMOS tube is connected to the gate end of the PMOS tube through the gate-end signal inverter, serving as the control end C of the MOSFET switch; the source end of the NMOS tube is connected to the source end of the PMOS tube, serving as the first connection end A of the MOSFET switch; the drain end of the NMOS tube is connected to the drain end of the PMOS tube, serving as the second connection end B of the MOSFET switch. When C is low level, the MOSFET switch is turned off. When C is high level, the MOSFET switch is turned on.

[0065] The control end of the MOSFET switch inputs a first control signal Vcom of high or low level, the first control signal Vcom is provided by the central control module, the first connection end of the MOSFET switch is connected to a bit line of a column of the internal computing array, the second connection end of the MOSFET switch is connected to the gate end of the input NMOS tube, and the source end of the input NMOS tube is grounded;

[0066] The second current mirror circuit includes two PMOS tubes with a common gate and a common source, the source ends of the two PMOS tubes are connected to the power supply end VDD, the gate ends of the two PMOS tubes are connected to the drain end of the input NMOS tube, the drain end of one of the PMOS tubes is connected to the drain end of the input NMOS tube, and the drain end of the other PMOS tube is connected to the bit line of a column of the output cache array.

[0067] The working process of the in-memory computing circuit and the output cache circuit is introduced in detail below.

[0068] The in-memory calculation circuit completes the multiplication and accumulation operation, and the multiplication operation is realized by the in-memory calculation array. The multiplication calculation truth table is shown in Table 1. Among them, open and close represent the high and low voltage levels of the word line WL respectively. The word line is open when it is high, and closed when it is low.

[0069] The states of every two rows of word lines in the in-memory computing array are complementary, and the states of every two rows of word lines together represent the input of a multiplication and accumulation operation. When the input is +1, the first row of the two rows is high level (on), and the second row is low level (off); when the input is -1, the first row of the two rows is low level (off), and the second row is high level (on).

[0070] The states of every two rows of magnetic tunnel junctions in the in-memory computing array are complementary, and the states of every two rows of magnetic tunnel junctions together represent the weight of a multiplication and accumulation operation. When the weight is +1, the first row of the two rows is in a high resistance state (AP) and the second row is in a low resistance state (P); when the weight is -1, the first row of the two rows is in a low resistance state (P) and the second row is in a high resistance state (AP).

[0071] As shown in the first row of Table 1, when the input is +1 and the weight is +1, the word line WL in the first row is turned on and the second row is turned off. At this time, the state of the MTJ in the first row is high impedance (AP) and the state of the MTJ in the second row is low impedance (P). Since the second row is turned off and the first row is turned on, the output MTJ state is high impedance (AP), i.e. +1. Similarly, when the input is +1 and the weight is -1, the first row is turned on and the output MTJ resistance state (P), i.e. -1, is output; when the input is -1 and the weight is +1, the second row is turned on and the output MTJ resistance state (P), i.e. -1, is output; when the input is -1 and the weight is -1, the second row is turned on and the output MTJ resistance state (AP), i.e. +1, is output.

[0072] Table 1 Multiplication truth table

[0073]

[0074] The above operation satisfies the XNOR logic, that is, the MTJ branch under the control of the WL realizes the XNOR logic through complementation to complete the multiplication operation.

[0075] The addition operation is implemented by a first current mirror circuit, which replicates a relatively constant current I BL To each column of the in-memory calculation array, an output voltage is formed on each column. The output voltage of each column of the in-memory calculation array is the calculation result of the multiplication and accumulation operation, recorded as V A0 ~V An , with V An For example, it can be expressed by Ohm's law as follows:

[0076] V An =I BL *R mtjs

[0077] Where R mtjs Indicates the resistance value of the resistor in the n+1th column.

[0078] like Figure 1As shown, the output voltage V of each column of the array is calculated in memory A0 ~V An The current I is transmitted to the NMOS input tube in the conversion circuit through the MOSFET switch as its gate voltage, and then copied to the output buffer array through the second current mirror. in 0~I in n is used as the write current of each column in the output cache array. According to the magnitude of the write current, the corresponding number of rows can be turned on to realize the reading and storage of the multiplication and accumulation operation results.

[0079] The steps to cache the calculation results in memory in real time are as follows:

[0080] In Phase 1, the control signal CLK of the controllable switch is low, the controllable switch is turned on, and V com Disconnect, at this time, the output buffer array is set to +1 (anti-parallel state, AP), and the fixed voltage V B It is at a high level, one side of the magnetic tunnel junction MTJ is grounded, and the writing of the AP state is completed.

[0081] In Phase 2, the control signal CLK of the controllable switch is high, the controllable switch is disconnected, and V com Open, calculate the output voltage V of each column of the array in memory A0 ~V An The second current mirror is used to convert the current into the write current of each column of the output cache array. At this time, the on and off of WWL0-WWLn are controlled to distinguish the write current.

[0082] For special explanation, when the output voltage of each column of the in-memory computing array is 16P~16AP (-16~+16), the corresponding write current can be distinguished by turning on 13 rows, 5 rows, and 2 rows respectively after calculation. When the write current is less than the critical flipping current of the magnetic tunnel junction after being diverted through the MTJ branches of the output cache array, the magnetic tunnel junction maintains state 1 unchanged.

[0083] like Figure 3 As shown, phase 1 completes writing, Out <1> ~Out <n>Represents the status of the cache unit, where Out <1> In the reset phase, the state is reset from -1 to +1, and the states of other cache units are reset to +1. In phase 2, the word line WL is turned on. During verification, the input is assumed to be +1, and the output resistance is 10 high-resistance resistors and 6 low-resistance resistors, that is, the output value is +4. Phase 2 reads "+4", first turning on WWL<0:12>, that is Figure 3 When the 15ns~25ns are in the middle, all 13 lines are turned on and Out <13> The value does not change, that is, the current I is written at this moment in0 Less than the critical current sum of 13 MTJ branches, MTJ cannot flip. 25ns~35ns, close WWL<5:12>, open only the first 5 rows, Out <5> The value changes, that is, the first 5 rows are flipped, so it can be determined that the write current range is within rows 5 to 13, which corresponds to the actual output "2". 35ns to 45ns, close WWL<2:4>, judge the flip, at this time, due to the large write current, Out <1> The flip has already occurred in the last judgment, but when the output of the multiplication and accumulation is between -16 and -8, that is, "0", the MTJ will not flip in the previous judgments (closing WWL<5:12> and WWL<2:4>).

[0084] The output voltage of each column of the in-memory calculation array is converted from -16 to +16 to 0 to 4 after being written into the output buffer array. Figure 4 As shown in the figure, the output completes the 2-bit read and is automatically stored in the MTJ of the corresponding row. The call of the cached in-memory calculation results can be read by the sense amplifier as follows Figure 3 Out <1> ,Out <5> ,Out <13> The above process completes the analog-to-digital conversion of the low bits of the calculation results in the memory and directly caches them in the non-volatile magnetic storage unit.

[0085] Further, in one embodiment, if Figure 5 As shown, the integrated storage and computing chip architecture also includes:

[0086] The first calculation signal control circuit 50 is connected between the central control module 10 and the in-memory calculation array, and is used to control the state of each row word line of the in-memory calculation array according to the second control signal of high and low levels, so as to provide input to the in-memory calculation array;

[0087] The central control module 10 is also used to convert the 0 / 1 data that can be input into the in-memory computing array in real time into a second control signal by means of voltage coding.

[0088] Figure 5 FIG. 5 shows an optional circuit structure of the first calculation signal control circuit 50. The first calculation signal control circuit 50 includes:

[0089] The number of MOSFET switches is the same as the number of rows of the in-memory computing array, each MOSFET switch includes an NMOS tube and a PMOS tube connected in parallel, and a gate-end signal inverter, the gate end of the NMOS tube is connected to the gate end of the PMOS tube through the gate-end signal inverter, and serves as a control end of the MOSFET switch; the source end of the NMOS tube is connected to the source end of the PMOS tube, and serves as a first connection end of the MOSFET switch; the drain end of the NMOS tube is connected to the drain end of the PMOS tube, and serves as a second connection end of the MOSFET switch;

[0090] The control terminal of each MOSFET switch inputs the second control signal, and the first connection terminal of each MOSFET switch is respectively connected to a high level terminal V C1 The second connection terminal of each MOSFET switch is respectively connected to a row of word lines of the in-memory computing array. C1 is high level, and the second control signal is transmitted to a row of word lines of the in-memory computing array.

[0091] Further, in one embodiment, referring to Figure 5 The storage-computing integrated chip architecture further includes: an input cache circuit 60 and a second computing signal control circuit 70,

[0092] The input cache circuit 60 includes an input cache array based on MRAM cells and a third read / write circuit in its periphery. The input cache array is used to cache 0 / 1 data that cannot be input into the in-memory computing array in real time. The third read / write circuit is used to perform read and write operations on the input cache array.

[0093] The second calculation signal control circuit 70 is connected between the input cache array and the in-memory calculation array, and is used to control the state of each row word line of the in-memory calculation array according to the third control signal of high and low levels generated after the cached 0 / 1 data is read, so as to provide input to the in-memory calculation array;

[0094] The central control module 10 is also used to control the read and write operations of the third read and write circuit, write the 0 / 1 data that cannot be input into the in-memory computing array in real time into the input cache array, and read out the 0 / 1 data cached in the input cache array when the in-memory computing array is idle.

[0095] It can be understood that the third read-write circuit includes a row decoder, a column decoder and a sense amplifier, and the sense amplifier is a voltage sensing or current sensing type. Figure 5 The row decoder, column decoder and sense amplifier of the third read / write circuit are shown.

[0096] Figure 5 FIG. 7 shows an optional circuit structure of the second calculation signal control circuit 70. The second calculation signal control circuit 70 includes:

[0097] The number of MOSFET switches is the same as the number of rows of the in-memory computation array;

[0098] and, a cache data inverter connected one-to-one with each MOSFET switch;

[0099] The third control signal is input to the input end of each cache data inverter, and the output end of each cache data inverter is connected to the control end of the MOSFET switch; the first connection end of each MOSFET switch is respectively connected to a high level end V C2 The second connection terminal of each MOSFET switch is respectively connected to a row of word lines of the in-memory computing array. C2 is high level, and the third control signal is transmitted to a row of word lines of the in-memory computing array.

[0100] The data input process is described in detail below.

[0101] For the 0 / 1 data that can be input into the in-memory computing array in real time, it is input into the MOSFET switch control terminal of the first computing signal control circuit through voltage coding, and the MOSFET switch is used to control the word line state of the in-memory computing array.

[0102] When there are multiple inputs, the 0 / 1 data to be cached reaches the row decoder and column decoder through address encoding and is cached in the input cache array. The 0 / 1 data cached in the input cache array can be read by the sensitive amplifier through timing call and input to the second calculation signal control circuit. Since there is an inversion when reading the data, it enters the second calculation signal control circuit, is first inverted, and then input to the control end of the MOSFET switch. The MOSFET switch is used to control the word line state of the calculation array in the memory.

[0103] Further, in one embodiment, continue to refer to Figure 5 , the integrated storage and computing chip architecture also includes:

[0104] A weight storage array based on MRAM cells, used to store weights for backup in the in-memory computing array;

[0105] The weight storage array and the input cache array share a third read-write circuit. When the weight of the in-memory computing array needs to be updated, the weight is read from the weight storage array and written into the in-memory computing array.

[0106] It should be noted that, from a functional point of view, the weight storage array does not belong to the input cache circuit, but it can be designed together with the input cache array and share the third read-write circuit.

[0107] In the above embodiments, the central control module is a microcontroller or FPGA. The central control module is used to control the movement of circuit signals and data. In addition to the functions mentioned above, it is also used to complete some non-multiplication-accumulation operations, such as ReLU activation and pooling operations.

[0108] Figure 6 A structural block diagram of the integrated memory and computing chip architecture is shown, including the central control module 10, in-memory computing circuit 20, output cache circuit 30, conversion circuit 40, first computing signal control circuit 50, input cache circuit 60 and second computing signal control circuit 70 mentioned in the above embodiments.

[0109] An MRAM-based integrated storage and computing chip architecture provided by an embodiment of the present invention has the following beneficial effects:

[0110] 1. The in-memory computing design applied to non-volatile memory adopts the memory-computing integrated paradigm of non-von Neumann architecture to realize in-memory multiplication and accumulation operations.

[0111] 2. It can realize real-time caching of calculation results, complete the reading of calculation results by writing into the output cache array, and read out the corresponding numbers through the sensitive amplifier.

[0112] 3. While caching the calculation results in real time, the calculation results are read in bits down (such as 5 bits to 2 bits), which reduces the calculation complexity. At the same time, due to the particularity of the corresponding application algorithm, a certain accuracy can be maintained.

[0113] 4. Real-time caching of input and output reduces bus pressure, power consumption and latency, and is suitable for multi-target detection and multi-layer reasoning applications. In multi-target detection, the input is cached, and the calculation scheme is flexible, which is suitable for reuse of small-scale arrays when computing power is insufficient.

[0114] The MRAM-based integrated storage and computing chip architecture provided by the embodiment of the present invention is applied. First, after the sensor data is input into the central control module, the central control module first determines whether the calculation can be completed in the in-memory computing module. If there are multiple inputs and parallel calculation is not possible, a part of the data is input in real time; the other part of the data is cached to the input cache array, and the cached data is then input by the second calculation signal control circuit.

[0115] Secondly, the in-memory computing circuit is responsible for completing the multiplication and accumulation operations, and the calculation results are cached in real time to the output cache array through the conversion circuit.

[0116] Finally, the central control module determines whether to continue the calculation. If yes, the calculation result in the output buffer array is read out and returned to the central control module. After the logic part in the central control module implements operations such as ReLU and Pool, it is input in real time. If no, the calculation result is directly output.

[0117] Figure 7 An application example of an embodiment of the present invention and its data processing process are shown. When multiple vehicles running red lights are captured, multiple pictures are transmitted to the integrated storage and computing chip in the camera through the sensor, one picture is input in real time, and the remaining pictures are cached for standby use. The real-time picture is automatically stored in the output cache after the calculation circuit in the MRAM memory completes the calculation. The data in the output cache array can be called by the central control module and then continue to be input into the next layer, which meets the requirements of multi-layer reasoning. The final output feature results are stored in the output cache, which is non-volatile and can be called at any time.

[0118] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.< / n>

Claims

1. A storage and computing integrated chip architecture based on MRAM, characterized in that: include: An in-memory computing circuit, the in-memory computing circuit comprising: An in-memory computing array based on MRAM cells is used to implement in-memory multiplication and accumulation operations. The states of every two rows of word lines in the in-memory computing array are complementary, and the states of every two rows of word lines jointly represent the input of a multiplication and accumulation operation. When the input is +1, the first row of the two rows of word lines is a high level, and the second row is a low level; when the input is -1, the first row of the two rows of word lines is a low level, and the second row is a high level; the states of every two rows of MTJs in the in-memory computing array are complementary, and the states of every two rows of MTJs jointly represent the weight of a multiplication and accumulation operation. When the weight is +1, the first row of the two rows of MTJs is in a high resistance state, and the second row is in a low resistance state; when the weight is -1, the first row of the two rows of MTJs is in a low resistance state, and the second row is in a high resistance state; The first current mirror circuit is connected to the bit lines of each column of the in-memory computing array and is used to replicate a relatively constant current to each column of the in-memory computing array so as to obtain an output voltage on each column. The output voltage of each column is used to represent the multiplication and accumulation calculation results of each column.

2. The MRAM-based integrated storage and computing chip architecture according to claim 1, characterized in that: Also includes: A first read / write circuit, used for performing read / write operations on the in-memory computing array; The central control module is used to control the read and write operations of the first read and write circuit, and when the weights stored in the in-memory computing array are updated, the new weights are written into the in-memory computing array.

3. The MRAM-based integrated storage and computing chip architecture according to claim 2, characterized in that: Also includes: An output cache circuit, comprising an output cache array based on MRAM cells and a second read-write circuit in its periphery, wherein the output cache array is used to cache the multiplication and accumulation calculation results of each column of the in-memory calculation array, the source lines of each column of the output cache array are connected to a fixed voltage, the bit lines of each column of the output cache array are grounded through a controllable switch, and the second read-write circuit is used to perform read and write operations on the output cache array; A conversion circuit, connected between the in-memory computing array and the output cache array, for converting the output voltage of each column of the in-memory computing array into a write current of each column of the output cache array; The central control module is also used to determine whether the multiplication-accumulation calculation results cached in the output cache array need to be continued to be calculated. If continued calculation is required, the second reading circuit is controlled to read the multiplication-accumulation calculation results cached in the output cache array for continued calculation; if continued calculation is not required, the multiplication-accumulation calculation results cached in the output cache array are read and output.

4. The MRAM-based integrated storage and computing chip architecture according to claim 3, characterized in that: The conversion circuit comprises: A plurality of conversion branches having the same number as the number of columns of the in-memory computing array, each conversion branch comprising a MOSFET switch, an input NMOS transistor and a second current mirror circuit, The MOSFET switch includes an NMOS tube and a PMOS tube connected in parallel, and a gate-end signal inverter, wherein the gate end of the NMOS tube is connected to the gate end of the PMOS tube through the gate-end signal inverter, serving as a control end of the MOSFET switch; the source end of the NMOS tube is connected to the source end of the PMOS tube, serving as a first connection end of the MOSFET switch; the drain end of the NMOS tube is connected to the drain end of the PMOS tube, serving as a second connection end of the MOSFET switch; A first control signal of high or low level is input to the control end of the MOSFET switch, the first control signal is provided by the central control module, a first connection end of the MOSFET switch is connected to a bit line of a column of the in-memory computing array, a second connection end of the MOSFET switch is connected to the gate end of the input NMOS tube, and a source end of the input NMOS tube is grounded; The second current mirror circuit includes two PMOS tubes with a common gate and a common source, the source ends of the two PMOS tubes are connected to the power supply end, the gate ends of the two PMOS tubes are connected to the drain end of the input NMOS tube, the drain end of one of the PMOS tubes is connected to the drain end of the input NMOS tube, and the drain end of the other PMOS tube is connected to the bit line of a column of the output cache array.

5. The MRAM-based integrated storage and computing chip architecture according to claim 2, characterized in that: Also includes: A first calculation signal control circuit, connected between the central control module and the in-memory calculation array, for controlling the state of each row word line of the in-memory calculation array according to a second control signal of high and low levels, so as to provide input to the in-memory calculation array; The central control module is also used to convert the 0 / 1 data that can be input into the in-memory computing array in real time into the second control signal through voltage coding.

6. The MRAM-based integrated storage and computing chip architecture according to claim 5, characterized in that: The first calculation signal control circuit comprises: MOSFET switches having the same number of rows as the in-memory computing array, each MOSFET switch comprising an NMOS tube and a PMOS tube connected in parallel, and a gate-end signal inverter, the gate end of the NMOS tube being connected to the gate end of the PMOS tube via the gate-end signal inverter, serving as a control end of the MOSFET switch; the source end of the NMOS tube being connected to the source end of the PMOS tube, serving as a first connection end of the MOSFET switch; the drain end of the NMOS tube being connected to the drain end of the PMOS tube, serving as a second connection end of the MOSFET switch; The control end of each MOSFET switch inputs the second control signal, the first connection end of each MOSFET switch is respectively connected to a high level end, and the second connection end of each MOSFET switch is respectively connected to a row of word lines of the in-memory computing array.

7. The MRAM-based integrated storage and computing chip architecture according to claim 6, characterized in that: Also includes: An input cache circuit, comprising an input cache array based on MRAM cells and a third read-write circuit in its periphery, wherein the input cache array is used to cache 0 / 1 data that cannot be input into the in-memory computing array in real time, and the third read-write circuit is used to perform read and write operations on the input cache array; A second calculation signal control circuit is connected between the input cache array and the in-memory calculation array, and is used to control the state of each row word line of the in-memory calculation array according to a third control signal of a high or low level generated after the cached 0 / 1 data is read, so as to provide input to the in-memory calculation array; The central control module is also used to control the read and write operations of the third read and write circuit, write the 0 / 1 data that cannot be input into the in-memory computing array in real time into the input cache array, and read out the 0 / 1 data cached in the input cache array when the in-memory computing array is idle.

8. The MRAM-based integrated storage and computing chip architecture according to claim 7, characterized in that: The second calculation signal control circuit comprises: The number of MOSFET switches is the same as the number of rows of the in-memory computing array; and, a cache data inverter connected in one-to-one correspondence with each MOSFET switch; The third control signal is input to the input end of each cache data inverter, and the output end of each cache data inverter is connected to the control end of the MOSFET switch; the first connection end of each MOSFET switch is respectively connected to a high level end, and the second connection end of each MOSFET switch is respectively connected to a row of word lines of the in-memory computing array.

9. The MRAM-based integrated storage and computing chip architecture according to claim 7, characterized in that: Also includes: A weight storage array based on MRAM cells, used to store the spare weights of the in-memory computing array; The weight storage array and the input cache array share the third read-write circuit. When the weight of the in-memory computing array needs to be updated, the weight is read from the weight storage array and written into the in-memory computing array.

10. The MRAM-based integrated storage and computing chip architecture according to claim 2, characterized in that: The central control module is a microcontroller or FPGA.

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