Neural network-based radio frequency microsystem three-dimensional packaging process yield prediction method

Abstract

The invention discloses a radio frequency microsystem three-dimensional packaging process yield prediction method based on a neural network, and the method comprises the steps: firstly, dividing a radio frequency microsystem packaging process flow into four key process steps, and collecting process parameters related in each step and corresponding yield information; then, a multi-layer neural network architecture is constructed, the multi-layer neural network architecture comprises four sub-networks and a main network, the four sub-networks correspond to four key process steps in the packaging process respectively, the yield of each key process step is predicted according to the input process parameters and the corresponding yield information, the main network integrates the output and input parameters of the four sub-networks, and the yield of each key process step is predicted; and finally predicting the yield of the whole radio frequency microsystem packaging process. And finally, integrating the multi-level neural network architecture into a three-dimensional packaging process management system of the radio frequency microsystem, performing real-time yield prediction and early warning, optimizing and adjusting the process flow, improving the success rate of the packaging process, reducing finished product failure caused by defects, and finally improving the production efficiency and economic benefits.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency microsystem three-dimensional packaging technology, and in particular to a method for predicting the yield of radio frequency microsystem three-dimensional packaging technology based on neural network. Background Art

[0002] With the rapid development of microelectronics technology, three-dimensional integrated circuits and their related advanced packaging technologies have shown great potential in improving system performance, shortening signal transmission paths, reducing power consumption and achieving high-density integration. Through vertical stacking and interconnection technology, three-dimensional packaging has significantly improved the integration of the system and shortened the length of electrical interconnections, thereby reducing signal delays. However, although three-dimensional packaging technology has significant advantages in high performance, low power consumption and miniaturization, its complex packaging process also brings new challenges and problems. In practical applications, the complexity of the packaging process can easily lead to various process defects, such as poor manufacturing of through-silicon vias, interface delamination, warping caused by thermal expansion mismatch, and stress mismatch between packaging materials and chips. These defects accumulate in the microsystem and may seriously affect the electrical performance and reliability of the system.

[0003] During the packaging process of RF microsystems, the complexity and precision of the packaging process make process defects more likely to occur, and these defects usually have a profound impact on the electrical performance and overall yield of the system. Since the operating frequency of RF microsystems is usually at the GHz level, there are extremely strict requirements on parasitic parameters, signal integrity and thermal management in the circuit. Defects in the packaging process, such as the formation of microcracks, TSV misalignment, solder joint defects, and warpage caused by thermal expansion coefficient, will directly affect the performance of RF microsystems.

[0004] The performance degradation caused by these packaging defects will not only reduce the overall yield of the RF microsystem, but also make it difficult for the product to meet the expected performance standards in the market, which will lead to large-scale rework or scrapping, resulting in economic losses in production costs. Obviously, it is particularly important to find effective detection and prediction methods for potential defects in these packaging processes. Identifying problems as early as possible in the manufacturing process and taking corrective measures can improve the final yield of the RF microsystem. Summary of the invention

[0005] The problem to be solved by the present invention is to provide a method for predicting the yield of a three-dimensional packaging process of a radio frequency microsystem based on a neural network, utilizing the significant advantages of neural network technology in complex data processing and pattern recognition, and establishing a complex nonlinear mapping relationship by learning a large amount of packaging process data to achieve accurate prediction of the yield of the packaging product.

[0006] The present invention adopts the following technical solution: a method for predicting the yield rate of a radio frequency microsystem three-dimensional packaging process based on a neural network, comprising the following steps:

[0007] S1. Data collection and preparation: Divide the RF microsystem packaging process into four key process steps, namely: RF chip layer preparation, adapter board preparation, RF antenna layer preparation and stacking interconnection process; collect the process parameters and corresponding yield information involved in the four key process steps;

[0008] S2. Prediction model construction: construct a multi-level neural network architecture, including four sub-networks and one main network; the four sub-networks correspond to the four key process steps in the packaging process, and predict the yield of each key process step according to the input process parameters and corresponding yield information; the main network integrates the output and input parameters of the four sub-networks to make a final prediction on the yield of the entire RF microsystem packaging process;

[0009] S3. Prediction model training, integration and application: Integrate the multi-level neural network architecture constructed in step S2 into the three-dimensional packaging process management system of the RF microsystem to perform real-time yield prediction and early warning.

[0010] Preferably, the four sub-networks are independent of each other, and each sub-network adopts a multi-layer perceptron structure, including: an input layer, a plurality of hidden layers and an output layer, and the neurons in each layer transmit information to all neurons in the next layer through a fully connected manner;

[0011] The input layer receives the corresponding key process step input parameters, including the collected process parameters and the corresponding yield information, and performs nonlinear transformation through weighted summation and activation function to map the original input data into a high-dimensional feature space; the hidden layer determines the number of neurons, extracts potential patterns and relationships, outputs the yield prediction results of the process step through the output layer, and passes them together with the input parameters to the main network for comprehensive analysis.

[0012] Preferably, each sub-network determines the number of neurons in the hidden layer by five-fold cross validation, as follows:

[0013] S2.1. Randomly divide the dataset into five parts, train five network models and repeat the evaluation. Each network is trained using four parts of the dataset and tested and verified using the remaining parts.

[0014] S2.2. If the prediction accuracy of any network in the test is less than 90%, the optimizer is started to improve the structure and parameters of the network;

[0015] S2.3. Re-randomly divide the data set, train and verify the five newly generated network models;

[0016] S2.4. Calculate the coefficient of determination R of the neural network 2 , the performance of the network model is evaluated; the determination coefficient is used to evaluate the degree of fit of the model to the observed data, and the calculation formula is as follows:

[0017]

[0018] Among them, y k Indicates the actual output value, represents the predicted output value of the neural network, represents the output mean, N represents the number of output variables; R 2 The value range of is between 0 and 1, and the closer it is to 1, the better the model fit;

[0019] S2.5. If the coefficient of determination is less than 0.9, start the optimizer and repeat steps S2.2 to S2.3 to rebuild and train the neural network until it passes the training.

[0020] Preferably, the Dropout mechanism is incorporated when building each sub-network. In each training process, some neurons are randomly discarded, and the outputs of the neurons to be discarded are set to zero. The discarded neurons do not participate in forward propagation and back propagation in the current training step, which is used to break the co-adaptability between neurons and reduce the risk of overfitting.

[0021] Preferably, in step S3, a training data set is constructed for prediction model training, including process parameters, detection data and corresponding yield information under different process conditions; the model training process adopts a supervised learning method, uses different optimization algorithms to improve the prediction accuracy and convergence speed of the prediction model, verifies the model through a cross-validation method, and evaluates the performance of the model on a test set.

[0022] Preferably, the RF microsystem includes, from bottom to top, an adapter board, an RF chip layer, and an RF antenna layer; the RF chip layer and the RF antenna layer are welded and connected via a number of interconnection solder joints, an RF antenna is correspondingly arranged above each interconnection solder joint in the RF antenna layer, the chip is placed in the middle of the RF chip layer, and the adapter board layer is provided with a number of through silicon vias below the chip.

[0023] Preferably, the RF chip layer adopts chip embedding technology, and the sub-network input parameters corresponding to the preparation of the RF chip layer include: material type, preparation temperature, lamination pressure, annealing temperature and annealing time;

[0024] The material type is a semiconductor material, including silicon, gallium nitride and gallium arsenide; the preparation temperature is in the range of 300° C. to 600° C.; the lamination pressure is the pressure applied during the lamination process, in the range of 10 MPa to 50 MPa;

[0025] The annealing temperature ranges from 200° C. to 400° C.; the annealing time ranges from 10 minutes to 1 hour.

[0026] Preferably, the adapter board is a key component for electrical connection, and the sub-network input parameters corresponding to the preparation of the adapter board include: TSV size, TSV spacing, preparation temperature and TSV defects; the TSV size has a diameter range of 20μm to 100μm; the TSV spacing ranges from 50μm to 150μm; the preparation temperature ranges from 350℃ to 450℃; the TSV defects include: voids, cracks, and dislocations.

[0027] Preferably, the RF antenna layer and the corresponding sub-network input parameters for preparation include: antenna material type, deposition thickness, etching process parameters, pattern accuracy and dielectric layer thickness; the antenna material is a metal material type, including copper, silver and gold; the deposition thickness ranges from 5μm to 20μm; the etching process parameters include etching solution concentration and etching time, the etching solution concentration ranges from 20% to 30%, and the etching time ranges from 30 seconds to 60 seconds; the pattern accuracy ranges from ±1μm, and the dielectric layer thickness ranges from 50μm to 150μm.

[0028] Preferably, the stacking interconnection process between the RF chip layer and the RF antenna layer, the corresponding sub-network input parameters include: inter-layer alignment accuracy, welding temperature, interconnection material and interconnection defect type; the alignment accuracy ranges within ±1μm; the welding temperature ranges between 300 and 350°C; the interconnection material includes tin-lead alloy, silver paste and lead-free solder; the interconnection defects include voids, cracks and short circuits.

[0029] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0030] 1. The method for predicting the yield of the three-dimensional packaging process of the radio frequency microsystem of the present invention effectively copes with the yield challenge brought by the complexity of the packaging process through a multi-level neural network structure; by constructing four sub-networks, which correspond to the key preparation steps of the three-dimensional packaging of the radio frequency microsystem, independent yield prediction is performed, and specific analysis is performed on the corresponding process steps to ensure the accuracy of the prediction; the output results of each sub-network are integrated through the main network, and the influence of each process step and its interaction are comprehensively analyzed to achieve accurate prediction of the packaging yield of the entire microsystem; through this hierarchical and step-by-step integration approach, accurate prediction of the packaging yield of the entire microsystem is achieved.

[0031] 2. The neural network of the present invention is flexible in design and has good adaptability and scalability. The sub-network can be independently trained and adjusted according to the specific packaging process requirements, and the main network can integrate more sub-network outputs to adapt to the introduction of new processes or the optimization of existing processes, thereby expanding the application scope of the method. This not only improves the applicability of the prediction method, but also provides strong support for future process improvements and technology upgrades. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a flowchart of the yield prediction method of the radio frequency microsystem three-dimensional packaging process of the present invention;

[0033] Figure 2 It is a schematic diagram of the structure of the radio frequency microsystem of the present invention;

[0034] Figure 3 This is a neural network framework diagram for yield prediction of the present invention;

[0035] Figure 4 It is a flowchart of building a neural network of the present invention;

[0036] Figure 5 It is a schematic diagram of the neural network structure of the present invention;

[0037] Figure 6 It is a schematic diagram of the mechanism of the discarding method of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the application is further elaborated in detail below in conjunction with the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in the field on this embodiment belong to the protection scope of the present invention. At the same time, for the step numbering in the embodiment of the present invention, it is only set for the convenience of explanation, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0039] The present invention provides a method for predicting the yield rate of a radio frequency microsystem three-dimensional packaging process based on a neural network, comprising the following steps:

[0040] (1) Overall framework design. The core of the present invention is to design a multi-level neural network architecture for predicting the yield of the three-dimensional packaging process of the RF microsystem. The architecture includes four sub-networks and one main network. The four sub-networks correspond to the four key steps in the packaging process: RF chip layer preparation, adapter board preparation, RF antenna layer preparation and stacking interconnection process. The main network is responsible for integrating the outputs of the four sub-networks and all input parameters to make a final prediction of the yield of the entire microsystem.

[0041] (2) Subnetwork design. The design of each subnetwork needs to be targeted at the specific process step, taking into account the key process parameters, possible defect types, and defect detection methods in that step. Each subnetwork should consist of an input layer, several hidden layers, and an output layer. The input layer receives specific process parameters and detection results, and the output layer outputs the yield prediction results of the process step. The output of each subnetwork, that is, the yield prediction value of the process step, will be passed to the main network together with all input parameters for comprehensive analysis.

[0042] (3) Main network design. The design of the main network aims to integrate the outputs of the four sub-networks and the input parameters of each sub-network to make a final prediction of the overall yield of the RF microsystem. The input of the main network includes the yield prediction values ​​from the four sub-networks and all the input process parameters. With this design, the main network can not only reflect the independent impact of each process step, but also consider the mutual impact between the process steps. The main network should have sufficient depth and breadth to capture the complex interactions between the process steps.

[0043] (4) Dataset construction and model training. In order to effectively train the above neural network, it is necessary to construct a data set containing rich actual process data. The data set should cover all process parameters, test data and corresponding yield information under different process conditions. Supervised learning methods are used in the training process, and different optimization algorithms are used to improve the prediction accuracy and convergence speed of the model. The model is verified using methods such as cross-validation, and the performance of the model is evaluated on the test set to ensure the prediction accuracy and robustness of the model.

[0044] (5) Integration and application. Finally, the multi-level neural network architecture can be integrated into the three-dimensional packaging process management system of the RF microsystem to achieve real-time yield prediction and early warning functions. The system can be applied to the production line to help engineers discover potential process defects at an early stage and optimize the process flow, thereby improving the overall yield of the RF microsystem.

[0045] In one embodiment of the present invention, Figure 1 As shown in FIG. 1 , the method for predicting the yield of the RF microsystem three-dimensional packaging process is as follows:

[0046] Step 1: Data collection and preparation.

[0047] In the entire RF microsystem packaging process, the first step is to collect and prepare packaging process data. The collected data includes all relevant process parameters and corresponding yield information involved in the RF chip layer, adapter board, RF antenna layer, and stacking interconnection process. The accuracy and completeness of this data information is crucial to the accuracy of subsequent yield prediction.

[0048] Step 2: Sub-network construction and prediction.

[0049] The radio frequency microsystem structure of this embodiment is as follows: Figure 2 As shown, from bottom to top, it includes: an adapter board 2, an RF chip layer 1, and an RF antenna layer 3; the RF chip layer 1 and the RF antenna layer 3 are welded and connected via a plurality of interconnection solder joints 4, and an RF antenna 7 is correspondingly arranged in the RF antenna layer 3 above each interconnection solder joint 4, and a chip 5 is placed in the middle of the RF chip layer 1, and the adapter board 2 is provided with a plurality of through silicon vias 6 under the chip.

[0050] The entire packaging process is divided into four key process steps, namely: RF chip layer preparation, adapter board preparation, RF antenna layer preparation and stacking interconnection process.

[0051] For these four key steps, this embodiment further constructs four independent sub-networks, each of which corresponds to a specific process step. The trained sub-networks can predict the yield of each process step based on the input process parameters and whether there are defects and the specific conditions of the defects. Due to the independence of the sub-networks, each process step can be specifically analyzed, thereby improving the accuracy of the prediction.

[0052] Step 3: Main network construction and prediction.

[0053] When all sub-networks have completed independent predictions, the main network of the present invention is built. The main network not only receives and integrates the output data of the four sub-networks, but also inputs all the input data of the four sub-networks into the main network for comprehensive processing. The main network predicts the final yield of the entire RF three-dimensional microsystem by analyzing these input and output data. This prediction result can not only help identify potential defects in the early stage of the production process, but also provide an important reference for the quality control of subsequent processes, avoid the cumulative effect of defects, and thus significantly improve the overall yield.

[0054] The overall framework of this embodiment is as follows Figure 3 As shown in the figure, the four sub-networks correspond to the four key process steps in the packaging process: RF chip layer preparation, adapter board preparation, RF antenna layer preparation and stacking interconnection process. Through the design of multi-level neural networks, the accuracy and reliability of yield prediction are effectively improved, and a feasible and flexible preventive quality control method is provided for the packaging process of RF three-dimensional microsystems.

[0055] Preferably, in the radio frequency three-dimensional microsystem of this embodiment, the radio frequency chip layer adopts chip embedding technology. This technology has significant advantages in radio frequency microsystems. However, the application of chip embedding technology also introduces more complex process steps, and the interaction between these steps has a significant impact on the yield of the chip layer.

[0056] The RF chip layer preparation sub-network achieves accurate prediction of chip layer yield by analyzing multiple key process parameters, especially the following five input variables: material type, preparation temperature, lamination pressure, annealing temperature and annealing time.

[0057] (1) Material type: The choice of material has a direct impact on the mechanical strength, electrical properties and thermal expansion coefficient of the chip layer. In the preparation of RF chips, commonly used materials include semiconductor materials such as silicon, gallium nitride (GaN) and gallium arsenide (GaAs). Silicon material is widely used due to its good thermal conductivity and mechanical strength. However, the thermal expansion coefficients of different materials vary greatly. For example, the thermal expansion coefficient of silicon is 2.6e-6 / K, while that of GaAs is 6.86e-6 / K. If the material type is not selected properly or the wrong combination is used, defects such as interface delamination and microcracks may occur, which will seriously affect the yield of the preparation process.

[0058] (2) Preparation temperature: Preparation temperature is an important parameter that affects the quality of chip layer molding. The preparation temperature of the RF chip layer is generally controlled between 300°C and 600°C. Too high a temperature, such as over 700°C, may cause excessive grain growth of the material, resulting in grain boundary voids or excessive oxidation, which in turn may cause problems such as bubbles and uneven molten layer; while too low a temperature may cause the material's crystal structure to be incomplete or the bonding to be weak, resulting in interface delamination or cracks due to stress concentration.

[0059] (3) Lamination pressure: The pressure applied during the lamination process directly affects the quality of interlayer bonding. Generally, the lamination pressure is controlled between 10MPa and 50MPa. However, if the pressure exceeds 60MPa, it may cause the material to deform or crush, resulting in defects such as deformation, material cracking or internal void collapse; and if the pressure is insufficient, less than 10MPa, it may lead to weak bonding, bubbles, delamination or even peeling.

[0060] (4) Annealing temperature: Annealing is a key step to eliminate internal stress of the material and repair crystal defects. The annealing temperature is generally controlled between 200°C and 400°C. If the annealing temperature is too high, such as exceeding 450°C, it may cause excessive softening or recrystallization of the material, resulting in thermal stress and microcracks; while if the temperature is too low, such as below 150°C, it may not be able to fully release the internal stress of the material, resulting in warping or cracking problems in subsequent processes.

[0061] (5) Annealing time: The control of annealing time is also crucial. Usually, the annealing time is set between 10 minutes and 1 hour. If the annealing time is too short (less than 10 minutes), it may lead to insufficient stress release or incomplete elimination of crystal defects, which may cause material cracking or delamination in subsequent processes; while if the annealing time is too long (more than 2 hours), it may lead to excessive adjustment of the microstructure of the material, causing new defects such as pores or excessive oxidation of the material.

[0062] Preferably, in the radio frequency three-dimensional microsystem of this embodiment, the adapter board is a key component of the electrical connection. Due to the high-precision requirements of the radio frequency system on signal transmission, the preparation quality of the adapter board is crucial to the performance and reliability of the entire system.

[0063] The adapter board preparation sub-network achieves accurate prediction of the adapter board preparation process by analyzing multiple key process parameters, with special attention to the following four input variables: TSV size, TSV spacing, preparation temperature, and TSV defects (such as voids, cracks, and misalignments).

[0064] (1) TSV size: The size of TSV directly affects the quality of electrical connection. In practical applications, the diameter of TSV is usually between 20μm and 100μm. Studies have shown that when the TSV diameter is less than 25μm, the risk of incomplete filling increases significantly, resulting in poor electrical contact; while a diameter greater than 75μm may cause hole wall damage or material deformation, resulting in signal loss or unstable transmission. Proper control of TSV size is the key to ensuring high-quality electrical connections.

[0065] (2) TSV spacing: TSV spacing has a significant impact on the layout of the adapter board and the stability of signal transmission. The TSV spacing is usually controlled between 50μm and 150μm. When the spacing is less than 50μm, electrical interference between TSVs may occur, resulting in short circuits or signal crosstalk; while when the spacing exceeds 150μm, the volume of the adapter board may increase, affecting the integration of the system, and may cause signal transmission errors or poor connections.

[0066] (3) Preparation temperature: The preparation temperature has a significant impact on the formation of TSV and the quality of the adapter. Generally, the preparation temperature should be controlled between 350℃ and 450℃. Too high a temperature (such as over 500℃) will cause excessive flow or ablation of the material, resulting in voids or cracks in the TSV, affecting the electrical connection; while too low a temperature (such as below 300℃) may result in incomplete TSV filling, resulting in unstable electrical connection or disconnection.

[0067] (4) TSV defects: a. Voids are usually caused by insufficient fluidity of the filling material or improper preparation temperature. Studies have shown that the presence of voids will cause a significant increase in electrical contact impedance (such as an increase of several times), affecting signal transmission, and in severe cases may cause complete signal loss. b. Cracks may be caused by excessively high preparation temperatures or stress concentration during the cooling process. The presence of cracks can cause electrical connections to break or become unstable, increase signal loss (such as loss exceeding 20%), and affect overall performance. c. Misalignment of TSV will affect its alignment with the chip layer or antenna layer, resulting in poor connection or signal transmission errors. Misalignment problems usually lead to increased signal transmission errors, which may cause signal distortion or data transmission failure.

[0068] Preferably, in the RF three-dimensional microsystem of this embodiment, the RF antenna layer is a key component, and its performance directly determines the signal transmission quality of the system. This not only requires the antenna layer to achieve efficient electromagnetic signal transmission and reception in a limited space, but also requires it to have excellent electromagnetic compatibility and mechanical stability. However, the complex preparation process and variable process parameters make the antenna layer prone to various defects during the preparation process, thereby affecting the overall yield of the microsystem. The input variables of the RF antenna layer preparation subnetwork include antenna material type, deposition thickness, etching process parameters, pattern accuracy, and dielectric layer thickness.

[0069] (1) Antenna material type: Common materials used for RF antenna layers include metal materials such as copper, silver, and gold, which have different conductivity and electromagnetic properties. For example, copper has a low resistivity of about 1.68 μΩ·cm and is often used in low-loss antennas; while gold has a slightly higher resistivity but has excellent oxidation resistance. However, the choice of material is also affected by the coefficient of thermal expansion. Material mismatch may cause cracks or delamination in the antenna layer due to thermal stress in subsequent processes. In addition, impurities and inhomogeneities in the material may form voids during the electroplating or deposition process, affecting the continuity and signal transmission of the antenna.

[0070] (2) Deposition thickness: Generally speaking, the deposition thickness needs to be precisely controlled between 5μm and 20μm. If the deposition thickness is less than 5μm, the resistance of the antenna may increase, which may lead to signal attenuation; if the thickness exceeds 20μm, the weight of the antenna may increase and the flexibility may decrease, or even cracks may occur during subsequent bending or stretching. For example, when the thickness is 10μm, the antenna can maintain sufficient mechanical strength while ensuring low loss, but when the thickness increases to 25μm, the excessive thickness may lead to local stress concentration, causing the antenna layer to warp or crack in the later stage of packaging.

[0071] (3) Etching solution concentration: The concentration of the etching solution usually needs to be controlled between 20% and 30%, and the etching time is generally 30 to 60 seconds. If the etching solution concentration is too high (over 35%), it may cause excessive etching, resulting in over-etching and blurred edges of the antenna pattern; while if the concentration is too low (below 15%), it may cause incomplete etching and form a residual layer, affecting the current distribution and transmission efficiency of the antenna.

[0072] (4) Pattern accuracy: The accuracy requirement of the antenna pattern is usually controlled within ±1μm to ensure that the design parameters of the antenna can be achieved. For example, for an antenna with a frequency of 5GHz, a pattern deviation of 1μm may cause the resonant frequency to shift by up to 20MHz, which will seriously affect the reliability of signal transmission.

[0073] (5) Dielectric layer thickness: The dielectric layer is usually made of low-loss materials, and the thickness needs to be controlled between 50μm and 150μm. A thickness of less than 50μm may cause impedance mismatch between the antenna and other circuits, increasing reflection loss; while a thickness of more than 150μm may cause signal delay and attenuation, affecting the working efficiency of the antenna. For example, in practical applications, when the thickness of the dielectric layer is 100μm, it can ensure good impedance matching and low signal loss; but when the thickness increases to 200μm, it may cause the antenna's operating frequency to drift significantly and increase the corresponding loss.

[0074] Furthermore, in the RF three-dimensional microsystem of this embodiment, the quality of the stacking interconnection process directly affects the overall performance and reliability of the RF microsystem. Improper control of interlayer alignment, welding accuracy, etc. may lead to defects such as voids, cracks, and short circuits, which seriously affect the electrical performance and mechanical stability of the microsystem. The input variables of the stacking interconnection process subnetwork include interlayer alignment accuracy, welding temperature, interconnection material, and interconnection defect type.

[0075] (1) Alignment accuracy: The alignment accuracy is usually required to be controlled within ±1μm to ensure the integrity of the electrical connection and the stability of signal transmission. However, in the actual process, once the alignment accuracy exceeds 2μm, it may lead to incomplete interconnection between layers or connection failure. For example, when stacking two layers of chips, if the alignment accuracy deviation reaches 3μm, some interconnection channels may not be able to achieve effective contact, forming an open circuit, resulting in interruption of signal transmission. In addition, the deviation may also cause stress concentration, resulting in cracks at the interface, affecting the long-term reliability of the chip.

[0076] (2) Soldering temperature: Generally, the soldering temperature needs to be controlled between 300 and 350°C. This temperature range can ensure that the interconnection material (such as tin-lead alloy or lead-free solder) is fully melted and forms a stable solder joint. If the soldering temperature is lower than 300°C, the solder may not be fully melted, forming a cold joint or a false joint, which in turn causes poor electrical connection; if the temperature exceeds 350°C, it may cause excessive diffusion or oxidation of the solder, forming voids or embrittlement of the solder joint. In addition, excessively high temperatures may damage sensitive circuit areas of the chip, resulting in reduced electrical performance.

[0077] (3) Interconnection materials: Commonly used interconnection materials include tin-lead alloy, silver paste and lead-free solder. Tin-lead alloy solder is widely used in traditional packaging processes due to its excellent wettability and low melting point (about 183°C). However, with the improvement of environmental protection requirements, lead-free solder (such as Sn-Ag-Cu alloy) has gradually become the mainstream choice. Its melting point is relatively high (about 217 to 220°C), but it may cause the mechanical strength of the solder joint to decrease. In addition, impurities or non-uniformity in the interconnection material may form voids or cracks during the welding process, affecting the reliability of the solder joint. For example, if the impurity content in the solder joint exceeds 0.1%, the probability of crack formation may be significantly increased.

[0078] (4) Interconnection defects (voids, cracks, short circuits): a. Voids are usually caused by residual gas in the solder or insufficient welding. If the diameter of the void exceeds 10% of the diameter of the solder joint, it may cause unreliable electrical connection or even cause an open circuit. b. Cracks are mostly caused by thermal stress during welding or solder embrittlement. If the crack length exceeds 20% of the solder joint diameter, it may cause a significant decrease in the mechanical strength of the solder joint. c. Short circuits mainly occur when the molten solder unexpectedly flows during the welding process, resulting in unnecessary electrical connections between adjacent interconnection points. The minimum spacing between interconnection points is usually required to be more than 50 microns to avoid short circuits. In actual operation, if the welding process is not strictly controlled and the void ratio reaches 15%, the finished product yield may drop by more than 15%; and the occurrence of short circuit defects may cause the entire module to fail, affecting the reliability and stability of the system.

[0079] In this embodiment, the yield prediction values ​​of each process step output by the sub-network will be input into the main network together with all the input data of the four sub-networks, in order to fully consider the interaction between the sub-networks and the influence between the process steps in the comprehensive prediction process. The main network can achieve accurate prediction of the overall yield of the RF three-dimensional microsystem by comprehensive processing of the output data and input data of each sub-network.

[0080] The neural network construction process of this embodiment is as follows: Figure 4 As shown in the figure, five-fold cross validation (CV) was used to determine the number of neurons in the hidden layer during the construction of each network.

[0081] The CV validation technique is to randomly divide the data set into five parts, train five network models and repeat the evaluation. Each network is trained using four parts of the data set and the remaining part is used for test validation. If any network has a prediction accuracy of less than 90% in the test, the optimizer in the flowchart will be started to improve the structure and parameters of the network. After the improvement, the data set will be randomly divided again, and the five newly generated network models will be trained and validated. After passing the accuracy test, the coefficient of determination (R 2 ) The final step is to evaluate the performance of the network model. The coefficient of determination is one of the indicators to measure the goodness of fit of the network model. It is used to evaluate the degree of fit of the model to the observed data. The calculation formula is as follows:

[0082]

[0083] Among them, y k Indicates the actual output value, represents the predicted output value of the neural network, R represents the output mean, and N represents the number of output variables. 2 The value range is between 0 and 1. The closer it is to 1, the better the model fit. If the value is less than 0.9, the optimizer is also started to rebuild and train the neural network until the entire training process is passed.

[0084] The neural network structure of this embodiment is as follows: Figure 5 As shown in Figure 1, each sub-network adopts a typical multi-layer perceptron structure, including an input layer, multiple hidden layers, and an output layer. The neurons in each layer transmit information to all neurons in the next layer through full connection.

[0085] Specifically, the input layer receives various parameter data of the packaging process, and performs nonlinear transformation through weighted summation and activation function to map these raw data into a high-dimensional feature space. The hidden layer continues to process these features, further extracts potential patterns and relationships, and finally gives the yield prediction value at the output layer. Since each layer of neurons in the fully connected network participates in the calculation of subsequent layers, it can learn complex features in the data and is suitable for tasks that require refined feature extraction. However, ordinary fully connected structures are prone to overfitting problems when processing high-dimensional data, that is, the network is too dependent on training data, resulting in insufficient generalization ability for new data.

[0086] Furthermore, this embodiment incorporates the Dropout mechanism when building each sub-network, such as Figure 6As shown in the figure, the dropout mechanism in the neural network is a regularization technique that aims to optimize the generalization ability of the neural network model. During each training process, some neurons are randomly "dropped" (that is, the output of these neurons is set to zero), so that these neurons do not participate in forward propagation and backpropagation in the current training step. This random dropout operation breaks the co-adaptability between neurons and forces the network to learn more robust feature representations, thereby effectively reducing the risk of overfitting.

[0087] Therefore, the network model with the Dropout mechanism performs better than the ordinary fully connected network structure in processing complex data patterns, especially in yield prediction tasks.

[0088] In summary, the RF microsystem three-dimensional packaging process yield prediction method of the present invention, by constructing multiple interrelated neural networks, gradually predicts the yield of each key process node in the packaging process, and finally comprehensively predicts the overall yield of the RF microsystem.

[0089] The prediction model consists of four sub-networks and one main network. The four sub-networks correspond to the four key preparation steps of RF microsystem three-dimensional packaging: RF chip layer preparation, adapter board preparation, RF antenna layer preparation, and stacking interconnection process. Each sub-network is responsible for predicting the yield of the corresponding process step. By training each sub-network, it can predict the yield of the process step based on the input process parameters, whether there are defects, and the specific situation of the defects. After completing the independent prediction of the four sub-networks, the input variables and output results of each sub-network will be passed into the main network as input data. The main network comprehensively analyzes and predicts the final yield of the entire RF microsystem based on the yield results of each process output by the four sub-networks.

[0090] At the same time, neural network technology is used to analyze and process the data of various key parameters in the packaging process to predict the yield of the finished product. Through this prediction method, manufacturers can optimize and adjust the process flow in the early stage of production, thereby improving the success rate of the packaging process, reducing the failure of finished products due to defects, and ultimately improving production efficiency and economic benefits. It can not only effectively alleviate the yield problem caused by the complexity of the packaging process, but also provide a feasible preventive quality control method for the packaging process of RF microsystems.

[0091] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for predicting the yield of a 3D packaging process of a radio frequency microsystem based on a neural network, characterized in that: The steps include: S1. Data collection and preparation: Divide the RF microsystem packaging process into four key process steps, namely: RF chip layer preparation, adapter board preparation, RF antenna layer preparation and stacking interconnection process; collect the process parameters and corresponding yield information involved in the four key process steps; S2. Prediction model construction: construct a multi-level neural network architecture, including four sub-networks and one main network; the four sub-networks correspond to the four key process steps in the packaging process, and predict the yield of each key process step based on the input process parameters and corresponding yield information; The main network integrates the output and input parameters of the four sub-networks to make a final prediction of the entire RF microsystem packaging process yield; S3. Prediction model training, integration and application: Integrate the multi-level neural network architecture constructed in step S2 into the three-dimensional packaging process management system of the RF microsystem to perform real-time yield prediction and early warning.

2. The method for predicting the yield rate of RF microsystem three-dimensional packaging process based on neural network according to claim 1, characterized in that: The four sub-networks are independent of each other, and each sub-network adopts a multi-layer perceptron structure, including: an input layer, a plurality of hidden layers and an output layer, and the neurons in each layer transmit information to all neurons in the next layer through a fully connected manner; The input layer receives the corresponding key process step input parameters, including the collected process parameters and the corresponding yield information, and performs nonlinear transformation through weighted summation and activation function to map the original input data into a high-dimensional feature space; the hidden layer determines the number of neurons, extracts potential patterns and relationships, outputs the yield prediction results of the process step through the output layer, and passes them together with the input parameters to the main network for comprehensive analysis.

3. The method for predicting the yield rate of RF microsystem three-dimensional packaging process based on neural network according to claim 2, characterized in that: The number of neurons in the hidden layer of each sub-network is determined by five-fold cross-validation as follows: S2.

1. Randomly divide the dataset into five parts, train five network models and repeat the evaluation. Each network is trained using four parts of the dataset and tested and verified using the remaining parts. S2.

2. If the prediction accuracy of any network in the test is less than 90%, the optimizer is started to improve the structure and parameters of the network; S2.

3. Re-randomly divide the data set, train and verify the five newly generated network models; S2.

4. Calculate the coefficient of determination R of the neural network 2 , the performance of the network model is evaluated; the determination coefficient is used to evaluate the degree of fit of the model to the observed data, and the calculation formula is as follows: Among them, y k Indicates the actual output value, represents the predicted output value of the neural network, represents the output mean, N represents the number of output variables; R 2 The value range of is between 0 and 1, and the closer it is to 1, the better the model fit; S2.

5. If the coefficient of determination is less than 0.9, start the optimizer and repeat steps S2.2 to S2.3 to rebuild and train the neural network until it passes the training.

4. The method for predicting the yield rate of RF microsystem three-dimensional packaging process based on neural network according to claim 3 is characterized in that: The Dropout mechanism is incorporated when building each sub-network. During each training process, some neurons are randomly discarded and the outputs of the discarded neurons are set to zero. The discarded neurons do not participate in forward propagation and back propagation in the current training step, which is used to break the co-adaptability between neurons and reduce the risk of overfitting.

5. The method for predicting the yield rate of RF microsystem three-dimensional packaging process based on neural network according to claim 1, characterized in that: In step S3, a training data set is constructed for prediction model training, including process parameters, test data and corresponding yield information under different process conditions; The model training process adopts supervised learning methods and uses different optimization algorithms to improve the prediction accuracy and convergence speed of the prediction model. The model is verified through cross-validation method, and the performance of the model is evaluated on the test set.

6. The method for predicting the yield rate of RF microsystem three-dimensional packaging process based on neural network according to claim 1, characterized in that: The radio frequency microsystem includes, from bottom to top, an adapter board, a radio frequency chip layer, and a radio frequency antenna layer; The RF chip layer and the RF antenna layer are welded and connected via a number of interconnection solder joints. An RF antenna is correspondingly arranged above each interconnection solder joint in the RF antenna layer. The chip is placed in the middle of the RF chip layer, and the adapter board is provided with a number of through silicon vias below the chip.

7. The method for predicting the yield rate of RF microsystem three-dimensional packaging process based on neural network according to claim 6, characterized in that: The RF chip layer adopts chip embedding technology, and the sub-network input parameters corresponding to the preparation of the RF chip layer include: material type, preparation temperature, lamination pressure, annealing temperature and annealing time; The material type is semiconductor material, including silicon, gallium nitride and gallium arsenide; the preparation temperature ranges from 300°C to 600°C; the lamination pressure is the pressure applied during the lamination process, ranging from 10MPa to 50MPa; the annealing temperature ranges from 200°C to 400°C; the annealing time ranges from 10 minutes to 1 hour.

8. The method for predicting the yield rate of RF microsystem three-dimensional packaging process based on neural network according to claim 6, characterized in that: The adapter board is a key component for electrical connection, and the sub-network input parameters corresponding to the preparation of the adapter board include: TSV size, TSV spacing, preparation temperature and TSV defects; The TSV size has a diameter range of 20 μm to 100 μm; the TSV spacing ranges from 50 μm to 150 μm; the preparation temperature ranges from 350° C. to 450° C.; the TSV defects include: voids, cracks, and dislocations.

9. The method for predicting the yield rate of RF microsystem three-dimensional packaging process based on neural network according to claim 6, characterized in that: The RF antenna layer, the preparation of the corresponding sub-network input parameters include: antenna material type, deposition thickness, etching process parameters, pattern accuracy and dielectric layer thickness; The antenna material is a metal material type, including copper, silver, and gold; the deposition thickness ranges from 5μm to 20μm; the etching process parameters include etching solution concentration and etching time, the etching solution concentration ranges from 20% to 30%, and the etching time ranges from 30 seconds to 60 seconds; the pattern accuracy ranges within ±1μm, and the dielectric layer thickness ranges from 50μm to 150μm.

10. The method for predicting yield rate of RF microsystem three-dimensional packaging process based on neural network according to claim 6, characterized in that: The stacking interconnection process between the RF chip layer and the RF antenna layer, the corresponding sub-network input parameters include: inter-layer alignment accuracy, welding temperature, interconnection material and interconnection defect type; The alignment accuracy is within the range of ±1μm; the soldering temperature is between 300 and 350°C; the interconnection materials include tin-lead alloy, silver paste and lead-free solder; the interconnection defects include voids, cracks and short circuits.

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