Hardware Trojan Detection and Recovery Method, Device, Medium and Processor for RISC-V

Abstract

The present invention discloses a hardware Trojan detection and recovery method, device, medium and processor for RISC-V, belonging to the technical field of hardware security, including: when the RISC-V processor executes an input instruction, backing up the information written to the general-purpose register bank to obtain backup information; constructing a pipeline architecture to perform hardware Trojan detection on one or more detection paths to obtain the Trojan detection results of each detection path; when there is a hardware Trojan attack in any one of the detection paths, suspending the pipeline architecture operation and resetting all stored data; retrieving the original information tampered with by the hardware Trojan from the backup information and writing it back to the corresponding position in the general-purpose register bank; using the pipeline architecture to perform fetching, decoding and execution operations again, and restoring the RISC-V processor to a normal state by using the written-back information. The detection and recovery structure proposed by the present invention is faster in speed and lower in power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of hardware security, and particularly relates to a method, device, medium and processor for detecting and recovering hardware Trojans for RISC-V. Background Art

[0002] In today's information age, electronic devices are used more and more widely and are becoming increasingly important. Among these electronic devices, a very important component - the chip - is indispensable, and ensuring the normal execution of the chip's functions is of utmost importance. Therefore, it is very necessary to perform hardware security detection on the chip to ensure its functions. When a hardware security problem is detected in the chip, it is necessary to eliminate or reduce the impact caused by this security problem.

[0003] RISC-V is short for the fifth generation of Reduced Instruction Set Computing (RISC). As an open-source instruction set architecture (ISA), it can be freely used for any purpose, allowing anyone to design and manufacture RISC-V processor chips and software. RISC-V is simpler, smaller, and more flexible than the previous four generations of RISC instruction sets. However, the open-source nature of RISC-V is a double-edged sword. When designers design processor chips based on the RISC-V instruction set, they can design a matching processor according to specific scenarios. However, at the same time, it is easier to insert hardware Trojans (HTs) during the design or production process of the processor.

[0004] Whether the hardware Trojan is deliberately designed and inserted by an attacker or due to a design defect of the designer, it will cause the hardware Trojan to be triggered under special circumstances, which may result in a decrease in circuit performance, a change in function, the leakage of key information, or even the failure of the entire chip. Existing hardware Trojan detection methods mainly propose some detection structures and clock cycle recovery methods when the general-purpose register sets (General Purpose Registers, abbreviated as GPRs) of the processor are attacked. However, there is still much room for improvement in the existing technology in terms of the detection speed of HTs, the information backup speed, and the recovery to the normal state after an HT attack. In addition, many existing detection methods only perform hardware Trojan detection and do not give solutions for Trojan elimination or processor function recovery. It is very necessary to perform function recovery after detecting a hardware Trojan to eliminate or reduce the possible impact and ensure the normal operation of the processor. Summary of the Invention

[0005] To solve the above technical problems, the present invention proposes a hardware Trojan detection and recovery method, device, medium, and processor for RISC-V, which can quickly detect HTs with low probability of triggering in the processor and quickly perform recovery processing after detecting HTs, quickly eliminating the impact caused by this type of HT. The idea of this method is applicable to various types of processors, etc., for quickly detecting and recovering HTs with low probability of triggering to solve the problems existing in the above-mentioned prior art.

[0006] To achieve the above object, the present invention provides a hardware Trojan detection and recovery method for a RISC-V processor, including the following steps:

[0007] When the RISC-V processor executes an input instruction, the information written to the general-purpose register bank is backed up in real time to obtain backup information;

[0008] Construct a pipeline architecture, select one or more detection paths in the pipeline architecture for hardware Trojan detection, and obtain the Trojan detection results of each detection path;

[0009] When there is a hardware Trojan attack in any one of the detection paths, control the operation of the pipeline architecture to pause and reset all the register data in the pipeline architecture;

[0010] Retrieve the original information tampered with by the hardware Trojan from the backup information and write it back to the corresponding position in the general-purpose register bank;

[0011] Use the pipeline architecture to perform instruction fetching, decoding, and execution operations in sequence again, and use the write-back information in the general-purpose register bank to restore the RISC-V processor to a normal state.

[0012] Optionally, the step of selecting one or more detection paths in the pipeline architecture for hardware Trojan detection and obtaining the Trojan detection results of each detection path specifically includes:

[0013] Select the start point and end point of each detection path;

[0014] Perform node partitioning on each detection path respectively to obtain a number of detection nodes;

[0015] Compare the information of all adjacent detection nodes between the start point and the end point on each detection path pairwise to obtain a number of node comparison results;

[0016] Compare the information of the start point and the end point of each detection path respectively to obtain the head and tail comparison results;

[0017] Concatenate the comparison results of several nodes of adjacent detection nodes in each detection path bit by bit in the information transfer direction in sequence, and then concatenate them with the head and tail comparison results to generate a single-channel comparison result;

[0018] Obtain the Trojan detection result of the corresponding detection path according to the single-channel comparison result.

[0019] Optionally, the obtaining the Trojan detection result of the corresponding detection path according to the single-channel comparison result includes:

[0020] Judge whether the information of the start point and the end point of the corresponding detection path is the same according to the data bits of the head and tail comparison results on the single-channel comparison result;

[0021] If they are the same, it is determined that there is no hardware Trojan on the corresponding detection path;

[0022] If they are not the same, it is determined that there is a hardware Trojan on the corresponding detection path, and according to the input instruction and other data bits of the single-channel comparison result, obtain the type of the hardware Trojan and the position of the hardware Trojan on the corresponding detection channel.

[0023] Optionally, the detection path includes: an address detection path and a data detection path;

[0024] After obtaining the Trojan detection results of each detection path, it further includes:

[0025] Perform a logical OR operation on the Trojan detection results of the address detection path and the Trojan detection results of the data detection path to generate a multi-channel Trojan detection result.

[0026] Optionally, the address detection path includes: a register address path, a load instruction address path, and a store instruction address path; the data detection path includes: a register data path and a store instruction data path;

[0027] Use the register address path, the load instruction address path, and the store instruction address path to respectively perform bit-by-bit concatenation on the Trojan detection results obtained after Trojan detection of the address detection path, and then perform a bitwise OR operation to obtain the Trojan detection result of the address detection path;

[0028] Use the register data path and the store instruction data path to respectively perform bit-by-bit concatenation on the Trojan detection results obtained after Trojan detection of the data detection path, and then perform a bitwise OR operation to obtain the Trojan detection result of the data detection path.

[0029] The present invention also provides a hardware Trojan detection and recovery device for a RISC-V processor, which is used to implement a hardware Trojan detection and recovery method for a RISC-V processor, including: a RISC-V processor and a hardware Trojan detection and recovery device;

[0030] The RISC-V processor includes: a control module, and a pipeline architecture built based on the RISC-V instruction set; the pipeline architecture includes: an instruction fetch module, a decoding module, an execution module, and a general-purpose register bank;

[0031] The hardware Trojan detection and recovery device includes: a backup module and a detection module;

[0032] The backup module is used to perform real-time backup on the information written into the general-purpose register bank when the RISC-V processor executes an input instruction, to obtain backup information;

[0033] The detection module is used to select one or more detection paths in the pipeline architecture for hardware Trojan detection, to obtain the Trojan detection results of each detection path;

[0034] The control module is used to control the suspension of the operations of each module in the pipeline architecture and reset all the register data in the pipeline architecture when there is a hardware Trojan attack in any one of the detection paths;

[0035] The general-purpose register bank is used to retrieve the original information tampered by the hardware Trojan from the backup information and write it back to the corresponding position in the general-purpose register bank;

[0036] The instruction fetch module, the decoding module, and the execution module in the pipeline architecture are used to respectively perform instruction fetching, decoding, and execution operations in sequence, and restore the RISC-V processor to the normal state by using the write-back information in the general-purpose register bank.

[0037] Optionally, the detection module includes:

[0038] A detection path selector, which is used to select the start point and the end point of each detection path;

[0039] A path node divider, which divides each detection path respectively to obtain a number of detection nodes;

[0040] A signal comparator, which is used to compare the information of all adjacent detection nodes between the start point and the end point of each detection path pairwise to obtain a number of node comparison results; and is also used to compare the information of the start point and the end point of each detection path respectively to obtain a head and tail comparison result;

[0041] A signal splicer for sequentially splicing bit by bit the comparison results of several adjacent detection nodes in each detection path in the information transmission direction, and then splicing with the head and tail comparison results to generate a single-channel comparison result;

[0042] A result generator for obtaining the hardware Trojan detection result of the corresponding detection path according to the single-channel comparison result.

[0043] Optionally, the hardware Trojan detection and recovery device further includes a composite judgment module:

[0044] The composite judgment module is used to perform a logical OR operation on the hardware Trojan detection results of the address detection path and the hardware Trojan detection results of the data detection path to generate a multi-channel hardware Trojan detection result.

[0045] The present invention also provides a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, each step of the hardware Trojan detection and recovery method for a RISC-V processor is implemented.

[0046] The present invention also provides a RISC-V system-on-chip, which internally integrates a hardware Trojan detection and recovery device for a RISC-V processor based on a CMOS semiconductor process. The hardware Trojan detection and recovery device and the RISC-V processor form an integrated RISC-V system-on-chip.

[0047] Compared with the prior art, the present invention has the following advantages and technical effects:

[0048] The hardware Trojan detection and function recovery system for a RISC-V processor proposed by the present invention quickly detects the key information of the transmission path. It not only detects the general-purpose register file, but also expands the detection scope to the paths through which the information to be written into the general-purpose register file passes, including the register address detection path, the register data detection path, the load instruction address detection path, the store instruction address detection path, and the store instruction data detection path. In addition, it also detects the paths when the load and store instructions access peripherals.

[0049] The backup structure of the present invention is ingenious and flexible, with lower power consumption. When backing up the register file, it does not back up all the data of the general-purpose register file, but only backs up the information of the register file written into the general-purpose register file. After detecting the HT, it does not rewrite all the information in the backup structure back to the general-purpose register file, but only returns the register file information with the same address from the backup structure according to the register file address written into the general-purpose register file when an exception occurs, improving the backup speed of the backup structure.

[0050] From detecting that an HT attack causes an abnormal state in the processor's pipeline to the processor's pipeline returning to a normal state, among the same type of detection and recovery structures, the recovery speed is the fastest, and the power consumption of the recovery structure is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings constituting a part of this application are used to provide a further understanding of this application. The schematic embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation to this application. In the drawings:

[0052] Figure 1 It is a schematic structural diagram of applying a hardware Trojan detection and recovery device on a RISC-V processor according to an embodiment of the present invention;

[0053] Figure 2 It is a basic flowchart of hardware Trojan detection according to an embodiment of the present invention;

[0054] Figure 3 It is a flowchart for judging the HT attack result of all detection paths according to an embodiment of the present invention;

[0055] Figure 4 It is a flowchart for judging the location of the HT attack according to an embodiment of the present invention;

[0056] Figure 5 It is a flowchart of a method for quickly recovering a RISC-V processor after detecting an HT according to an embodiment of the present invention;

[0057] Figure 6 It is a circuit diagram of a register address detection module according to an embodiment of the present invention;

[0058] Figure 7 It is a circuit diagram of a register data detection module according to an embodiment of the present invention;

[0059] Figure 8 It is a circuit diagram of a load instruction address detection module according to an embodiment of the present invention;

[0060] Figure 9 It is a circuit structure diagram of a backup module circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0061] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The following will refer to the drawings and combine the embodiments to detail this application.

[0062] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0063] This embodiment proposes a hardware Trojan detection and recovery method, device, medium, and processor for RISC-V processors, aiming to detect hardware Trojans at the register transfer level (RTL) of RISC-V processors. When a hardware Trojan is detected in the detection path of the processor, the processor function recovery process is performed in a timely manner. Applying the embodiments of the present invention can improve the speed of detecting hardware Trojans in the processor, reduce the time for the processor to recover from an abnormal state to a normal state, and minimize the impact range caused by the hardware Trojan as much as possible.

[0064] This embodiment takes a processor (CPU) with a three-stage pipeline based on the RISC-V instruction architecture as an example to provide a hardware Trojan detection and recovery method, device, medium, and processor for RISC-V processors.

[0065] As Figure 1 shown, it is a schematic structural diagram of a RISC-V system-on-chip integrated with a hardware Trojan detection and recovery device provided by this embodiment.

[0066] Among them, the RISC-V processor 100 includes: a control module 101, and a pipeline architecture built based on the RISC-V instruction set; the pipeline architecture includes: an instruction fetch module 102, a decoding module 103, an execution module 104, and a general-purpose register bank 105. The general-purpose register bank (General Purpose Registers, abbreviated as GPRs) is composed of multiple general-purpose data registers and multiple general-purpose address registers, and is used in the RISC-V processor to store necessary information during the execution of some instructions to efficiently execute various data operations and memory operations.

[0067] The hardware Trojan detection and recovery device for RISC-V processors includes: a backup module 200 and a detection module 300;

[0068] The backup module 200 is used to perform real-time backup on the information written to the general-purpose register bank 105 when the RISC-V processor executes input instructions to obtain backup information;

[0069] The detection module 300 is used to select one or more detection paths in the pipeline architecture for hardware Trojan detection to obtain the Trojan detection results of each detection path;

[0070] The control module 101 is configured to control the suspension of operations of each module in the pipeline architecture and reset all the stored data in the pipeline architecture when there is a hardware Trojan attack in any of the detection paths;

[0071] The general-purpose register file 105 is further configured to retrieve the original information tampered by the hardware Trojan from the backup information and write it back to the corresponding position in the general-purpose register file 105;

[0072] The instruction fetch module 102, the decoding module 103, and the execution module 104 in the pipeline architecture respectively perform instruction fetching, decoding, and execution operations in sequence, and restore the RISC-V processor to the normal state by using the write-back information in the general-purpose register file 105.

[0073] In this embodiment, the RISC-V processor supports the RV32IM instruction set, that is, it includes the 32-bit basic integer instruction set RV32I and the multiplication and division extension instruction set RV32M. The definitions of these instruction sets are all defined in detail in the RISC-V open-source instruction set architecture. Specifically, RV32IM has six instruction formats, namely R-type instructions, I-type instructions, S-type instructions, B-type instructions, U-type instructions, and J-type instructions. Among them, R-type instructions are used for operations between registers; I-type instructions are used for accessing short immediate numbers in memory and accessing external storage devices. In the embodiment of the present invention, I-type instructions mainly refer to load instructions; S-type instructions are used to control store instructions. It should be noted that although the RISC-V open-source instruction set architecture has detailed standard definitions for various instruction formats, on the one hand, the instruction set architecture can be further extended with custom instructions or instruction sets, and on the other hand, designers can design RISC-V processors with different circuit structures, operating effects, and efficiencies based on the instruction set architecture. The embodiment of the present invention mainly detects whether the above three types of instructions are attacked by hardware Trojans when running in a three-stage pipeline RISC-V processor and restores the instruction cycle, so as to restore the normal operation of the processor.

[0074] As a schematic embodiment, the embodiments of the present invention take a RISC-V processor with a three-stage pipeline structure as an example for Trojan detection and program recovery. The three-stage pipeline of the RISC-V processor 100 includes an instruction fetch stage, a decode stage, and an execution stage, corresponding to an instruction fetch module 102, a decode module 103, and an execution module 104 respectively. Among them, the instruction fetch stage means that the processor fetches the instruction to be executed from the read-only memory (ROM) in the peripheral device 600. The decode stage means that the processor decodes the fetched instruction according to the RISC-V instruction set. The execution stage means that the processor performs different execution processes on the information after decoding different instructions according to the RISC-V instruction set. Most existing computer processors and embedded processors include these three stages. Some processors will further subdivide or expand and add other pipeline stages to each of these stages, so as to obtain a processor with a longer and more complex pipeline. In this embodiment, since the RISC-V processor 100 also supports the RV32M instruction set, the pipeline architecture of the RISC-V processor 100 further includes a multiplication and division operation module 106.

[0075] This embodiment proposes a design of a hardware Trojan detection and recovery architecture for a RISC-V processor with an instruction fetch stage, a decode stage, and an execution stage. In a preferred manner, the pipeline composition of the RISC-V processor 100 serves as the core of the improved RISC-V processor, and the hardware Trojan detection and recovery device is integrated with the RISC-V processor 100 (core) as a newly added circuit module to form a new RISC-V processor with hardware Trojan detection and function recovery. In particular, as Figure 1 shown, the inside of this new RISC-V processor is based on Complementary Metal Oxide Semiconductor (CMOS) semiconductor process, and integrates the hardware Trojan detection and recovery device for the RISC-V processor, and forms an integrated RISC-V System on Chip (SoC) with the RISC-V processor core 100. Figure 1 Figure 1 shows a schematic structural diagram of a RISC-V processor integrated with a hardware Trojan detection and recovery device proposed in this embodiment.

[0076] For the hardware Trojan detection and recovery device, its main components include a backup module 200 and a detection module 300.

[0077] In a preferred embodiment, the detection module 300 can further internally include a register address detection module 301, a register data detection module 302, a load instruction address detection module 303, a store instruction address detection module 304, and a store instruction data detection module 305 based on different RISC-V instruction types and information types (data or address), which are respectively used to perform hardware Trojan detection on the data or address of three types of instructions, namely R-type instructions, I-type instructions, and S-type instructions.

[0078] Based on Figure 1 For the RISC-V system-on-chip provided in the embodiment, the embodiment of the present invention also provides a hardware Trojan detection and recovery method for a RISC-V processor, including the following steps:

[0079] When the RISC-V processor executes an input instruction, the information written to the general-purpose register file is backed up in real time to obtain backup information;

[0080] A pipeline architecture is constructed, and one or more detection paths are selected in the pipeline architecture to perform hardware Trojan detection, and the Trojan detection results of each detection path are obtained;

[0081] When there is a hardware Trojan attack in any one of the detection paths, control is used to pause the operation of the pipeline architecture, and all the register data in the pipeline architecture is reset;

[0082] The original information tampered by the hardware Trojan is retrieved from the backup information and written back to the corresponding position in the general-purpose register file;

[0083] The pipeline architecture is used to perform instruction fetching, decoding, and execution operations in sequence again, and the RISC-V processor is restored to the normal state by using the write-back information in the general-purpose register file.

[0084] As a specific embodiment, as Figure 2 shown, it is a flowchart of steps of the hardware Trojan detection and recovery method for a RISC-V processor according to the embodiment of the present invention. When implementing the hardware Trojan detection and recovery method for a RISC-V processor, the RISC-V processor includes: a control module 101, and a pipeline architecture constructed based on the RISC-V instruction set; the pipeline architecture includes: an instruction fetch module 102, a decoding module 103, an execution module 104, and a general-purpose register file 105; then for the RISC-V processor with this type of pipeline architecture, the hardware Trojan detection and recovery method can be implemented, including:

[0085] Step S1: When the RISC-V processor executes an input instruction, the information written to the general-purpose register bank 105 is backed up in real time to obtain backup information;

[0086] Step S2: Select one or more detection paths in the pipeline architecture for hardware Trojan detection to obtain the Trojan detection results of each detection path;

[0087] Step S3: When there is a hardware Trojan attack in any of the detection paths, control the suspension of the operations of each module in the pipeline architecture and reset all the register data in the pipeline architecture;

[0088] Step S4: Retrieve the original information tampered with by the hardware Trojan from the backup information and write it back to the corresponding position in the general-purpose register bank 105;

[0089] Step S5: Use the instruction fetch module 102, decoding module 103, and execution module 104 in the pipeline architecture to perform instruction fetching, decoding, and execution operations respectively, and restore the RISC-V processor to the normal state using the write-back information in the general-purpose register bank 105.

[0090] In specific implementation, when the detection module 300 performs hardware Trojan detection, the selection of the detection path is crucial. In this embodiment, the detection paths include two types: address detection paths and data detection paths. Among them, the detection module 300 includes various internal detection modules: register address detection module 301, register data detection module 302, load instruction address detection module 303, store instruction address detection module 304, and store instruction data detection module 305.

[0091] Preferably, an implementation manner of step S2 is as Figure 3 shown. That is, select one or more detection paths in the pipeline architecture for hardware Trojan detection to obtain the Trojan detection results of each detection path, specifically including:

[0092] Step S21: Select the start point and end point of each detection path;

[0093] Step S22: Perform node partitioning on each detection path respectively to obtain a number of detection nodes;

[0094] Step S23: Compare the information of all adjacent detection nodes between the start point and the end point on each detection path pairwise to obtain a number of node comparison results;

[0095] Step S24: Compare the information of the start point and the end point of each detection path respectively to obtain the head and tail comparison results;

[0096] Step S25: Concatenate several node comparison results of adjacent detection nodes in each detection path bit by bit in the information transfer direction in sequence, and then concatenate them with the head and tail comparison results to generate a single-channel comparison result;

[0097] Step S26: Obtain the hardware Trojan detection result of the corresponding detection path according to the single-channel comparison result.

[0098] In specific implementation, the register address detection module 301, the register data detection module 302, the load instruction address detection module 303, the store instruction address detection module 304, and the store instruction data detection module 305 respectively select and divide nodes for the address or data path of the internal pipeline architecture of the RISC-V processor according to the corresponding instruction execution process, and perform hardware Trojan detection in parallel.

[0099] Among them, the register address detection module 301 is used to detect the address in the information path where the information needs to be written to the general-purpose register bank 105 (General Purpose Registers, abbreviated as GPRs) after the execution of the R-type instruction. Compared with the existing technology, this embodiment adds the detection of the address because the hardware Trojan can attack both data and address.

[0100] The register data detection module 302 is used to detect the data in the information path where the information needs to be written to the general-purpose register bank 105 after the execution of the R-type instruction. Compared with the existing technology, this embodiment expands the detection range of the information written to the general-purpose register bank 105, and expands the data detection to the source of the written information.

[0101] The load instruction address detection module 303 is used to detect the address in the information path where the load instruction (load instruction) accesses the peripheral device 600 from the RISC-V processor 100.

[0102] The store instruction detection module includes two sub-modules: the store instruction address detection module 304 and the store instruction data detection module 305. The function of the store instruction address detection module 304 is to detect the address in the information path where the store instruction stores the information of the RISC-V processor 100 to the peripheral device 600; the function of the store instruction data detection module 305 is to detect the data in the information path when the store instruction stores the information of the RISC-V processor 100 to the peripheral device 600.

[0103] The backup module 200 backs up the information written to the general-purpose register file 105 each time when the RISC-V processor 100 runs normally. After detecting a hardware Trojan attack, the general-purpose register file 105 finds out the attacked 32-bit registers and retrieves the correct information before the attack from the backup module 200 and writes it back to the corresponding registers. In specific implementation, the register address detection module 301 selects the address path flowing through the instruction fetch module 102, the decoding module 103, the execution module 104, and writing back to the general-purpose register file 105 as the register address detection path according to the processing flow of the R-type RV32IM instruction in the processor and the micro-architecture definition of RISC-V, and divides the nodes and compares the information of this path according to the above steps S21 to S26 to obtain the Trojan detection result of this path. Other detection modules follow the same analogy when executing the detection paths of corresponding instruction types.

[0104] Therefore, for the case of parallel detection of multiple detection paths, the judgment of hardware Trojan detection needs to comprehensively consider the detection results of multiple paths. Specifically, the detection paths include two types: address detection paths and data detection paths. Then, the hardware Trojan detection and recovery device further includes: a composite judgment module 400, configured to perform a logical OR operation on the Trojan detection results of the address detection path and the Trojan detection results of the data detection path to generate a multi-channel Trojan detection result. In specific implementation, if the Trojan detection results of the address detection path and the Trojan detection results of the data detection path are both splicings of comparison results of different pairs of nodes, that is, they are multi-bit data, the composite judgment module 400 first performs a bitwise OR operation on the Trojan detection results of the address detection path and the Trojan detection results of the data detection path respectively, and then performs a logical OR operation on the results of these two bitwise OR operations again to generate the multi-channel Trojan detection result.

[0105] According to different instruction types, the address detection path and the data detection path are divided into more detection paths: among them, the address detection path includes a register address detection path, a load instruction address detection path, and a store instruction address detection path; the data detection path includes a register data detection path and a store instruction data detection path. Correspondingly, each sub-module in the detection module 300 performs Trojan detection on the corresponding detection path. The detection operations of the five sub-detection modules 301 to 305 in this embodiment are processed in parallel, so that the RISC-V processor can quickly recover from an abnormal state to a normal state. The new architecture for fast detection and recovery of hardware Trojans proposed in this embodiment has obvious improvements in the detection speed and recovery ability.

[0106] Preferably, for each detection module, its internal composition includes:

[0107] A detection path selector for selecting the start and end points of each detection path;

[0108] A path node divider that divides nodes for each detection path respectively to obtain a number of detection nodes;

[0109] A signal comparator for pairwise comparing the information of all adjacent detection nodes from the start point to the end point on each detection path to obtain a number of node comparison results; and also for comparing the information of the start point and the end point of each detection path respectively to obtain a start - end comparison result;

[0110] A signal splicer for sequentially bit - by - bit splicing a number of node comparison results of adjacent detection nodes on each detection path in the information transfer direction, and then splicing with the start - end comparison result to generate a single - channel comparison result;

[0111] A result generator for obtaining the Trojan detection result of the corresponding detection path according to the single - channel comparison result.

[0112] Further, a preferred implementation manner of step S26 is as Figure 4 shown. Obtaining the Trojan detection result of the corresponding detection path according to the single - channel comparison result includes:

[0113] Step S261: Judge whether the information of the start point and the end point of the corresponding detection path is the same according to the data bits of the start - end comparison result in the single - channel comparison result; if the same, execute step S262; if not the same, execute step S263;

[0114] Step S262: Determine that there is no hardware Trojan on the corresponding detection path and set the Trojan detection result to "0";

[0115] Step S263: Determine that there is a hardware Trojan on the corresponding detection path and set the Trojan detection result to "1"; and obtain the type of the hardware Trojan and the position of the hardware Trojan on the corresponding detection channel according to the input instruction and other data bits of the single - channel comparison result.

[0116] This embodiment sets a premise that during the detection process, when not under HT attack, the address or data of the detection path will not change. The detection module 300 of this embodiment detects the corresponding detection path according to the instruction type. The detection process of one of the detection modules is briefly described below:

[0117] First, in this embodiment, the path for transmitting the key information corresponding to the input instruction is selected as the detection path, and node division is performed to obtain detection nodes. The number of division points obtained for different paths is different. When each path transmits data or an address, the data or address obtained at the starting point of the path is used as a reference standard for whether the information has changed. Since it is a pipeline circuit architecture, the information transmitted by the previous nodes on the path is always obtained earlier than the subsequent path nodes. If the information of a certain node in the detection path changes, it will cause the subsequent detection path interval and nodes to transmit incorrect information that has already been changed, rather than the information at the starting point of the detection path. The incorrect information will be continuously transmitted in the subsequent nodes of the path until an HT attack occurs again and the information is changed again. Secondly, the information of the two division points at the starting point and the end point of a detection path, as well as the information of all two adjacent division points on the path, are compared pairwise; if the information of the two division points being compared is the same, the comparison result is represented by a one-bit binary value as "0", otherwise it is "1". Thirdly, all the comparison results of the detection path are concatenated; preferably, the concatenation operation is performed in the order from right to left according to the information transmission direction, that is, from the low bit to the high bit of the binary number, and the comparison result of the starting point and the end point is placed at the highest bit, that is, the leftmost bit, to obtain the result after the concatenation operation. For example, on a certain detection path, there are four division points a, b, c, and d, where a is the starting point and d is the end point. The comparison result of the information of a and d is 1, and the comparison results of each two adjacent nodes a and b, b and c, and c and d are 0, 0, and 1 respectively. Then the result after the four-bit concatenation operation is 4’b1100, where b represents binary and 4 represents the data bit width. Of course, those skilled in the art can adopt other concatenation methods and place the comparison result of the starting point and the end point at other bit positions. When performing subsequent detection and judgment, the information of the corresponding data bits can be deduced for comparison, which does not affect the judgment of the Trojan detection result. After obtaining the concatenation results of the Trojan detection for each node, fast HT judgment can be achieved according to the values of each data bit. Specifically, after obtaining the concatenation result for each detection path, first judge whether the highest bit of the concatenation result, that is, the comparison result of the starting point and the end point of the detection path, is "1". If the highest bit is "1", it indicates that an HT attack has been detected in the detection path; otherwise, that is, the highest bit is "0", it is determined that there is no HT attack in the detection path. After detecting that the highest bit of the concatenation result is "1", it is also necessary to combine the information flow direction on the same detection path and the detection results between any two adjacent detection nodes to determine the position of the detection path corresponding to the occurrence of HT. For example, in addition to the highest bit of the concatenation result, find the results where the other bits of the detection result are "1", which means that the position between the two comparison points corresponding to these other bits is determined to be the position of the specific HT attack.There may be multiple other bits with a value of "1" in the path, that is, there may be multiple HT attacks occurring simultaneously in the path; otherwise, the result of the other bits is "0", indicating that there is no HT attack between the two comparison points of these other bits. Finally, the situation of HT attacks occurring in the detection path can be analyzed. After determining the specific location of the HT attack detection path, combined with the current input instruction, the location of the HT payload can be quickly located and found, thus providing the possibility to eliminate the HT impact from the root cause.

[0118] For the extended instruction set RV32M of the RISC-V instruction set architecture, the processor should be additionally integrated with corresponding modules capable of executing arithmetic instructions such as multiplication, division, and remainder (referred to as "multiplication and division instructions"), that is Figure 1 the multiplication and division operation module 106 in. And there is also a chance or possibility that hardware trojans are inserted in the data path for executing such instructions. Since the execution process of arithmetic control instructions such as division and remainder also occupies the space of the general-purpose register bank 105, the trojan detection process for such multiplication, division, and remainder instructions is also executed by the register data detection module 302. However, since the multiplication and division operation module 106 is different from the instruction fetch module 102, decoding module 103, execution module 104, and general-purpose register bank 105 in the pipeline architecture, when selecting the data detection path for such instructions, although it is still a type of register data detection path, the input starting point of its detection path is different from that of general R-type instructions, that is, its detection channel has two starting points. It requires both the detection starting point like that of conventional general R-type instructions and a new detection starting point pulled out from the multiplication and division operation module 106. Therefore, its detection channel has different sub-paths, but at most only one of the sub-paths where the two starting detection nodes are located is transmitting information during information transfer, and then the two sub-paths converge in the execution module 104 and form a path to write back to the general-purpose register bank 105. All paths passed through during the data transfer process should be included in the data detection channel related to such multiplication and division instructions. When generating the trojan detection result, the comparison result of the information at the starting point and the ending point of the path where the multiplication / division / remainder instructions in the RV32M instruction set executed by the multiplication and division operation module 106 are located can be used as the highest bit of the concatenated result; while the comparison result of the information at the starting point and the ending point of the path where the general R-type instructions are located is used as a certain bit (bit) in the concatenated result.

[0119] In addition, since the detection paths of load instructions and store instructions need to communicate with the peripheral device 600, and there are usually multiple devices in the peripheral device 600, there are multiple comparison results between the two comparison points. The multiple comparison results between the two division points need to be logically ORed and then used as the final result of the two comparison points. When an HT attack occurs between these two division points, it is also necessary to further combine instructions to determine on which peripheral device path the Trojan attack has occurred.

[0120] Since the detection path includes an address detection path and a data detection path, where the address detection path includes: a register address path, a load instruction address path, and a store instruction address path; the data detection path includes: a register data path and a store instruction data path. Then the hardware Trojan detection and recovery method further includes: performing a logical OR operation on the Trojan detection results of the address detection path and the Trojan detection results of the data detection path to generate a multi-channel Trojan detection result. Specifically, in implementation, if the Trojan detection results of the address detection path and the Trojan detection results of the data detection path are both splicings of comparison results of different pairwise nodes, that is, they are multi-bit data, the composite judgment module 400 first performs a bitwise OR operation on the Trojan detection results of the address detection path and the Trojan detection results of the data detection path respectively, and then performs a logical OR operation on the results of these two bitwise OR operations to generate the multi-channel Trojan detection result. Among them, the Trojan detection results obtained by separately performing Trojan detection on the register address path, the load instruction address path, and the store instruction address path are bitwise spliced and then bitwise OR operation is performed to obtain the Trojan detection result of the address detection path; the Trojan detection results obtained by separately performing Trojan detection on the register data path and the store instruction data path are bitwise spliced and then bitwise OR operation is performed to obtain the Trojan detection result of the data detection path. That is, when a hardware Trojan attack occurs in any one of the register address path, the load instruction address path, and the store instruction address path, it is determined that a Trojan attack has occurred in the address detection path, and the Trojan flag bit in its Trojan detection result is set to "1", otherwise it is set to "0"; similarly, when a hardware Trojan attack occurs in any one of the register data path and the store instruction data path, it is determined that a Trojan attack has occurred in the data detection path, and the Trojan flag bit in its Trojan detection result is set to "1", otherwise it is set to "0". Performing a logical OR operation on the Trojan detection results of the address detection path and the Trojan detection results of the data detection path, the equivalent effect is obtained: when a Trojan attack occurs in any one of the address detection paths or any one of the data detection paths, the Trojan flag bit of the multi-channel Trojan detection result is set to "1" to report the hardware Trojan attack behavior. The above process can be implemented by the composite judgment module 400. The composite judgment module 400 analyzes the single-channel comparison results of the five sub-modules 301-305 in the detection module 300 to obtain the Trojan detection results of each channel, judges the type of HT and the specific location where HT occurs, and summarizes them into multi-channel Trojan detection results. Further, when the composite judgment module 400 detects an HT attack, the valid flag bit in the Trojan detection result is used to restore the normal operation of the RISC-V processor 100, including operations such as pipeline flushing, internal register flushing of the detection module 300, and stopping the backup of the control backup module 200.

[0121] In specific implementation, this embodiment can adopt the method for restoring the RISC-V processor program function as shown in Figure 5 . In step S5, the instruction fetch module 102, the decoding module 103, and the execution module 104 in the pipeline architecture are respectively used to perform instruction fetching, decoding, and execution operations in sequence again. By using the write-back information from the backup module 200 in the general-purpose register bank 105, the RISC-V processor is restored to the normal state. Specifically, when the Trojan flag in the HT detection result output by the composite judgment module 400 is "1", it indicates that a hardware Trojan has been inserted at a certain position inside the current RISC-V processor. Therefore, it is necessary to start the recovery program to restore the processor to normal. Specifically, when the HT flag bit is "1", for the execution of other instructions that need to access the general-purpose register bank 105, the information that originally needed to be written into the general-purpose register bank 105 will be attacked by the Trojan and be tampered with into incorrect information, resulting in the incorrect information being written into the general-purpose register bank 105. At the same time, if the processor is not intervened, the influence caused by HT will spread. Therefore, the pipeline processing of the processor is first suspended to prevent the influence caused by HT from spreading further.

[0122] The recovery method in step S5 includes:

[0123] Step S51: Suspend the pipeline of the processor;

[0124] Step S52: Flush the registers in the pipeline and the detection module 300;

[0125] Step S53: The general-purpose register bank 105 retrieves the correct information from the backup module 200 again and writes it back to the attacked register inside it;

[0126] Step S54: Reset the registers at the same position in the backup module 200 and stop backing up the general-purpose register bank 105;

[0127] Step S55: Roll back the address of the instruction fetch module 102 to the instruction address attacked by the hardware Trojan, that is, the address pointed to by the program counter PC, and reread the corresponding instruction;

[0128] Step S56: The decoding module 103 starts to decode the instruction and fetches the correct information from the general-purpose register bank 105; the backup module 200 restarts backing up the information in the corresponding registers in the general-purpose register bank 105;

[0129] Step S57: The execution module 104 executes the instruction, and the processor is restored to the normal state.

[0130] Specifically, since neither the load instruction nor the store instruction needs to write information to the general-purpose register bank 105 before accessing the peripheral 600, the above processes 2), 3), 5), and 6) are not required during the recovery process after detecting HT. Additionally, the store instruction is used to access the peripheral 600 rather than the general-purpose register bank 105. Therefore, if an HT attack occurs in the path where the store instruction transmits information, this embodiment provides an enable signal to "stop writing" to the peripheral 600, thereby preventing the impact caused by HT from spreading to the peripheral 600.

[0131] In a preferred embodiment, the hardware Trojan detection and recovery device and method provided in this embodiment is HT for low-probability trigger conditions. For the RISC-V processor core 100 with a three-stage pipeline, assuming that the probability of execution or non-execution of each instruction is set to 1 / 2, the Trojan detection process using the hardware Trojan detection device and method provided by the present invention requires at least one clock (the clock length may vary depending on the circuit structure design), and the RISC-V processor recovery process requires three clock cycles, a total of five clock cycles. During the RISC-V processor recovery process, the first clock cycle pauses the pipeline, the second clock cycle general-purpose register group 105 retrieves data from the backup module 200; and the third clock cycle, after the instruction resumes execution, the decoding module 103 retrieves the correct data from the general-purpose register group 105. As the number of pipeline stages increases, the clock cycles consumed by the detection process also increase. Therefore, the hardware Trojan detection and recovery method provided by the embodiment of the present invention requires at least five clocks to detect the Trojan and restore the normal operation of the processor. Since the probability of triggering a hardware Trojan in each clock cycle is 1 / 2, too frequent hardware Trojan attacks will result in not having enough time to complete the Trojan detection process and function recovery. Therefore, the hardware Trojan detection and recovery device and method provided in the embodiments of the present invention are mainly aimed at low-probability hardware Trojans with a triggering frequency of less than 1 / 32. In actual applications, hardware Trojans are all concealed, that is, their triggering frequency is usually low. For example, HTs in the form of finite state machines (FSMs), counters, and combinations of FSMs and counters all have a common feature: the HT is only triggered when the set low-probability triggering conditions are met. During the actual circuit operation, the HT is not triggered, and these HTs remain silent, that is, most HTs are highly concealed. For example, hardware Trojans usually will not be triggered within 5 clock cycles, to prevent the hardware Trojans from being discovered too early, which is one of the purposes of attackers designing HTs. Furthermore, from the perspective of digital circuit technology, since each clock cycle is typically very fast, typically in the nanosecond range, as long as the hardware Trojan trigger frequency is not too high, the detection and recovery device provided by the embodiments of the present invention can detect the hardware Trojan in the three-stage pipeline RISC-V processor and eliminate its impact within five clock cycles, making Trojan detection and program recovery very fast. Therefore, the detection method and device provided by the embodiments of the present invention detect and recover the function of low-probability hardware Trojans, matching the needs of actual application scenarios.

[0132] In order to further improve the speed of hardware Trojan detection and function recovery and reduce power consumption, the embodiment of the present invention is directed to Figure 1Each module of the hardware Trojan detection and recovery device in the embodiment is designed, implemented, and optimized based on digital circuits. The hardware Trojan detection and recovery circuit provided in this embodiment mainly solves three technical problems: First, a new detection architecture for hardware Trojans with low probability of triggering is designed based on the RISC-V processor to achieve real-time and fast detection of hardware Trojans; second, the resource consumption required for backing up information in the general-purpose register bank 105 in the processor is minimized, and the power consumption is reduced at the same time; third, how to quickly recover after detecting a hardware Trojan to prevent the spread of the impact caused by the trigger of the hardware Trojan.

[0133] For the above five detection paths, namely: the register address path, the load instruction address path, the store instruction address path, the register data path, and the store instruction data path, there are three types of hardware target Trojans that the circuit provided in this embodiment can detect:

[0134] 1) HT attacks occurring inside any pipeline circuit module involved in the above five detection paths;

[0135] 2) HT attacks occurring between each pipeline circuit module in the above five detection paths;

[0136] 3) HT attacks occurring between the RISC-V processor 100 and the peripheral 600 in the above load instruction address detection path, store instruction data, and store instruction address detection paths.

[0137] In the RISC-V processor, input instructions are usually stored in off-chip memory outside the chip. As Figure 1 shown, the ROM in the peripheral 600 needs to be accessed when reading instructions. In particular, when executing some instructions, the data and addresses involved may be stored in the RAM in the peripheral 600, such as the load instruction in the I-type instruction and the store instruction in the S-type instruction. In addition, the execution of some instructions also involves connecting more external devices through various interfaces in the peripheral 600, such as URAT, GPIO, and SPI, for data communication and address access. In particular, the RISC-V processor 100 is communicatively connected to each component in the peripheral 600 through the RIB bus 500.

[0138] (1) Circuit design of the register address detection module 301:

[0139] The register address detection module provided by the embodiments of the present invention mainly targets the R-type instructions in RISC-V, including the R-type instructions in the basic instruction set RV32I and the R-type instructions (referred to as multiplication and division instructions) and load instructions in the RV32M extended instruction set. After the RISC-V processor executes an R-type instruction or a load instruction and reads information from the peripheral device 600, it needs to write the information back to the general-purpose register file 105. Therefore, HT detection needs to be performed on the write-back address path. It should be noted that in this circuit, for the address detection of the load instruction, it only focuses on the address path between when the load instruction fetches information from the peripheral device 600 and writes it back to the general-purpose register file 105. Therefore, since the path of the load instruction for writing to the register file is the same as that of the regular R-type instruction, the address detection of the load instruction for writing GPRs is placed in the register address detection module 301, while the address path before the load instruction accesses the peripheral device is implemented by the load instruction address detection module 303.

[0140] As Figure 6 shown, it is a register address detection circuit diagram of the register address detection module according to the embodiments of the present invention implemented based on digital circuits. Taking the division of the register address detection path into five detection nodes as an example, in the Figure 6 register address detection circuit, according to the direction of information transfer in the register address path, five detection nodes P1 to P5 are divided from the register address path of the RISC-V processor, which are respectively:

[0141] P1: The starting point of the register address path, and what needs to be detected is the output from the instruction fetch module 102, preferably the destination register (rd) address in the fetched R-type instruction, that is, the instruction content inst_i[11:7] from the 7th bit to the 11th bit;

[0142] P2: The second detection node, which is the output signal of the destination register rd address flowing through the decoding module 103;

[0143] P3: The third detection node, and what needs to be detected is the input signal ie_reg_waddr_o of the destination register rd address flowing through the decoding module 103 to the execution module 104;

[0144] P4: The fourth detection node, and what needs to be detected is the output signal ex_reg_waddr_o inside the execution module 104 where the destination register rd address flows through;

[0145] P5: The end point of the register address path, which needs to detect the input signal waddr_i of the destination register rd address flowing through the execution module 104 to the input end of the general-purpose register bank 105. It should be noted that those skilled in the art can set different numbers of detection nodes for comparison according to specific input R-type instructions.

[0146] In addition, Figure 6 The shown register address detection circuit further includes three input control signals, namely:

[0147] En1: The first enable signal En1 is used to control whether information needs to be written into the general-purpose register bank 105 during the decoding stage of the instruction. It is true when writing is required, that is, the logical value is "1";

[0148] En2: The second enable signal En2 is used to control whether information needs to be written into the general-purpose register bank 105 during the execution stage of the instruction. It is true when writing is required, that is, the logical value is "1";

[0149] En3: The third enable signal En3 is used to indicate whether the current instruction needs to execute instructions such as multiplication / division / remainder in the RV32M extended instruction set (referred to as multiplication and division instructions). If the current executed instruction is from the multiplication and division operation module 106, the information sent to the above five detection nodes by the detection path will be different. That is, before the signal of the fourth detection node P4 is sent into the detection circuit for comparison, an additional level of comparator is required to select the input signal.

[0150] rst is the reset signal of the circuit.

[0151] HT flag bit: It is a 1-bit signal output by the composite judgment module 400. When an HT attack is detected on any detection channel, this flag bit is "1", otherwise it is "0".

[0152] The first counter: It is used to calculate the time required for the RV32M extended instruction set instructions from the multiplication and division operation module 106 during the decoding and execution stages. Among them, in order to focus on showing the core components of the register address detection circuit, the first counter is not shown in Figure 6 In Figure 6 In this, the core circuit of this detection circuit is mainly composed of several D flip-flops, a two-to-one selector, a comparator, and basic logic gate circuits, etc.

[0153] In the register address detection module 301, there are two parallel paths in the middle of the detection path, namely the conventional R-type instruction path. Since the path of the load instruction for writing the register file is the same as the conventional R-type instruction path, the address detection of the load instruction for writing GPRs is placed in the register address detection module 301, and also the R-type instruction path in the RV32M extended instruction set such as multiplication, division, and remainder. Therefore, it is necessary to determine the instruction type to execute which path. These two paths happen to be between two adjacent division points, so there is no influence on the information comparison of the division points. First, analyze the instruction output by the instruction fetch module 102 to determine whether it is an instruction such as division. Specifically, the operation process of the register address detection circuit is as follows: First, judge according to the type of the instruction. For the instructions in the RV32M extended instruction set (referred to as multiplication and division instructions), a first counter is required to control the generation of intermediate variables, while for ordinary R-type instructions and load instructions, the enable signal for writing to the general-purpose register file 105 in the decoding stage generates intermediate variables; then the enable signal for writing to the general-purpose register file 105 in the execution stage, combined with whether the first counter has completed the counting of the set value, and then classify and compare the information of the detection nodes to obtain the register address comparison results of each detection node.

[0154] If the instruction is a conventional R-type instruction, that is, the instruction only passes through the transmission path of the internal pipeline of the processor, there is no need to use a counter to generate a control signal, that is, there is no need to generate the write address intermediate variable R3. However, when the first enable signal En1 of the decoding module 103 is true, the signal inst_i[11:7] of the first detection node P1 is directly stored as the instruction write address intermediate variable R1, and the signal id_reg_waddr_o of the second detection node P2 is directly stored as the write address intermediate variable R2 of "decoding → GPRs".

[0155] If the current instruction is an instruction in the RV32M extension instruction set, an enable signal for controlling the first counter, i.e., the third enable signal En3, will be given. Since division and remainder instructions in the RISC-V processor usually require multiple clock cycles during the execution stage, for example, M = 35 clock cycles, and the first counter starts counting from the decoding module 103 and uses one more clock cycle to compare the information of the division point after the end, it is necessary to control the first counter to count M + 2 clock cycles, that is, the counter counts from "0" to "M + 1". Moreover, some information at the division point before the start of operations such as division needs to be backed up to generate intermediate variables, and D flip-flops are used to temporarily store the information of these division points in the detection path so that after the operation is completed, it can be compared with the information of the detection nodes in the subsequent detection path. For example, before the first counter finishes counting, the output of the first counter is "0", the first detection node P1(inst_i[11:7]) is temporarily stored as the instruction write address intermediate variable R1, and the first detection node P2(id_reg_waddr_o) is temporarily stored as the write address intermediate variable R2 of "decoding → GPRs"; when the first counter starts counting, that is, from when the output of the first counter is "1", that is, the entire interval of non-zero values, ie_reg_waddr_o is temporarily stored as the write address intermediate variable R3 of "execution → GPRs".

[0156] When the second enabling signal En2 (ex_reg_we_o) in the execution stage is true, node division and information comparison are performed on the regular transmission path of the R-type instruction through the internal pipeline of the processor. For instructions such as division, it is also necessary to combine the end of the count of the first counter, that is, whether it is the value of M + 1, and then perform information comparison on the detection nodes. The information of the first detection node P1, that is, inst_i[11:7] (the intermediate variable of the instruction write address) at the starting division point, is compared with the information of the fifth detection node P5, that is, (waddr_i) at the end point, to obtain the register address comparison result; the information of the first detection node P1, inst_i[11:7], is compared with the signal id_reg_waddr_o (the intermediate variable of the write address R2) of the second detection node P2, the signal id_reg_waddr_o of the second detection node P2 is compared with the signal ie_reg_waddr_o (the intermediate variable of the write address R3) of the third detection node P3, the signal ie_reg_waddr_o of the third detection node P3 is compared with the signal ex_reg_waddr_o of the fourth detection node P4, and the signal ex_reg_waddr_o of the fourth detection node P4 is compared with the signal waddr_i of the end point P5, respectively obtaining the comparison results of five intervals of the register address on the transmission channel. Finally, a total of five comparison results are obtained. And registers, such as D flip-flops, are used to separately save the five comparison results, and then these comparison results are concatenated in order to obtain the hardware Trojan detection result of the register detection module 301.

[0157] (2) Circuit design of the register data detection module 302:

[0158] As Figure 7 shown, it is a circuit diagram of a register data detection module implemented based on digital circuits according to an embodiment of the present invention.

[0159] The core purpose of the register data detection module 302 is to perform hardware Trojan detection by writing the information back to the common data path of the general-purpose register file 105 after executing a general R-type instruction or a load instruction to read information from the peripheral 600. Similar to the register address detection module 301, there are some intervals in the detection path of the register data detection module 302 where there are two starting division points from different paths of the transmission path, and there are two paths: the conventional R-type instruction path, that is, the first starting point, and the instruction path in the RV32M extended instruction set such as division and remainder, that is, the second starting point. These two paths form a "Y" structure, and the common part of the two paths has been incorporated into the conventional R-type instruction general path. Therefore, path detection also needs to be performed separately according to the instruction type. Thus, a second counter is needed to control the timing, and an enable signal also needs to be generated for instruction paths such as division in the execution stage to control the counting of the second counter. Different from the number of clocks required for the register address detection module 301 to complete counting, the counting completion times of the first counter and the second counter should differ by two clock cycles because the first counter starts counting in the decoding stage of the pipeline structure, and the second counter starts counting in the next clock cycle of the execution stage. Therefore, the count values required for the first counter and the second counter are related to the information to be detected, the pipeline structure, and their transmission order in the pipeline result.

[0160] As Figure 7 shown, take the example that the data detection path of the R-type instruction is divided into three detection nodes by the register data detection circuit, and the data detection paths of the division and remainder instructions in the RV32M extended instruction set are divided into two detection nodes.

[0161] Specifically, for the data detection paths of the conventional R-type instructions and load instructions, that is, the three detection nodes of the general R-type instruction path L1 are: Q1 → Q2 → Q3, where,

[0162] Q1: The first starting point of the register data path, which detects the signal from inside the execution module 104, that is, the data result reg_wdata that needs to be written to the general-purpose register file 105 after the execution of various instructions inside the execution module 104;

[0163] Q2: The second detection node, which detects the output signal ex_reg_wdata_o of the data flowing through the execution module 104 that needs to be written to the general-purpose register file 105;

[0164] Q3: The end point of the register data path, which detects the input signal wdata_i of the data flowing through the execution module 104 to the general register file 105 that needs to be written to the general-purpose register file 105.

[0165] The instruction path and data detection path in the RV32M extension instruction set, that is, the multiplication and division extension instruction path L2 is: DQ1 → DQ2 → Q2 → Q3. Among them, the starting point of its data detection path is different from that of the conventional R-type instruction, and after going through multiple detection points, it converges to the Q2 detection node. The intersection point of the two paths "Y" is at the Q2 detection node, and the signal of this detection node is ex_reg_wdata_o. That is, before converging to the Q2 detection node, the two newly added detection nodes are:

[0166] DQ1: The second starting point of the register data path, which detects the signal from inside the multiplication and division operation module 106, that is, the data result result_o after the multiplication and division instructions are operated in the multiplication and division operation module 106;

[0167] DQ2: The second detection node of the multiplication and division extension instruction path L2, which needs to detect the output signal div_result_o of the data flowing through the multiplication and division operation module 106 written to the general-purpose register bank 105.

[0168] In addition, Figure 7 The shown register data detection circuit further includes other input signals:

[0169] En4: The fourth enable signal, which is used to control writing the data "0" to the general-purpose register bank 105 to reset or reset its corresponding register, that is, the data written to the general-purpose register bank 105 by the general R-type instruction path is 0 or currently it is a no operation instruction (nop);

[0170] Counter completion: The second counter counts from "0" to "M - 1".

[0171] Figure 7 The shown register data detection circuit is mainly composed of several comparators, selectors, D flip-flops, and digital logic gate devices, etc. Among them, in order to focus on showing the core components of the register data detection circuit, the second counter is not shown in Figure 7 The circuit passes the second enable signal En2 (ex_reg_we_o) of "execute → GPRs", and then monitors whether the RV32M extension instruction has completed execution through the second counter, and whether En4 is true, and then classifies and compares the information of each adjacent detection node to obtain the comparison result of each register data.

[0172] During specific implementation, first, on the premise that En2 is true in the execution stage, for the multiplication / division extended instruction path L2, the counter needs to count from 0 to 6'd34 (the (M - 1)-th clock cycle), and at the same time, it is also necessary to process and compare the information of the division point on the general R-type instruction path L1 before comparing the information of the division point on the multiplication / division extended instruction path L2. Because at most only one of the two paths is working, the information of the starting division point of the non-working path is "0". Then, if En2 is true and the instruction path L1 is working, further determine whether En4 is true. If it is true, that is, the data written back to the general-purpose register bank 105 by the general R-type instruction path L1 is "0" or the nop instruction is currently being executed, and there is no need to process the information of the starting detection nodes of the two paths. The information of the detection nodes can be directly compared; otherwise, if the written data is not "0", it is also necessary to process the information of the detection nodes on the multiplication / division extended instruction path L2 and then compare the information of the detection nodes on the general instruction path L1. Finally, the general R-type instruction path L1 obtains the comparison results of the register data of the three detection nodes, and the multiplication / division extended instruction path L2 obtains the comparison results of the register data of the other three detection nodes. All the register data comparison results are concatenated as the output. For example, a, b, and C represent the register data comparison results 1 to 3 respectively, where C is the highest bit of path L1, and m, n, and K represent the register data comparison results 4 to ⑥ respectively, where K is the highest bit of path L2 and also the highest bit of the detection result of the register data detection module. The six regs data comparison results are concatenated in the order defined above to obtain a concatenated 6-bit comparison result {K, n, m, C, b, a}.

[0173] (3) Circuit design of the load instruction address detection module 303:

[0174] The load instruction address detection module 303: Performs HT detection on the address path of the load instruction from the start of execution until the corresponding peripheral 600 reads information. The main circuit diagram of the load instruction address detection module 303 is as Figure 8 shown. In Figure 8 the load instruction address detection circuit, according to the transmission information direction of the load instruction address path, four detection nodes J1 to J4 are divided from the load instruction address detection path, which are respectively:

[0175] J1: The starting point of the load instruction address path, which detects the signal from inside the execution module 104, that is, the result (op1_add_op2_res) after adding the two operands inside the execution module

[0176] J2: The second detection node of the load instruction address path, which detects the output signal (ex_mem_raddr_o) of the execution module 104 when the address of the load instruction accessing the peripheral 600 flows through it;

[0177] J3: The third detection node of the load instruction address path, which detects the input signal (m0_addr_i) of the RIB bus 500 when the address of the load instruction accessing the peripheral 600 flows through it;

[0178] J4: The end point of the load instruction address path, which detects the multiple output signals of the RIB bus 500 when the address of the load instruction accessing the peripheral 600 flows through it. For example, the output signals s0_addr_o to s5_addr_o corresponding to six peripherals.

[0179] In addition, Figure 8 The shown load instruction address detection circuit further includes an input control terminal:

[0180] En5: The fifth enable signal, which is used as the write enable signal (ex_mem_we_o) when the RISC-V processor core 100 stores information to the peripheral 600. In the actual circuit, information such as the opcode may also be needed to determine whether the current instruction is a load instruction.

[0181] Similarly, as Figure 8 shown, the basic circuit composition of the load instruction address detection module 303 includes several flip-flops, selectors, comparators, and combinational logic circuits. The circuit compares the information of the detection nodes according to whether the type of the instruction is a load instruction and whether the enable signal En5 written to the peripheral 600 in the execution stage is 0, and then the comparison results of each load instruction address can be obtained. Specifically, in implementation, Figure 8The composite comparison circuit structure in the lower left corner is used to select different peripheral accesses. There are multiple comparison cases between two detection nodes. For example, there are six peripherals 600 in the RISC-V processor. Therefore, it is necessary to determine where the signal op1_add_op2_res[27:0] of the first detection node J1 comes from. Therefore, it needs to be compared with the signals s0_addr_o[27:0]~s5_addr_o[27:0] of the fourth detection node J4 (end point) respectively. There are six possible cases for the six peripherals. Then, the logical OR operation result of these six comparison results is used as the real comparison result. The detection circuit in this embodiment only has the case of accessing the peripheral 600 through the core 100 of the processor. The high four bits [31:28] of the 32-bit address represent the access of the RISC-V processor 100 to the peripheral 600. Therefore, when comparing with the division point of accessing the peripheral 600, only the information of the lower 28 bits [27:0] needs to be compared. The address of the division point is compared through combinational logic to generate an enable signal to control the output information of the selector, and then the comparison result is output through a D flip-flop. The detection nodes of the load instruction address detection path are compared for information according to the method as described above Figure 3 shown, and four comparison results of the load instruction address detection path are obtained. Finally, all the load instruction address comparison results are concatenated in order as the output.

[0182] (4) Circuit design of the store instruction address detection module 304:

[0183] The store instruction address detection module 304 is used to perform HT detection on the address path when the store instruction needs to store the address in the information into the peripheral 600. The store instruction address detection circuit also divides multiple detection nodes from the store instruction address path according to the transmission information direction of the store instruction address path. For example, four detection nodes K1~K4 can be preferably set, which are in turn: the signal inside the execution module 104, the output signal of the address flowing through the execution module 104 when the store instruction stores information into the peripheral 600, the input signal of the address flowing through the RIB bus 500 when the load instruction stores information into the peripheral 600, and the end point signal reaching a certain peripheral. Since the store instruction address detection module 304 circuit can be implemented by a circuit similar to the load instruction address detection module 303, that is, it is implemented by several flip-flops, selectors, comparators, composite comparison circuits, digital logic gate circuits, etc. The circuits of both. Those skilled in the art can according to Figure 8 the inspiration and perform corresponding circuit design based on the RISC-V standard definition. Therefore, the circuit implementation embodiment of the store instruction address detection module 304 will not be described in detail.

[0184] In specific implementation, the information comparison at the division point can be performed according to whether the type of the instruction is a store instruction and whether the enable signal for writing to the memory in the execution stage is "1", and the comparison results of the addresses of each store instruction can be obtained. Among them, for the store instruction, the write address ex_mem_waddr_o to the peripheral (such as RAM) needs to be detected, and for the load instruction, the read address ex_mem_raddr_o needs to be detected; the ex_mem_we_o signal can be used to be in an inverse relationship in these two circuits, and ex_mem_we_o is "1" when the store instruction needs to write to the peripheral 600. The division point of the store instruction address detection path is compared for information according to the method as Figure 3 shown above to obtain the comparison results of the addresses of four store instructions, and finally all the comparison results of the store instruction addresses are concatenated in order as the output.

[0185] (5) Circuit design of the store instruction data detection module 305:

[0186] The store instruction data detection module 305 is used to perform HT detection on the data path when the store instruction needs to store the data in the information to the peripheral 600. Similarly, the detection idea of the store instruction data detection module 305 is similar to that of the store instruction address detection module 304, and the structures are also relatively similar. The differences are as follows: the information input at the division point of the store instruction data detection module 305 is data, and all the data is 32 bits, while the information input at the division point of the store instruction address detection module 304 is the address. The store instruction data detection circuit can divide multiple detection nodes from the store instruction data detection path according to the information transfer direction of the store instruction data path. For example, three detection nodes W1 to W3 are set up, which are respectively: the store data signal from inside the execution module 104, the input signal of the data flowing through the RIB bus 500 when the store instruction stores information to the peripheral 600, and the output signal of the data flowing through the RIB bus 500 to access each peripheral when the store instruction stores information to the peripheral 600. The information at the division point of the store instruction data detection path is compared, and three comparison results of the store instruction data are obtained according to the node comparison method described above. Finally, all the comparison results of the store instruction data are concatenated in order as the output. Those skilled in the art can Figure 8 be inspired by this and perform corresponding circuit design based on the RISC-V standard definition. Therefore, the circuit implementation embodiments of the store instruction data detection module 305 will not be elaborated further.

[0187] (6) Circuit design of the composite judgment module 400:

[0188] The composite judgment module 400 is used to splice the single-channel comparison results of each sub-module 301-305 in the detection module 300 and then perform unified hardware Trojan judgment to obtain specific information about the HT. For example, it can judge the type of HT and the specific location in the detected path where the HT occurs. Since the circuit of the composite judgment module 400 needs to splice multiple single-channel comparison results and perform HT analysis, the HT flag bit can be obtained through combinational logic circuits such as data splicing logic gates and "bitwise OR" gates. If the logical OR operation of the multi-channel Trojan detection results obtains a logical "1", it indicates that there is at least one HT on a certain channel; otherwise, the HT flag bit is "0". When it is judged that an HT attack occurs in the current instruction, the instructions of the execution module 104 and the program counter PC (address) are respectively judged as: incorrect instructions and incorrect PC. As Figure 1 shown, in the system-on-chip of the RISC-V processor, the incorrect PC will be fed back to the instruction fetch module 102 for PC rollback in the instruction fetch stage, that is, the current PC of the instruction fetch module 102 is replaced with the incorrect PC when an exception occurs. After the PC rollback, the instruction corresponding to this PC is fetched again from the ROM, and the RISC-V processor 100 flushes the pipeline and re-executes the instruction to achieve function recovery. Those skilled in the art can make corresponding circuit designs based on the inspiration described in the above method and based on the RISC-V standard definition. Therefore, the circuit implementation embodiments of the composite judgment module 400 will not be described in detail.

[0189] (7) Circuit design of the backup module 200:

[0190] In order to realize the backup of the information in the general-purpose register file 105, a new backup structure is proposed in this embodiment. Each time the RISC-V processor writes information to the general-purpose register file 105, even if the general-purpose register file 105 contains multiple registers, such as 32 32-bit registers, only one 32-bit register is written in the embodiment of the present invention, that is, only the register in the general-purpose register file 105 that is written with new information needs to be quickly backed up. Therefore, when the backup module 200 backs up the information in the general-purpose register file 105, it can adopt such as Figure 9The circuit shown is implemented. Except for the general-purpose register bank 105, other logic circuits can be integrated in the backup module 200. In specific implementation, when the instruction is executed normally, since the RISC-V processor is not under HT attack, the information written to the general-purpose register bank 105 is normal. The backup register bank 201 of the backup structure will also make a normal backup of the general-purpose register bank 105, but the backed-up information will be 1 clock cycle slower than the information written back to the general-purpose register bank 105 normally, and the information in the backup structure will not be given back to the general-purpose register bank 105 without detecting HT. When the HT flag signal "1" indicating the result of detecting the HT attack is sent from the detection module 300, the abnormal information is also written into the general-purpose register bank 105 within the same 1 clock cycle, so unexpected information appears in the general-purpose register bank 105. Secondly, in the next clock cycle, the general-purpose register bank 105 will retrieve the information of the register bank overwritten by the abnormal information from the backup structure according to the register bank address corresponding to the detected abnormal information. That is to say, the data in the general-purpose register bank 105 is restored to the state before the HT attack; at the same time, the backup structure no longer backs up the data in the abnormal information, but replaces this data with 0 of the same number of bits and writes it into the backup structure to prevent the abnormal information from being written into the backup structure. Finally, when the instruction fetch module 102 tumbles and fetches the address of the instruction corresponding to the occurrence of the HT attack again, a signal indicating the completion of the instruction tumbling will be given to the backup module 200. According to this tumbling completion signal, the backup module 200 will write back the backed-up information from the general-purpose register bank 105 again in the next clock cycle to prevent the loss of the backed-up information. This makes the information content in the backup structure the same as that in the general-purpose register bank 105, and there is only a 1-clock-cycle delay in timing.

[0191] This embodiment proposes a new architecture for RTL-level hardware Trojan detection and rapid recovery of the RISC-V processor. It is proposed to quickly detect some paths for transmitting critical information, not only detect the general-purpose register bank 105 itself, but also expand the detection scope to the data path and address path through which the information to be written into the general-purpose register bank 105 passes. In addition, the data and address paths when the load and store instructions in the basic instruction set RV32I of RISC-V access external devices are also detected. Among them, the detection speed of the detection module provided in this embodiment is related to the execution of the instruction type, and the fastest detection result in this embodiment only uses 1 clock cycle.

[0192] After detecting an HT attack, in this embodiment, there is not too much idle or invalid data (commonly known as "bubbles") in the circuit design, and the processing process shows compactness and parallelism. As a result, from the detection of an HT attack that causes the pipeline of the processor to enter an abnormal state to the pipeline of the processor returning to the normal state, only 3 clock cycles are used. Among the same type of detection and recovery structures, the recovery speed of this embodiment is the fastest, and the power consumption of the recovery structure is lower.

[0193] Furthermore, based on the same inventive concept as the above embodiment, this embodiment also provides a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements each module of the hardware Trojan detection and recovery device for the RISC-V processor, or each step of the hardware Trojan detection and recovery method for the RISC-V processor.

[0194] Furthermore, based on the same inventive concept as the above embodiment, this embodiment also provides a RISC-V system-on-chip, which internally integrates the hardware Trojan detection and recovery device for the RISC-V processor based on the CMOS semiconductor process. The hardware Trojan detection and recovery device and the RISC-V processor form an integrated RISC-V system-on-chip (SoC).

[0195] In addition, this embodiment also implements the hardware Trojan detection and recovery device for the RISC-V processor using digital circuits based on a three-stage pipeline RISC-V processor, and deploys it on a field-programmable gate array (FPGA) for physical verification.

[0196] Taking the FPGA chip of the ZYNQ7000 series as the platform, the hardware Trojan detection and recovery circuit implemented using Verilog HDL can be functionally tested and verified. During the verification process, the experimental results show that all simple HTs inserted between any two adjacent detection points on each detection path and between the starting point and the ending point of the developed hardware Trojan detection and recovery point can be detected. For example, an HT with a low probability of triggering is designed: the signal reg_waddr_i of the decoding module 103 is designed as the hardware Trojan trigger signal. For example, a finite state machine (FSM) formed when it is continuously 5'h4 (h represents hexadecimal), 5'h5, 5'h6, 5'h7. When the FSM appears three times, the condition of the HT is triggered, and the information of "reg_waddr" is changed to the value of "reg_waddr + 4'hf". Finally, the designed HT is inserted into the decoding module 103 of the RISC-V processor.

[0197] 1) Functional verification:

[0198] To verify the Trojan detection and recovery capabilities of the proposed circuit, Vivado was used for compilation, simulation, and synthesis to generate a bitstream file. The bitstream file was then burned from a host computer into an FPGA development board using the Joint Test Action Group (JTAG) serial port for on-board verification. Finally, predefined buttons on the FPGA development board were operated to observe whether the output signal was correct. The Vivado tool's online logic analyzer (ILA) was used to capture the waveform of the signal after board installation to determine whether an anomaly occurred. Experimental results show that when a hardware Trojan is triggered, this embodiment can quickly detect the erroneous instruction and instruction address, namely the corresponding PC value, and then initiate a rollback of the PC value in instruction fetch module 102 to the original address. During the decoding phase, re-executing the instruction retrieves the correct data from the corresponding register group in general-purpose register group 105. At this point, the processor has returned to normal operation.

[0199] 2) Hardware resource consumption:

[0200] Table 1 shows the resource consumption of the original RISC-V architecture and the new detection and recovery architecture. Experimental data shows that the hardware Trojan detection and recovery circuit provided by this embodiment consumes relatively few hardware resources. The design, testing, and verification of this embodiment have been completed, achieving the intended design goals.

[0201] Table 1

[0202]

[0203] The above are merely preferred embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A hardware Trojan detection and recovery method for RISC-V processors, characterized in that, Including the following steps: When the RISC-V processor executes an input instruction, real-time backup of the information written to the general-purpose register file is performed to obtain backup information; A pipeline architecture is constructed, and one or more detection paths are selected in the pipeline architecture for hardware Trojan detection to obtain the Trojan detection results of each detection path; When there is a hardware Trojan attack in any one of the detection paths, control is used to pause the operation of the pipeline architecture and reset all the register data in the pipeline architecture; Retrieve the original information tampered with by the hardware Trojan from the backup information and write it back to the corresponding position in the general-purpose register file; Use the pipeline architecture to sequentially perform instruction fetching, decoding, and execution operations again, and use the write-back information in the general-purpose register file to restore the RISC-V processor to a normal state; The step of selecting one or more detection paths in the pipeline architecture for hardware Trojan detection to obtain the Trojan detection results of each detection path specifically includes: Select the start point and end point of each detection path; Perform node partitioning on each detection path respectively to obtain a number of detection nodes; Compare the information of all adjacent detection nodes between the start point and the end point on each detection path pairwise to obtain a number of node comparison results; Compare the information of the start point and the end point of each detection path to obtain a head-tail comparison result; Concatenate the several node comparison results of the adjacent detection nodes of each detection path in sequence according to the information transmission direction bit by bit, and then concatenate them with the head-tail comparison result to generate a single-channel comparison result; According to the single-channel comparison result, obtain the Trojan detection result of the corresponding detection path.

2. The hardware Trojan detection and recovery method for RISC-V processors according to claim 1, characterized in that, The step of obtaining the Trojan detection result of the corresponding detection path according to the single-channel comparison result includes: Judge whether the information of the start point and the end point of the corresponding detection path is the same according to the data bits of the head-tail comparison result in the single-channel comparison result; If they are the same, it is determined that there is no hardware Trojan on the corresponding detection path; If they are not the same, it is determined that there is a hardware Trojan on the corresponding detection path, and according to the input instruction and other data bits of the single-channel comparison result, obtain the type of the hardware Trojan and the position of the hardware Trojan on the corresponding detection channel.

3. The hardware Trojan detection and recovery method for a RISC-V processor according to claim 1, characterized in that, The detection paths include: an address detection path and a data detection path; After obtaining the Trojan detection results of each detection path, it further includes: Perform a logical OR operation on the Trojan detection result of the address detection path and the Trojan detection result of the data detection path to generate a multi-channel Trojan detection result.

4. The hardware Trojan detection and recovery method for RISC-V processors according to claim 3, wherein The address detection path includes: a register address path, a load instruction address path, and a store instruction address path; the data detection path includes: a register data path and a store instruction data path; Use the register address path, the load instruction address path, and the store instruction address path to respectively perform bit-by-bit concatenation on the Trojan detection results obtained after hardware Trojan detection of the address detection path, and then perform a bit-by-bit OR operation to obtain the Trojan detection result of the address detection path; The register data path and the storage instruction data path are used to perform bitwise concatenation on the Trojan detection results obtained after Trojan detection on the data detection path respectively, and then perform bitwise OR operation to obtain the Trojan detection result of the data detection path.

5. A hardware Trojan detection and recovery device for RISC-V processors, characterized in that, For implementing the hardware Trojan detection and recovery method for a RISC-V processor according to any one of claims 1-4, including: A RISC-V processor, including: a control module, and a pipeline architecture built based on the RISC-V instruction set; the pipeline architecture includes: an instruction fetch module, a decoding module, an execution module, and a general-purpose register file; A hardware Trojan detection and recovery device, including: a backup module and a detection module; The backup module is used to perform real-time backup on the information written into the general-purpose register file when the RISC-V processor executes an input instruction to obtain backup information; The detection module is used to perform hardware Trojan detection on one or more selected detection paths in the pipeline architecture to obtain the Trojan detection results of each detection path; The control module is used to control the suspension of the operations of each module in the pipeline architecture and reset all the register data in the pipeline architecture when there is a hardware Trojan attack in any one of the detection paths; The general-purpose register file is used to retrieve the original information tampered by the hardware Trojan from the backup information and write it back to the corresponding position in the general-purpose register file; The instruction fetch module, the decoding module, and the execution module in the pipeline architecture are used to perform instruction fetching, decoding, and execution operations respectively in sequence, and restore the RISC-V processor to the normal state by using the write-back information in the general-purpose register file; The detection module includes: A detection path selector for selecting the start point and the end point of each detection path; A path node divider for respectively dividing each detection path into nodes to obtain a number of detection nodes; A signal comparator for comparing the information of all adjacent detection nodes from the start point to the end point on each detection path pairwise to obtain a number of node comparison results; and also for comparing the information of the start point and the end point of each detection path respectively to obtain a head and tail comparison result; A signal splicer for successively performing bitwise concatenation on the number of node comparison results of adjacent detection nodes on each detection path according to the information transfer direction, and then concatenating with the head and tail comparison result to generate a single-channel comparison result; A result generator for obtaining the Trojan detection result of the corresponding detection path according to the single-channel comparison result.

6. The hardware Trojan detection and recovery device for a RISC-V processor according to claim 5, wherein, The hardware Trojan detection and recovery device further includes a composite judgment module: The composite judgment module is used to perform a logical OR operation on the Trojan detection result of the address detection path and the Trojan detection result of the data detection path to generate a multi-channel Trojan detection result.

7. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it realizes each step of the hardware Trojan detection and recovery method for a RISC-V processor according to any one of claims 1-4.

8. A RISC-V system-on-chip, characterized in that, Inside it, a hardware Trojan detection and recovery device for a RISC-V processor as described in any one of claims 5-6 is integrated based on a CMOS semiconductor process, and the hardware Trojan detection and recovery device and the RISC-V processor form an integrated RISC-V system-on-chip.

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