Hybrid ADC circuit and module for charge domain SRAM in-memory computing

Abstract

The present invention discloses a hybrid ADC circuit and module for charge domain SRAM in-memory calculation, and relates to the technical field of integrated circuit design. The hybrid ADC circuit of the present invention includes: a reference voltage selector, a digital-to-analog converter, a dynamic comparator, a shift register, a decoder, a successive approximation control logic, a random number generator, and two input switches. The present invention divides the 6-bit quantization process of the analog signal into: first performing high 3-bit quantization and then performing low 3-bit quantization. The present invention fully reuses the reference voltage for high 3-bit quantization, greatly reducing the number of capacitors required for the circuit, saving the area overhead and power consumption of the circuit; the present invention uses a random number generator to control the operation of the digital-to-analog converter, so that when performing low 3-bit quantization, the quantized result is used as a probability bit stream to perform serial calculations in the random domain, which can effectively reduce the area overhead and power consumption of the peripheral shift accumulation circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and more specifically to: 1. a hybrid ADC circuit for charge domain SRAM in-memory calculation; 2. a hybrid ADC module for charge domain SRAM in-memory calculation. Background Art

[0002] The research scheme of in-memory computing circuit based on SRAM is mainly divided into two directions: digital in-memory computing circuit and analog in-memory computing circuit. Both have their own advantages and disadvantages. Designers often make compromises for different application scenarios. In the in-memory computing scheme, the weights expressed in binary form will be written into the SRAM array in advance through the write circuit. In the digital in-memory computing circuit, the input binary number will be dot-multiplied with the corresponding weight binary. Therefore, the parallelism of the digital in-memory computing circuit is very high, but because it is essentially a one-bit multiplication by a one-bit multiplication, its overall energy efficiency is very poor. Analog in-memory computing innovatively converts binary numbers into corresponding analog quantities (voltage, time), and can realize a multi-bit multiplication of a single bit operation in one computing cycle, which greatly improves the computing energy efficiency. However, due to the need for digital-to-analog conversion and analog-to-digital conversion, the analog domain in-memory computing circuit usually requires a large number of DAC circuits and ADC circuits. These additional circuits consume a lot of chip area outside the array.

[0003] And although the analog domain in-memory computing solution has higher energy efficiency advantages and smaller area overhead within the array as the number of processing bits increases, this also means that a higher-precision ADC readout circuit is required and a large number of shift-and-accumulate circuit modules are required outside the array. This greatly increases the area overhead of the analog domain in-memory computing circuit. The traditional solution is to perform shift accumulation in the analog domain and then use an ADC for quantized output, but this also faces problems such as decreased quantization accuracy. Therefore, as the accuracy of data processing by the in-memory computing circuit continues to improve, how to effectively reduce the area overhead of high-precision ADC circuits and shift-and-accumulate circuit modules outside the array has gradually become a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0004] Based on this, in order to solve the problem of excessive area overhead of ADC quantization circuit and peripheral shift-and-accumulate circuit module in the prior art, a hybrid ADC circuit and module for charge domain SRAM in-memory calculation is provided to solve the problem.

[0005] The present invention is implemented by the following technical solutions:

[0006] In a first aspect, the present invention provides a hybrid ADC circuit for charge domain SRAM in-memory calculation, for calculating an analog signal V AIFirst perform high 3-bit quantization, then perform low 3-bit quantization.

[0007] The hybrid ADC circuit for charge domain SRAM in-memory calculation includes: reference voltage selector V_Choose, digital-to-analog converter DAC_3, dynamic comparator Comp, shift register Shift_Reg, decoder Decoder, successive approximation control logic SAR-logic, random number generator Random, 2 input switches S A ~S B .

[0008] The control end of V_Choose is connected to the output end of the Decoder, and the output end is used to output the reference voltage V ref , and through S B Connect to the input of DAC_3; the output of Random is used to output 3 random number signals Q <0> ~Q <2> , and connected to the control end of DAC_3; the output end of DAC_3 is used to output the comparison signal V out , and connect to the inverting input of Comp; V AI By S A Connect the in-phase input of Comp; the output of Comp is connected to the input of SAR-logic; the output of SAR-logic is connected to the input of Shift_Reg; the output of Shift_Reg is connected to the input of Decoder.

[0009] At high 3-bit quantization, S A , S B On, DAC_3 is based on Q <0> ~Q <2> , and combined with V ref To adjust V out , Comp to V AI and V out Perform three successive approximation comparisons; the result of the Pth comparison of Comp is processed by SAR-logic and Shift_Reg in turn to obtain the Pth high 3-bit code D, and the Qth high 3-bit code is decoded by Decoder to control V_Choose to adjust V ref To adjust the V used for the Q+1th comparison out ; P∈[1,3], Q∈[0,2]; The high 3 bits of the 0th code are the initial value, and the high 3 bits of the 3rd code are the high 3 bits of the quantization result D[2:0].

[0010] At low 3-bit quantization, S A On, S B Disconnect, DAC_3 according to Q <0> ~Q <2> To adjust V out , Comp to V AI and Vout Perform 8 random comparisons and output the 8-bit probability bit stream corresponding to the lower 3-bit code D[5:3].

[0011] The implementation of the hybrid ADC circuit for charge domain SRAM in-memory computing is based on the method or process of an embodiment of the present disclosure.

[0012] In a second aspect, the present invention discloses a hybrid ADC module for charge domain SRAM in-memory computing, which adopts the layout of a hybrid ADC circuit for charge domain SRAM in-memory computing disclosed in the first aspect.

[0013] The implementation of the hybrid ADC module for charge domain SRAM in-memory computation is in accordance with the method or process of an embodiment of the present disclosure.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] 1. The present invention provides a hybrid ADC circuit, which converts the analog signal V AI The 6-bit quantization process is divided into first high 3-bit quantization and then low 3-bit quantization; wherein, the present invention fully reuses the reference voltage V ref To perform high 3-bit quantization, the capacitor array of the upper 3 bits is removed while ensuring the quantization accuracy, which greatly reduces the number of capacitors required for the circuit and saves the area overhead and power consumption of the circuit; the present invention introduces random calculation and uses a random number generator to control the operation of the digital-to-analog converter, so that when performing low 3-bit quantization, the quantized result is used as a probability bit stream to perform serial calculation in the random domain, which can effectively reduce the area overhead and power consumption of the peripheral shift-and-add circuit.

[0016] 2. The dynamic comparator of the present invention introduces complementary inputs to improve its input voltage range; at the same time, normally-on transistors are added between the output end of the dynamic pre-amplifier circuit and the differential input pair tubes, and between the tail current source and the differential input pair tubes to reduce the impact of kickback noise and ensure the use effect of the dynamic comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 A signal flow diagram of the hybrid ADC circuit for charge domain SRAM in-memory calculation provided in Embodiment 1 of the present invention when performing high 3-bit quantization;

[0019] Figure 2 A signal flow diagram of the hybrid ADC circuit for charge domain SRAM in-memory calculation provided in Embodiment 1 of the present invention when performing low 3-bit quantization;

[0020] Figure 3 for Figure 1 The circuit structure diagram of V_Choose in the figure;

[0021] Figure 4 for Figure 1 The circuit structure diagram of DAC_3 in the figure;

[0022] Figure 5 for Figure 1 The circuit structure diagram of Random in the figure;

[0023] Figure 6 for Figure 1 The circuit structure diagram of Comp;

[0024] Figure 7 for Figure 1 The circuit structure diagram of SAR-logic in the figure;

[0025] Figure 8 for Figure 1 The circuit structure diagram of Shift_Reg in the figure;

[0026] Fig. 9 for Figure 1 The circuit structure diagram of the Decoder in the figure;

[0027] Fig.10 A brief schematic diagram of a hybrid ADC circuit for charge domain SRAM in-memory calculation provided in Embodiment 1 of the present invention;

[0028] Fig.11 A partial signal timing diagram of a hybrid ADC circuit for charge domain SRAM in-memory calculation provided in Embodiment 1 of the present invention;

[0029] Fig.12 A processing effect diagram of a hybrid ADC circuit for charge domain SRAM in-memory calculation provided by Embodiment 1 of the present invention;

[0030] Fig.13 This is a comparison diagram between the hybrid ADC circuit for charge domain SRAM in-memory calculation provided in Example 1 of the present invention and other ADC circuits. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0034] Example 1

[0035] See also Figure 1 , 2 , which is a hybrid ADC circuit for charge domain SRAM in-memory calculation provided in this embodiment 1, and shows the signal flow diagram of the hybrid ADC circuit when performing high 3-bit quantization and low 3-bit quantization respectively. In fact, it also shows the circuit architecture of the hybrid ADC circuit.

[0036] It should be noted that the hybrid ADC circuit for charge domain SRAM in-memory calculation provided in this embodiment 1 is intended to process the analog signal V AI Complete 6-bit quantization - first perform high 3-bit quantization, then perform low 3-bit quantization.

[0037] like Figure 1 , 2 As shown in FIG. 1 , the hybrid ADC circuit for charge domain SRAM in-memory calculation can be divided into the following according to the functions: 1 reference voltage selector V_Choose, 1 digital-to-analog converter DAC_3, 1 dynamic comparator Comp, 1 shift register Shift_Reg, 1 decoder Decoder, 1 successive approximation control logic SAR-logic, 1 random number generator Random, 2 input switches S A ~S B .

[0038] From the connection point of view:

[0039] The control end of V_Choose is connected to the output end of the Decoder, and the output end is used to output the reference voltage V ref , and through S B Connect to the input of DAC_3; the output of Random is used to output 3 random number signals Q <0> ~Q <2> , and connected to the control end of DAC_3; the output end of DAC_3 is used to output the comparison signal V out , and connect to the inverting input of Comp; V AI By S A Connect the in-phase input of Comp; the output of Comp is connected to the input of SAR-logic; the output of SAR-logic is connected to the input of Shift_Reg; the output of Shift_Reg is connected to the input of Decoder.

[0040] In terms of working method:

[0041] 1. The high 3-bit quantization uses successive approximation control logic and will perform three successive approximation comparisons.

[0042] Specifically: At high 3-bit quantization, S A , S B On, DAC_3 is based on Q <0> ~Q <2> , and combined with V ref To adjust V out , Comp to V AI and V out Perform three successive approximation comparisons.

[0043] Among them, the result of the Pth comparison of Comp is processed by SAR-logic and Shift_Reg in turn to obtain the Pth high 3-bit code, and the Qth high 3-bit code is decoded by Decoder to control V_Choose to adjust V ref To adjust the V used for the Q+1th comparison out ; P∈[1,3], Q∈[0,2].

[0044] The 0th high 3-bit code is the initial value, and the 3rd high 3-bit code is the high 3-bit quantization result D[2:0].

[0045] 2. Low 3-bit quantization uses a random quantization method and will perform 8 random comparisons.

[0046] Specifically, at low 3-bit quantization, S A On, S BDisconnect, DAC_3 according to Q <0> ~Q <2> To adjust V out , Comp to V AI and V out Perform 8 random comparisons and output the 8-bit probability bit stream corresponding to the lower 3-bit code D[5:3].

[0047] For each comparison, Comp will output a result of 1 or 0; then, the results of 8 comparisons constitute an 8-bit code stream and serve as an 8-bit probability bit stream corresponding to the lower 3-bit code D[5:3].

[0048] Specifically, each part of the hybrid ADC circuit is introduced one by one:

[0049] ① V_Choose is intended to provide the V required for high 3-bit quantization ref .

[0050] See also Figure 3 , V_Choose can be designed to include: 8 transmission gates G <0> ~G <7> .

[0051] G <n>The control terminal is connected to the control signal SW <n>, the input terminal is connected to the analog voltage VREF <n>, the output terminal is connected to V ref ; n∈[0,7].

[0052] Among them, VREF <n>=(n+1)*VDD / 8; VDD represents the power supply voltage.

[0053] Specifically, SW <n>When G is 1, <n>On, VREF <n>With V ref Connectivity; SW <n>When G is 0, <n>Disconnect, VREF <n>With V ref Not connected.

[0054] That is, the input of V_Choose is 8 equally spaced analog voltages - 8 equally spaced analog voltages divide VDD into 8 first-level intervals (including: [0, VREF <0> ]、[VREF <0> ,VREF <1> ]、[VREF <1> ,VREF <2> ]、[VREF <2> ,VREF <3> ]、[VREF <3> ,VREF <4> ]、[VREF <4> ,VREF <5> ]、[VREF <5> ,VREF <6> ]、[VREF <6> ,VREF <7> ]), the difference voltage of each level interval is fixed at VDD / 8, and the 8 level intervals correspond to the upper 3 bits; the output of V_Choose is V ref .

[0055] It should be noted that in each comparison cycle of the high 3-bit quantization: only one transmission gate is turned on, while the other seven transmission gates are turned off; thus, the analog voltage corresponding to the turned-on transmission gate is used as V ref .

[0056] Of course, V_Choose can also adopt other designs, but they should meet the above requirements.

[0057] ② DAC_3 is designed to provide adjustable V out .

[0058] See also Figure 4 DAC_3 can be designed to include: 4 groups of capacitor arrays C 0 ~C 3 , 3 switch S 1 ~S 3 .

[0059] C 0 , C 1 , C 2 , C 3 The capacitance values ​​are 1C, 1C, 2C, and 4C respectively; where C represents the unit capacitance. 0 , C 1 , C 2 , C 3 A single capacitor can be used, or multiple capacitors of equal value can be connected in parallel.

[0060] C 0 ~C 3 Connect one end of V out , and through S B Connect V ref ;

[0061] C 0 The other end of C is grounded; m The other end is connected to S m The moving end; S m The fixed end of the 0 , the fixed end is grounded; m∈[1,3]; where V 0 =VDD / 8; VDD represents the power supply voltage.

[0062] S 1 Q <0> Control to switch; S 2 Q <1> Control switch; S 3 Q <2> Control switching.

[0063] Specifically, Q <0> When S is 0, 1 Switch to C 1 Ground; Q <0> When S is 1, 1 Switch to C 1 Connect V 0 ;Q <1> When S is 0, 2 Switch to C 2 Ground; Q <1> When S is 1, 2 Switch to C 2 Connect V 0 ;Q <2> When S is 0, 3 Switch to C 3 Ground; Q <2> When S is 1, 3 Switch to C 3 Connect V 0 .

[0064] It should be noted that at high 3-bit quantization, S B On, Q <0> , Q <1> , Q <2> 000, V ref With C 0 , C 1 , C 2 , C 3 The voltage on the upper plate is superimposed to form V out ;

[0065] At low 3-bit quantization, S B Disconnect, Q <0> , Q <1> , Q <2> Switch to any state except 000 (including: 001, 010, 100, 011, 110, 101, 111), V 0 The capacitor is charged from the lower plate to form V on the upper plate of the capacitor. out . So C 0 ~C 3 The charge and discharge is done by the traditional C*VDD 2 becomes C*V 0 2 ; Due to V 0 VDD / 8 greatly reduces the power consumption of the capacitor array during the quantization process.

[0066] Of course, DAC_3 may also adopt other designs, but it should meet the above requirements.

[0067] ③ Random aims to provide 3 random number signals Q <0> ~Q <2> .

[0068] See also Figure 5 , Random can be designed to include: 3 D flip-flops D8~D10, 1 XOR gate XOR0, 3 AND gates AND 0 ~AND 2 .

[0069] The clock input end of D8~D10 is connected to the clock signal CP; the set end of D8, the clear end of D9, and the clear end of D10 are connected to the control signal SDN; the data output end of D8 is connected to the data input end of D9 and is set to node q <0> ; The data output terminal of D9 is connected to the data input terminal of D10 and is set as node q <1> ; The data output terminal of D10 is set to node q <2> ;

[0070] The first input terminal of XOR0 is connected to q <1> , the second input terminal is connected to q <2> , the output end is used to output the judgment signal FeedBack; the data input end of D8 is connected to FeedBack;

[0071] AND x The first input terminal is connected to q <x>The second input terminal is connected to SDN, and the output terminal is used to output a random number signal Q <x>; x∈[0,2].

[0072] See ②, when quantizing at high 3 bits, Q <0> , Q <1> , Q <2> Keep 000;

[0073] At low 3-bit quantization, Q <0> , Q <1> , Q <2> Switch to any state except 000 (including: 001, 010, 100, 011, 110, 101, 111): Random is controlled by SDN and randomly generates a group of 3-bit binary codes (i.e., any group of 001, 010, 100, 011, 110, 101, 111) in each comparison cycle of the lower 3-bit quantization.

[0074] Of course, Random can also adopt other designs, but it should meet the above requirements.

[0075] ④ Comp aims to AI and V out Comparison: When the quantization is high 3 bits, the comparison result of Comp will be processed by the subsequent SAR-logic and Shift_Reg; when the quantization is low 3 bits, the comparison result of Comp will form an 8-bit code stream.

[0076] Considering the power consumption, Comp first uses a two-stage dynamic pre-amplifier circuit to AI 、V out The difference is pre-amplified; and the output of the dynamic pre-amplification circuit part is accelerated and latched through the latch circuit part based on positive feedback design.

[0077] That is to say, Comp can be designed to include: a dynamic pre-amplifier circuit section, a latch circuit section, and a control circuit section. The dynamic pre-amplifier circuit section is used for V AI 、V out The difference is pre-amplified in two stages; the latch circuit part is used to accelerate the latching of the output of the dynamic pre-amplification circuit part based on positive feedback; the control circuit part is used to regulate the dynamic pre-amplification circuit part and the latch circuit part to achieve normal operation.

[0078] See also Figure 6 , the various parts of Comp can be specifically designed as:

[0079] 401. The dynamic pre-amplification circuit includes: a first-stage pre-amplification circuit and a second-stage pre-amplification circuit.

[0080] The first-stage pre-amplification circuit includes: 4 PMOS tubes M0~M3, 4 NMOS tubes M4~M7; the source ends of M0 and M1 are connected to VDD; the gate ends of M0 and M1 are connected to the clock signal CLK; the drain end of M0 is connected to the source end of M2 and is set to the node VX; the drain end of M1 is connected to the source end of M3 and is set to the node VY; the gate ends of M2 and M3 are grounded; the drain end of M2 is connected to the drain end of M4; the drain end of M3 is connected to the drain end of M5; the gate end of M4 is connected to the voltage signal VIP; the gate end of M5 is connected to the voltage signal VIN; the source end of M4 and the source end of M5 are connected to the drain end of M6; the gate end of M6 is connected to VDD; the source end of M6 is connected to the drain end of M7; the gate end of M7 is connected to CLK; the source end of M7 is grounded;

[0081] The secondary pre-amplification circuit includes: 4 PMOS tubes M8~M11, 4 NMOS tubes M12~M15; the source end of M8 is connected to VDD, the gate end is connected to the clock signal CLK_BAR, and the drain end is connected to the source end of M9; the gate end of M9 is grounded, and the drain end is connected to the source end of M10 and the source end of M11; the gate end of M10 is connected to VIN; the gate end of M11 is connected to VIP; the drain end of M10 is connected to the drain end of M13, the gate end of M12, and the gate end of M13; the drain end of M11 is connected to the drain end of M14, the gate end of M14, and the gate end of M15; the drain end of M12 is connected to VX; the drain end of M15 is connected to VY; the source ends of M12, M13, M14, and M15 are grounded.

[0082] Since the dynamic pre-amplifier circuit uses a differential input, it can be designed as follows: VIN is V AI VIP is V out ; It can also be designed as: VIN is V out VIP is V AI .

[0083] It should be noted that normally-on transistors (i.e., M2, M3, M6, M9) are added between the output end (i.e., VX, VY) of the dynamic pre-amplifier circuit and the differential input pair tubes (i.e., M4, M5, M10, M11), and between the tail current source (M7, M8) and the differential input pair tubes (M4, M5, M10, M11). This can cut off the loop from the output end (i.e., VX, VY) to the input end (i.e., VIP, VIN) to suppress the kickback noise.

[0084] 402. The latch circuit unit includes: 3 PMOS tubes M16~M18, and 4 NMOS tubes M19~M22; the source terminal of M16 is connected to VDD, the gate terminal is connected to CLK_BAR, and the drain terminal is connected to the source terminal of M17 and the source terminal of M18; the drain terminal of M17 is connected to the drain terminal of M19, the drain terminal of M20, and the gate terminal of M21, and is set to the node VON; the drain terminal of M18 is connected to the gate terminal of M20, the drain terminal of M21, and the drain terminal of M22, and is set to the node VOP; the gate terminal of M17 is connected to VOP; the gate terminal of M18 is connected to VON; the gate terminal of M19 is connected to VX; the gate terminal of M20 is connected to VOP; the gate terminal of M21 is connected to VON; the gate terminal of M22 is connected to VY; the source terminals of M19, M20, M21, and M22 are grounded.

[0085] 403. The control circuit unit includes: 3 inverters INV0~INV2; the input end of INV0 is connected to CLK, and the output end is used to output CLK_BAR; the input end of INV1 is connected to VON, and the output end is used to output the control signal VOUTP; the input end of INV2 is connected to VOP, and the output end is used to output the control signal VOUTN.

[0086] Comp includes two working phases, one is the reset phase and the other is the comparison phase: when in the reset phase, VOUTN and VOUTP are both low levels; when in the comparison phase, due to the different charging speeds of different circuit power supplies of VIP and VIN to VX and VY, M19 and M22 open at different speeds, which will make one of VON and VOP reach a high level faster, and then through the positive feedback of the latch circuit part, the other of VON and VOP will be a low level - then when VOUTN and VOUTP are high-low levels or low-high levels respectively, the comparison phase ends.

[0087] In general, Comp uses differential input to effectively suppress common-mode noise and even-order distortion. Comp does not have any external bias voltage and has a simple structure. By introducing a complementary differential pair structure, the dynamic input voltage range of the circuit is increased to meet the needs of the quantization range:

[0088] When the common-mode level of VIN and VIP (i.e., VIN / 2+VIP / 2) is high (i.e., exceeds the threshold voltage of the NMOS tube), the comparison can be completed only by dynamic pre-amplification of the NMOS tube input;

[0089] When the common-mode voltage of VIN and VIP (i.e., VIN / 2+VIP / 2) is low (i.e., does not exceed the threshold voltage of the NMOS tube), the PMOS tube differential input is used for dynamic pre-amplification to achieve comparison.

[0090] Of course, Comp may also adopt other designs, but they should meet the above requirements.

[0091] ⑤ SAR-logic works at high 3-bit quantization and does not work at low 3-bit quantization.

[0092] See also Figure 7 , SAR-logic can be designed to include: 4 D flip-flops D0~D3 and 1 XOR gate XOR1.

[0093] The first input terminal of XOR1 is connected to VOUTP, the second input terminal is connected to VOUTN, and the output terminal is used to output the clock signal CLK_LATCH;

[0094] The clock inputs of D0, D1, D2, and D3 are connected to CLK_LATCH;

[0095] The set end of D0 is connected to the reset signal RST; the clear ends of D1, D2, and D3 are connected to RST;

[0096] The data input terminal of D0 is grounded;

[0097] The data output terminal of D0 is connected to the data input terminal of D1 and is used to output a control signal V1;

[0098] The data output terminal of D1 is connected to the data input terminal of D2 and is used to output a control signal V2;

[0099] The data output terminal of D2 is connected to the data input terminal of D3 and is used to output a control signal V3;

[0100] The data output terminal of D3 is used to output an end signal EOC.

[0101] Among them, when RST arrives, the output end of D0 is set to 1, and the output ends of D1, D2, and D3 are set to 0; when the rising edge of CLK_LATCH arrives, D0 accepts 0 at the data input end and changes V1 from 1 to 0; V1 passes through D1, D2, and D3 in turn to form V2, V3, and EOC in turn; when EOC is a high level, it means that the high 3-bit quantization is completed.

[0102] Specifically, for the three comparisons of the upper 3 bits quantization, the states of V1, V2, and V3 generated by SAR-logic change from 100→010→001, corresponding to assigning 1 to the highest bit, the second highest bit, and the lowest bit of the upper 3 bits, respectively, to represent the bits being compared.

[0103] Of course, SAR-logic can also adopt other designs, but it should meet the above requirements.

[0104] ⑥ Shift_Reg works at high 3-bit quantization and does not work at low 3-bit quantization.

[0105] See also Figure 8 , Shift_Reg can be designed to include: 4 D flip-flops D4~D7.

[0106] The set terminal of D4 is connected to V1; the set terminal of D5 is connected to V2; the set terminal of D6 is connected to V3; the set terminal S of D7 is connected to EOC;

[0107] The data input terminals of D4, D5, and D6 are connected to VOUTP;

[0108] The data output terminal of D4 is used to output the highest bit D in the high 3-bit code <2> ;

[0109] The data output terminal of D5 is used to output the middle bit D in the high 3-bit code. <1> ;

[0110] The data output terminal of D6 is used to output the lowest bit D in the high 3-bit code <0> .

[0111] Among them, when RST comes, the output terminals of D4, D5, D6, and D7 are all set to 0; when the high 3-bit is quantized, the VOUTP output by Comp in each comparison cycle is used as the comparison result and input into the data input terminals of D4~D6; when V1~V3 and EOC come, the corresponding position will be set to 1, and at the same time, it is determined whether the current bit 1 is retained based on VOUTP.

[0112] That is to say, each time Shift_Reg outputs D <0> , D <1> , D <2> It represents the result of the current comparison cycle.

[0113] Of course, Shift_Reg may also adopt other designs, but it should meet the above requirements.

[0114] ⑦ The decoder works in the first two comparison cycles of high 3-bit quantization, does not work in the third comparison cycle of high 3-bit quantization, and does not work in low 3-bit quantization.

[0115] See also Fig. 9 , the decoder can be designed to include: 7 inverters INV3~INV9, 8 NAND gates 0 ~NAND7.

[0116] The input end of INV3 is connected to the enable signal EN, and the output end is used to output the inverted signal EN_bar;

[0117] The input terminal of INV4 is connected to D <0> The output end is connected to the input end of INV5 and set to node D_bar <0> ; The input of INV5 is connected to D_bar <0> , the output end is used to output the delay signal D_delay <0> ;

[0118] The input terminal of INV6 is connected to D <1> The output end is connected to the input end of INV7 and set to node D_bar <1> ; The input of INV7 is connected to D_bar <1> , the output end is used to output the delay signal D_delay <1> ;

[0119] The input terminal of INV8 is connected to D <2> The output end is connected to the input end of INV9 and set to node D_bar <2> ; The input of INV9 is connected to D_bar <2> , the output end is used to output the delay signal D_delay <2> ;

[0120] NAND 0 ~NAND 7 The fourth input terminal of is connected to EN_bar;

[0121] NAND 0 、NAND 2 、NAND 4 、NAND 6 The first input terminal is connected to D_bar <0> ;

[0122] NAND 1 、NAND 3 、NAND 5 、NAND 7 The first input terminal is connected to D_delay <0> ;

[0123] NAND 0 、NAND 1 、NAND 4 、NAND 5 The second input terminal is connected to D_bar <1> ;

[0124] NAND 2 、NAND 3 、NAND 6 、NAND 7 The second input terminal is connected to D_delay <1> ;

[0125] NAND 0 、NAND 1 、NAND 2 、NAND 3 The third input terminal is connected to D_bar <2> ;

[0126] NAND 4 、NAND 5 、NAND 6 、NAND 7 The third input terminal is connected to D_delay <2> ;

[0127] NAND n The output terminal is used to output the control signal SW <n>; n∈[0,7].

[0128] It should be noted that:

[0129] At the initial moment of high 3-bit quantization, D <0> , D <1> , D <2> Initialized to 100, the Decoder converts D <0> , D <1> , D <2> Decode into one-hot code and pass it through SW <0> ~SW <7> (SW only <4> is 1, other signals are 0) to control V-Choose;

[0130] Then the first comparison of the high 3-bit quantization is performed: D after the first comparison <0> , D <1> , D <2> has changed; the Decoder converts D <0> , D <1> , D <2> Decode into one-hot code and pass it through SW <0> ~SW <7> Control of V-Choose;

[0131] Then the second comparison of the high 3-bit quantization is performed: D after the second comparison <0> , D <1> , D <2> has changed; the Decoder converts D <0> , D <1> , D <2> Decoded into a one-hot code and passed through SW <0> ~SW <7> Control of V-Choose;

[0132] Finally, the third comparison of high 3-bit quantization is performed: D after the third comparison <0> , D <1> , D <2> A change has occurred. At this time, D <0> , D <1> , D <2> The composed D[2:0] is used as the high 3-bit quantization result.

[0133] Of course, the decoder can also adopt other designs, but it should meet the above requirements.

[0134] In other words, the above process is:

[0135] In the initial state, the output D of Shift_Reg <0> , D <1> , D <2> is 100, and the Decoder completes the decoding based on 100 to control V-Choose to generate the appropriate V ref , and then make the first comparison;

[0136] After the first comparison, SAR-logic determines based on the comparison result whether to keep the highest bit 1 and set the second highest bit 1. If it is to be kept, then the output D of Shift_Reg <0> , D <1> , D <2> becomes 110, and the Decoder completes the decoding based on 110 to control V-Choose to generate the appropriate V ref , and then make a second comparison; if you do not want to keep it, then the output D of Shift_Reg <0> , D <1> , D <2> Keep it as 100, the Decoder completes the decoding based on 100 to control V-Choose to generate the appropriate V ref , and then the second comparison is performed. And so on, when the third comparison is completed, the output D of Shift_Reg is <0> , D <1> , D <2> It is the high 3-bit quantization result.

[0137] In summary, see Fig.10 :

[0138] The hybrid ADC circuit adopts successive approximation control logic when performing high 3-bit quantization: for high 3-bit quantization, the voltage at the inverting input of Comp in the first comparison cycle is VDD / 2, the voltage in the second comparison cycle is VDD / 2±VDD / 4, and the voltage in the third comparison cycle is VDD / 2±VDD / 4±VDD / 8; then, after three comparisons of high 3-bit quantization, the voltage to be quantized falls within a certain range - the voltage difference across Comp (that is, the voltage difference between the non-inverting input and the inverting input) is reduced to VDD / 8 (that is, within 8LSB, LSB represents the least significant bit).

[0139] Since the high 3-bit quantization reuses V ref Quantization is performed to avoid the situation where the CDAC part (that is, DAC_3) is too large, which causes the area of ​​the entire hybrid ADC circuit to be too large (the area of ​​DAC_3 is only 14% of the entire hybrid ADC circuit).

[0140] The hybrid ADC circuit uses random quantization for the low 3 bits: for the low 3 bits, Random controls DAC_3 to randomly select a voltage, and generates 8 low 3 bits of binary codes randomly within 8 comparison cycles, such as 010-110-101-…-111; then the low 3 bits of binary codes are converted into the corresponding V by DAC_3. out , in order to complete the comparison and quantization of the residual voltage through Comp. Since the lower 3-bit binary code is random, the result of its quantization is a string of code streams - which contains K 1s and (8-K) 0s. The proportion of the number of 1s in this code stream to the total is the ratio of the voltage difference between the two ends of Comp to 8LSB, which can also be understood as the corresponding probability, and then corresponds to a specific voltage. Since the code stream follows the calculation principle of the random domain, the original mathematical operations in the binary system are converted into mathematical operations in the random domain - the circuit overhead required for mathematical operations in the random domain is much smaller than that of mathematical operations in the binary domain, which can reduce the area overhead and power consumption of the peripheral shift accumulation circuit.

[0141] To understand the above process, please refer to Fig.11 ——It shows V AI In [VREF <5> ,VREF <6> ]The corresponding partial signal timing diagram.

[0142] Simulation Verification

[0143] In order to illustrate the effect of the hybrid ADC circuit, the above hybrid ADC circuit is simulated, and the results are as follows:

[0144] 1. V AI is a single-frequency sinusoidal signal with a frequency of 537.1KHz and a sampling rate of 50MHz. After being processed by the above hybrid ADC circuit, the spectrum of the quantized result is as follows Fig.12 As shown: the effective number of bits (ENOB) is 5.97 (bits), the signal-to-noise-distortion ratio (SNDR) is 37.7 (dB), the spurious-free dynamic range (SFDR) is 51.84 (dB), and the total harmonic distortion (THD) is -50.46 (dB), all of which have achieved excellent results.

[0145] 2. The commonly used ADC structures in existing in-memory computing circuits (including: SS ADC, SAR ADC, Flash ADC) are introduced and compared with the above hybrid ADC circuits. The area and energy consumption per bit conversion (fJ / Conv) are investigated. The results are as follows: Fig.13 shown.

[0146] It can be seen that the power consumption of the hybrid ADC circuit designed in this paper is the smallest and the area is also relatively small (although it is slightly larger than the SS ADC, the power consumption is much smaller than the SS ADC). It is the design that achieves the best balance between area and power consumption among the four ADCs.

[0147] 3. The traditional storage-calculation ADC only focuses on the optimization of the quantization process, while the above hybrid ADC circuit takes into account the optimization of the peripheral shift-accumulation circuit: Since the low 3-bit quantization generates an 8-bit code stream, the subsequent peripheral shift-accumulation circuit (generally using an adder) can be designed based on the random calculation circuit, using fewer devices to achieve the same function: the area of ​​the peripheral shift-accumulation circuit can be reduced from 315μm 2 Down to 180μm 2 , a decrease of nearly half.

[0148] Example 2

[0149] This embodiment 2 discloses a hybrid ADC module for charge domain SRAM in-memory calculation, which adopts the layout of a hybrid ADC circuit for charge domain SRAM in-memory calculation disclosed in embodiment 1. The mode of packaging into a module makes it easier to promote and apply the above circuit.

[0150] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0151] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.< / n> < / x> < / x> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A hybrid ADC circuit for charge domain SRAM in-memory calculation, which is used to calculate the analog signal V AI Firstly, high 3-bit quantization is performed, and then low 3-bit quantization is performed, wherein: It includes: reference voltage selector V_Choose, digital-to-analog converter DAC_3, dynamic comparator Comp, shift register Shift_Reg, decoder Decoder, successive approximation control logic SAR-logic, random number generator Random, 2 input switches S A ~S B ; The control end of V_Choose is connected to the output end of the Decoder, and the output end is used to output the reference voltage V ref , and through S B Connect to the input of DAC_3; the output of Random is used to output 3 random number signals Q <0> ~Q <2> , and connected to the control end of DAC_3; the output end of DAC_3 is used to output the comparison signal V out , and connected to the inverting input of Comp; V AI By S A Connect to the in-phase input of Comp; the output of Comp is connected to the input of SAR-logic; the output of SAR-logic is connected to the input of Shift_Reg; the output of Shift_Reg is connected to the input of Decoder; At high 3-bit quantization, S A , S B On, DAC_3 is based on Q <0> ~Q <2> , and combined with V ref To adjust V out , Comp to V AI and V out Perform three successive approximation comparisons; the result of the Pth comparison of Comp is processed by SAR-logic and Shift_Reg in turn to obtain the Pth high 3-bit code, and the Qth high 3-bit code is decoded by Decoder to control V_Choose to adjust V ref To adjust the V used for the Q+1th comparison out ; P∈[1,3], Q∈[0,2]; The high 3 bits of the 0th code are the initial value, and the high 3 bits of the 3rd code are the high 3 bits of the quantization result D[2:0]; At low 3-bit quantization, S A On, S B Disconnect, DAC_3 according to Q <0> ~Q <2> To adjust V out , Comp to V AI and V out Perform 8 random comparisons and output the 8-bit probability bit stream corresponding to the lower 3-bit code D[5:3].

2. A hybrid ADC circuit for charge domain SRAM in-memory calculation according to claim 1, characterized in that: V_Choose includes: 8 transmission gates G <0> ~G <7> ; G <n>The control terminal is connected to the control signal SW <n>, the input terminal is connected to the analog voltage VREF <n>, the output terminal is connected to V ref ; n∈[0,7];< / n> < / n> < / n> Among them, VREF <n> =(n+1)*VDD / 8; VDD represents the power supply voltage.< / n> 3. A hybrid ADC circuit for charge domain SRAM in-memory calculation according to claim 1, characterized in that: DAC_3 includes: 4 groups of capacitor arrays C0~C3, 3 switching switches S1~S3; The capacitance values ​​of C0, C1, C2, and C3 are 1C, 1C, 2C, and 4C respectively; where C represents the unit capacitance; One end of C0~C3 is connected to V out , and through S B Connect V ref ; The other end of C0 is grounded; m The other end is connected to S m The moving end; S m The fixed end 1 is connected to the reference voltage V0, and the fixed end 2 is grounded; m∈[1,3]; wherein V0=VDD / 8; VDD represents the power supply voltage; S1 is affected by Q <0> Control to switch; S2 is controlled by Q <1> Control switch; S3 is controlled by Q <2> Control switching; At high 3-bit quantization, Q <0> , Q <1> , Q <2> Keep 000; when quantizing at low 3 bits, Q <0> , Q <1> , Q <2> Switch to any state except 000.

4. The hybrid ADC circuit for charge domain SRAM in-memory computing according to claim 1, characterized in that: Random includes: 3 D flip-flops D8~D10, 1 XOR gate XOR0, 3 AND gates AND0~AND2; The clock input end of D8~D10 is connected to the clock signal CP; the set end of D8, the clear end of D9, and the clear end of D10 are connected to the control signal SDN; the data output end of D8 is connected to the data input end of D9 and is set to node q <0> ; The data output terminal of D9 is connected to the data input terminal of D10 and is set as node q <1> ; The data output terminal of D10 is set to node q <2> ; The first input terminal of XOR0 is connected to q <1> , the second input terminal is connected to q <2> , the output end is used to output the judgment signal FeedBack; the data input end of D8 is connected to FeedBack; AND x The first input terminal is connected to q <x>The second input terminal is connected to SDN, and the output terminal is used to output a random number signal Q <x> ；x∈[0,2]。< / x> < / x> 5. The hybrid ADC circuit for charge domain SRAM in-memory calculation according to claim 1, characterized in that: Comp includes: dynamic pre-amplification circuit part, latch circuit part, control circuit part; Dynamic pre-amplification circuit for V AI 、V out The difference is pre-amplified in two stages; The latch circuit unit is used to accelerate the latching of the output of the dynamic pre-amplification circuit unit based on positive feedback; The control circuit part is used to regulate the dynamic pre-amplification circuit part and the latch circuit part to achieve normal operation.

6. A hybrid ADC circuit for charge domain SRAM in-memory computing according to claim 5, characterized in that: The dynamic pre-amplification circuit includes: a primary pre-amplification circuit and a secondary pre-amplification circuit; The first-stage pre-amplification circuit includes: 4 PMOS tubes M0~M3, 4 NMOS tubes M4~M7; the source ends of M0 and M1 are connected to VDD; the gate ends of M0 and M1 are connected to the clock signal CLK; the drain end of M0 is connected to the source end of M2 and is set to the node VX; the drain end of M1 is connected to the source end of M3 and is set to the node VY; the gate ends of M2 and M3 are grounded; the drain end of M2 is connected to the drain end of M4; the drain end of M3 is connected to the drain end of M5; the gate end of M4 is connected to the voltage signal VIP; the gate end of M5 is connected to the voltage signal VIN; the source end of M4 and the source end of M5 are connected to the drain end of M6; the gate end of M6 is connected to VDD; the source end of M6 is connected to the drain end of M7; the gate end of M7 is connected to CLK; the source end of M7 is grounded; The secondary pre-amplification circuit includes: 4 PMOS tubes M8~M11, 4 NMOS tubes M12~M15; the source end of M8 is connected to VDD, the gate end is connected to the clock signal CLK_BAR, and the drain end is connected to the source end of M9; the gate end of M9 is grounded, and the drain end is connected to the source end of M10 and the source end of M11; the gate end of M10 is connected to VIN; the gate end of M11 is connected to VIP; the drain end of M10 is connected to the drain end of M13, the gate end of M12, and the gate end of M13; the drain end of M11 is connected to the drain end of M14, the gate end of M14, and the gate end of M15; the drain end of M12 is connected to VX; the drain end of M15 is connected to VY; the source ends of M12, M13, M14, and M15 are grounded; Where VIN is V AI VIP is V out ; or, VIN is V out VIP is V AI ; The latch circuit section includes: 3 PMOS tubes M16~M18, 4 NMOS tubes M19~M22; the source end of M16 is connected to VDD, the gate end is connected to CLK_BAR, and the drain end is connected to the source of M17 and the source end of M18; the drain end of M17 is connected to the drain end of M19, the drain end of M20, and the gate end of M21, and is set to the node VON; the drain end of M18 is connected to the gate end of M20, the drain end of M21, and the drain end of M22, and is set to the node VOP; the gate end of M17 is connected to VOP; the gate end of M18 is connected to VON; the gate end of M19 is connected to VX; the gate end of M20 is connected to VOP; the gate end of M21 is connected to VON; the gate end of M22 is connected to VY; the source ends of M19, M20, M21, and M22 are grounded; The control circuit section includes: 3 inverters INV0~INV2; the input end of INV0 is connected to CLK, and the output end is used to output CLK_BAR; the input end of INV1 is connected to VON, and the output end is used to output the control signal VOUTP; the input end of INV2 is connected to VOP, and the output end is used to output the control signal VOUTN.

7. A hybrid ADC circuit for charge domain SRAM in-memory computing according to claim 6, characterized in that: SAR-logic includes: 4 D flip-flops D0~D3, 1 XOR gate XOR1; The first input terminal of XOR1 is connected to VOUTP, the second input terminal is connected to VOUTN, and the output terminal is used to output the clock signal CLK_LATCH; The clock inputs of D0, D1, D2, and D3 are connected to CLK_LATCH; The set end of D0 is connected to the reset signal RST; the clear ends of D1, D2, and D3 are connected to RST; The data input terminal of D0 is grounded; The data output terminal of D0 is connected to the data input terminal of D1 and is used to output a control signal V1; The data output terminal of D1 is connected to the data input terminal of D2 and is used to output a control signal V2; The data output terminal of D2 is connected to the data input terminal of D3 and is used to output a control signal V3; The data output terminal of D3 is used to output an end signal EOC.

8. The hybrid ADC circuit for charge domain SRAM in-memory computing according to claim 7, characterized in that: Shift_Reg includes: 4 D flip-flops D4~D7; The set terminal of D4 is connected to V1; the set terminal of D5 is connected to V2; the set terminal of D6 is connected to V3; the set terminal S of D7 is connected to EOC; The data input terminals of D4, D5, and D6 are connected to VOUTP; The data output terminal of D4 is used to output the highest bit D in the high 3-bit code <2> ; The data output terminal of D5 is used to output the middle bit D in the high 3-bit code. <1> ; The data output terminal of D6 is used to output the lowest bit D in the high 3-bit code <0> ; The clock control terminal of D4 is connected to the data output terminal of D5; the clock control terminal of D5 is connected to the data output terminal of D6; the clock control terminal of D6 is connected to the data output terminal of D7; the input signal terminal and clock control terminal of D7 are grounded; the reset terminals of D4, D5, D6 and D7 are connected to RST.

9. The hybrid ADC circuit for charge domain SRAM in-memory computing according to claim 7, characterized in that: The decoder includes: 7 inverters INV3~INV9, 8 NAND gates NAND0~NAND7; The input end of INV3 is connected to the enable signal EN, and the output end is used to output the inverted signal EN_bar; The input terminal of INV4 is connected to D <0> The output end is connected to the input end of INV5 and set to node D_bar <0> ; The input of INV5 is connected to D_bar <0> , the output end is used to output the delay signal D_delay <0> ; The input terminal of INV6 is connected to D <1> The output end is connected to the input end of INV7 and set to node D_bar <1> ; The input of INV7 is connected to D_bar <1> , the output end is used to output the delay signal D_delay <1> ; The input terminal of INV8 is connected to D <2> The output end is connected to the input end of INV9 and set to node D_bar <2> ; The input of INV9 is connected to D_bar <2> , the output end is used to output the delay signal D_delay <2> ; The fourth input terminals of NAND0~NAND7 are all connected to EN_bar; The first input terminals of NAND0, NAND2, NAND4, and NAND6 are connected to D_bar <0> ; The first input terminals of NAND1, NAND3, NAND5, and NAND7 are connected to D_delay <0> ; The second input terminals of NAND0, NAND1, NAND4, and NAND5 are connected to D_bar <1> ; The second input terminals of NAND2, NAND3, NAND6, and NAND7 are connected to D_delay <1> ; The third input terminals of NAND0, NAND1, NAND2, and NAND3 are connected to D_bar <2> ; The third input terminals of NAND4, NAND5, NAND6, and NAND7 are connected to D_delay <2> ; NAND n The output terminal is used to output the control signal SW <n> ；n∈[0,7]。< / n> 10. A hybrid ADC module for charge domain SRAM in-memory computing, characterized in that: It adopts the layout of a hybrid ADC circuit for charge domain SRAM in-memory calculation as described in any one of claims 1-9.

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