A TSV test diagnosis circuit and method based on BIST

Abstract

The present invention belongs to the technical field of testability design of very large-scale integrated circuits, discloses a TSV test diagnosis circuit and method based on BIST, provides a hardware circuit architecture for TSV test and diagnosis, comprises a test access port controller, a test data register, a test vector generator, a shift register, a double edge trigger, a TSV test controller and an improved loading chip packaging register, a capture chip packaging register, wherein the test access port controller is responsible for configuring the test path, the test mode and the test enable signal, the test enable is synchronized by the double edge trigger and activates the TSV test controller, controls the chip packaging register improved based on the lossless compression structure to perform the test, and realizes efficient fault detection and diagnosis of different fault types. The present invention effectively reduces the test time through the collaboration of test vector generation and response compression, and provides an innovative solution for efficient and reliable TSV test and diagnosis.

Description

Technical Field

[0001] The invention belongs to the technical field of testability design of very large scale integrated circuits, and in particular relates to a TSV test diagnosis circuit and method based on BIST. Background Art

[0002] Chiplet technology integrates multiple small chips into one package through internal interconnection technology to form a dedicated functional chip, solving problems such as limited chip size, high development cost, and long manufacturing cycle. Through advanced packaging technologies such as 2.5D and 3D, Chiplet achieves high-performance on-chip interconnection, improves system integration and performance optimization space, and breaks through the physical and material limitations of existing IC development. Among them, 3D Chiplet uses an interconnection structure based on through silicon vias (TSV) to replace overly long global wiring, reduce transmission delays and power consumption, and improve system performance.

[0003] Built-in Self-Test (BIST) is a technology that embeds test circuits inside the chip. It can independently complete fault detection and diagnosis and is a key method in through-silicon via testing. The main advantages of BIST are to increase test speed, reduce test costs and support online testing, especially for complex three-dimensional integrated circuits. However, traditional TSV testing methods still have significant shortcomings, such as reliance on external test equipment, which increases costs, and some architectures require independent hardware for each TSV, resulting in excessive hardware overhead. In addition, existing test architectures also have limitations in diagnostic functions. They usually require loading a large number of test vectors and transferring test responses multiple times, resulting in long diagnostic time and inability to support diagnosis of different fault types. Summary of the invention

[0004] To solve the above technical problems, the present invention provides a TSV test diagnosis circuit and method based on BIST, which is based on the IEEE Std 1838 standard, and achieves the invention purpose of high diagnostic accuracy, low diagnostic time, and low hardware overhead by improving the function of the die wrapper register (DWR) and introducing a lossless compression circuit, thereby solving the problems of long test and diagnosis time and excessive hardware resources.

[0005] The TSV test diagnosis circuit based on BIST of the present invention comprises several layers of core particles, and adjacent core particles are connected through TSV; each layer of core particles comprises a test access port controller, a test data register, a double edge trigger, a shift register, a test vector generator, a loading chip packaging register, a capture chip packaging register and a TSV test controller.

[0006] Wherein, the test access port controller transmits a test data register enable signal and a test enable signal to the test data register, which are used to control the test data register and test start respectively;

[0007] The test data register stores the test signal and outputs the test start signal BistSel to achieve synchronous transmission across clock domains through double-edge triggers;

[0008] The double edge trigger transmits the synchronized signal to the TSV test controller;

[0009] The TSV test controller cooperates with the test vector generator and the shift register, and the TSV test controller controls the test vector generator to generate a test vector, loads the test vector into the loading chip package register, and receives the returned test response signal from the capture chip package register and performs analysis and processing;

[0010] The chip package loader register is responsible for the injection of test signals. The chip package loader register receives the test vector from the TSV test controller and applies it to the TSV.

[0011] Capture the response signal returned by the chip package register from the TSV and save the fault location information in the test mode;

[0012] The test vector generator is used to realize dynamic test vector generation; the shift register is used to switch different test iterations and output the test group signal Group_en[total-1:0], where the bit width total-1 is the total number of test iterations; only one of the test iterations is tested each time, numbered 0, 1, ..., total-1, when testing the test iteration numbered t, Group_en[t]=1, and the remaining bits are 0, where t=0, 1, ..., total-1.

[0013] Further, the TSV test diagnosis mode includes a master test mode TMASTER, a slave test mode TSLAVE, a master test diagnosis mode TDMASTER, and a slave test diagnosis mode TDSLAVE;

[0014] The test access port controller transmits the test data register enable signal and the test enable signal to the test data register, which are used to control the test data register and test start, respectively. That is, in the TSV test diagnosis mode, the test data register enable signal takes effect, the test data register is turned on, and the test enable signal is transmitted from the TPAC to the test data register through the TDI port, and the test is turned on; after the test is completed, the test data register transmits the test end signal to the test access port controller;

[0015] The test access port controller provides the master test mode synchronization signal TM, the slave test mode synchronization signal TS, the master test diagnostic mode synchronization signal TDM, and the slave test diagnostic mode synchronization signal TDS to the double-edge trigger; in the master test mode TMASTER, TM is 1, and the other synchronization signals are 0; in the slave test mode TSLAVE, TS is 1, and the other synchronization signals are 0; in the master test diagnostic mode TDMASTER, TDM is 1, and the other synchronization signals are 0; in the slave test diagnostic mode TDSLAVE, TDS is 1, and the other synchronization signals are 0.

[0016] Furthermore, the BistSel input of the double edge-triggered trigger is connected to the test data output of the test data register, and is connected to the D input of the first-stage D trigger in the double edge-triggered trigger, the Q output of the first-stage D trigger is connected to the D input of the second-stage D trigger, the Q output of the second-stage D trigger is connected to the data input of the three-state gate, and both stages of triggers are controlled by the fast clock func_clk; the two inputs of the or gate or1 are respectively connected to the TM and TDM signals from the test access port controller, and the output is connected to the control end of the three-state gate; the output end global signal of the three-state gate is synchronized to each chip through TSV; only the Only the BistSel signal of the chip selected as TMASTER or TDMASTER mode can be synchronized to other chiplets through TSV to ensure that the test is started synchronously; the global signal is connected to one of the input ends of AND gate and1 and AND gate and2; the two input ends of OR gate or2 are respectively connected to the TM signal and the TS signal, and the output end is connected to one of the input ends of AND gate and1; the two input ends of OR gate or3 are respectively connected to the TDM signal and the TDS signal, and the output end is connected to one of the input ends of AND gate and2; the output end TG of AND gate and1 and the output end TDG of AND gate and2 are both connected to the TSV test controller.

[0017] Furthermore, the loading chip packaging register is composed of an SC module, two multiplexers, and an OR gate, wherein the input ends of the OR gate or4 are respectively connected to the TDG signal and the TG signal from the double-edge trigger, and the output end is connected to the data selection end of the multiplexer mux4; the 0 input end of the multiplexer mux4 is connected to the test data input end CTI, the 1 input end is connected to the output test vector reference signal TP_bist of the test vector generator, and the output end is connected to the test input end SI of the SC; the 1 input end of the multiplexer mux5 is connected to the test data output end CTO of the SC, the 0 input end is connected to the CFI port, the selection end is connected to the control signal DWRL_sel, and the output end is connected to CFO; the function input port DI of the SC module is connected to CFO; all the loading chip packaging registers L of each layer of core particles are connected to each other through the first position of the CTI and CTO ports.

[0018] Furthermore, the capture chip packaging register Capture DWR is composed of two XOR gates, one OR gate, one AND gate, three multiplexers, and one SC module; wherein the input end of the XOR gate xor1 is respectively connected to the output TP_true and CFI signals from the test vector generator, and the output is connected to an input end of the OR gate or5; the other input end of the OR gate or5 is the test output data port CFO, and the output port of the OR gate or5 is connected to the 1 input end of the multiplexer mux1; the other input end of the multiplexer mux1 is the test data input port CTI, and the output end is connected to the 0 input end of the multiplexer mux2; the two input ends of the XOR gate xor2 are respectively the output end of the XOR gate xor1 and fx, and fx is the XOR value of the CTO signals of the following three SC modules on the current capture chip packaging register chain; the output end is connected to the 1 input end of the multiplexer mux2; the two input ends of the AND gate and3 are respectively TDG and the grouping signal Group_en[t], wherein Capture The TSV connected to DWR is tested in the test iteration numbered t, and the output of gate and3 is connected to the data selection end of multiplexer mux2; the output of multiplexer mux2 is connected to the test input SI of the SC module; the 1 input of multiplexer mux3 is connected to the test data output CTO of SC, the 0 input is connected to the CFI port, the selection end is connected to the control signal DWRC_sel, and the output end is connected to CFO; the functional input port DI of the SC module is connected to CFO, and the test data output end is CTO; all capture chip packaging registers are connected to each other through the first position of the CTI and CTO ports.

[0019] The present invention also discloses a TSV test and diagnosis method based on BIST, which is implemented based on the above test and diagnosis circuit and includes the following steps:

[0020] Step 1: Configure the test path and add the chips of the upper and lower layers of the TSV to be tested to the test path;

[0021] Step 2, select the test mode. If the test diagnosis mode is turned on, set any one of the chips to the master test diagnosis mode TDMASTER, and the other chips are set to the slave test diagnosis mode TDSLAVE; if the test mode is turned on, set any one of the chips to the master test mode TMASTER, and the other chips are set to the slave test mode TSLAVE;

[0022] Step 3: Test enable, the test start signal is transmitted from the TDI port, and the signal is synchronized to other chiplets through the chiplet set as TDMASTER or TMASTER to start the test synchronously;

[0023] Step 4, test / diagnosis, under the TSV test controller, the capture chip package register and the load chip package register are driven by the functional clock, the test vector generator generates a test vector, the load chip package register sends the test vector to the TSV, and the capture chip package register captures the test response from the TSV and determines whether there is a fault; if in TDMASTER or TDSLAVE mode, the test response is compressed into a 4-bit signal and stored in the capture chip package register to determine what type of fault exists; in TMASTER or TSLAVE mode, the capture chip package register connected to the faulty TSV stores a value of 1, otherwise it is 0;

[0024] Step 5, capture end signal, after the test or diagnosis is completed, the test data register captures the end signal, and the capture chip package register and the load chip package register are driven by the test clock;

[0025] Step 6: Shift out the test response, capture the value in the chip package register and shift it out serially to observe whether there is a fault;

[0026] Step 7: Determine whether the test is completed. If completed, end the entire process; otherwise, continue to shift the enable signal from the TDI port.

[0027] The beneficial effects of the present invention are:

[0028] (1) The present invention realizes a high degree of integration of test and diagnosis functions, and improves DWR. For the capture chip package register, a linear feedback shift register with serial input is introduced as a lossless compression structure, and the registers of four consecutive capture chip package registers are used as storage units of the linear feedback shift register. An OR gate is introduced to transform the capture chip package register chain into a linear feedback shift register chain for lossless compression; for the loading chip package register, a multiplexer is introduced to support chip TSV testing and diagnostic mode, and the test vector generated by the on-chip test vector generator is used to realize autonomous execution of test diagnosis operations without relying on test equipment, thereby reducing test overhead. The above improvements embed diagnosis into the test process, and can diagnose and locate various types of faults, supporting the detection and diagnosis of multiple fault types including short circuits, open circuits, delays, crosstalk, etc.;

[0029] (2) The architecture proposed in the present invention adopts a modular design. Each chip layer is independently equipped with a transmitter chip package register, a capture chip package register and related control modules, so that it can flexibly adapt to the test requirements of chiplet systems of different sizes. By following the IEEE 1838 standard, the architecture realizes the standardization and reuse of hardware resources, reduces the complexity of design and implementation, and enhances compatibility with external test equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the overall architecture of TSV testing and diagnosis according to an embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of the structure of a double-edge-triggered trigger according to an embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of the structure of the chip packaging register loaded in an embodiment of the present invention;

[0033] Figure 4 is a schematic diagram of the structure of the capture chip packaging register according to an embodiment of the present invention;

[0034] Figure 5 is a schematic diagram of the connection structure of the capture chip packaging register according to an embodiment of the present invention;

[0035] Figure 6 It is a state transition diagram of the state machine used by the TSV test controller;

[0036] Figure 7 is a flow chart of a TSV test and diagnosis method based on BIST according to an embodiment of the present invention;

[0037] Figure 8 It is a timing waveform diagram corresponding to the TSV grouping test process of an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments in conjunction with the accompanying drawings.

[0039] The overall structure of a TSV test and diagnosis circuit proposed by the present invention is as follows: Figure 1 As shown in the figure, the structure realizes efficient testing and accurate fault diagnosis of multi-layer stacked chips, and is developed around the generation, loading, capture, analysis and compression of test signals, and consists of multiple key modules. The single-layer core particle includes a test access port controller, a test data register, a double-edge triggered flip-flop, a TSV test controller, a test vector generator, a shift register, and two improved chip packaging registers: a loading chip packaging register and a capturing chip packaging register.

[0040] like Figure 1As shown in FIG. 1 , the test access port controller in the TSV test diagnosis circuit is located at the interface layer of the architecture and is responsible for communicating with external test equipment through a standard boundary scan interface. The test access port controller transmits external input test instructions and signals to internal modules. As a storage and transmission module for test signals, the test data register is directly connected to the test access port controller to manage the transmission of enable signals. The output signal of the test data register is synchronously transmitted across clock domains through a double-edge-triggered flip-flop. The double-edge-triggered flip-flop is used to ensure the stability of signal transmission in multi-layer chips. The double-edge-triggered flip-flop transmits the synchronized signal to the TSV test controller. The TSV test controller cooperates with the test vector generator and the shift register, receives the generated test vector from the test vector generator and loads it into the loading chip package register, and receives the returned test response signal from the capture chip package register and analyzes and processes it. The loading chip package register is responsible for injecting test signals. The loading chip package register receives the test vector from the TSV test controller and applies it to the TSV. The capture chip package register receives the returned response signal from the TSV, saves the fault location information in the test mode, and compresses the location and fault type information into a test signature using a linear feedback shift register in the diagnostic mode. The test vector generator and the shift register are used to realize dynamic test vector generation, including test vectors applied to the victim TSV and the attack TSV in the test mode and the diagnostic mode, and the shift register is used to switch different test iterations.

[0041] The double-edge trigger realizes the synchronous transmission of the test signal by the rising of the clock, ensuring the signal stability and reliability across clock domains and multi-layer chip stacking. Taking the chiplet system with three chiplets bound as an example, the specific structure is as follows Figure 2 shown.

[0042] like Figure 3 As shown, the chip package register is loaded to send the test vector to the target TSV through the signal path (red solid line); TP_bist connects the test vector generator, and CFO connects the adjacent core die through TSV.

[0043] like Figure 4 As shown, the capture chip package register is connected to other core grains through the CFI port. The xor1 capture value is compared with the correct value. If it is 0, it means there is no fault. Otherwise, there is a fault. The or gate is responsible for fixing the fault value to the capture chip package register without being disturbed by other test responses. xor2 uses fx to convert the capture chip package register into a linear feedback shift register. By multiplexing the capture chip package register, the hardware overhead is reduced. In the test mode, the signal captured from the TSV goes through the red line to save and remove the fault information. In the diagnostic mode, the or gate and mux1 are not used, and the green solid line path is used to achieve test compression.

[0044] like Figure 5 As shown in the figure, assuming that there are two chip packaging registers on the capture chip packaging register chain, the capture chip packaging registers of each layer of core particles need to be connected in series to form a capture chip packaging register chain. Each capture chip packaging register and the following three capture chip packaging registers form a 4-bit serial input linear feedback shift register to support lossless compression. Add three SC modules without fx evaluation at the end of the capture chip packaging register chain to avoid the situation where the fx ports of the last three SC modules cannot be connected.

[0045] In the diagnosis mode, the test vectors of 0010110 and 0101100 are applied to the victim TSV and the attack TSV respectively, and different faults will be compressed into different compression signatures, as shown in Table 1.

[0046] Table 1 Compressed signatures corresponding to different faults

[0047]

[0048] The test response of the victim TSV is observed. The test response of each fault is different. The linear feedback shift register in the capture chip package register is used for compression to obtain 4 different test signatures. Therefore, the fault type can be determined by the test signature.

[0049] The finite state machine state transition diagram used by the TSV test controller is as follows Figure 6As shown. Through six core states and clear state transition logic, test vector generation, response capture, iteration counting, state retention, and shift output are completed in sequence according to test and diagnosis requirements. The initial state of FSM is reset. In this state, the system completes the initialization reset, clears all register data and restores the default settings to prepare for the test process. When the system reset signal (Reset) is invalid and the test enable signal (TDG or TG) is valid, FSM transfers to the test execution state and starts to execute the test. In the test execution state, the system generates test vectors and loads them to the target TSV through the test path, while capturing the test response signal and performing real-time analysis. When the test is completed, the Sign_stop signal indicates whether to continue processing the next round of tests. If Sign_stop and TG are valid at the same time, the state machine transfers to the test iteration switching state; if Sign_stop is invalid, FSM will continue to stay in the test execution state and perform the next round of test operations. After entering the test iteration switching state, the system determines whether the current test iteration is completed. If the counting signal Count is valid, it indicates that there are still remaining test groups to be executed, and the FSM transfers back to the test execution state to perform the next set of tests; if the counting signal Count is invalid, it indicates that all test iterations have been completed, and the FSM transfers to the capture state. In the state state, the test data register captures the end signal and is ready to shift out the test results. After all test responses are captured, the FSM enters the waiting shift state, waiting for the shift operation of the test response signal to be completed. This stage is controlled by the Update_en signal. If Update_en is invalid, the FSM will continue to stay in this state until the shift is completed. When Update_en is valid, the FSM transfers to the test judgment state. In the test judgment state, the FSM determines the next operation based on the test mode and global state. If the test enable signal TDG is invalid, it indicates that the test process is over, the FSM transfers back to the reset state, and the system enters the reset phase; if the test enable signal TDG is valid, the system will re-enter the test execution state and start a new test cycle.

[0050] like Figure 7 As shown, a TSV test and diagnosis method based on BIST is implemented based on the above circuit. The TSV to be tested is the TSV between core 0 and core 1. The method includes the following steps:

[0051] Step 1: Configure the test path: Include the cores of the upper and lower layers of the TSV to be tested (core 0 and core 1) into the test path;

[0052] Step 2. Select the test mode: Turn on the diagnostic mode, set chip 0 to the test diagnostic mode (TDMASTER), and chip 1 to the test diagnostic mode (TDSLAVE);

[0053] Step 3, test enable: transmit the test start signal (2-bit high level) from the TDI port, and synchronize the test start signal of chip 0 to chip 1 to achieve synchronous start of the test;

[0054] Step 4, test / diagnosis: Under the control of the TSV test controller, the capture chip package register and the load chip package register are driven by the functional clock. The test vector generator generates the test vector, the load chip package register sends the test vector to the TSV, and the capture chip package register captures the test response returned from the TSV and detects whether there is a fault. At the same time, the test response is compressed into a 4-bit signal and stored in the capture chip package register to determine the fault type;

[0055] Step 5, capture end signal: after the test or diagnosis is completed, the test data register receives the end signal, and the capture chip package register and the load chip package register are switched to the test clock driving state;

[0056] Step 6: Shift out the test response: shift out the stored value in the capture chip package register in serial form to check whether there is a fault;

[0057] Step 7: Determine whether the test is completed: If the test iteration is completed, the test is terminated; otherwise, the enable signal continues to be transmitted from the TDI port and the process is repeated.

[0058] The state transition of the state machine and the changes of key signals in the TSV group test process are as follows: Figure 8As shown. After a test is removed, the state machine enters the test judgment (state 4) to determine whether the test process needs to be executed. At this time, the Count signal is set to 1 and the system starts testing; then, the state machine switches to the test iteration switch (state 5), updates the current test group number, and identifies the current test group by increasing the Count signal, and activates the corresponding Group_en signal. For example, Group_en=1 indicates that the second group is activated. At the same time, Pattern_group[2:0] is synchronously updated to the corresponding test vector number, and the test vector is loaded for the current group; in the test execution (state 1) stage, the state machine executes the actual T SV test operation, generate test vectors and capture test response signals; when the test of the current group is completed, the Sign_stop signal is set to 1, the state machine switches to state capture (state 2), the capture of the flag end signal is completed, and the capture_done signal is set to 1, indicating that the test data has been successfully captured. At this stage, the captured response signal is temporarily stored and waits for subsequent shift operations; then, the state machine enters the waiting shift (state 0), and the system waits for the shift signal Update_en to complete the shift out operation of the captured data; when the shift is completed, the state machine returns to the test judgment (state 4) to determine whether the next set of tests is required. If the Count signal does not reach the maximum value, it enters the next set of tests. At this time, Group_en and Pattern_group are updated to the new test group number. If all group tests are completed, the state machine ends the test process and returns to the initial state.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to be a further limitation of the present invention. All equivalent changes made using the contents of the present specification and drawings are within the protection scope of the present invention.

Claims

1. A TSV test and diagnosis circuit based on BIST, characterized in that: The circuit includes several layers of core particles, and adjacent core particles are connected through TSV; each layer of core particles includes a test access port controller, a test data register, a double-edge trigger, a shift register, a test vector generator, a load chip package register, a capture chip package register and a TSV test controller, Wherein, the test access port controller transmits a test data register enable signal and a test enable signal to the test data register, which are used to control the test data register and test start respectively; The test data register stores the test signal and outputs the test start signal BistSel to achieve synchronous transmission across clock domains through double-edge triggers; The double edge trigger transmits the synchronized signal to the TSV test controller; The TSV test controller cooperates with the test vector generator and the shift register, and the TSV test controller controls the test vector generator to generate a test vector, loads the test vector into the loading chip package register, and receives the returned test response signal from the capture chip package register and performs analysis and processing; The chip package loader register is responsible for the injection of test signals. The chip package loader register receives the test vector from the TSV test controller and applies it to the TSV. Capture the response signal returned by the chip package register from the TSV and save the fault location information in the test mode; The test vector generator is used to realize dynamic test vector generation; the shift register is used to switch different test iterations and output the test grouping signal Group_en[total-1:0], where the bit width total-1 is the total number of test iterations; The loading chip packaging register is composed of an SC module, two multiplexers, and an OR gate, wherein the input end of the OR gate or4 is respectively connected to the TDG signal and the TG signal from the double-edge trigger, and the output end is connected to the data selection end of the multiplexer mux4; the 0 input end of the multiplexer mux4 is connected to the test data input end CTI, the 1 input end is connected to the output test vector reference signal TP_bist of the test vector generator, and the output end is connected to the test input end SI of the SC; the 1 input end of the multiplexer mux5 is connected to the test data output end CTO of the SC, the 0 input end is connected to the CFI port, the selection end is connected to the control signal DWRL_sel, and the output end is connected to CFO; the function input port DI of the SC module is connected to CFO; all the loading chip packaging registers of each layer of core particles are connected through the first position of the CTI and CTO ports; The capture chip packaging register Capture DWR is composed of two XOR gates, an OR gate, an AND gate, three multiplexers, and an SC module; wherein the input end of the XOR gate xor1 is respectively connected to the output TP_true and CFI signals from the test vector generator, and the output is connected to an input end of the OR gate or5; the other input end of the OR gate or5 is the test output data port CFO, and the output port of the OR gate or5 is connected to the 1 input end of the multiplexer mux1; the other input end of the multiplexer mux1 is the test data input port CTI, and the output end is connected to the 0 input end of the multiplexer mux2; the two input ends of the XOR gate xor2 are respectively the output end of the XOR gate xor1 and fx, and fx is the XOR value of the CTO signals of the following three SC modules on the current core capture chip packaging register chain; the output end is connected to the 1 input end of the multiplexer mux2; the two input ends of the AND gate and3 are respectively TDG and the grouping signal Group_en[t], wherein Capture The TSV connected to DWR is tested in the test iteration numbered t, and the output of gate and3 is connected to the data selection end of multiplexer mux2; the output of multiplexer mux2 is connected to the test input SI of the SC module; the 1 input of multiplexer mux3 is connected to the test data output CTO of SC, the 0 input is connected to the CFI port, the selection end is connected to the control signal DWRC_sel, and the output end is connected to CFO; the functional input port DI of the SC module is connected to CFO, and the test data output end is CTO; all capture chip packaging registers are connected to each other through the first position of the CTI and CTO ports.

2. A TSV test and diagnosis circuit based on BIST according to claim 1, characterized in that: The TSV test diagnosis mode includes the master test mode TMASTER, the slave test mode TSLAVE, the master test diagnosis mode TDMASTER, and the slave test diagnosis mode TDSLAVE; The test access port controller transmits a test data register enable signal and a test enable signal to the test data register, which are used to control the test data register and test start, respectively. That is, in the TSV test diagnosis mode, the test data register enable signal takes effect, the test data register is turned on, and the test enable signal is transmitted from the test access port controller to the test data register through the TDI port, and the test is turned on; after the test is completed, the test data register transmits a test end signal to the test access port controller; The test access port controller provides the master test mode synchronization signal TM, the slave test mode synchronization signal TS, the master test diagnostic mode synchronization signal TDM, and the slave test diagnostic mode synchronization signal TDS to the double-edge trigger; in the master test mode TMASTER, TM is 1, and the other synchronization signals are 0; in the slave test mode TSLAVE, TS is 1, and the other synchronization signals are 0; in the master test diagnostic mode TDMASTER, TDM is 1, and the other synchronization signals are 0; in the slave test diagnostic mode TDSLAVE, TDS is 1, and the other synchronization signals are 0.

3. A TSV test and diagnosis circuit based on BIST according to claim 1, characterized in that: The BistSel input of the double edge-triggered trigger is connected to the test data output of the test data register, and is connected to the D input of the first-stage D trigger in the double edge-triggered trigger. The Q output of the first-stage D trigger is connected to the D input of the second-stage D trigger. The Q output of the second-stage D trigger is connected to the data input of the tri-state gate. Both stages of the trigger are controlled by the fast clock func_clk. The two inputs of the or gate or1 are respectively connected to the TM and TDM signals from the test access port controller, and the output is connected to the control end of the tri-state gate. The global signal at the output of the tri-state gate is synchronized to each chip through TSV. Only the chip selected as Only the BistSel signal of the chip in TMASTER or TDMASTER mode can be synchronized to other chiplets through TSV to ensure that the test is started synchronously; the global signal is connected to one of the input ends of AND gate and1 and AND gate and2; the two input ends of OR gate or2 are respectively connected to the TM signal and TS signal, and the output end is connected to one of the input ends of AND gate and1; the two input ends of OR gate or3 are respectively connected to the TDM signal and TDS signal, and the output end is connected to one of the input ends of AND gate and2; the output end TG of AND gate and1 and the output end TDG of AND gate and2 are both connected to the TSV test controller.

4. A TSV test and diagnosis method based on BIST, characterized in that: The test diagnosis circuit according to any one of claims 1 to 3 is implemented, comprising the following steps: Step 1: Configure the test path and add the chips of the upper and lower layers of the TSV to be tested to the test path; Step 2, select the test mode. If the test diagnosis mode is turned on, set any one of the chips to the master test diagnosis mode TDMASTER, and the other chips are set to the slave test diagnosis mode TDSLAVE; if the test mode is turned on, set any one of the chips to the master test mode TMASTER, and the other chips are set to the slave test mode TSLAVE; Step 3: Test enable, the test start signal is transmitted from the TDI port, and the signal is synchronized to other chiplets through the chiplet set as TDMASTER or TMASTER to start the test synchronously; Step 4, test / diagnosis, under the TSV test controller, the capture chip package register and the load chip package register are driven by the functional clock, the test vector generator generates a test vector, the load chip package register sends the test vector to the TSV, and the capture chip package register captures the test response from the TSV and determines whether there is a fault; if in TDMASTER or TDSLAVE mode, the test response is compressed into a 4-bit signal and stored in the capture chip package register to determine what type of fault exists; in TMASTER or TSLAVE mode, the capture chip package register connected to the faulty TSV stores a value of 1, otherwise it is 0; Step 5, capture end signal, after the test or diagnosis is completed, the test data register captures the end signal, and the capture chip package register and the load chip package register are driven by the test clock; Step 6: Shift out the test response, capture the value in the chip package register and shift it out serially to observe whether there is a fault; Step 7: Determine whether the test is completed. If completed, end the entire process; otherwise, continue to shift the enable signal from the TDI port.

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