Electrostatic protection simulation method and system for three-dimensional chip

Abstract

The invention relates to the technical field of electrostatic protection simulation, and particularly discloses an electrostatic protection simulation method and system for a three-dimensional chip, and the method comprises the following steps: S1, collecting related data of previous electrostatic protection simulation, including simulation condition parameters and simulation results of each simulation, and hardware parameters of the three-dimensional chip; s2, acquiring hardware parameters of the three-dimensional chip needing to be simulated currently, comparing the hardware parameters with hardware parameters in historical data, and calculating similarity; selecting historical chip data with high similarity with the current chip hardware parameters; s3, screening simulation conditions and results of chips similar to the hardware parameters of the current chip from the historical data, calculating passing rates under the similar conditions, and identifying the simulation conditions with the passing rates lower than a specific threshold value as the simulation conditions which are emphatically considered; and S4, performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters so as to evaluate the performance and reliability of the current three-dimensional chip under similar conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of electrostatic protection simulation technology, and in particular to an electrostatic protection simulation method and system for a three-dimensional chip. Background Art

[0002] Electrostatic protection of three-dimensional chips refers to the phenomenon of electrostatic discharge, that is, during the manufacturing, transportation, and use of integrated circuit chips, a certain amount of charge will accumulate in the external environment or internal structure of the chip, and these accumulated charges will instantly enter the integrated circuit through the chip pins.

[0003] Electrostatic protection simulation of three-dimensional chips is a method that uses computer simulation technology to analyze and verify the behavior and performance of integrated circuits under electrostatic discharge (ESD) conditions; using SPICE and ESD device behavior models, it allows comprehensive, quantitative and dynamic verification of ESD protection circuit design based entirely on ESD discharge functions at the chip level.

[0004] In the existing technology, with the continuous advancement of three-dimensional chip technology, its scale and complexity are also growing continuously; this growth not only brings higher performance and more functions, but also makes the simulation calculation amount increase exponentially; the complex structure, diverse material properties and complex charge accumulation and release mechanism of three-dimensional chips all put forward extremely high requirements on simulation accuracy; however, high-precision simulation often means huge computing cost and time consumption, which has become an important bottleneck restricting the research and development and application of three-dimensional chips. Summary of the invention

[0005] The purpose of the present invention is to provide a three-dimensional chip electrostatic protection simulation method and system to solve the above technical problems.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A three-dimensional chip electrostatic protection simulation method includes the following steps:

[0008] Step S1: Acquire historical simulation data of electrostatic protection simulation, wherein the historical simulation data includes simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip of each electrostatic protection simulation; the simulation condition parameters include discharge voltage and discharge current, the simulation results include pass and fail, and the hardware parameters include size and electrostatic sensitivity of packaging materials;

[0009] Step S2: when performing electrostatic protection simulation on the current three-dimensional chip, obtaining hardware parameters of the current three-dimensional chip and recording them as current hardware parameters; recording the three-dimensional chip in the historical simulation data as a historical three-dimensional chip, and recording the hardware parameters of the historical three-dimensional chip as historical hardware parameters;

[0010] Obtain the similarity between the current hardware parameters and the historical hardware parameters Among them, Hp i Represents the i-th current hardware parameter of the current 3D chip, Hp i ′ represents the i-th historical hardware parameter of the historical three-dimensional chip; the historical three-dimensional chips whose similarity is greater than or equal to the preset similarity threshold are selected and recorded as similar three-dimensional chips;

[0011] Step S3: Select all similar three-dimensional chips from the historical simulation data, and their corresponding simulation condition parameters and simulation results, and record them as similar simulation condition parameters and similar simulation results; obtain the pass rate of each similar simulation condition parameter Wherein m is the number of times similar simulation results corresponding to similar simulation condition parameters are passed, and N is the total number of similar simulation results; similar simulation condition parameters whose pass rate is lower than a preset pass rate threshold are selected and recorded as key simulation condition parameters;

[0012] Step S4: performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters.

[0013] As a further solution of the present invention: if there is an i-th historical hardware parameter that does not exist on the historical three-dimensional chip, then directly record HP i ′=0; if the i-th current hardware parameter does not exist on the current three-dimensional chip, then directly record Hp i =0.

[0014] As a further solution of the present invention: if the similarity of the historical three-dimensional chip is less than a preset similarity threshold, then the historical three-dimensional chip is not similar to the current three-dimensional chip.

[0015] As a further solution of the present invention: if the pass rate of the similar simulation condition parameter is greater than or equal to a preset pass rate threshold, the similar simulation condition parameter is a non-key simulation condition parameter.

[0016] As a further solution of the present invention: the setting range of the pass rate threshold is [60%, 100%].

[0017] As a further solution of the present invention: the process of performing electrostatic protection simulation on the current three-dimensional chip includes:

[0018] The electrostatic protection simulation of the current three-dimensional chip is performed according to each key simulation condition parameter in turn. If the simulation results obtained under the electrostatic protection simulation of each key simulation condition parameter are all passed, then there is no abnormality in the electrostatic protection of the current three-dimensional chip; if the simulation result obtained under the electrostatic protection simulation of any key simulation condition parameter is failed, then there is an abnormality in the electrostatic protection of the current three-dimensional chip.

[0019] As a further solution of the present invention: a three-dimensional chip electrostatic protection simulation system, comprising:

[0020] Data acquisition module: acquiring historical simulation data of electrostatic protection simulation, wherein the historical simulation data includes simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip of each electrostatic protection simulation; the simulation condition parameters include discharge voltage and discharge current, the simulation results include pass and fail, and the hardware parameters include size and electrostatic sensitivity of packaging materials;

[0021] Chip screening module: when performing electrostatic protection simulation on the current three-dimensional chip, the hardware parameters of the current three-dimensional chip are obtained and recorded as the current hardware parameters; the three-dimensional chip in the historical simulation data is recorded as the historical three-dimensional chip, and the hardware parameters of the historical three-dimensional chip are recorded as the historical hardware parameters;

[0022] Obtain the similarity between the current hardware parameters and the historical hardware parameters Among them, Hp i Represents the i-th current hardware parameter of the current 3D chip, Hp i ′ represents the i-th historical hardware parameter of the historical three-dimensional chip; the historical three-dimensional chips whose similarity is greater than or equal to the preset similarity threshold are selected and recorded as similar three-dimensional chips;

[0023] Parameter screening module: select all similar three-dimensional chips, their corresponding simulation condition parameters and simulation results from the historical simulation data, and record them as similar simulation condition parameters and similar simulation results; obtain the pass rate of each similar simulation condition parameter Wherein m is the number of times similar simulation results corresponding to similar simulation condition parameters are passed, and N is the total number of similar simulation results; similar simulation condition parameters whose pass rate is lower than a preset pass rate threshold are selected and recorded as key simulation condition parameters;

[0024] Simulation module: performs electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters.

[0025] Beneficial effects of the present invention:

[0026] The present invention uses historical simulation data, and the solution can predict and evaluate the performance of the current three-dimensional chip in electrostatic protection based on past experience. This method can significantly improve the accuracy of the simulation because it uses actual historical data rather than relying solely on theoretical models or assumptions. Through the analysis and screening of historical data, the solution can identify the simulation conditions that have the greatest impact on the current chip, thereby avoiding comprehensive simulation of all possible simulation conditions, saving a lot of computing resources and time, and greatly improving simulation efficiency. The method provides a systematic way to select key simulation condition parameters, helping engineers and decision makers to better understand which factors are most likely to affect the performance of the chip, so as to make more scientific and reasonable design and improvement decisions. Through effective electrostatic protection simulation, potential electrostatic problems can be foreseen and solved before the product is released, reducing product failure rates, and improving user satisfaction and market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention will be further described below in conjunction with the accompanying drawings.

[0028] Figure 1 It is a schematic flow chart of a method for simulating electrostatic protection of a three-dimensional chip according to the present invention. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] See also Figure 1 As shown, the present invention is a three-dimensional chip electrostatic protection simulation method, comprising the following steps:

[0031] Step S1: Acquire historical simulation data of electrostatic protection simulation, wherein the historical simulation data includes simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip of each electrostatic protection simulation; the simulation condition parameters include discharge voltage and discharge current, the simulation results include pass and fail, and the hardware parameters include size and electrostatic sensitivity of packaging materials;

[0032] It should be noted that data records of multiple electrostatic protection simulations are collected. These records should include the specific conditions, results and related three-dimensional chip hardware parameters of each simulation. Ensure the accuracy and completeness of the data for subsequent analysis and use. The discharge voltage is the discharge voltage value used in each recorded simulation, usually in volts (V), and the discharge current is the discharge current value used in each recorded simulation, usually in amperes (A). Other possible simulation condition parameters, such as temperature, humidity and other environmental factors, should also be recorded. The simulation result is the result of each simulation, that is, whether the electrostatic protection test has been passed, usually expressed as "pass" or "fail". The size of the three-dimensional chip is the recorded physical size of the three-dimensional chip, including length, width, height, etc.; the electrostatic sensitivity of the packaging material is the recorded electrostatic sensitivity level of the chip packaging material, which helps to evaluate the performance of the chip in different electrostatic environments. The hardware parameters also include the structure of the chip, material type, etc.

[0033] Step S2: when performing electrostatic protection simulation on the current three-dimensional chip, obtaining hardware parameters of the current three-dimensional chip and recording them as current hardware parameters; recording the three-dimensional chip in the historical simulation data as a historical three-dimensional chip, and recording the hardware parameters of the historical three-dimensional chip as historical hardware parameters;

[0034] Obtain the similarity between the current hardware parameters and the historical hardware parameters Among them, Hp i Represents the i-th current hardware parameter of the current 3D chip, Hp i ′ represents the i-th historical hardware parameter of the historical three-dimensional chip; the historical three-dimensional chips whose similarity is greater than or equal to the preset similarity threshold are selected and recorded as similar three-dimensional chips;

[0035] It is understandable that marking the three-dimensional chip in the historical simulation data as a historical three-dimensional chip is a step to distinguish the chip currently being simulated from the chip that has been simulated in history; at the same time, the hardware parameters of the historical three-dimensional chip are also marked accordingly for subsequent comparison and analysis; the similarity calculation formula measures the similarity between the two parameter vectors by calculating the sum of the absolute values ​​of the difference between them; the smaller the difference, the more similar the two parameters are. According to the calculated similarity value, select those historical three-dimensional chips whose similarity with the current three-dimensional chip is greater than or equal to the preset similarity threshold. These selected historical three-dimensional chips are considered to be sufficiently similar to the current chip in hardware characteristics, so their simulation results are of reference value to the current chip.

[0036] As a preferred embodiment of the present invention, if the i-th historical hardware parameter does not exist on the historical three-dimensional chip, then HP is directly recorded. i′=0; if the i-th current hardware parameter does not exist on the current three-dimensional chip, then directly record Hp i =0;

[0037] It is worth noting that in the field of computer science and algorithms, it is often necessary to process and compare the hardware parameters of multiple 3D chips. However, due to various reasons (such as different models, different batches, etc.), some hardware parameters may not exist on all 3D chips.

[0038] It is understandable that when the i-th historical hardware parameter does not exist on the historical 3D chip, the hardware parameter is directly recorded as 0; the purpose of this is to avoid algorithm or program errors caused by the lack of a certain parameter. This ensures that when comparing the current hardware parameters with the historical hardware parameters, even if some parameters are missing, the consistency and comparability of the data can be maintained.

[0039] As a preferred embodiment of the present invention, if the similarity of the historical three-dimensional chip is less than a preset similarity threshold, then the historical three-dimensional chip is not similar to the current three-dimensional chip;

[0040] It is worth noting that the setting of the similarity threshold needs to be adjusted according to the specific application scenario and requirements. If the threshold is too high, some chips that are actually similar may be misjudged as dissimilar; if the threshold is too low, some dissimilar chips may be misjudged as similar.

[0041] Step S3: Select all similar three-dimensional chips from the historical simulation data, and their corresponding simulation condition parameters and simulation results, and record them as similar simulation condition parameters and similar simulation results; obtain the pass rate of each similar simulation condition parameter Wherein m is the number of times similar simulation results corresponding to similar simulation condition parameters are passed, and N is the total number of similar simulation results; similar simulation condition parameters whose pass rate is lower than a preset pass rate threshold are selected and recorded as key simulation condition parameters;

[0042] It is understandable that the above steps are intended to screen out similar three-dimensional chips from historical simulation data and calculate the pass rates of their simulation condition parameters in order to determine the simulation condition parameters that need to be focused on. After calculating the pass rates of all similar simulation condition parameters, simulation condition parameters with pass rates lower than the preset pass rate threshold are selected and recorded as key simulation condition parameters. These parameters may be key points that need special attention or optimization in future simulation experiments.

[0043] As a preferred embodiment of the present invention, if the pass rate of the similar simulation condition parameter is greater than or equal to a preset pass rate threshold, the similar simulation condition parameter is a non-key simulation condition parameter;

[0044] It is understandable that in the process of simulation data analysis or optimization, it is often necessary to evaluate the effects of different simulation condition parameters to determine which parameters have a greater impact on the simulation results and thus require special attention or optimization. By comparing the pass rate of similar simulation condition parameters with the preset pass rate threshold, it is determined whether these hardware parameters are key simulation condition parameters. This judgment method is based on a simple comparison logic: if the pass rate is high enough (i.e., greater than or equal to the threshold), it is considered that the parameter has a relatively small impact on the simulation results and is therefore not a key simulation condition parameter; on the contrary, if the pass rate is lower than the threshold, it may be considered that the parameter has an important impact on the simulation results and requires special attention and optimization.

[0045] As a preferred embodiment of the present invention, the setting range of the pass rate threshold is [60%, 100%];

[0046] It is worth noting that the preset pass rate threshold needs to be reasonably set according to the specific application scenarios and requirements. If the threshold is too high, some actually important parameters may be misjudged as non-key points; if the threshold is too low, unnecessary points of concern may be added. Setting such a threshold range helps to balance sensitivity and specificity. If the threshold is too high (close to 100%), too many simulation conditions may be misjudged as requiring attention; if the threshold is too low, the simulation conditions that really require attention may not be effectively screened out. The range of [60%, 100%] provides a relatively loose standard that allows a certain degree of fluctuation while ensuring that the pass rate is only considered a key issue when it is significantly lower than the general level.

[0047] Step S4: performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters;

[0048] As a preferred embodiment of the present invention, the process of performing electrostatic protection simulation on the current three-dimensional chip includes:

[0049] Perform electrostatic protection simulation on the current three-dimensional chip according to each key simulation condition parameter in turn. If the simulation results obtained under the electrostatic protection simulation of each key simulation condition parameter are all passed, then the electrostatic protection of the current three-dimensional chip is normal; if the simulation result obtained under the electrostatic protection simulation of any key simulation condition parameter is not passed, then the electrostatic protection of the current three-dimensional chip is abnormal;

[0050] It is understandable that if the simulation results obtained under the electrostatic protection simulation of all key simulation condition parameters are passed, it is considered that the electrostatic protection of the current three-dimensional chip is normal. If the simulation result obtained under the electrostatic protection simulation of any key simulation condition parameter is not passed, it is considered that the electrostatic protection of the current three-dimensional chip is abnormal.

[0051] A three-dimensional chip electrostatic protection simulation system, comprising:

[0052] Data acquisition module: acquiring historical simulation data of electrostatic protection simulation, wherein the historical simulation data includes simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip of each electrostatic protection simulation; the simulation condition parameters include discharge voltage and discharge current, the simulation results include pass and fail, and the hardware parameters include size and electrostatic sensitivity of packaging materials;

[0053] Chip screening module: when performing electrostatic protection simulation on the current three-dimensional chip, the hardware parameters of the current three-dimensional chip are obtained and recorded as the current hardware parameters; the three-dimensional chip in the historical simulation data is recorded as the historical three-dimensional chip, and the hardware parameters of the historical three-dimensional chip are recorded as the historical hardware parameters;

[0054] Obtain the similarity between the current hardware parameters and the historical hardware parameters Among them, Hp i Represents the i-th current hardware parameter of the current 3D chip, Hp i ′ represents the i-th historical hardware parameter of the historical three-dimensional chip; the historical three-dimensional chips whose similarity is greater than or equal to the preset similarity threshold are selected and recorded as similar three-dimensional chips;

[0055] Parameter screening module: select all similar three-dimensional chips, their corresponding simulation condition parameters and simulation results from the historical simulation data, and record them as similar simulation condition parameters and similar simulation results; obtain the pass rate of each similar simulation condition parameter Wherein m is the number of times similar simulation results corresponding to similar simulation condition parameters are passed, and N is the total number of similar simulation results; similar simulation condition parameters whose pass rate is lower than a preset pass rate threshold are selected and recorded as key simulation condition parameters;

[0056] Simulation module: performs electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters.

[0057] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A three-dimensional chip electrostatic protection simulation method, characterized in that: The following steps are involved: Step S1: Acquire historical simulation data of electrostatic protection simulation, wherein the historical simulation data includes simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip of each electrostatic protection simulation; the simulation condition parameters include discharge voltage and discharge current, the simulation results include pass and fail, and the hardware parameters include size and electrostatic sensitivity of packaging materials; Step S2: when performing electrostatic protection simulation on the current three-dimensional chip, obtaining hardware parameters of the current three-dimensional chip and recording them as current hardware parameters; recording the three-dimensional chip in the historical simulation data as a historical three-dimensional chip, and recording the hardware parameters of the historical three-dimensional chip as historical hardware parameters; Obtain the similarity between the current hardware parameters and the historical hardware parameters Among them, Hp i Represents the i-th current hardware parameter of the current 3D chip, Hp i ′ represents the i-th historical hardware parameter of the historical three-dimensional chip; the historical three-dimensional chips whose similarity is greater than or equal to the preset similarity threshold are selected and recorded as similar three-dimensional chips; Step S3: Select all similar three-dimensional chips from the historical simulation data, and their corresponding simulation condition parameters and simulation results, and record them as similar simulation condition parameters and similar simulation results; obtain the pass rate of each similar simulation condition parameter Where m is the number of times similar simulation results corresponding to similar simulation condition parameters are passed, and N is the total number of similar simulation results; Select similar simulation condition parameters whose pass rate is lower than a preset pass rate threshold and record them as key simulation condition parameters; Step S4: performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters.

2. The electrostatic protection simulation method for a three-dimensional chip according to claim 1, characterized in that: In step S2, if the i-th historical hardware parameter does not exist on the historical three-dimensional chip, then directly record Hp i ′=0; if the i-th current hardware parameter does not exist on the current three-dimensional chip, then directly record Hp i =0.

3. The electrostatic protection simulation method for a three-dimensional chip according to claim 1, characterized in that: In step S2, if the similarity of the historical three-dimensional chip is less than a preset similarity threshold, the historical three-dimensional chip is not similar to the current three-dimensional chip.

4. The electrostatic protection simulation method for a three-dimensional chip according to claim 1, characterized in that: In step S3, if the pass rate of the similar simulation condition parameter is greater than or equal to a preset pass rate threshold, the similar simulation condition parameter is a non-key simulation condition parameter.

5. The electrostatic protection simulation method for a three-dimensional chip according to claim 1, characterized in that: In step S3, the setting range of the pass rate threshold is [60%, 100%].

6. The electrostatic protection simulation method for a three-dimensional chip according to claim 1, characterized in that: In step S4, the process of performing electrostatic protection simulation on the current three-dimensional chip includes: The electrostatic protection simulation of the current three-dimensional chip is performed according to each key simulation condition parameter in turn. If the simulation results obtained under the electrostatic protection simulation of each key simulation condition parameter are all passed, then there is no abnormality in the electrostatic protection of the current three-dimensional chip; if the simulation result obtained under the electrostatic protection simulation of any key simulation condition parameter is failed, then there is an abnormality in the electrostatic protection of the current three-dimensional chip.

7. A three-dimensional chip electrostatic protection simulation system, characterized in that: include: Data acquisition module: acquiring historical simulation data of electrostatic protection simulation, wherein the historical simulation data includes simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip of each electrostatic protection simulation; the simulation condition parameters include discharge voltage and discharge current, the simulation results include pass and fail, and the hardware parameters include size and electrostatic sensitivity of packaging materials; Chip screening module: when performing electrostatic protection simulation on the current three-dimensional chip, the hardware parameters of the current three-dimensional chip are obtained and recorded as the current hardware parameters; Recording the three-dimensional chip in the historical simulation data as a historical three-dimensional chip, and recording the hardware parameters of the historical three-dimensional chip as historical hardware parameters; Obtain the similarity between the current hardware parameters and the historical hardware parameters Among them, Hp i Represents the i-th current hardware parameter of the current 3D chip, Hp i ′ represents the i-th historical hardware parameter of the historical three-dimensional chip; the historical three-dimensional chips whose similarity is greater than or equal to the preset similarity threshold are selected and recorded as similar three-dimensional chips; Parameter screening module: select all similar three-dimensional chips, their corresponding simulation condition parameters and simulation results from the historical simulation data, and record them as similar simulation condition parameters and similar simulation results; obtain the pass rate of each similar simulation condition parameter Where m is the number of times similar simulation results corresponding to similar simulation condition parameters are passed, and N is the total number of similar simulation results; Select similar simulation condition parameters whose pass rate is lower than a preset pass rate threshold and record them as key simulation condition parameters; Simulation module: performs electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters.

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