Wiring method for realizing single-ended-differential multiplexing pin and FPGA (Field Programmable Gate Array) substrate

Abstract

The invention discloses a wiring method for realizing a single-ended-differential multiplexing pin and an FPGA (Field Programmable Gate Array) substrate, and the method comprises the steps: determining an adjacent interval which meets the design requirements of differential impedance and single-ended impedance at the same time, and obtaining a first range of the adjacent interval; determining an adjacent interval meeting the design requirements of the differential signal and the single-ended signal on the crosstalk noise at the same time, and obtaining a second range of the adjacent interval; and taking an intersection of the first range and the second range as a standard adjacent interval, and determining a wiring scheme according to the standard adjacent interval. According to the method provided by the invention, the wire spacing design wiring scheme capable of simultaneously meeting the requirements of the single-ended signal and the differential signal on crosstalk and impedance is adopted, so that the pins in the FPGA substrate designed according to the wiring scheme can meet the multiplexing rule of the single-ended signal and the differential signal.

Description

Technical Field

[0001] The invention belongs to the technical field of concentrated circuits, and in particular relates to a wiring method for realizing single-ended-differential multiplexing pins and an FPGA substrate. Background Art

[0002] Field Programmable Gate Array (FPGA) has been praised as the "universal chip" in the chip industry. It is field programmable and can realize the logical functions of almost any chip through programming. It also means that the same signal pin in different applications can be given different signal types such as single-ended and differential through software programming. As the interface signal rate increases, signal integrity issues frequently emerge. In order to improve the signal integrity design of the signal channel, designers hope that the positive and negative signal lines of the two pins of the differential signal are close to each other to produce higher coupling; the single-ended signal is the opposite, and the two pins of the signal are hoped to be far away to minimize coupling.

[0003] Due to the programmability of FPGA, when routing the above two pins on the IC package substrate, it is not possible to predefine whether it is a differential or single-ended signal, which poses a challenge to the coupling used in the substrate routing. Due to the characteristics of differential signals such as high signal rate, small amplitude, and susceptibility to interference, its line requirements are higher than single-ended signals; therefore, when designing current FPGAs, the routing scheme is mainly designed based on differential signals as the standard. However, differential pins are not fully compatible with single-ended signals, which makes the single-ended signal transmission quality of FPGAs made according to traditional routing schemes poor. Summary of the invention

[0004] The embodiment of the present invention provides a wiring method for realizing single-ended-differential multiplexed pins and an FPGA substrate, which can solve the problem of poor single-ended signal transmission quality of FPGAs manufactured according to traditional wiring schemes.

[0005] In a first aspect, an embodiment of the present invention provides a wiring method for implementing single-ended-differential multiplexed pins, the method comprising:

[0006] Determine an adjacent spacing that satisfies the design requirements of differential impedance and single-ended impedance at the same time, and obtain a first range of adjacent spacing, wherein the adjacent spacing is the spacing between two adjacent multiplexing pipelines, and the multiplexing pins of the differential signal and the single-ended signal are on the multiplexing pipeline;

[0007] Determine an adjacent spacing that satisfies the design requirements of the differential signal and the single-ended signal for crosstalk noise, and obtain a second range of the adjacent spacing;

[0008] The intersection of the first range and the second range is taken as a standard adjacent spacing, and a wiring scheme is determined according to the standard adjacent spacing.

[0009] In the second aspect, an embodiment of the present invention provides an FPGA substrate, the wiring scheme of which is determined based on a standard adjacent spacing, the standard adjacent spacing being the intersection of a first range and a second range of adjacent spacing, the adjacent spacing being the spacing between two adjacent multiplexing pipelines, and the multiplexing pins of single-ended signals and differential signals being on the multiplexing pipelines; the first range is sufficient to simultaneously meet the design requirements of differential impedance and single-ended impedance, and the second range simultaneously meets the design requirements of differential signals and single-ended signals for crosstalk noise.

[0010] The beneficial effect of the embodiments of the present invention compared with the prior art is: according to the method provided by the present invention, a line width design wiring scheme is adopted that can simultaneously meet the requirements of single-ended signals and differential signals for crosstalk and impedance, so that the pins in the FPGA manufactured according to this wiring scheme can realize the multiplexing of single-ended signals and differential signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A flowchart of a wiring method for implementing single-ended-differential multiplexed pins provided in an embodiment of the present invention;

[0012] Figure 2 A schematic diagram of a multiplexing pipeline provided by an embodiment of the present invention;

[0013] Figure 3 A schematic diagram of a first curve and a second curve provided by an embodiment of the present invention;

[0014] Figure 4 A schematic diagram of a differential signal / single-ended signal crosstalk noise curve provided by an embodiment of the present invention;

[0015] Figure 5 A schematic diagram of signal quality comparison provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0017] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0018] It should also be understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0019] As used in the present specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]", depending on the context.

[0020] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0021] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0022] Differential signals are composed of two single-ended signals with opposite phases, namely, positive phase signals and anti-phase signals, and have the characteristics of high speed, small amplitude, and strong anti-interference. Compared with differential signals, traditional single-ended signals have lower speed and larger amplitude. Therefore, in traditional wiring schemes, the multiplexed pins designed according to the constraint rules of differential signals can barely transmit single-ended signals. However, in FPGAs, with the development of DDR, a typical application of single-ended signals, especially parallel interface signals such as DDR3 / DDR4, the speed of single-ended signals has increased, the amplitude has decreased, and they are susceptible to crosstalk. Since the transmission direction of single-ended signals is the same, compared with differential signals, when DDR single-end is used, the signal between the two pins will produce strong crosstalk, or violate the conventional single-ended signal 50ohm impedance; resulting in excessive crosstalk, signal link impedance mismatch to form signal reflection, high communication bit error rate and other problems. Therefore, the single-ended signal transmission quality of FPGAs made according to traditional wiring schemes is poor.

[0023] In view of this, the present invention provides a wiring method for realizing single-ended-differential multiplexed pins, which adopts a line width design wiring scheme that can simultaneously meet the requirements of single-ended signals and differential signals for crosstalk and impedance, so that the pins in the FPGA manufactured according to this wiring scheme can realize the multiplexing of single-ended signals and differential signals.

[0024] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0025] The wiring method for implementing single-ended-differential multiplexed pins provided in the embodiment of the present invention can be applied to electronic devices such as mobile terminals, personal notebook computers, supercomputers, etc. The embodiment of the present invention does not impose any restrictions on the specific type of electronic devices.

[0026] Figure 1 The flowchart of a wiring method for implementing single-ended-differential multiplexed pins provided by an embodiment of the present invention is shown. As an example but not a limitation, this wiring method can be applied to the above electronic device. Exemplarily, the method may include steps S101-S103, and each step is described below.

[0027] S101, determining adjacent spacings that simultaneously meet design requirements of differential impedance and single-ended impedance, and obtaining a first range of adjacent spacings.

[0028] In a possible implementation, a first variation curve of differential impedance as a function of adjacent spacing may be drawn first, and then the first variation curve may be intercepted according to the design requirements of differential impedance to obtain a first sub-range of adjacent spacing. Similarly, a second variation curve of single-ended impedance as a function of adjacent spacing may be drawn, and then the second variation curve may be intercepted according to the design requirements of single-ended impedance to obtain a second sub-range of adjacent spacing. Afterwards, the intersection of the first sub-range and the second sub-range is taken as the first range of adjacent spacing.

[0029] Exemplarily, the adjacent spacing is the spacing between two adjacent multiplexing pipelines, and the multiplexing pipelines are provided with multiplexing pins for differential signals and single-ended signals.

[0030] For example, see Figure 2 In (a), A and B are multiplexed pins, and the pipelines they are on are multiplexed pipelines. When transmitting differential signals, pin A can transmit positive-phase signals, and pin B can transmit negative-phase signals. C and D are other third-party pin-related signal lines, and A, B, C, and D can all be microstrip line structures. See Figure 2 In (b), the adjacent spacing is the distance S1 between the pipelines where A and B are located, S2 is the spacing between the multiplexed pipeline and the adjacent non-multiplexed pipeline, and W is the line width of the multiplexed pipeline.

[0031] In one example, under the first preset wiring condition, starting from the conventional minimum adjacent spacing, a preset scanning step of the adjacent spacing can be set to simulate the size of the differential impedance at different adjacent spacings; and a first curve can be drawn according to the simulation results (see Figure 3 (a) in the figure.

[0032] Exemplarily, the first preset wiring condition may be that the line width W=1.8 mil, the line thickness is 0.59 mil, the dielectric thickness under the line surface is 1.2 mil, and the relative dielectric constant is 4.2.

[0033] Exemplarily, the preset scanning step of adjacent spacings may be 0.5 times the line width, that is, 0.9 mil.

[0034] Alternatively, see Figure 3 In (a), if the design requirement of the differential impedance is 100 ohm±5%, that is, the absolute value of the differential impedance is required to be within 95 ohm-105 ohm, then the first sub-range may include 1.5 times the line width to 4 times the line width.

[0035] In one example, similarly, under the first preset wiring condition, starting from the conventional minimum adjacent spacing, a preset scanning step of the adjacent spacing can be set to simulate the size of the single-ended impedance at different adjacent spacings; a second curve can be drawn according to the simulation results (see Figure 3 (b) in the figure.

[0036] Alternatively, see Figure 3 In (b), if the design requirement of the single-ended impedance is 50 ohm±5%, that is, the absolute value of the single-ended impedance is required to be within 47.5 ohm-52.5 ohm, then the second sub-range may include 1 times the line width to 3 times the line width.

[0037] For example, if the design requirement of the differential impedance is 100 ohm±5% and the design requirement of the single-ended impedance is 50 ohm±5%, then the first range may include 1.5-3 times of the line width.

[0038] S102, determining an adjacent spacing that satisfies the design requirements of the differential signal and the unit signal for crosstalk noise, and obtaining a second range of the adjacent spacing.

[0039] In a possible implementation, differential signal crosstalk noise curves corresponding to different adjacent spacings may be plotted, and then the differential signal crosstalk noise curves are selected according to the design requirements of the differential crosstalk noise to obtain the third sub-range of the connected spacing. Single-ended signal crosstalk noise curves corresponding to different adjacent spacings are plotted, and then the single-ended signal crosstalk noise curves are selected according to the design requirements of the single-ended crosstalk noise to obtain the fourth sub-range of the adjacent spacing. The intersection of the third sub-range and the fourth sub-range is then used as the second sub-range of the connected spacing.

[0040] Exemplarily, the differential crosstalk noise may be the crosstalk noise when the multiplexed pipeline transmits a differential signal. Correspondingly, the single-ended crosstalk noise may be the crosstalk noise when the multiplexed pipeline transmits a single-ended signal.

[0041] In one example, under the second preset wiring condition, starting from the conventional minimum adjacent spacing, a preset scan step of the adjacent spacing can be set to simulate the size of the differential crosstalk noise at different adjacent spacings; and differential signal crosstalk noise curves corresponding to different adjacent spacings can be drawn according to the simulation results.

[0042] Exemplarily, the second preset wiring condition can be: let the C pin signal be the attack line, the amplitude is a 1V step signal, the routing length is 1000mil (close to the longest routing of a general FPGA substrate), and the rising edge time is 0.1ns; A and B are the victim lines respectively; S2 is set to a value greater than 2 times the line width, for example 2.5 times the line width.

[0043] For example, under the second preset wiring condition, the differential signal crosstalk noise curve can be drawn starting from the adjacent spacing equal to 1 times the line width, with the preset 0.5 times the line width as the scanning step (see Figure 4 (a) in the figure, until the adjacent spacing is equal to 4 times the line width. The specific values ​​of differential crosstalk noise corresponding to different adjacent line widths can be seen in the following Table 1.

[0044] Table 1

[0045] S1 1W 1.5W 2W 2.5W 3W 3.5W 4W Differential crosstalk noise (mv) 22 23 24 25 26 26 27

[0046] Alternatively, see Figure 4 In (a), if the design requirement of the differential crosstalk noise is that the crosstalk coefficient of the differential crosstalk noise is not greater than 2.5%, the third sub-range may include 1 times the line width to 2.5 times the line width.

[0047] In one example, similarly, under the third preset wiring condition, starting from the conventional minimum adjacent spacing, a preset scan step of the adjacent spacing can be set to simulate the size of the single-ended crosstalk noise at different adjacent spacings; and the single-ended signal crosstalk noise curves corresponding to different adjacent spacings can be drawn according to the simulation results.

[0048] Exemplarily, the third preset wiring condition may be: let the B pin signal be the attack line, the amplitude be a 1V step signal, the routing coupling length be 1000mil, and the rising edge time be 0.1ns; A be the victim line; S2=2.5W.

[0049] For example, under the third preset wiring condition, the single-ended signal crosstalk noise curve can be drawn starting from the adjacent spacing equal to 1 times the line width, with the preset 0.5 times the line width as the scanning step (see Figure 4(b) in the figure, until the adjacent spacing is equal to 4 times the line width. The specific values ​​of the single-ended crosstalk noise corresponding to different adjacent line widths can be seen in the following Table 2.

[0050] Table 2

[0051] S1 1W 1.5W 2W 2.5W 3W 3.5W 4W Single-ended crosstalk noise (mv) 83 63 50 40 32 27 22

[0052] Alternatively, see Figure 4 In (b), if the design requirement of the single-ended crosstalk noise is that the crosstalk coefficient of the single-ended crosstalk noise is not greater than 5%, the fourth sub-range may include 2 times the line width to 4 times the line width.

[0053] Exemplarily, if the design requirement of differential crosstalk noise is that the crosstalk coefficient of differential crosstalk noise is not greater than 2.5%, and the design requirement of single-ended crosstalk noise is that the crosstalk coefficient of single-ended crosstalk noise is not greater than 5%, then the second range may include 2-2.5 times the line width.

[0054] S203: Taking the intersection of the first range and the second range as a standard adjacent spacing, and determining a wiring scheme according to the standard adjacent spacing.

[0055] Exemplarily, the standard adjacent spacing may include 2-2.5 times the line width.

[0056] According to the method provided by the present invention, a line width design wiring scheme is adopted that can simultaneously meet the requirements of single-ended signals and differential signals for crosstalk and impedance, so that the pins in the FPGA manufactured according to this wiring scheme can realize the multiplexing of single-ended signals and differential signals.

[0057] The embodiment of the present invention further provides an FPGA, wherein the wiring scheme of the FPGA is designed according to the above wiring method, and the spacing of the multiplexing pipelines thereon is within the standard connection spacing.

[0058] Exemplarily, the standard adjacent spacing is the intersection of the first range and the second range of adjacent spacing, and the connected spacing is the spacing between two connected multiplexing pipelines. The multiplexing pins of single-ended signals and differential signals are on the multiplexing pipeline. The first range simultaneously meets the design requirements of differential signal impedance and single-ended signal pair impedance, and the second range simultaneously meets the design requirements of differential signal crosstalk and single-ended signal pair crosstalk.

[0059] In one example, the first range includes 1.5-3 times the line width, and the second range may include 2-2.5 times the line width.

[0060] Exemplarily, the standard adjacent spacing may include 2-2.5 times the line width.

[0061] In order to better illustrate the beneficial effects of the present invention, the following simulation experiments were conducted:

[0062] Figure 5Shown is a schematic diagram of signal quality comparison provided by an embodiment of the present invention.

[0063] For example, see Figure 5 , Figure 5 (a) is a schematic diagram of the signal quality of the DDR parallel interface of the FPGA substrate using the traditional layout. Figure 5 (b) is a schematic diagram of the signal quality of the DDR parallel interface of the FPGA substrate laid out using the wiring method provided by the present invention.

[0064] Depend on Figure 5 It can be seen that the FPGA substrate using the traditional layout violates the electrical rules, while the FPGA substrate using the wiring method provided by the present invention passes the electrical rules.

[0065] Therefore, according to the method provided by the present invention, a line width design wiring scheme is adopted that can simultaneously meet the requirements of single-ended signals and differential signals for crosstalk and impedance, so that the pins in the FPGA manufactured according to this wiring scheme can realize the multiplexing of single-ended signals and differential signals.

[0066] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0067] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0068] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0069] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, any modifications made without departing from the concept of the present invention should be deemed to belong to the protection scope of the present invention.

Claims

1. A wiring method for realizing single-ended-differential multiplexing pins, characterized in that: include: Determine an adjacent spacing that satisfies the design requirements of both differential impedance and single-ended impedance, and obtain a first range of the adjacent spacing, wherein the adjacent spacing is the spacing between two adjacent multiplexing pipelines, and the multiplexing pins of the differential signal and the single-ended signal are on the multiplexing pipeline; Determine an adjacent spacing that satisfies the design requirements of the differential signal and the single-ended signal for crosstalk noise, and obtain a second range of the adjacent spacing; The intersection of the first range and the second range is used as a standard adjacent spacing, and a wiring scheme is determined according to the standard adjacent spacing.

2. The method according to claim 1, characterized in that The step of determining an adjacent spacing that satisfies the design requirements of both differential impedance and single-ended impedance to obtain a first range of the adjacent spacing includes: Draw a first variation curve of the differential impedance as the adjacent spacing varies; According to the design requirement of the differential impedance, intercepting the first variation curve to obtain a first sub-range of the adjacent spacing; Draw a second variation curve of the single-ended impedance as the adjacent spacing changes, wherein the single-ended impedance is the impedance of the multiplexing pipeline when transmitting the single-ended signal; According to the design requirement of the single-ended impedance, the second variation curve is intercepted to obtain a second sub-range of the adjacent spacing; The intersection of the first sub-range and the second sub-range is taken as the first range.

3. The method according to claim 2, characterized in that The design requirement of the differential impedance is that the differential impedance is within 95 ohm-105 ohm; the first sub-range includes 1.5 times the line width to 4 times the line width.

4. The method according to claim 2, characterized in that: The design requirement of the single-ended impedance is that the single-ended impedance is within 47.5 ohm-52.5 ohm; the second sub-range includes 1 times the line width to 3 times the line width.

5. The method according to claim 1, characterized in that The determining of the adjacent spacing that satisfies the design requirements of the differential signal and the unit signal for crosstalk noise to obtain a second range of the adjacent spacing includes: Draw the differential signal crosstalk noise curve corresponding to different adjacent spacings; The differential signal crosstalk noise curve is selected according to the design requirements of the differential crosstalk noise to obtain the third sub-range of the adjacent spacing, wherein the differential crosstalk noise is the crosstalk noise when the multiplexing pipeline transmits the differential signal; Draw the single-ended signal crosstalk noise curve corresponding to different adjacent spacings; The single-ended signal crosstalk noise curve is selected according to the design requirements of the single-ended crosstalk noise to obtain the fourth sub-range of the adjacent spacing, wherein the single-ended crosstalk noise is the crosstalk noise when the multiplexing pipeline transmits the single-ended signal; The intersection of the third sub-range and the fourth sub-range is taken as the second range.

6. The method according to claim 5, characterized in that The design requirement of the differential crosstalk noise is that the crosstalk coefficient of the differential crosstalk noise is not greater than 2.5%, and the third sub-range includes 1 times the line width to 2.5 times the line width.

7. The method according to claim 5, characterized in that The design requirement of the single-ended crosstalk noise is that the crosstalk coefficient of the single-ended crosstalk noise is not greater than 5%, and the fourth sub-range includes 2 times the line width to 4 times the line width.

8. An FPGA substrate, characterized in that: The wiring scheme of the FPGA substrate is determined based on a standard adjacent spacing, wherein the standard adjacent spacing is the intersection of a first range and a second range of adjacent spacing, wherein the adjacent spacing is the spacing between two adjacent multiplexing pipelines, and the multiplexing pins of single-ended signals and differential signals are on the multiplexing pipelines; the first range is sufficient to simultaneously meet the design requirements of differential impedance and single-ended impedance, and the second range simultaneously meets the design requirements of differential signals and single-ended signals for crosstalk noise.

9. The FPGA substrate according to claim 8, characterized in that: The first range includes 1.5 times the line width to 3 times the line width, and the second range includes 2 times the line width to 2.5 times the line width.

10. The FPGA substrate according to claim 9, characterized in that: The standard adjacent spacing includes 2 times the line width to 2.5 times the line width.

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