Intelligent information comprehensive processing NPU daughter card

Abstract

The invention relates to the technical field of NPU daughter cards, in particular to an intelligent information comprehensive processing NPU daughter card which comprises an AI processor, a storage unit, an interface unit, a clock circuit, a power conversion circuit and an FMC connector. The storage unit comprises an EMMC (Embedded Multi Media Card), an SPIFlash (Serial Peripheral Interface Flash) and three LPDDR4Xs (Low The interface unit comprises an RGMII, an SGMII, a USB3.0, a PCIE 3.0, an I2C, an RS232, a GPIO, a JTAG, and an HDMI. The system has the characteristics of high integration level, convenience and easiness in use, high environmental adaptability and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of NPU daughter cards, and in particular to an intelligent information comprehensive processing NPU daughter card. Background Art

[0002] NPU stands for "Neural Network Processor" and is a dedicated chip used to process large-scale neural network calculations. Neural network is a computing method based on simulating the human nervous system, which processes data through learning and training to better understand the content and present results. NPU is a highly efficient accelerator that makes this processing faster and more efficient.

[0003] NPU card is an accelerator card focused on neural network reasoning, which is usually installed in servers, data centers or cloud computing platforms. It consists of specialized hardware and software that can execute a large number of algorithms, process large amounts of data, complete traditional work, and accelerate artificial intelligence (AI) and deep learning (DL) tasks. NPU cards are usually used together with processors or GPUs to process complex tasks more quickly and efficiently.

[0004] Generally, NPU daughter cards are mainly used in the fields of drones, missiles, special vehicles, ships, special robots, etc. to realize functions such as target detection, mission planning, and data processing. Currently, there is no NPU daughter card product based on the CPU+NPU+GPU architecture to realize functions such as intelligent target detection, mission planning, and data processing. Summary of the invention

[0005] The purpose of the present invention is to provide an intelligent information integrated processing NPU daughter card to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] An intelligent information comprehensive processing NPU daughter card, comprising:

[0008] AI processor, storage unit, interface unit, clock circuit, power conversion circuit, and FMC connector;

[0009] The AI ​​processor uses SOC architecture, integrates CPU, GPU and NPU, and has a computing power of 20Tops@I NT8;

[0010] The external interfaces of the AI ​​processor include Serdes, EMMC, RGMII, USB, UART, CAN, MIP I, HDMI, SPI, I2C.I2S and GPI0, among which Serdes can be configured as PCI E, SATA, SGMII or USB3.0, and UART and CAN pins are multiplexed;

[0011] The power conversion circuit is used to provide 12V voltage to the module through the FMC connector, and output multiple voltages to the storage unit, the interface unit and the clock circuit after secondary voltage conversion;

[0012] The FMC connector is directly connected to the AI ​​processor through RGMII, SGMII, USB3.0, PCI E3.0, I2C, RS232, GPIO, JTAG, and HDMI interfaces.

[0013] The storage unit uses three LPDDR4X DDR chips to connect to the AI ​​processor to achieve data exchange.

[0014] The storage unit is connected to the AI ​​processor using a SPI FLASH and is used to store the processor startup program.

[0015] The storage unit is connected to the AI ​​processor using one EMMC and is used to store the processor operating system;

[0016] The clock circuit is used to provide a stable time reference signal and synchronize and control various operations and data transmission.

[0017] Preferably, the structural dimensions of the daughter card are 70 mm×125 mm.

[0018] Preferably, the interfaces of the daughter card include RGMII×1, SGMII×1, USB3.0×1, PCI E3.0×4, I2C×1, RS232×2, GPIO×6, JTAG×1 、 HDM I Tx × 1.

[0019] Preferably, the connector used is an FMC connector with a total number of cores of 400.

[0020] Preferably, the daughter card is used as a PCI E EP node in coprocessor mode, or as a RC node in main processor mode for independent use, and is switched to EP / RC working mode by pulling up and down the GPI0 pin.

[0021] Preferably, the external power supply provides 12V voltage to the daughter card through a connector, and after voltage conversion inside the daughter card, multiple voltages are output to power each chip of the module.

[0022] Preferably, the processor adopts the Ascend 310B processor, and the Ascend 310B processor is based on the ARM+NPU+GPU architecture.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The present invention integrates unitization, adopts mature processing schemes and unitization ideas, simplifies redundant circuits, and reduces power consumption.

[0025] The present invention adopts a miniaturized design concept, and the components are packaged reasonably to minimize the size and volume.

[0026] The present invention is designed based on a high-performance processor to ensure the real-time performance and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the principle of the NPU daughter card of the present invention;

[0028] Figure 2 It is a schematic diagram of the structural dimensions of the present invention;

[0029] Figure 3 This is a schematic diagram of the FMC interface definition of the present invention; DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] Embodiment 1:

[0032] See also Figure 1-3 , an intelligent information comprehensive processing NPU daughter card, comprising:

[0033] AI processor, storage unit, interface unit, clock circuit, power conversion circuit, FMC connector

[0034] The AI ​​processor uses a SOC architecture, integrating CPU, GPU and NPU, with a computing power of 20Tops@I NT8. The external interfaces of the AI ​​processor include Serdes, EMMC, RGMII, USB, UART, CAN, M IPI, HDMI, SPI, I2C.I2S and GPI0, etc. Among them, Serdes can be configured as PCI E, SATA, SGMII or USB3.0, and UART and CAN pins are multiplexed.

[0035] The power conversion circuit is used to provide 12V voltage to the module through the FMC connector, and output multiple voltages to the storage unit, interface unit and clock circuit after secondary voltage conversion;

[0036] The storage unit uses 3 domestic LPDDR4x@4266MHz, with a bandwidth of 96 bits and a total capacity of 12GB / ;

[0037] The storage unit uses a domestic 64MB SPI FLASH;

[0038] The storage unit uses a 128G domestic EMMC;

[0039] The clock circuit is used to provide a stable time reference signal and synchronize and control various operations and data transmission;

[0040] The interface unit includes RGMII, SGMII, USB2.0, PCI E3.0, I2C, RS232 transceivers, and integrates an HDMI video interface.

[0041] RGMII: 1 Ethernet RGMII interface, compatible with 1000Mbps / 100Mbps / 10Mbps;

[0042] SGMII: 1 Ethernet SGMII interface, compatible with 1000Mbps / 100Mbps / 10Mbps;

[0043] USB: 1 USB port, supporting USB2.0HOST+DEVICE mode and USB3.0HOST+DEVICE mode interface;

[0044] PCI E: 1 PCIe3.0×4 interface, supporting DMA data transmission;

[0045] I2C: 1 I2C interface, supports standard mode 100kbit / s, fast mode 400kbit / s, high-speed mode 3.4Mbit / s;

[0046] RS232: 1 RS232 interface, transmission rate 115200bps;

[0047] GPIO: 6 GPIO interfaces;

[0048] JTAG: 1 JTAG interface, compatible with IEEE 1149.6 standard;

[0049] HDMI: 1 HDMITx, supports 4K resolution.

[0050] The FMC connector is directly connected to the processor through interfaces such as RGMII, SGMII, USB3.0, PCI E3.0, I2C, RS232, GPIO, JTAG, and HDMI.

[0051] Embodiment 2:

[0052] See also Figure 3 , FMC connectors are connected by Figure 3 The definitions shown lead out related interface, power supply and other signals.

Claims

1. An intelligent information integrated processing NPU daughter card, characterized in that: include: AI processor, storage unit, interface unit, clock circuit, power conversion circuit, and FMC connector; The AI ​​processor uses SOC architecture, integrates CPU, GPU and NPU, and has a computing power of 20Tops@INT8; The external interfaces of the AI ​​processor include SerdeS, EMMC, RGMII, USB, UART, CAN, MIPI, HDMI, SPI, I2C.I2S and GPI0, among which Serdes can be configured as PCIE, SATA, SGMII or USB3.0, and UART and CAN pins are multiplexed; The power conversion circuit is used to provide 12V voltage to the module through the FMC connector, and output multiple voltages to the storage unit, the interface unit and the clock circuit after secondary voltage conversion; The FMC connector is directly connected to the AI ​​processor through RGMII, SGMII, USB3.0, PCIE3.0, I2C, RS232, GPIO, JTAG, and HDMI interfaces. The storage unit uses three LPDDR4X DDR chips to connect to the AI ​​processor to achieve data exchange. The storage unit is connected to the AI ​​processor using a SPI FLASH and is used to store the processor startup program. The storage unit is connected to the AI ​​processor using one EMMC and is used to store the processor operating system; The clock circuit is used to provide a stable time reference signal and synchronize and control various operations and data transmission.

2. The intelligent information integrated processing NPU daughter card according to claim 1, characterized in that: The structural dimensions of the daughter card are 70 mm×125 mm.

3. The intelligent information integrated processing NPU daughter card according to claim 1, characterized in that: The interfaces of the daughter card include RGMII×1, SGMII×1, USB3.0×1, PCIE3.0×4, I2C×1, RS232×2, GPIO×6, JTAG×1 、 HDMI Tx×1.

4. The intelligent information integrated processing NPU daughter card according to claim 1, characterized in that: The connector used is an FMC connector with a total of 400 cores.

5. The intelligent information integrated processing NPU daughter card according to claim 1, characterized in that ,This daughter card is used as the EP node of PCIE in coprocessor mode, or as the RC node in main processor mode for independent use, and switches to EP / RC working mode by pulling up and down the GPI0 pin.

6. The intelligent information integrated processing NPU daughter card according to claim 1, characterized in that ,The external power supply provides 12V voltage to the daughter card through the connector, and after the voltage conversion inside the daughter card, it outputs multiple voltages to power each chip in the module.

7. The intelligent information integrated processing NPU daughter card according to claim 1, characterized in that: The processor adopts the Ascend 310B processor, and the Ascend 310B processor is based on the ARM+NPU+GPU architecture.

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