Integrated circuit synthesis scanning electron microscope graph generation method, apparatus and device, and medium

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an integrated circuit synthesis scanning electron microscope graph generation method and device, equipment and a medium, and the method comprises the steps: obtaining layout parameters, and determining a test image according to the layout parameters. Performing fillet processing on a target corner in the layout contour in the test image to obtain a fillet processing image; performing roughness adjustment on the layout contour in the fillet processing image to obtain a roughness adjustment image; adding gray value intensity background information to the roughness adjustment image to obtain a gray adjustment image; and noise information is added to the gray level adjustment image to obtain an integrated circuit synthesis scanning electron microscope image. According to the scheme, it can be ensured that the obtained integrated circuit synthetic scanning electron microscope graph is vivid, analysis can be conducted based on the integrated circuit synthetic scanning electron microscope graph on the premise that part of research projects do not need to use CDSEM, the advancing speed of the research projects is increased, and the cost of the research projects is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method, device, equipment and medium for generating a synthetic scanning electron microscope image of an integrated circuit. Background Art

[0002] After each process step in the semiconductor manufacturing production line, it is necessary to use a scanning electron microscope (Critical Dimension Scanning Electron Microscope, CDSEM) for feature dimension measurement to conduct random inspections of wafer products in a timely manner, and judge whether the integrated circuits in the wafer products meet the requirements after the exposure, development, etching, grinding and other steps based on the obtained SEM images. If the requirements are met, the subsequent steps can be promoted. If the requirements are not met, the loss can be stopped in time. In addition, the computational lithography and yield improvement departments will also frequently use CDSEM to collect data. The computational lithography department uses the collected SEM images to establish lithography models, etching models, model verification, etc. These SEM images provide strong data support for lithography simulation verification, and the yield improvement department can propose targeted yield improvement methods by analyzing the collected SEM images.

[0003] In recent years, with the advancement of semiconductor manufacturing processes, the step of measuring and inspecting products using CDSEM has become increasingly important.

[0004] However, the applicant found that due to the long measurement time of CDSEM, it is impossible to obtain a large number of SEM images in a short period of time, making it difficult to obtain enough SEM images for analysis in some research projects, which slows down the progress of the research projects. Summary of the invention

[0005] In order to solve the problems in the related art, the embodiments of the present disclosure provide a method, device, equipment and medium for generating a synthetic scanning electron microscope image of an integrated circuit.

[0006] In a first aspect, an embodiment of the present disclosure provides a method for generating a synthetic scanning electron microscope image of an integrated circuit, comprising:

[0007] Acquire layout parameters, and determine a test image according to the layout parameters, wherein the test image includes a layout matching the layout parameters;

[0008] Rounding the target corners in the layout outline in the test image to obtain a rounded corner processed image, where the target corners are other corners in the layout outline except the corners generated by intercepting the test image;

[0009] Performing roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image;

[0010] adding gray value intensity background information to the roughness adjusted image to obtain a grayscale adjusted image;

[0011] Noise information is added to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit.

[0012] In one embodiment of the present disclosure, rounding is performed on a target corner in a layout outline in a test image to obtain a rounded image, including:

[0013] In the layout outline in the test image, an adjacent corner corresponding to the target corner is determined, where the adjacent corner is the corner with the smallest adjacent distance between the vertex in the layout outline and the vertex of the target corner;

[0014] If the adjacent distance is less than a preset photolithography process length threshold, the target corner is rounded using the adjacent distance as the rounding radius to obtain a rounded image;

[0015] If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius, and the target corner is rounded to obtain a rounded image.

[0016] In one embodiment of the present disclosure, roughness adjustment is performed on a layout outline in a rounded corner processed image to obtain a roughness adjusted image, including:

[0017] Obtaining the distance r from the target pixel in the layout outline in the rounded image to the edge of the layout outline closest to the target pixel;

[0018] based on Get pixel position offset c (r) , where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant;

[0019] Determine a pixel offset direction of the target pixel, where the pixel offset direction points from the pixel position of the target pixel to a projection point of the target pixel on an edge of the layout contour closest to the target pixel;

[0020] Based on the pixel position of the target pixel, the pixel position offset c (r) and pixel offset direction to obtain the roughness adjustment pixel position;

[0021] The pixel position of the target pixel in the rounding process image is set as the roughness adjustment pixel position to obtain the roughness adjustment image.

[0022] In one embodiment of the present disclosure, adding gray value intensity background information to the roughness adjusted image to obtain the gray scale adjusted image includes:

[0023] Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ;

[0024] based on Get the adjusted gray value C(rE), where e is a natural constant, b is a preset gray value attenuation coefficient, C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold;

[0025] The grayscale value of the target pixel in the roughness adjustment image is set to the adjustment grayscale value C(rE) to obtain a grayscale adjustment image.

[0026] In one embodiment of the present disclosure, adding noise information to a grayscale adjusted image to obtain a synthetic SEM image of an integrated circuit includes:

[0027] based on Get the noise gray value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjusted image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel;

[0028] Set the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value C n (i,j) to obtain the SEM image of the integrated circuit synthesis.

[0029] In one embodiment of the present disclosure, the layout parameters include at least one of the parameters of the minimum unit of layout design, the type of layout geometry, the size of the layout, and the layout capture window.

[0030] In a second aspect, an embodiment of the present disclosure provides a device for generating a synthetic scanning electron microscope image of an integrated circuit, comprising:

[0031] A parameter acquisition module is configured to acquire layout parameters and determine a test image according to the layout parameters, wherein the test image includes a layout matching the layout parameters;

[0032] A rounding processing module is configured to round a target corner in a layout outline in a test image to obtain a rounded corner processed image, wherein the target corner is a corner in the layout outline other than a corner generated by intercepting the test image;

[0033] A roughness adjustment module is configured to perform roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image;

[0034] A grayscale adjustment module is configured to add grayscale value intensity background information to the roughness adjusted image to obtain a grayscale adjusted image;

[0035] The noise adding module is configured to add noise information to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit.

[0036] In one embodiment of the present disclosure, the rounded corner processing module is specifically configured as follows:

[0037] In the layout outline in the test image, an adjacent corner corresponding to the target corner is determined, where the adjacent corner is the corner with the smallest adjacent distance between the vertex in the layout outline and the vertex of the target corner;

[0038] If the adjacent distance is less than a preset photolithography process length threshold, the target corner is rounded using the adjacent distance as the rounding radius to obtain a rounded image;

[0039] If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius, and the target corner is rounded to obtain a rounded image.

[0040] In one embodiment of the present disclosure, the roughness adjustment module is specifically configured as follows:

[0041] Obtaining the distance r from the target pixel in the layout outline in the rounded image to the edge of the layout outline closest to the target pixel;

[0042] based on Get pixel position offset c (r) , where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant;

[0043] Determine a pixel offset direction of the target pixel, where the pixel offset direction points from the pixel position of the target pixel to a projection point of the target pixel on an edge of the layout contour closest to the target pixel;

[0044] Based on the pixel position of the target pixel, the pixel position offset c (r) and pixel offset direction to obtain the roughness adjustment pixel position;

[0045] The pixel position of the target pixel in the rounding process image is set as the roughness adjustment pixel position to obtain the roughness adjustment image.

[0046] In one embodiment of the present disclosure, the grayscale adjustment module is specifically configured as follows:

[0047] Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ;

[0048] based on Get the adjusted gray value C(rE), where e is a natural constant, b is a preset gray value attenuation coefficient, C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold;

[0049] The grayscale value of the target pixel in the roughness adjustment image is set to the adjustment grayscale value C(rE) to obtain a grayscale adjustment image.

[0050] In one embodiment of the present disclosure, the noise adding module is specifically configured as follows:

[0051] based on Get the noise gray value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjusted image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel;

[0052] Set the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value C n (i,j) to obtain the SEM image of the integrated circuit synthesis.

[0053] In one embodiment of the present disclosure, the layout parameters include at least one of the parameters of the minimum unit of layout design, the type of layout geometry, the size of the layout, and the layout capture window.

[0054] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising a memory and a processor, wherein the memory is used to store one or more computer instructions, and wherein the one or more computer instructions are executed by the processor to implement a method as described in any one of the first aspects.

[0055] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, a method as described in any one of the first aspects is implemented.

[0056] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the layout parameters, and determining the test image according to the layout parameters. The target corners in the layout contour in the test image are rounded to obtain a rounded image; the roughness of the layout contour in the rounded image is adjusted to obtain a roughness adjusted image; gray value intensity background information is added to the roughness adjusted image to obtain a grayscale adjusted image; noise information is added to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit. Through the above scheme, it can be ensured that the rounded corners of the layout in the synthetic SEM image of the integrated circuit and the roughness of the layout contour are close to the rounded corners of the layout and the roughness of the layout contour in the SEM image obtained by sampling wafer products by CDSEM in reality, and it can also be ensured that the gray value intensity background and noise information of the synthetic SEM image of the integrated circuit are similar to those of the real SEM image, so that the obtained synthetic SEM image of the integrated circuit is more realistic, so that some research projects can be analyzed based on the synthetic SEM image of the integrated circuit without using CDSEM, thereby accelerating the advancement of the research project and reducing the cost of the research project.

[0057] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0059] Figure 1 A flow chart of a method for generating a synthetic SEM image of an integrated circuit according to an embodiment of the present disclosure is shown.

[0060] Figure 2 A schematic diagram showing a test image according to an embodiment of the present disclosure.

[0061] Figure 3 A schematic diagram showing a test image according to an embodiment of the present disclosure.

[0062] Figure 4 Schematic diagram showing a rounded corner processed image according to an embodiment of the present disclosure

[0063] Figure 5 A schematic diagram showing a roughness adjustment image according to an embodiment of the present disclosure.

[0064] Figure 6 A schematic diagram showing a grayscale adjusted image according to an embodiment of the present disclosure.

[0065] Figure 7 A schematic diagram showing a composite SEM image of an integrated circuit according to an embodiment of the present disclosure.

[0066] Figure 8 A structural block diagram of a device for generating a synthetic scanning electron microscope image of an integrated circuit according to an embodiment of the present disclosure is shown.

[0067] Fig. 9 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0068] Fig.10 A schematic diagram showing the structure of a computer system suitable for implementing the method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0069] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0070] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0071] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0072] In the present disclosure, if it involves operations of obtaining user information or user data or displaying user information or user data to others, the operations are all authorized and confirmed by the user, or actively selected by the user.

[0073] In recent years, with the advancement of semiconductor manufacturing processes, the step of measuring and inspecting products using CDSEM has become increasingly important.

[0074] However, the applicant found that the SEM images required CDSEM to work overtime. Since CDSEM is expensive and takes a long time to measure, if the imaging quality is high, it will significantly increase its measurement time, making it difficult to collect a large number of SEM images and unable to obtain a large number of SEM images in a short time. Therefore, in some research projects, it is difficult to obtain enough SEM images for analysis, which slows down the progress of the research projects.

[0075] In order to solve the above problems, the present disclosure provides a method, device, equipment and medium for generating a synthetic scanning electron microscope image of an integrated circuit.

[0076] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the layout parameters, and determining the test image according to the layout parameters. The target corners in the layout contour in the test image are rounded to obtain a rounded image; the roughness of the layout contour in the rounded image is adjusted to obtain a roughness adjusted image; gray value intensity background information is added to the roughness adjusted image to obtain a grayscale adjusted image; noise information is added to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit. Through the above scheme, it can be ensured that the rounded corners of the layout in the synthetic SEM image of the integrated circuit and the roughness of the layout contour are close to the rounded corners of the layout and the roughness of the layout contour in the real SEM image obtained by sampling the wafer product by the real CDSEM, and it can also be ensured that the gray value intensity background and noise information of the synthetic SEM image of the integrated circuit are similar to those of the real SEM image, so that the obtained synthetic SEM image of the integrated circuit is more realistic, so that some research projects can be analyzed based on the synthetic SEM image of the integrated circuit without using CDSEM, thereby accelerating the advancement of the research project and reducing the cost of the research project.

[0077] Figure 1 FIG. 1 is a flow chart showing a method for generating a synthetic SEM image of an integrated circuit according to an embodiment of the present disclosure. Figure 1 As shown, the integrated circuit synthetic scanning electron microscope image generation method includes the following steps S101-S105:

[0078] In step S101, a layout parameter is obtained, and a test image is determined according to the layout parameter;

[0079] Wherein, the test image includes a layout matching the layout parameters;

[0080] In one embodiment of the present disclosure, the layout parameters include at least one of the parameters of the minimum unit of layout design, the type of layout geometry, the size of the layout, and the layout capture window.

[0081] The minimum unit of layout design can be understood as the minimum counting unit when designing the layout. For example, the minimum unit of layout design can be a 1000dbu decibel voltage unit.

[0082] The layout geometry category can be used to indicate which type of geometry the layout outline belongs to. For example, the layout geometry category can include a rectangle, a square, a polygon surrounded only by broken lines, a figure surrounded by broken lines and curves, etc.

[0083] The size of the layout can be used to indicate the length of the edges, the curvature of the edges, the angle between the edges, etc. It can also be used to indicate the size of the area where the layout is located. For example, the layout is located within a 1um*1um square.

[0084] The parameters of the layout capture window may include the magnification of the layout capture window, etc. For example, the magnification of the layout capture window is 100k.

[0085] For example, Figure 2 FIG. 1 is a schematic diagram showing a test image according to an embodiment of the present disclosure. Figure 2 As shown, in test image 201, test image 202 and test image 203, the layout outline 200 is a rectangle that does not include a square; in test image 204, the layout outline 200 is a square; in test image 205, test image 206 and test image 207, the layout outline 200 is a polygon surrounded by broken lines; in test image 208, the layout outline 200 is a figure surrounded by broken lines and curves.

[0086] In step S102, a target corner in the layout outline of the test image is rounded to obtain a rounded image;

[0087] The target corners are the corners in the layout contour other than the corners generated by intercepting the test image;

[0088] In one embodiment of the present disclosure, all corners among the corners of the layout outline that coincide with the edge of the test image capture range can be determined as corners generated by capturing the test image, and some corners among the corners of the layout outline that coincide with the edge of the test image capture range can be randomly selected to be determined as corners generated by capturing the test image, or some corners among the corners of the layout outline that coincide with the edge of the test image capture range can be selected based on input corner indication information to be determined as corners generated by capturing the test image.

[0089] In one embodiment of the present disclosure, rounding the target corners in the layout outline in the test image can be understood as rounding the target corners based on a preset rounding radius; it can also be understood as rounding the target corners by randomly selecting a rounding radius within a preset rounding radius range.

[0090] For example, Figure 3 A schematic diagram showing a test image according to an embodiment of the present disclosure, Figure 4 FIG. 1 is a schematic diagram showing a rounded corner processed image according to an embodiment of the present disclosure. Figure 3 as well as Figure 4 As shown, in the layout outline of the test image 301, the target corners include corners 302 to corners 309. By performing rounding processing on corners 302 to corners 308, a rounded corner processed image 401 can be obtained. In the layout outline of the rounded corner processed image 401, corners 402 to corner 409 are rounded corners.

[0091] In step S103, the roughness of the layout outline in the rounded corner processed image is adjusted to obtain a roughness adjusted image;

[0092] In one embodiment of the present disclosure, the roughness adjustment of the layout outline in the rounded corner processed image can be understood as adjusting the positions of pixels in the layout outline so that the layout outline after the roughness adjustment appears rough and non-smooth.

[0093] For example, Figure 5 FIG. 1 is a schematic diagram showing a roughness adjustment image according to an embodiment of the present disclosure. Figure 4 as well as Figure 5 As shown, the roughness of the layout outline 400 of the rounded corner processed image 401 is adjusted to obtain a roughness adjusted image 501 , and the outline of the layout outline 500 of the roughness adjusted image 501 presents a rough and non-smooth effect.

[0094] In step S104, gray value intensity background information is added to the roughness adjusted image to obtain a gray scale adjusted image;

[0095] For example, Figure 6 FIG. 1 is a schematic diagram showing a grayscale adjustment image according to an embodiment of the present disclosure. Figure 5 as well as Figure 6 As shown, by adding gray value intensity background information to the roughness adjusted image 501 , a gray scale adjusted image 601 can be obtained.

[0096] In step S105, noise information is added to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit.

[0097] In one embodiment of the present disclosure, adding noise information to the grayscale adjusted image can be understood as adding at least one of Poisson noise and Gaussian noise to the grayscale adjusted image. Poisson noise can be understood as noise caused by random fluctuations of the electron beam in the primary electron beam of the scanning electron microscope, that is, the shot noise of the electron beam, and Gaussian noise can be understood as the shot noise of the electronic equipment of the microscope.

[0098] For example, Figure 7 Schematic diagram of a composite SEM image of an integrated circuit according to an embodiment of the present disclosure is shown. Figure 6 as well as Figure 7 As shown, by adding noise information to the grayscale adjusted image 601, a synthetic SEM image 701 of the integrated circuit can be obtained.

[0099] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the layout parameters, and determining the test image according to the layout parameters. The target corners in the layout contour in the test image are rounded to obtain a rounded image; the roughness of the layout contour in the rounded image is adjusted to obtain a roughness adjusted image; gray value intensity background information is added to the roughness adjusted image to obtain a grayscale adjusted image; noise information is added to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit. Through the above scheme, it can be ensured that the rounded corners of the layout in the synthetic SEM image of the integrated circuit and the roughness of the layout contour are close to the rounded corners of the layout and the roughness of the layout contour in the real SEM image obtained by sampling the wafer product by the real CDSEM, and it can also be ensured that the gray value intensity background and noise information of the synthetic SEM image of the integrated circuit are similar to those of the real SEM image, so that the obtained synthetic SEM image of the integrated circuit is more realistic, so that some research projects can be analyzed based on the synthetic SEM image of the integrated circuit without using CDSEM, thereby accelerating the advancement of the research project and reducing the cost of the research project.

[0100] In one embodiment of the present disclosure, rounding is performed on a target corner in a layout outline in a test image to obtain a rounded image, including:

[0101] In the layout outline in the test image, an adjacent corner corresponding to the target corner is determined, where the adjacent corner is the corner with the smallest adjacent distance between the vertex in the layout outline and the vertex of the target corner;

[0102] If the adjacent distance is less than a preset photolithography process length threshold, the target corner is rounded using the adjacent distance as the rounding radius to obtain a rounded image;

[0103] If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius, and the target corner is rounded to obtain a rounded image.

[0104] According to the technical solution provided by the embodiment of the present disclosure, the adjacent corner corresponding to the target corner is determined in the layout contour in the test image, and when the adjacent distance is less than the preset lithography process length threshold, the target corner is rounded with the adjacent distance as the rounding radius, thereby ensuring that the target corner after rounding will not be distorted due to a large rounding radius; and when the adjacent distance is greater than or equal to the lithography process length threshold, the target corner is rounded with the lithography process length threshold as the rounding radius to obtain a rounded image, so that the target corner after rounding can be made closer to the corner of the layout after the lithography process in reality, which helps to improve the realism of the layout contour in the integrated circuit synthetic scanning electron microscope image.

[0105] In one embodiment of the present disclosure, roughness adjustment is performed on a layout outline in a rounded corner processed image to obtain a roughness adjusted image, including:

[0106] Obtaining the distance r from the target pixel in the layout outline in the rounded image to the edge of the layout outline closest to the target pixel;

[0107] based on Get pixel position offset c (r) , where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant;

[0108] Determine a pixel offset direction of the target pixel, where the pixel offset direction points from the pixel position of the target pixel to a projection point of the target pixel on an edge of the layout contour closest to the target pixel;

[0109] Based on the pixel position of the target pixel, the pixel position offset c (r) and pixel offset direction to obtain the roughness adjustment pixel position;

[0110] The pixel position of the target pixel in the rounding process image is set as the roughness adjustment pixel position to obtain the roughness adjustment image.

[0111] In the above scheme, by obtaining the distance from the target pixel in the layout contour in the rounded corner processed image to the layout contour edge closest to the target pixel, and further obtaining the pixel position offset, the pixel offset direction of the target pixel is determined, and the roughness adjustment pixel position is obtained based on the pixel position of the target pixel, the pixel position offset and the pixel offset direction, and the pixel position of the target pixel in the rounded corner processed image is set as the roughness adjustment pixel position to obtain the roughness adjustment image, which can ensure that the roughness of the layout contour in the roughness adjustment image is close to the roughness of the layout contour after being processed by the photolithography process in reality, which helps to improve the realism of the layout contour in the integrated circuit synthetic scanning electron microscope image.

[0112] In one embodiment of the present disclosure, adding gray value intensity background information to the roughness adjusted image to obtain the gray scale adjusted image includes:

[0113] Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ;

[0114] based on Get the adjusted gray value C(rE), where e is a natural constant, b is a preset gray value attenuation coefficient, C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold;

[0115] The grayscale value of the target pixel in the roughness adjustment image is set to the adjustment grayscale value C(rE) to obtain a grayscale adjustment image.

[0116] In the above scheme, by obtaining the minimum distance from the target pixel to the edge of the layout contour in the roughness adjustment image and the preset grayscale value attenuation pixel step, and further obtaining the adjusted grayscale value, the grayscale value of the target pixel in the roughness adjustment image is set to the adjusted grayscale value to obtain the grayscale adjustment image. This can ensure that the grayscale of the pixel in the grayscale adjustment image is closer to the grayscale of the pixel in the scanning electron microscope image obtained by random inspection of wafer products by CDSEM in reality, which helps to improve the realism of the synthetic scanning electron microscope image of the integrated circuit.

[0117] In one embodiment of the present disclosure, adding noise information to a grayscale adjusted image to obtain a synthetic SEM image of an integrated circuit includes:

[0118] based on Get the noise gray value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjusted image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel;

[0119] Set the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value C n (i,j) to obtain the SEM image of the integrated circuit synthesis.

[0120] In one implementation of the present disclosure, Q G Can be preset to 10, Q P Can be preset to 42.

[0121] In the above scheme, by obtaining the noise grayscale value and setting the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value to obtain a synthetic scanning electron microscope image of the integrated circuit, Poisson noise and Gaussian noise can be superimposed on the image, so that the noise in the synthetic scanning electron microscope image of the integrated circuit is closer to the noise in the scanning electron microscope image obtained by random inspection of wafer products by CDSEM in reality, thereby improving the realism of the synthetic scanning electron microscope image of the integrated circuit.

[0122] Figure 8 A structural block diagram of a device for generating a synthetic scanning electron microscope image of an integrated circuit according to an embodiment of the present disclosure is shown.

[0123] The device may be implemented as part or all of an electronic device through software, hardware, or a combination of both.

[0124] like Figure 8 As shown, the integrated circuit synthetic scanning electron microscope image generating device 800 includes:

[0125] The parameter acquisition module 801 is configured to acquire layout parameters and determine a test image according to the layout parameters, wherein the test image includes a layout matching the layout parameters;

[0126] A rounding processing module 802 is configured to perform rounding processing on target corners in the layout outline in the test image to obtain a rounded corner processing image, wherein the target corners are other corners in the layout outline except the corners generated by intercepting the test image;

[0127] The roughness adjustment module 803 is configured to perform roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image;

[0128] A grayscale adjustment module 804 is configured to add grayscale value intensity background information to the roughness adjusted image to obtain a grayscale adjusted image;

[0129] The noise adding module 805 is configured to add noise information to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit.

[0130] In one embodiment of the present disclosure, the rounded corner processing module 802 is specifically configured as follows:

[0131] In the layout outline in the test image, an adjacent corner corresponding to the target corner is determined, where the adjacent corner is the corner with the smallest adjacent distance between the vertex in the layout outline and the vertex of the target corner;

[0132] If the adjacent distance is less than a preset photolithography process length threshold, the target corner is rounded using the adjacent distance as the rounding radius to obtain a rounded image;

[0133] If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius, and the target corner is rounded to obtain a rounded image.

[0134] In one embodiment of the present disclosure, the roughness adjustment module 803 is specifically configured as follows:

[0135] Obtaining the distance r from the target pixel in the layout outline in the rounded image to the edge of the layout outline closest to the target pixel;

[0136] based on Get pixel position offset c (r), where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant;

[0137] Determine a pixel offset direction of the target pixel, where the pixel offset direction points from the pixel position of the target pixel to a projection point of the target pixel on an edge of the layout contour closest to the target pixel;

[0138] Based on the pixel position of the target pixel, the pixel position offset c (r) and pixel offset direction to obtain the roughness adjustment pixel position;

[0139] The pixel position of the target pixel in the rounding process image is set as the roughness adjustment pixel position to obtain the roughness adjustment image.

[0140] In one embodiment of the present disclosure, the grayscale adjustment module 804 is specifically configured as follows:

[0141] Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ;

[0142] based on Get the adjusted gray value C(rE), where e is a natural constant, b is a preset gray value attenuation coefficient, C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold;

[0143] The grayscale value of the target pixel in the roughness adjustment image is set to the adjustment grayscale value C(rE) to obtain a grayscale adjustment image.

[0144] In one embodiment of the present disclosure, the noise adding module 805 is specifically configured as follows:

[0145] based on Get the noise gray value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjusted image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel;

[0146] Set the grayscale value of the target pixel in the grayscale adjustment image to the noise grayscale value C n (i,j) to obtain the SEM image of the integrated circuit synthesis.

[0147] In one embodiment of the present disclosure, the layout parameters include at least one of the parameters of the minimum unit of layout design, the type of layout geometry, the size of the layout, and the layout capture window.

[0148] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the layout parameters, and determining the test image according to the layout parameters. The target corners in the layout contour in the test image are rounded to obtain a rounded image; the roughness of the layout contour in the rounded image is adjusted to obtain a roughness adjusted image; gray value intensity background information is added to the roughness adjusted image to obtain a grayscale adjusted image; noise information is added to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit. Through the above scheme, it can be ensured that the rounded corners of the layout in the synthetic SEM image of the integrated circuit and the roughness of the layout contour are close to the rounded corners of the layout and the roughness of the layout contour in the real SEM image obtained by sampling the wafer product by the real CDSEM, and it can also be ensured that the gray value intensity background and noise information of the synthetic SEM image of the integrated circuit are similar to those of the real SEM image, so that the obtained synthetic SEM image of the integrated circuit is more realistic, so that some research projects can be analyzed based on the synthetic SEM image of the integrated circuit without using CDSEM, thereby accelerating the advancement of the research project and reducing the cost of the research project.

[0149] The present disclosure also discloses an electronic device, Fig. 9 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0150] like Fig. 9 As shown, the electronic device includes a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method according to an embodiment of the present disclosure.

[0151] Fig.10 A schematic diagram showing the structure of a computer system suitable for implementing the method according to an embodiment of the present disclosure is shown.

[0152] like Fig.10 As shown, the computer system includes a processing unit, which can perform the various methods in the above-mentioned embodiments according to the program stored in the read-only memory (ROM) or the program loaded from the storage part into the random access memory (RAM). In the RAM, various programs and data required for the operation of the computer system are also stored. The processing unit, ROM and RAM are connected to each other through a bus. The input / output (I / O) interface is also connected to the bus.

[0153] The following components are connected to the I / O interface: an input part including a keyboard, a mouse, etc.; an output part including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage part including a hard disk, etc.; and a communication part including a network interface card such as a LAN card, a modem, etc. The communication part performs a communication process via a network such as the Internet. The drive is also connected to the I / O interface as needed. Removable media, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive as needed so that the computer program read therefrom is installed into the storage part as needed. Among them, the processing unit can be implemented as a processing unit such as a CPU, a GPU, a TPU, an FPGA, an NPU, etc.

[0154] In particular, according to an embodiment of the present disclosure, the method described above can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program tangibly contained on a machine-readable medium, and the computer program includes a program code for executing the above method. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium.

[0155] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0156] The units or modules involved in the embodiments described in the present disclosure may be implemented by software or programmable hardware. The units or modules described may also be set in a processor, and the names of these units or modules do not constitute limitations on the units or modules themselves in some cases.

[0157] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system in the above embodiment; or a computer-readable storage medium that exists independently and is not assembled into a device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the method described in the present disclosure.

[0158] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A method for generating a synthetic scanning electron microscope image of an integrated circuit, characterized in that: include: Acquiring layout parameters, and determining a test image according to the layout parameters, wherein the test image includes a layout matching the layout parameters; Performing rounding processing on target corners in the layout outline in the test image to obtain a rounded corner processed image, wherein the target corners are other corners in the layout outline except the corners generated by intercepting the test image; Performing roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image; Adding grayscale value intensity background information to the roughness-adjusted image to obtain a grayscale-adjusted image; Noise information is added to the grayscale adjusted image to obtain a synthetic SEM image of the integrated circuit.

2. The method for generating a synthetic SEM image of an integrated circuit according to claim 1, characterized in that: The rounding of the target corners in the layout outline in the test image to obtain a rounded image includes: In the layout outline in the test image, determining an adjacent corner corresponding to the target corner, wherein the adjacent corner is a corner having a minimum adjacent distance between a vertex in the layout outline and a vertex of the target corner; If the adjacent distance is less than a preset photolithography process length threshold, rounding the target corner with the adjacent distance as the rounding radius to obtain the rounded corner processed image; If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius to perform fillet processing on the target corner to obtain the fillet processing image.

3. The method for generating a synthetic SEM image of an integrated circuit according to claim 1, characterized in that: The step of adjusting the roughness of the layout contour in the rounded corner processed image to obtain a roughness adjusted image includes: Obtaining the distance r from the target pixel in the layout outline in the rounded image to the edge of the layout outline closest to the target pixel; based on Obtaining a pixel position offset c(r), where rms is a preset root mean square surface roughness, ξ is a preset autocorrelation length, a is a preset roughness index, and e is a natural constant; Determine a pixel offset direction of a target pixel, where the pixel offset direction points from a pixel position of the target pixel to a projection point of the target pixel on an edge of a layout contour closest to the target pixel; Acquire a roughness adjustment pixel position based on a pixel position of a target pixel, the pixel position offset c(r), and the pixel offset direction; The pixel position of the target pixel in the rounded corner processed image is set as the roughness adjusted pixel position to obtain a roughness adjusted image.

4. The method for generating a synthetic SEM image of an integrated circuit according to claim 1, characterized in that: The step of adding grayscale value intensity background information to the roughness adjusted image to obtain a grayscale adjusted image includes: Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ; based on Get the adjusted gray value C(rE), where e is a natural constant, b is a preset gray value attenuation coefficient, C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold; The grayscale value of the target pixel in the roughness adjustment image is set as the adjustment grayscale value C(rE) to obtain the grayscale adjustment image.

5. The method for generating a synthetic SEM image of an integrated circuit according to claim 1, characterized in that: The step of adding noise information to the grayscale adjusted image to obtain a synthetic SEM image of an integrated circuit includes: based on Get the noise gray value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjusted image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel; The grayscale value of the target pixel in the grayscale adjustment image is set to the noise grayscale value C n (i, j) to obtain a synthetic SEM image of the integrated circuit.

6. The method for generating a synthetic SEM image of an integrated circuit according to any one of claims 1 to 5, characterized in that: The layout parameters include at least one of the parameters of the minimum unit of layout design, the type of layout geometry, the size of the layout, and the layout capture window.

7. An integrated circuit synthetic scanning electron microscope image generation device, characterized in that: include: A parameter acquisition module is configured to acquire layout parameters and determine a test image according to the layout parameters, wherein the test image includes a layout matching the layout parameters; A rounding processing module is configured to perform rounding processing on target corners in the layout outline in the test image to obtain a rounding processing image, wherein the target corners are other corners in the layout outline except the corners generated by intercepting the test image; A roughness adjustment module is configured to perform roughness adjustment on the layout outline in the rounded corner processed image to obtain a roughness adjusted image; A grayscale adjustment module, configured to add grayscale value intensity background information to the roughness adjusted image to obtain a grayscale adjusted image; The noise adding module is configured to add noise information to the grayscale adjusted image to obtain a synthetic scanning electron microscope image of the integrated circuit.

8. The integrated circuit synthetic scanning electron microscope image generating device according to claim 7, characterized in that: The rounded corner processing module is specifically configured as follows: In the layout outline in the test image, determining an adjacent corner corresponding to the target corner, wherein the adjacent corner is a corner having a minimum adjacent distance between a vertex in the layout outline and a vertex of the target corner; If the adjacent distance is less than a preset photolithography process length threshold, rounding the target corner with the adjacent distance as the rounding radius to obtain the rounded corner processed image; If the adjacent distance is greater than or equal to the photolithography process length threshold, the photolithography process length threshold is used as the fillet radius to perform fillet processing on the target corner to obtain the fillet processing image.

9. The integrated circuit synthetic scanning electron microscope image generating device according to claim 7, characterized in that: The roughness adjustment module is specifically configured as follows: Obtaining the distance r from the target pixel in the layout outline in the rounded image to the edge of the layout outline closest to the target pixel; Based on c(r)=rms 2 *e -(rξ)2a r obtains the pixel position offset c(r), where rms is the preset root mean square surface roughness, ξ is the preset autocorrelation length, a is the preset roughness index, and e is a natural constant; Determine a pixel offset direction of a target pixel, where the pixel offset direction points from a pixel position of the target pixel to a projection point of the target pixel on an edge of a layout contour closest to the target pixel; Acquire a roughness adjustment pixel position based on a pixel position of a target pixel, the pixel position offset c(r), and the pixel offset direction; The pixel position of the target pixel in the rounded corner processed image is set as the roughness adjusted pixel position to obtain a roughness adjusted image.

10. The integrated circuit synthetic scanning electron microscope image generating device according to claim 7, characterized in that: The grayscale adjustment module is specifically configured as follows: Get the minimum distance r from the target pixel to the edge of the layout contour in the roughness adjustment image E And the preset gray value attenuation pixel step r t ; based on Get the adjusted gray value C(rE), where e is a natural constant, b is a preset gray value attenuation coefficient, C G is the preset maximum grayscale threshold, C E is the preset minimum grayscale threshold; The grayscale value of the target pixel in the roughness adjustment image is set as the adjustment grayscale value C(rE) to obtain the grayscale adjustment image.

11. The integrated circuit synthetic scanning electron microscope image generating device according to claim 7, characterized in that: The noise adding module is specifically configured as follows: based on Get the noise gray value C n (i, j), where (i, j) is the pixel coordinate of the target pixel in the grayscale adjusted image, C s (i, j) is the grayscale value of the target pixel in the grayscale adjusted image, Q G is the preset Gaussian noise coefficient, Q P is the preset Poisson noise coefficient, R(i,j) is a random number that conforms to the Gaussian distribution and corresponds to the target pixel; The grayscale value of the target pixel in the grayscale adjustment image is set to the noise grayscale value C n (i, j) to obtain a synthetic SEM image of the integrated circuit.

12. The integrated circuit synthetic scanning electron microscope image generating device according to any one of claims 7 to 11, characterized in that: The layout parameters include at least one of the parameters of the minimum unit of layout design, the type of layout geometry, the size of the layout, and the layout capture window.

13. An electronic device, characterized in that: The method comprises a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method steps described in any one of claims 1 to 6.

14. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method steps described in any one of claims 1 to 6 are implemented.

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