Display device

Abstract

The display device of the present invention includes: a first display panel including first pixels and first data lines and driven by a plurality of frames; a second display panel including a second pixel and a second data line, and driven by a plurality of the frames; a display driving circuit for controlling a plurality of the frames; and a signal transmission line electrically connected to the first data line, the second data line, and the display driving circuit, the plurality of frames including a first frame and a second frame, the display driving circuit transmitting a first data signal to the signal transmission line during the first frame, and transmitting a second data signal to the signal transmission line during the second frame. The display driving circuit transmits a second data signal to the signal transmission line during the second frame.

Description

Technical Field

[0001] The present invention relates to a display device which drives a plurality of display panels by using a display driving circuit. Background Art

[0002] Recently, with the development of mobile communication technology, electronic devices have changed to a form that is not only easy to carry, but also can freely access wired and wireless networks. For example, portable display devices such as smartphones and tablet PCs can support multiple functions such as Internet access and multimedia content playback in addition to call and message sending and receiving functions.

[0003] As described above, a display device in various forms generally has a display panel, and can provide various contents (e.g., images, dynamic images, etc.) to a user in a visual manner through the display panel. The display device is composed of a timing controller embedded driver (TED) for driving the display panel. Summary of the invention

[0004] An object of the present invention is to provide a display device that drives a plurality of display panels using one display driving circuit.

[0005] A display device according to an embodiment of the present invention may include: a first display panel, including a first pixel and a first data line, and driven by multiple frames; a second display panel, including a second pixel and a second data line, and driven by multiple frames, and arranged at a distance from the first display panel; a display driving circuit, used to drive the first display panel and the second display panel, and control the multiple frames; and a signal transmission line, electrically connected to the first data line, the second data line and the display driving circuit, the multiple frames including a first frame and a second frame different from the first frame, the display driving circuit sends a first data signal for driving the first display panel to the signal transmission line during the first frame, and the display driving circuit sends a second data signal for driving the second display panel to the signal transmission line during the second frame.

[0006] The first display panel and the second display panel may face each other.

[0007] The display driving circuit may be disposed between the first display panel and the second display panel.

[0008] The display driving circuit may include: a data driver connected to the signal transmission line; and a driving controller for controlling the data driver.

[0009] The first display panel may include a first scan driver outputting a first scan signal during the first frame, and the second display panel may include a second scan driver outputting a second scan signal different from the first scan signal during the second frame.

[0010] The first display panel can provide the first data signal to the first pixel, and the first pixel emits light according to the first scanning signal and the first data signal. The second display panel can provide the second data signal to the second pixel, and the second pixel emits light according to the second scanning signal and the second data signal.

[0011] The first scan driver may include multiple first shift registers driven sequentially, the second scan driver may include multiple second shift registers driven sequentially, and the display driving circuit may provide a first scan start signal to a first first shift register among the multiple first shift registers, and provide a second scan start signal different from the first scan start signal to a first second shift register among the multiple second shift registers.

[0012] The first scan driver may output the first scan signal according to the first scan start signal, and the second scan driver may output the second scan signal according to the second scan start signal.

[0013] The first scan start signal and the second scan start signal may not overlap.

[0014] The display device may further include: a voltage generator that receives a power control signal from the display driving circuit and controls the on / off of each of the first display panel and the second display panel according to the power control signal.

[0015] The display driving circuit can drive the first display panel and the second display panel in one of a first mode, a second mode and a third mode. In the first mode, the first display panel is turned on and the second display panel is turned off. The display driving circuit can drive at least one frame among the multiple frames as the first frame.

[0016] In the second mode, the first display panel is turned off, the second display panel is turned on, and the display driving circuit can drive at least one frame among the multiple frames as the second frame.

[0017] In the third mode, the first display panel is turned on, the second display panel is turned on, and the display driving circuit can use the first frame and the second frame to drive the first display panel and the second display panel respectively, and the first frame and the second frame can be provided alternately.

[0018] In the third mode, a driving frequency of the first display panel and a driving frequency of the second display panel may be the same.

[0019] The first data signal and the second data signal may be provided to each of the first display panel and the second display panel through the signal transmission line.

[0020] An area of ​​the first display panel may be larger than an area of ​​the second display panel.

[0021] It may also include: a third display panel, including third pixels and a third data line, and driven by multiple frames, and configured to be separated from the first display panel and the second display panel. The display driving circuit can also be used to drive the third display panel, and the signal transmission line can also be electrically connected to the third data line. The multiple frames can also include a third frame different from the first frame and the second frame. The display driving circuit can send a third data signal for driving the third display panel to the signal transmission line during the third frame.

[0022] The first display panel and the third display panel may face each other.

[0023] The first data signal, the second data signal, and the third data signal may be provided to each of the first display panel, the second display panel, and the third display panel through the signal transmission line.

[0024] An area of ​​the second display panel may be greater than an area of ​​the third display panel.

[0025] (Effects of the Invention)

[0026] According to the above, the first display panel and the second display panel can be driven by one display driving circuit. That is, the display device can easily drive multiple display panels using one display driving circuit. Therefore, the internal space of the display device can be saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a perspective view showing a display device in an unfolded state according to an embodiment of the present invention.

[0028] Figure 2 It is shown Figure 1 A three-dimensional diagram of the folding process of the display device shown.

[0029] Figure 3 FIG. 1 is a cross-sectional view of a display panel and a sensor panel according to an embodiment of the present invention.

[0030] Figure 4 FIG. 1 is a cross-sectional view of a display panel and a sensor panel according to an embodiment of the present invention.

[0031] Figure 5 It is a diagram for explaining a schematic structure of a display device according to an embodiment of the present invention.

[0032] Figure 6 FIG. 1 is a side view of a display device according to an embodiment of the present invention.

[0033] Figure 7 is a block diagram of a display device according to an embodiment of the present invention.

[0034] Figure 8 It is a waveform diagram for explaining the operation of the display device according to one embodiment of the present invention.

[0035] Fig. 9 It is a diagram for explaining a schematic structure of a display device according to an embodiment of the present invention.

[0036] Fig.10 It is a waveform diagram for explaining the operation of the display device according to one embodiment of the present invention.

[0037] Description of Reference Numerals

[0038] 1000: electronic device; DP: display panel; ISP: sensor panel; CF: flexible printed circuit; TED: display driver circuit; PMIC: voltage generator; TC: driver controller; DC: data driver DETAILED DESCRIPTION

[0039] In this specification, when it is mentioned that a certain component (or region, layer, part, etc.) is "on" another component, "connected" or "combined with" another component, it means that the certain component can be directly configured / connected / combined on the other component, or a third-party component can be configured between them.

[0040] The same reference numerals represent the same components. In addition, in the drawings, the thickness, ratio and size of the components are exaggerated for effective description of the technical content. "And / or" includes all of the combinations that can be defined by the components related to each other.

[0041] The terms first, second, etc. can be used to describe a variety of constituent elements, but the constituent elements are not limited to the terms. The terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element can be referred to as the second constituent element, and by analogy, the second constituent element can also be referred to as the first constituent element. Unless the context clearly indicates a different meaning, a singular expression includes a plural expression.

[0042] In addition, terms such as "lower", "lower side", "upper", and "upper side" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0043] The terms "including" or "having" should be understood as intending to specify the existence of the features, numbers, steps, actions, constituent elements, parts or their combinations recorded in the specification, but are not intended to preclude the existence or additional possibilities of one or more other features, numbers, steps, actions, constituent elements, parts or their combinations.

[0044] Unless defined differently, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. Also, terms that are the same as those defined in generally used dictionaries should be interpreted as having meanings consistent with those in the context of the relevant technology, wherein, unless explicitly defined, they should not be interpreted as overly ideal or overly formal meanings.

[0045] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0046] Figure 1 This is a perspective view showing a display device in an unfolded state according to an embodiment of the present invention. Figure 2 It is shown Figure 1 A three-dimensional diagram of the folding process of the display device shown.

[0047] Reference Figure 1 and Figure 2 The display device 1000 may be a device activated by an electrical signal. For example, the display device 1000 may be a mobile phone, a tablet PC, a car navigation system, a game console, or a wearable device, but is not limited thereto. In the specification of the present invention, the display device 1000 is illustrated as an example of a mobile phone.

[0048] The display device 1000 may include a first display surface FS defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. The display device 1000 may provide an image IM to a user through the first display surface FS. The image IM may include not only dynamic images but also static images. Figure 1 , a clock window and an icon are shown as an example of the image IM. The display device 1000 can display the image IM on the first display surface FS parallel to each of the first direction DR1 and the second direction DR2 toward the third direction DR3. Based on the direction in which the image IM is displayed, the front (or upper surface) and the back (or lower surface) of each structure can be defined. The front and back surfaces can be opposite to each other in the third direction DR3, and the normal directions of the front and back surfaces can be parallel to the third direction DR3.

[0049] The first display surface FS may include a first active area F-AA and a first peripheral area F-NAA. Moreover, in the first active area F-AA, various forms of external inputs may be sensed. The first peripheral area F-NAA may be adjacent to the first active area F-AA. The first peripheral area F-NAA may have a prescribed color. The first peripheral area F-NAA may surround the first active area F-AA. Thus, in fact, the shape of the first active area F-AA may be defined by the first peripheral area F-NAA. However, this is merely an illustrative illustration, and the first peripheral area F-NAA may be configured adjacent to only one side of the first active area F-AA, or may be omitted. The display device 1000 of an embodiment of the present invention may include active areas of various shapes, which are not limited to a certain embodiment.

[0050] The display device 1000 may include a second display surface RS. The second display surface RS may be defined as a surface facing at least a portion of the first display surface FS. That is, the second display surface RS may be defined as a portion of the rear surface of the display device 1000. In the inwardly folded state, the second display surface RS may be visible to the user.

[0051] The second display surface RS may include a second active area R-AA and a second peripheral area R-NAA. The second active area R-AA may include an electronic module area EMA. The display device 1000 may display an image IM through the second active area R-AA. In addition, various forms of external inputs may be sensed in the second active area R-AA. The second peripheral area R-NAA may be adjacent to the second active area R-AA. The second peripheral area R-NAA may have a prescribed color. The second peripheral area R-NAA may surround the second active area R-AA. Thus, in fact, the shape of the second active area R-AA may be defined by the second peripheral area R-NAA. However, this is only an illustrative illustration, and the second peripheral area R-NAA may be configured adjacent to only one side of the second active area R-AA, and may also be omitted. The display device 1000 of an embodiment of the present invention may include active areas of various shapes, which are not limited to a certain embodiment.

[0052] Various electronic modules may be configured in the electronic module area EMA. For example, the electronic module may include at least one of a camera, a speaker, a light sensor, and a thermal sensor. The electronic module area EMA may sense an external subject received through the first or second display surface FS, RS, or provide a sound signal such as voice to the outside through the first or second display surface FS, RS. The electronic module may also include a plurality of structures, which are not limited to a certain embodiment.

[0053] The electronic module area EMA may be surrounded by the second active area R-AA and the second peripheral area R-NAA. However, the present invention is not limited thereto, and the electronic module area EMA may be disposed in the second active area R-AA, which is not limited to a certain embodiment.

[0054] The display device 1000 may sense external input applied from the outside. The external input may include various forms of input provided from the outside of the display device 1000. For example, the external input includes not only contact based on a part of the body such as a hand of a user, but also external input applied close to or adjacent to the display device 1000 at a prescribed distance. In addition, various forms such as force, pressure, temperature, and light may be included.

[0055] In addition, Figure 1 The first direction DR1 to the third direction DR3 are shown in the following drawings. The directions indicated by the first to third directions DR1, DR2, and DR3 described in this specification are relative concepts and can be changed to other directions. In addition, the directions indicated by the first to third directions DR1, DR2, and DR3 can be described as the first to third directions, and the same reference numerals can be used.

[0056] The display device 1000 may include at least one folding area FA1 and non-folding areas NFA1 and NFA2 adjacent to the folding area FA1. The non-folding areas NFA1 and NFA2 may be spaced apart from each other across the folding area FA1. The non-folding areas NFA1 and NFA2 may include a first non-folding area NFA1 and a second non-folding area NFA2. For example, the first non-folding area NFA1 may be spaced apart from the first non-folding area NFA1 and disposed on one side of the folding area FA1 along the first direction DR1, and the second non-folding area NFA2 may be spaced apart from the first non-folding area NFA1 and disposed on the other side of the folding area FA1 in the opposite direction of the first direction DR1.

[0057] The display device 1000 may be folded with the folding axis FX1 as a reference. The folding axis FX1 may be an imaginary axis extending along the second direction DR2. The folding axis FX1 may be parallel to the short side direction of the display device 1000. The folding axis FX1 may extend along the second direction DR2 on the first display surface FS.

[0058] In one embodiment, the first non-folding area NFA1 and the second non-folding area NFA2 may be opposite to each other, and the display device 1000 may be in-folded so that the first display surface FS is not exposed to the outside.

[0059] Furthermore, unlike the figure, in one embodiment, the display device 1000 can be folded outward (outer-folding) to expose the first display surface FS to the outside. In addition, in one embodiment, the display device 1000 can make the first display surface FS visible to the user in the unfolded state, and make the second display surface RS visible to the user in the in-folded state.

[0060] Figure 3 FIG. 1 is a cross-sectional view of a display panel and a sensor panel according to an embodiment of the present invention.

[0061] Reference Figure 3 The display device 1000 may include a display panel DP and a sensor panel ISP. The display panel DP may include a base layer 110 , a circuit layer 120 , a light emitting element layer 130 , and an encapsulation layer 140 .

[0062] The base layer 110 may be a member providing a base surface for configuring the circuit layer 120. The base layer 110 may be a glass substrate, a metal substrate or a polymer substrate. However, the embodiment is not limited thereto, and the base layer 110 may be an inorganic layer, an organic layer or a composite material layer.

[0063] The base layer 110 may have a multi-layer structure. For example, the base layer 110 may include a first synthetic resin layer, a silicon oxide (SiOx) layer disposed on the first synthetic resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second synthetic resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0064] Each of the first and second synthetic resin layers may include a polyimide resin. Furthermore, each of the first and second synthetic resin layers may include at least one of an acrylate resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, in this specification, a "~~" type resin means a functional group containing "~~".

[0065] The circuit layer 120 may be disposed on the base layer 110. The circuit layer 120 may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base layer 110 by coating, deposition, and the like, and then the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by multiple photoresist processes. Subsequently, the semiconductor pattern, the conductive pattern, and the signal line included in the circuit layer 120 may be formed.

[0066] The light emitting element layer 130 may be disposed on the circuit layer 120. The light emitting element layer 130 may include a light emitting element. For example, the light emitting element layer 130 may include an organic light emitting substance, a quantum dot, a quantum rod, a micro-LED, or a nano-LED.

[0067] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may protect the light emitting element layer 130 from impurities such as moisture, oxygen, and dust particles.

[0068] The sensor panel ISP may be formed on the display panel DP through a continuous process. In this case, the sensor panel ISP may be described as being directly configured on the display panel DP. The description of direct configuration may mean that no third-party component is configured between the sensor panel ISP and the display panel DP. That is, no additional bonding member may be configured between the sensor panel ISP and the display panel DP. Alternatively, the sensor panel ISP may be bonded to the display panel DP through a bonding member. The bonding member may include a common bonding agent or adhesive.

[0069] Figure 4 FIG. 1 is a cross-sectional view of a display panel and a sensor panel according to an embodiment of the present invention. Figure 4 In the process of explaining Figure 3 The same reference numerals are given to the components that have been described, and the description thereof will be omitted.

[0070] Reference Figure 4 At least one inorganic layer may be formed on the upper surface of the base layer 110. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed into multiple layers. The multiple inorganic layers may constitute a barrier layer and / or a buffer layer. In this embodiment, the display panel DP is shown to include a buffer layer BFL.

[0071] The buffer layer BFL may improve the bonding force between the base layer 110 and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0072] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the present invention is not limited thereto, and the semiconductor pattern may also include amorphous silicon, low temperature polysilicon, or oxide semiconductor.

[0073] Figure 4 Only a local semiconductor pattern is shown, and semiconductor patterns may also be configured in other areas. The semiconductor patterns may be arranged according to specific rules within the range of the pixel. The electrical properties of the semiconductor pattern may be different depending on whether it is doped or not. The semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be doped at a lower concentration than the first region.

[0074] The conductivity of the first region is greater than that of the second region, and it can substantially act as an electrode or a signal line. The second region can substantially correspond to the active (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be the active of a transistor, another portion can be the source or drain of the transistor, and another portion can be a connecting electrode or a connecting signal line.

[0075] Each pixel may have an equivalent circuit including seven transistors, a capacitor, and a light-emitting element, and the equivalent circuit of the pixel may be deformed into various forms. Figure 4 Schematically shows a transistor 100PC and a light emitting element 100PE included in a pixel.

[0076] The transistor 100PC may include a source SC1, an active electrode A1, a drain electrode D1, and a gate electrode G1. The source SC1, the active electrode A1, and the drain electrode D1 may be formed from a semiconductor pattern. The source SC1 and the drain electrode D1 may extend from the active electrode A1 in opposite directions to each other in a cross section. Figure 4 1 shows a portion of a connection signal line SCL formed from a semiconductor pattern. Although not shown separately, the connection signal line SCL can be electrically connected to the drain D1 of the transistor 100PC on a plane.

[0077] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may be stacked together on a plurality of pixels and cover the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. Not only the first insulating layer 10, but also the insulating layer of the circuit layer 120 described later may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-mentioned substances, but is not limited thereto.

[0078] The gate G1 is disposed on the first insulating layer 10. The gate G1 may be a part of the metal pattern. The gate G1 may overlap the active A1. The gate G1 may be used as a mask in the process of doping the semiconductor pattern.

[0079] The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the gate G1. The second insulating layer 20 may be stacked together on the pixel. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In the present embodiment, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0080] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may have a single layer or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0081] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 penetrating the first, second and third insulating layers 10, 20 and 30.

[0082] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single-layer silicon oxide layer. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0083] The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40 and the fifth insulating layer 50.

[0084] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and cover the second connection electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0085] The light emitting element layer 130 may be disposed on the circuit layer 120. The light emitting element layer 130 may include a light emitting element 100PE. For example, the light emitting element layer 130 may include an organic light emitting substance, a quantum dot, a quantum rod, a micro-LED, or a nano-LED. In the following, although the light emitting element 100PE is an organic light emitting element, it is not particularly limited thereto.

[0086] The light emitting element 100PE may include: a first electrode AE, a light emitting layer EL and a second electrode CE. The first electrode AE ​​may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a contact hole CNT-3 penetrating the sixth insulating layer 60.

[0087] The pixel definition film 70 may be disposed on the sixth insulating layer 60 and cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel definition film 70. The opening 70-OP of the pixel definition film 70 exposes at least a portion of the first electrode AE.

[0088] The first active area F-AA (see Figure 1 ) and the second active area R-AA (refer to Figure 2) may include a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA. In the present embodiment, the light emitting region PXA is defined to correspond to a portion of the first electrode AE ​​exposed through the opening 70-OP.

[0089] The light-emitting layer EL may be disposed on the first electrode AE. The light-emitting layer EL may be disposed in a region corresponding to the opening 70-OP. That is, the light-emitting layer EL may be formed separately in each pixel. In the case where the light-emitting layer EL is formed separately in each pixel, each light-emitting layer EL may emit light of at least one color of blue, red, and green. However, this is not limited thereto, and the light-emitting layers EL may also be connected together and provided to the pixel together. In this case, the light-emitting layer EL may provide blue light, or may also provide white light.

[0090] The second electrode CE may be disposed on the light emitting layer EL. The second electrode CE may have an integral shape and be commonly disposed in a plurality of pixels.

[0091] Although not shown, a hole control layer may be disposed between the first electrode AE ​​and the light-emitting layer EL. The hole control layer may be disposed on the light-emitting region PXA and the non-light-emitting region NPXA. The hole control layer may include a hole transport layer and may further include a hole injection layer. An electron control layer may be disposed between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer. The hole control layer and the electron control layer may be formed together in a plurality of pixels using an open mask.

[0092] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may include an inorganic layer, an organic layer, and an inorganic layer stacked in sequence, but the layers constituting the encapsulation layer 140 are not limited thereto.

[0093] The inorganic layer can protect the light emitting element layer 130 from moisture and oxygen, and the organic layer can protect the light emitting element layer 130 from impurities such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include an acrylic organic layer, but is not limited thereto.

[0094] The sensor panel ISP may include a base insulating layer 201 , a first conductive layer 202 , a sensing insulating layer 203 , a second conductive layer 204 , and a cover insulating layer 205 .

[0095] The base insulating layer 201 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride and silicon oxide. Alternatively, the base insulating layer 201 may also be an organic layer including epoxy resin, acrylic resin or imide resin. The base insulating layer 201 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0096] Each of the first conductive layer 202 and the second conductive layer 204 may have a single-layer structure, or a multi-layer structure stacked along the third direction DR3.

[0097] The conductive layer of the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or their alloys. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, graphene, etc.

[0098] The conductive layer of the multi-layer structure may include a metal layer. The metal layer may have a three-layer structure of titanium / aluminum / titanium, for example. The conductive layer of the multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0099] At least one of the sensing insulating layer 203 and the cap insulating layer 205 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0100] At least one of the sensing insulating layer 203 and the cover insulating layer 205 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0101] Figure 5 It is a diagram for explaining a schematic structure of a display device according to an embodiment of the present invention. Figure 6 FIG. 1 is a side view of a display device according to an embodiment of the present invention.

[0102] Reference Figure 5 and Figure 6, the display device 1000 may include: a flexible circuit board CF, a display driving circuit TED, a voltage generator PMIC, a first display panel DP1 and a second display panel DP2.

[0103] The first display panel DP1 and the second display panel DP2 may be connected to the display panel DP (refer to Figure 4 )correspond.

[0104] The first display panel DP1 may be aligned with the first display surface FS (see Figure 1 That is, the first active area AA1 (refer to Figure 7 ) can be connected with the first display surface FS (refer to Figure 1 )correspond.

[0105] The second display panel DP2 may be aligned with the second display surface RS (see Figure 2 That is, the second effective area AA2 (refer to Figure 7 ) can be connected with the second display surface RS (refer to Figure 2 )correspond.

[0106] The second display panel DP2 may be spaced apart from the first display panel DP1. The area of ​​the first display panel DP1 may be greater than the area of ​​the second display panel DP2.

[0107] The flexible circuit board CF according to an embodiment of the present invention may include a flexible printed circuit board (FPCB).

[0108] A display driving circuit TED and a voltage generator PMIC may be installed on the flexible circuit board CF. For example, the display driving circuit TED and the voltage generator PMIC may be configured on the flexible circuit board CF in a chip on film (COF) manner. The display driving circuit TED may drive the first display panel DP1 and the second display panel DP2. The voltage generator PMIC may control the switching of each of the first display panel DP1 and the second display panel DP2. As the flexible circuit board CF is bent, the first display panel DP1 and the second display panel DP2 may face each other, so that the display driving circuit TED may be configured between the first display panel DP1 and the second display panel DP2.

[0109] Figure 7 is a block diagram of a display device according to an embodiment of the present invention.

[0110] Reference Figure 7, the display device 1000 may include: a display driving circuit TED, a voltage generator PMIC, a first display panel DP1 and a second display panel DP2. The display driving circuit TED may include a driving controller TC and a data driver DC.

[0111] The driving controller TC may receive the image signal RGB and the control signal CTRL from the main controller (eg, microcontroller). The driving controller TC may output the image data signal DS by adjusting the grayscale level of the image signal RGB. The first display panel DP1 and the second display panel DP2 may be driven based on the image data signal DS.

[0112] The driving controller TC may generate a scan control signal SCS, a first scan start signal SSP1, a second scan start signal SSP2, and a data control signal DCS based on the control signal CTRL. The driving controller TC may output a power control signal VCS for controlling the voltage generator PMIC. The driving controller TC may control the data driver DC according to the data control signal DCS.

[0113] The data driver DC may receive a data control signal DCS and an image data signal DS from a driving controller TC. The data driver DC may transform the image data signal DS into a data signal Vdata. The data signal Vdata may include a first data signal Vdata1 and a second data signal Vdata2. The data driver DC outputs the first data signal Vdata1 and the second data signal Vdata2 to a plurality of signal transmission lines SL1, SL2 to SLm (m is a natural number greater than 1). Each of the first data signal Vdata1 and the second data signal Vdata2 is an analog voltage corresponding to a grayscale value of the image data signal DS.

[0114] The data driver DC may provide the first data signal Vdata1 and the second data signal Vdata2 to the plurality of first data lines DL11, DL12 to DL1m electrically connected to the first display panel DP1 and the plurality of second data lines DL21, DL22 to DL2m electrically connected to the second display panel DP2 through the plurality of signal transmission lines SL1, SL2 to SLm. That is, the first display panel DP1 and the second display panel DP2 may share the plurality of signal transmission lines SL1, SL2 to SLm, and the first data signal Vdata1 and the second data signal Vdata2 may be provided to each of the first display panel DP1 and the second display panel DP2 through the plurality of signal transmission lines SL1, SL2 to SLm.

[0115] The plurality of signal transmission lines SL1, SL2 to SLm may be electrically connected to each of the plurality of first data lines DL11, DL12 to DL1m and the plurality of second data lines DL21, DL22 to DL2m. That is, the plurality of signal transmission lines SL1, SL2 to SLm, the plurality of first data lines DL11, DL12 to DL1m and the plurality of second data lines DL21, DL22 to DL2m may be connected to each other.

[0116] Each of the first display panel DP1 and the second display panel DP2 may be electrically connected to the driving controller TC, the data driver DC, and the voltage generator PMIC.

[0117] The first display panel DP1 may include: a first scan driver SD1, a plurality of first scan lines SCL11, SCL12, SCL13, a plurality of first data lines DL11, DL12~DL1m and a first pixel PX1, and the second display panel DP2 may include: a second scan driver SD2, a plurality of second scan lines SCL21, SCL22, SCL23, a plurality of second data lines DL21, DL22~DL2m and a second pixel PX2.

[0118] The first scan driver SD1 and the second scan driver SD2 may receive a scan control signal SCS from the drive controller TC. The scan control signal SCS may include a clock signal provided to each of the plurality of shift registers of the first scan driver SD1 and the second scan driver SD2. Furthermore, the scan control signal SCS may provide a gate high level voltage (referred to as VGH) and a gate low level voltage (referred to as VGL) to the first scan driver SD1 and the second scan driver SD2. The gate high level voltage may refer to a high level voltage of a gate signal, and the gate low level voltage may refer to a low level voltage of a gate signal. The scan control signal SCS may be provided to the first scan driver SD1 and the second scan driver SD2 in common.

[0119] The first scan driver SD1 may receive a first scan start signal SSP1 from the driving controller TC. The second scan driver SD2 may receive a second scan start signal SSP2 from the driving controller TC.

[0120] The first scan driver SD1 may include a plurality of first shift registers SR1 that are sequentially driven. Figure 7 Although three first shift registers SR1 are exemplarily shown in FIG. 1 , the number of the first shift registers of an embodiment of the present invention is not limited thereto. For example, the number of the plurality of first shift registers SR1 can be appropriately provided according to the size of the area of ​​the first active area AA1 .

[0121] The driving controller TC may provide a first scanning start signal SSP1 and the corresponding clock signal to a first first shift register among the plurality of first shift registers SR1. The first first shift register may receive the first scanning start signal SSP1 as a carry signal. When the first scanning start signal SSP1 and the scanning control signal SCS are provided to the first first shift register, the first first shift register may provide a 1-1th scanning signal to the first pixel PX1 through the first scanning line SCL11.

[0122] A second first shift register among the plurality of first shift registers SR1 may be connected to the first first shift register. The second first shift register may receive the 1-1 scanning signal as a carry signal. When the 1-1 scanning signal and the corresponding clock signal are provided to the second first shift register, the second first shift register may provide the 1-2 scanning signal to the first pixel PX1 through the first scanning line SCL12.

[0123] A third first shift register among the plurality of first shift registers SR1 may be connected to the second first shift register. The third first shift register may receive the 1-2 scan signal as a carry signal. When the 1-2 scan signal and the corresponding clock signal are provided to the third first shift register, the third first shift register may provide the 1-3 scan signal to the first pixel PX1 through the first scan line SCL13.

[0124] That is, the first scan driver SD1 may output a plurality of first scan signals to the plurality of first scan lines SSL11 ˜ SSL13 in response to the scan control signal SCS and the first scan start signal SSP1 . The first scan driver SD1 may operate according to whether the first scan start signal SSP1 is provided.

[0125] The second scan driver SD2 may include a plurality of second shift registers SR2 that are sequentially driven. Figure 7 Although three second shift registers SR2 are exemplarily shown in the figure, the number of the second shift registers in one embodiment of the present invention is not limited thereto. For example, the number of the plurality of second shift registers SR2 can be appropriately provided according to the size of the area of ​​the second effective area AA2. Figure 7 The number of multiple first shift registers SR1 and the number of multiple second shift registers SR2 are shown as the same, but the area of ​​the first effective area AA1 of one embodiment of the present invention can be larger than the area of ​​the second effective area AA2, and thus, the number of multiple first shift registers SR1 can be greater than the number of multiple second shift registers SR2.

[0126] The driving controller TC can provide a second scanning start signal SSP2 and the corresponding clock signal to a first second shift register among the plurality of second shift registers SR2. The first second shift register can receive the second scanning start signal SSP2 as a carry signal. When the second scanning start signal SSP2 and the scanning control signal SCS are provided to the first second shift register, the first second shift register can provide a 2-1 scanning signal to the second pixel PX2 through the second scanning line SCL21.

[0127] A second second shift register among the plurality of second shift registers SR2 may be connected to the first second shift register. The second second shift register may receive the 2-1st scanning signal as a carry signal. When the 2-1st scanning signal and the corresponding clock signal are provided to the second second shift register, the second second shift register may provide the 2-2nd scanning signal to the second pixel PX2 through the second scan line SCL22.

[0128] A third second shift register among the plurality of second shift registers SR2 may be connected to the second second shift register. The third second shift register may receive the 2-2 scan signal as a carry signal. When the 2-2 scan signal and the corresponding clock signal are provided to the third second shift register, the third second shift register may provide the 2-3 scan signal to the second pixel PX2 through the second scan line SCL23.

[0129] That is, the second scan driver SD2 may provide a plurality of second scan signals to the plurality of second scan lines SSL21 ˜ SSL23 in response to the scan control signal SCS and the second scan start signal SSP2 . The second scan driver SD2 may operate according to whether the second scan start signal SSP2 is provided.

[0130] The first display panel DP1 may provide a first data signal Vdata1 to the first pixel PX1. The first data signal Vdata1 may be transmitted to the first pixel PX1 through a plurality of data lines DL11, DL12 to DL1m.

[0131] The first pixel PX1 may emit light according to the first scan signal and the first data signal Vdata1 .

[0132] The second display panel DP2 may provide the second data signal Vdata2 to the second pixel PX2. The second data signal Vdata2 may be transmitted to the second pixel PX2 through a plurality of data lines DL21, DL22 to DL2m.

[0133] The second pixel PX2 may emit light according to the second scan signal and the second data signal Vdata2.

[0134] According to the present invention, the first data signal Vdata1 and the second data signal Vdata2 can be provided to the first display panel DP1 and the second display panel DP2 through a plurality of signal transmission lines SL1, SL2~SLm. Thus, the first data signal Vdata1 can be provided to each of the first display panel DP1 and the second display panel DP2 at the same time. At this time, even if the first data signal Vdata1 is provided to the second display panel DP2, the second scan start signal SSP2 can be used to control so that the plurality of second scan signals cannot be provided to the second display panel DP2, so that the second pixel PX2 does not emit light corresponding to the first data signal Vdata1. That is, the second display panel DP2 may not provide an image corresponding to the first data signal Vdata1. That is, the display device 1000 can easily drive the plurality of display panels DP1 and DP2 using one display drive circuit TED. Therefore, the internal space of the display device 1000 can be saved.

[0135] Furthermore, according to the present invention, the second data signal Vdata2 can be provided to each of the first display panel DP1 and the second display panel DP2 at the same time. At this time, even if the second data signal Vdata2 is provided to the first display panel DP1, the first scan start signal SSP1 can be used to control so that the plurality of first scan signals cannot be provided to the first display panel DP1, so that the first pixel PX1 does not emit light corresponding to the second data signal Vdata2. That is, the display device 1000 can easily drive the plurality of display panels DP1 and DP2 using one display driving circuit TED.

[0136] The first display panel DP1 may define a first active area AA1 and a first non-active area NAA1. The first active area AA1 may be adjacent to the first active area F-AA (see Figure 1 ), the first non-active area NAA1 may overlap with the first peripheral area F-NAA (refer to Figure 1 The first pixel PX1 may be disposed in the first active area AA1, and the first scan driver SD1 may be disposed in the first non-active area NAA1.

[0137] The second display panel DP2 may be defined with a second active area AA2 and a second non-active area NAA2. The second active area AA2 may be aligned with the second active area R-AA (see Figure 2 ) overlaps, the second non-active area NAA2 may overlap with the second peripheral area R-NAA (refer to Figure 2The second pixel PX2 may be disposed in the second active area AA2, and the second scan driver SD2 may be disposed in the second non-active area NAA2.

[0138] The voltage generator PMIC may receive a power control signal VCS from the driving controller TC. The voltage generator PMIC may generate voltages required for the actions of the first display panel DP1 and the second display panel DP2 according to the power control signal VCS. In one embodiment of the present invention, the voltage generator PMIC may generate a first driving voltage ELVDD1 and a first power supply voltage ELVSS1 required for the actions of the first display panel DP1, and may generate a second driving voltage ELVDD2 and a second power supply voltage ELVSS2 required for the actions of the second display panel DP2.

[0139] When the voltage generator PMIC supplies the first driving voltage ELVDD1 and the first power supply voltage ELVSS1 to the first display panel DP1, the first display panel DP1 may be in an on state. When the voltage generator PMIC supplies the second driving voltage ELVDD2 and the second power supply voltage ELVSS2 to the second display panel DP2, the second display panel DP2 may be in an on state.

[0140] When the voltage generator PMIC does not provide the first driving voltage ELVDD1 and the first power voltage ELVSS1 to the first display panel DP1, the first display panel DP1 may be in an off state. When the voltage generator PMIC does not provide the second driving voltage ELVDD2 and the second power voltage ELVSS2 to the second display panel DP2, the second display panel DP2 may be in an off state. That is, the voltage generator PMIC may control the on and off of each display panel in the first display panel DP1 and the second display panel DP2 according to the power control signal VCS.

[0141] Figure 8 It is a waveform diagram for explaining the operation of the display device according to one embodiment of the present invention.

[0142] Reference Figure 7 and Figure 8 , each of the first display panel DP1 and the second display panel DP2 may be driven using a plurality of frames FR.

[0143] The plurality of frames FR may include a first frame FR1, a second frame FR2, and a third frame FR3. The operation of the display device 1000 during the first frame FR1 may be different from the operation of the display device 1000 during the second frame FR2.

[0144] The control signal CTRL may include a vertical synchronization signal Vsync. One frame FR may be defined as a period from a falling edge of the vertical synchronization signal Vsync to a next falling edge. However, this is merely exemplary, and the definition of a frame FR of an embodiment of the present invention is not limited thereto. For example, one frame FR may also be defined as a period from a rising edge of the vertical synchronization signal Vsync to a next rising edge.

[0145] The driving controller TC may control the first scanning start signal SSP1 and the second scanning start signal SSP2 in units of a plurality of frames FR. For example, the driving controller TC may provide each of the first scanning start signal SSP1 and the second scanning start signal SSP2 separately or alternately or not.

[0146] The voltage generator PMIC may provide a voltage for driving the first display panel DP1 and the second display panel DP2 according to a power control signal VCS. The power control signal VCS may include a first switch signal DP1 on / off and a second switch signal DP2 on / off. The voltage generator PMIC may control the power of the first display panel DP1 and / or the second display panel DP2 in units of a plurality of frames FR.

[0147] If the first switch signal DP1 on / off is at an active level, the first display panel DP1 may be provided with the first driving voltage ELVDD1 and the first power voltage ELVSS1. At this time, the first display panel DP1 may be in an on state. For example, the active level of the first switch signal DP1 on / off may be a high level.

[0148] If the first switch signal DP1 on / off is at an inactive level, the first display panel DP1 may not be provided with a driving voltage ELVDD1 and a first power voltage ELVSS1. At this time, the first display panel DP1 may be in an off state. For example, the inactive level of the first switch signal DP1 on / off may be a low level.

[0149] If the second switch signal DP2 on / off is at an active level, the second display panel DP2 may be provided with a second driving voltage ELVDD2 and a second power voltage ELVSS2. At this time, the second display panel DP2 may be in an on state. For example, the active level of the second switch signal DP2 on / off may be a high level.

[0150] If the second switch signal DP2 on / off is an inactive level, the second drive voltage ELVDD2 and the second power voltage ELVSS2 may not be provided to the second display panel DP2. At this time, the second display panel DP2 may be in an off state. For example, the inactive level of the second switch signal DP2 on / off may be a low level.

[0151] The data driver DC may send a data signal Vdata to a plurality of first data lines DL11, DL12 to DL1m. The data signal Vdata may include a first data signal Vdata1 and a second data signal Vdata2. The data driver DC may control the first data signal Vdata1 and / or the second data signal Vdata2 in units of a plurality of frames FR. For example, the data driver DC may provide each of the first data signal Vdata1 and the second data signal Vdata2 separately or alternately or not.

[0152] The display driving circuit TED according to an embodiment of the present invention may drive the first display panel DP1 and the second display panel DP2 using one of the first mode MD1 , the second mode MD2 and the third mode MD3 .

[0153] The first mode MD1 may be a mode in which the first switching signal DP1 on / off is at an active level and the second switching signal DP2 on / off is at an inactive level. That is, the first mode MD1 may be referred to as a first display panel DP1 single driving mode.

[0154] In the first mode MD1, the first display panel DP1 is turned on and the second display panel DP2 is turned off, and the display driving circuit TED can drive at least one frame FR among the multiple frames FR of the first display panel DP1 as the first frame FR1. The display driving circuit TED can also drive one frame FR among the multiple frames FR of the first display panel DP1 as the third frame FR3.

[0155] The first frame FR1 may be a frame for driving the first display panel DP1.

[0156] During the first frame FR1, the first scan start signal SSP1 may rise. The first scan driver SD1 may output the first scan signal to the first display panel DP1. During the first frame FR1, the data driver DC may send the first data signal Vdata1 to the plurality of first data lines DL11, DL12 to DL1m. The first display panel DP1 may be driven according to the first data signal Vdata1 and the first scan signal. That is, the display driving circuit TED may send the first data signal Vdata1 corresponding to the first display panel DP1 to the plurality of first data lines DL11, DL12 to DL1m during the first frame FR1.

[0157] At this time, the first data signal Vdata1 can also be provided to the second display panel DP2 through multiple second data lines DL21, D22~DL2m, but since the second scan start signal SSP2 does not rise during the first frame FR1, the second scan signal will not be provided to the second display panel DP2, so the first data signal Vdata1 will not drive the second display panel DP2.

[0158] The third frame FR3 may be a frame in which the first display panel DP1 and the second display panel DP2 are not driven. The third frame FR3 may be called a blank interval. The third frame FR3 may be used to control the driving frequency of the first display panel DP1 or the second display panel DP2.

[0159] In the case where one frame FR has 120 Hz (hertz), and the first frame FR1 and the third frame FR3 are alternately provided during the first mode MD1, the driving frequency of the first display panel DP1 may be 60 Hz. However, this is merely exemplary, and the driving frequency of the first display panel DP1 of an embodiment of the present invention may be controlled according to the providing cycle of the first frame FR1. For example, in the case where the first frame FR1 is continuous during the first mode MD1, the driving frequency of the first display panel DP1 may be 120 Hz.

[0160] Also, when one frame FR has 240 Hz and the first frame FR1 and the third frame FR3 are alternately provided during the first mode MD1, the driving frequency of the first display panel DP1 may be 120 Hz. Also, when the first frame FR1 is continuous during the first mode MD1, the driving frequency of the first display panel DP1 may be 240 Hz.

[0161] The second mode MD2 may be a mode in which the first switch signal DP1 on / off is an inactive level and the second switch signal DP2 on / off is an active level. That is, the second mode MD2 may be referred to as a second display panel DP2 separate driving mode.

[0162] In the second mode MD2, the first display panel DP1 is turned off and the second display panel DP2 is turned on, and the display driving circuit TED can drive at least one frame FR among the multiple frames FR of the second display panel DP2 as the second frame FR2. The display driving circuit TED can also drive one frame FR among the multiple frames FR of the second display panel DP2 as the third frame FR3.

[0163] The second frame FR2 may be a frame for driving the second display panel DP2.

[0164] During the second frame FR2, the second scan start signal SSP2 may rise. The second scan driver SD2 may output a second scan signal to the second display panel DP2. The second scan signal may be different from the first scan signal. During the second frame FR2, the data driver DC may send a second data signal Vdata2 to a plurality of second data lines DL21, D22 to DL2m. The second display panel DP2 may be driven according to the second data signal Vdata2 and the second scan signal. That is, the display driving circuit TED may send a second data signal Vdata2 corresponding to the second display panel DP2 to a plurality of second data lines DL21, D22 to DL2m during the second frame FR2.

[0165] At this time, the second data signal Vdata2 can also be provided to the first display panel DP1 through multiple first data lines DL11, D12~DL1m, but since the first scan start signal SSP1 does not rise during the second frame FR2, the first scan signal will not be provided to the first display panel DP1, so the second data signal Vdata2 will not drive the first display panel DP1.

[0166] The first scanning start signal SSP1 and the second scanning start signal SSP2 may not rise together during one frame FR. That is, the first scanning start signal SSP1 and the second scanning start signal SSP2 may not overlap each other.

[0167] In the case where one frame FR has 120 Hz (hertz), and the second frame FR2 and the third frame FR3 are alternately provided during the second mode MD2, the driving frequency of the second display panel DP2 may be 60 Hz. However, this is merely exemplary, and the driving frequency of the second display panel DP2 of an embodiment of the present invention may be controlled according to the providing cycle of the second frame FR2. For example, in the case where the second frame FR2 is continuous during the second mode MD2, the driving frequency of the second display panel DP2 may be 120 Hz.

[0168] Also, when one frame FR has 240 Hz and the second frame FR2 and the third frame FR3 are alternately provided during the second mode MD2, the driving frequency of the second display panel DP2 may be 120 Hz. Also, when the second frame FR2 is continuous during the second mode MD2, the driving frequency of the second display panel DP2 may be 240 Hz.

[0169] The third mode MD3 may be a mode in which the first switch signal DP1 on / off is at an active level and the second switch signal DP2 on / off is at an active level. That is, the third mode MD3 may be referred to as a mode in which the first display panel DP1 and the second display panel DP2 are driven simultaneously.

[0170] In the third mode MD3, the first display panel DP1 is turned on and the second display panel DP2 is turned on, and the display driving circuit TED can drive the first display panel DP1 and the second display panel DP2 respectively using the first frame FR1 and the second frame FR2. The display driving circuit TED can also drive multiple frames FR of the first display panel DP1 and the second display panel DP2 as the third frame FR3.

[0171] In the case where one frame FR has 120 Hz (hertz), and the first frame FR1 and the second frame FR2 are alternately provided during the third mode MD3, the driving frequency of the first display panel DP1 may be 60 Hz, and the driving frequency of the second display panel DP2 may be 60 Hz. At this time, the first frame FR1 and the second frame FR2 are alternately provided, and the driving frequency of the first display panel DP1 and the driving frequency of the second display panel DP2 may be the same.

[0172] Also, in the case where one frame FR has 240 Hz and the first frame FR1 and the second frame FR2 are alternately provided during the third mode MD3 , the driving frequency of the first display panel DP1 may be 120 Hz, and the driving frequency of the second display panel DP2 may be 120 Hz.

[0173] Unlike the present invention, the existing first display panel can be driven by the first display driving circuit, and the second display panel can be driven separately by the second display driving circuit and the first display panel. However, according to the present invention, the first display panel DP1 and the second display panel DP2 can be driven by one display driving circuit TED. That is, the display device 1000 can easily drive multiple display panels DP1 and DP2 using one display driving circuit TED. Therefore, the internal space of the display device 1000 can be saved.

[0174] Fig. 9 It is a diagram for explaining a schematic structure of a display device according to an embodiment of the present invention. Fig.10 is a waveform diagram for explaining the operation of a display device according to an embodiment of the present invention. Fig. 9 and Fig.10 In the process of explaining Figure 5 and Figure 8 The same reference numerals are given to the components that have been described, and the description thereof will be omitted.

[0175] Reference Figure 7 , Fig. 9 as well as Fig.10 The display device 1000-1 may include: a first display panel DP1, a second display panel DP2, and a third display panel DP3. The third display panel DP3 may be connected to the display panel DP (refer to Figure 4 )correspond.

[0176] The second display surface RS (refer to Figure 2 ) may be provided in plurality. The second display panel DP2 may be provided in plurality of second display surfaces RS (refer to Figure 2 The third display panel DP3 may overlap with one of the plurality of second display surfaces RS (refer to Figure 2 ) overlaps another display surface in the .

[0177] The data driver DC outputs the data signal Vdata to the plurality of signal transmission lines SL1, SL2 to SLm. The data signal Vdata may further include: a third data signal Vdata3, a fourth data signal Vdata4 and a fifth data signal Vdata5.

[0178] The data driver DC may further provide a third data signal Vdata3, a fourth data signal Vdata4, and a fifth data signal Vdata5 through a plurality of first data lines DL11, DL12-DL1m, a plurality of second data lines DL21, DL22-DL2m, and a plurality of third data lines electrically connected to the third display panel DP3. That is, the first display panel DP1, the second display panel DP2, and the third display panel DP3 may share a plurality of signal transmission lines SL1, SL2-SLm, and the third data signal Vdata3, the fourth data signal Vdata4, and the fifth data signal Vdata5 are provided to each of the first display panel DP1, the second display panel DP2, and the third display panel DP3 through the plurality of signal transmission lines SL1, SL2-SLm.

[0179] The plurality of signal transmission lines SL1, SL2 to SLm may be electrically connected to each of the plurality of first data lines DL11, DL12 to DL1m, the plurality of second data lines DL21, DL22 to DL2m, and the plurality of third data lines. That is, the plurality of signal transmission lines SL1, SL2 to SLm, the plurality of first data lines DL11, DL12 to DL1m, the plurality of second data lines DL21, DL22 to DL2m, and the plurality of third data lines may be connected to each other.

[0180] The third display panel DP3 may include a third scan driver, a plurality of third scan lines, a plurality of third data lines, and third pixels. The third pixels may be different from the first pixels PX1 and the second pixels PX2.

[0181] The third display panel DP3 may be spaced apart from the first display panel DP1 and the second display panel DP2. The area of ​​the second display panel DP2 may be greater than the area of ​​the third display panel DP3.

[0182] A display driving circuit TED and a voltage generator PMIC may be installed on the flexible circuit board CF. The display driving circuit TED may further drive the third display panel DP3. In one embodiment of the present invention, the voltage generator PMIC may also generate a third driving voltage and a third power supply voltage required for the operation of the third display panel DP3, and may also control the switching of the third display panel DP3. As the flexible circuit board CF is bent, the first display panel DP1 may face the second display panel DP2 and the third display panel DP3.

[0183] Each of the first display panel DP1, the second display panel DP2 and the third display panel DP3 may be driven using a plurality of frames FR.

[0184] The plurality of frames FR may include a third frame FR3, a fourth frame FR4, a fifth frame FR5, and a sixth frame FR6. During each of the fourth to sixth frames FR4-FR6, actions of the display device 1000-1 may be different from each other.

[0185] The driving controller TC may also control the third scanning start signal SSP3 in units of a plurality of frames FR. For example, the driving controller TC may provide the first scanning start signal SSP1, the second scanning start signal SSP2 and the third scanning start signal SSP3 individually or alternately or not.

[0186] The voltage generator PMIC may also provide a voltage for driving the third display panel DP3 according to the power control signal VCS. The power control signal VCS may further include a third switch signal DP3on / off. The voltage generator PMIC may control the power of the first display panel DP1, the second display panel DP2 and / or the third display panel DP3 in units of a plurality of frames FR.

[0187] If the third switch signal DP3 on / off is at an active level, the third drive voltage and the third power supply voltage may be provided to the third display panel DP3. At this time, the third display panel DP3 may be in an on state. For example, the active level of the third switch signal DP3 on / off may be a high level.

[0188] If the third switch signal DP3 on / off is an inactive level, the third drive voltage and the third power supply voltage may not be provided to the third display panel DP3. At this time, the third display panel DP3 may be in an off state. For example, the inactive level of the third switch signal DP3 on / off may be a low level.

[0189] The data driver DC may transmit a data signal Vdata to a plurality of signal transmission lines SL1, SL2 to SLm. The data signal Vdata may further include a third data signal Vdata3, a fourth data signal Vdata4, and a fifth data signal Vdata5.

[0190] The data driver DC may control the third data signal Vdata3, the fourth data signal Vdata4, and / or the fifth data signal Vdata5 in units of a plurality of frames FR. For example, the data driver DC may provide the third data signal Vdata3, the fourth data signal Vdata4, and / or the fifth data signal Vdata5 individually, alternately, or not.

[0191] The display driving circuit TED according to an embodiment of the present invention may drive the first display panel DP1 , the second display panel DP2 , and the third display panel DP3 using one of the fourth mode MD4 , the fifth mode MD5 , the sixth mode MD6 , and the seventh mode MD7 .

[0192] The fourth mode MD4 may be a mode in which the third switch signal DP3 on / off is at an active level and the first switch signal DP1 on / off and the second switch signal DP2 on / off are at an inactive level. That is, the fourth mode MD4 may be referred to as a third display panel DP3 single drive mode.

[0193] In the fourth mode MD4, the third display panel DP3 is turned on and the first display panel DP1 and the second display panel DP2 are turned off, and the display driving circuit TED can drive at least one frame FR of the plurality of frames FR of the third display panel DP3 as the fourth frame FR4. Fig.10 The figure shows that the fourth frame FR4 is driven continuously during the fourth mode MD4, but it is not limited thereto. For example, the display driving circuit TED can also drive one frame FR of the plurality of frames FR of the third display panel DP3 as the third frame FR3 in the fourth mode MD4.

[0194] The fourth frame FR4 may be a frame for driving the third display panel DP3.

[0195] During the fourth frame FR4, the third scan start signal SSP3 may rise. The third scan driver may output the third scan signal to the third display panel DP3. During the fourth frame FR4, the data driver DC may send the third data signal Vdata3 to the plurality of third data lines. The third display panel DP3 may be driven according to the third data signal Vdata3 and the third scan signal. That is, the display driving circuit TED may send the third data signal Vdata3 corresponding to the third display panel DP3 to the plurality of third data lines during the fourth frame FR4.

[0196] At this time, the third data signal Vdata3 can also be provided to each display panel in the first display panel DP1 and the second display panel DP2 through multiple first data lines DL11, DL12~DL1m and multiple second data lines DL21, DL22~DL2m. However, since the first and second scan start signals SSP1 and SSP2 do not rise during the fourth frame FR4, the first and second scan signals will not be provided to the first display panel DP1 and the second display panel DP2 respectively, so the third data signal Vdata3 will not drive the first display panel DP1 and the second display panel DP2.

[0197] The driving frequency of the first display panel DP1, the second display panel DP2, or the third display panel DP3 may be controlled using the third frame FR3.

[0198] In the case where the fourth frame FR4 is continuous during the fourth mode MD4, the driving frequency of the third display panel DP3 may be 120 Hz. However, this is merely exemplary, and the driving frequency of the third display panel DP3 of an embodiment of the present invention may be controlled according to the providing period of the fourth frame FR4. For example, in the case where one frame FR has 120 Hz (hertz), and the fourth frame FR4 and the third frame FR3 are alternately provided during the fourth mode MD4, the driving frequency of the third display panel DP3 may be 60 Hz.

[0199] The fifth mode MD5 may be a mode in which the second switch signal DP2 on / off is at an active level and the first switch signal DP1 on / off and the third switch signal DP3 on / off are at an inactive level. That is, the fifth mode MD5 may be referred to as a second display panel DP2 single drive mode.

[0200] In the fifth mode MD5, the second display panel DP2 is turned on and the first display panel DP1 and the third display panel DP3 are turned off, and the display driving circuit TED can drive at least one frame FR among the multiple frames FR of the second display panel DP2 as the fifth frame FR5. The display driving circuit TED can also drive one frame FR among the multiple frames FR of the second display panel DP2 as the third frame FR3.

[0201] The fifth frame FR5 may be a frame for driving the second display panel DP2.

[0202] During the fifth frame FR5, the second scan start signal SSP2 may rise. The second scan driver SD2 may output the second scan signal to the second display panel DP2. During the fifth frame FR5, the data driver DC may send the fourth data signal Vdata4 to the plurality of second data lines DL21, D22 to DL2m. The second display panel DP2 may be driven according to the fourth data signal Vdata4 and the second scan signal. That is, the display driving circuit TED may send the fourth data signal Vdata4 corresponding to the second display panel DP2 to the plurality of second data lines DL21 to DL2m during the fifth frame FR5.

[0203] At this time, the fourth data signal Vdata4 can also be provided to the first display panel DP1 and the third display panel DP3 through multiple first data lines DL11, D12~DL1m and multiple third data lines. However, since the first scan start signal SSP1 and the third scan start signal SSP3 do not rise during the fifth frame FR5, the first scan signal and the third scan signal will not be provided to the first display panel DP1 and the third display panel DP3 respectively, so the fourth data signal Vdata4 will not drive the first display panel DP1 and the third display panel DP3.

[0204] The first, second, and third scan start signals SSP1, SSP2, and SSP3 may not rise together during one frame FR. That is, the first, second, and third scan start signals SSP1, SSP2, and SSP3 may not overlap with each other.

[0205] In the case where one frame FR has 120 Hz (hertz), and the fifth frame FR5 and the third frame FR3 are alternately provided during the fifth mode MD5, the driving frequency of the second display panel DP2 may be 60 Hz. However, this is merely exemplary, and the driving frequency of the second display panel DP2 of an embodiment of the present invention may be controlled according to the providing cycle of the second frame FR2. For example, in the case where the fifth frame FR5 is continuous during the fifth mode MD5, the driving frequency of the second display panel DP2 may be 120 Hz.

[0206] The sixth mode MD6 may be a mode in which the first switch signal DP1 on / off is active level, the second switch signal DP2 on / off is active level, and the third switch signal DP3 on / off is inactive level. That is, the sixth mode MD6 may be called a mode in which the first display panel DP1 and the second display panel DP2 are driven simultaneously.

[0207] In the sixth mode MD6, the first display panel DP1 is turned on and the second display panel DP2 is turned on, and the third display panel DP3 is turned off. The display driving circuit TED can drive the first display panel DP1 and the second display panel DP2 using the sixth frame FR6 and the fifth frame FR5 respectively. The display driving circuit TED can also drive the multiple frames FR of the first display panel DP1 and the second display panel DP2 as the third frame FR3.

[0208] The sixth frame FR6 may be a frame for driving the first display panel DP1.

[0209] During the sixth frame FR6, the first scan start signal SSP1 rises. The first scan driver SD1 may output the first scan signal to the first display panel DP1. During the sixth frame FR6, the data driver DC may send the fifth data signal Vdata5 to the plurality of first data lines DL11-DL1m. The first display panel DP1 may be driven according to the fifth data signal Vdata5 and the first scan signal. That is, the display driving circuit TED may send the fifth data signal Vdata5 corresponding to the first display panel DP1 to the plurality of first data lines DL11, DL12-DL1m during the sixth frame FR6.

[0210] At this time, the fifth data signal Vdata5 can also be provided to the second display panel DP2 and the third display panel DP3 through multiple second data lines DL21, DL22~DL2m and multiple third data lines. However, since the second scan start signal SSP2 and the third scan start signal SSP3 do not rise during the sixth frame FR6, the second scan signal and the third scan signal will not be provided to the second display panel DP2 and the third display panel DP3 respectively. Therefore, the fifth data signal Vdata5 will not drive the second display panel DP2 and the third display panel DP3.

[0211] In the case where one frame FR has 120 Hz (hertz), and the fifth frame FR5 and the sixth frame FR6 are alternately provided during the sixth mode MD6, the driving frequency of the first display panel DP1 may be 60 Hz, and the driving frequency of the second display panel DP2 may be 60 Hz. At this time, the fifth frame FR5 and the sixth frame FR6 are alternately provided, and the driving frequency of the first display panel DP1 and the driving frequency of the second display panel DP2 may be the same.

[0212] The seventh mode MD7 may be a mode in which the first switch signal DP1 on / off and the third switch signal DP3 on / off are active levels and the second switch signal DP2 on / off is inactive levels. That is, the seventh mode MD7 may be called a mode in which the first display panel DP1 and the third display panel DP3 are driven simultaneously.

[0213] In the seventh mode MD7, the first display panel DP1 and the third display panel DP3 are turned on, and the second display panel DP2 can be turned off. The display driving circuit TED can drive the first display panel DP1 and the third display panel DP3 using the sixth frame FR6 and the fourth frame FR4 respectively. The display driving circuit TED can also drive the multiple frames FR of the first display panel DP1 and the second display panel DP2 as the third frame FR3.

[0214] In the case where one frame FR has 120 Hz (hertz), and the fourth frame FR4 and the sixth frame FR6 are alternately provided during the seventh mode MD7, the driving frequency of the first display panel DP1 may be 60 Hz, and the driving frequency of the third display panel DP3 may be 60 Hz. At this time, the fourth frame FR4 and the sixth frame FR6 are alternately provided, and the driving frequency of the first display panel DP1 and the driving frequency of the third display panel DP3 may be the same.

[0215] Unlike the present invention, the existing first display panel can be driven by the first display driving circuit, the second display panel can be driven by the second display driving circuit, and the third display panel can be driven by the third display driving circuit. However, according to the present invention, the first display panel DP1, the second display panel DP2, and the third display panel DP3 can be driven by one display driving circuit TED. That is, the display device 1000-1 can easily drive multiple display panels DP1, DP2, DP3 using one display driving circuit TED. Therefore, the internal space of the display device 1000 can be saved.

[0216] Although the above description is made with reference to the preferred embodiments of the present invention, it is understood by a person skilled in the art or a person of ordinary skill in the art that various modifications and changes may be made to the present invention without departing from the concept of the present invention and the technical scope of the present invention as described in the attached claims. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the attached claims.

Claims

1. A display device, in, include: A first display panel includes a first pixel and a first data line, and is driven using a plurality of frames; A second display panel includes second pixels and second data lines, is driven by a plurality of the frames, and is spaced apart from the first display panel; a display driving circuit, configured to drive the first display panel and the second display panel, and control a plurality of the frames; and a signal transmission line, electrically connected to the first data line, the second data line and the display driving circuit, The plurality of frames include a first frame and a second frame different from the first frame, The display driving circuit sends a first data signal for driving the first display panel to the signal transmission line during the first frame period. The display driving circuit sends a second data signal for driving the second display panel to the signal transmission line during the second frame.

2. The display device according to claim 1, wherein: The first display panel and the second display panel face each other.

3. The display device according to claim 1, wherein: The display driving circuit is arranged between the first display panel and the second display panel.

4. The display device according to claim 1, wherein: The display driving circuit comprises: a data driver connected to the signal transmission line; and A driving controller is used to control the data driver.

5. The display device according to claim 1, wherein: The first display panel includes a first scan driver that outputs a first scan signal during the first frame and provides the first data signal to the first pixel, and the second display panel includes a second scan driver that outputs a second scan signal different from the first scan signal during the second frame and provides the second data signal to the second pixel. The first pixel emits light according to the first scanning signal and the first data signal, and the second pixel emits light according to the second scanning signal and the second data signal. The first scanning driver includes a plurality of first shift registers driven sequentially, and the second scanning driver includes a plurality of second shift registers driven sequentially. The display driving circuit provides a first scan start signal to a first first shift register among the plurality of first shift registers, and provides a second scan start signal different from the first scan start signal to a first second shift register among the plurality of second shift registers.

6. The display device according to claim 5, wherein: The first scan driver outputs the first scan signal according to the first scan start signal, The second scan driver outputs the second scan signal according to the second scan start signal.

7. The display device according to claim 5, wherein: The first scan start signal and the second scan start signal do not overlap.

8. The display device according to claim 1, wherein: Also includes: The voltage generator receives a power control signal from the display driving circuit, and controls the opening and closing of each display panel in the first display panel and the second display panel according to the power control signal.

9. The display device according to claim 1, wherein: The display driving circuit drives the first display panel and the second display panel in one of a first mode, a second mode and a third mode. In the first mode, the first display panel is turned on, the second display panel is turned off, and the display driving circuit drives at least one frame among the plurality of frames as the first frame. In the second mode, the first display panel is turned off, the second display panel is turned on, and the display driving circuit drives at least one frame among the plurality of frames as the second frame. In the third mode, the first display panel is turned on, the second display panel is turned on, and the display driving circuit drives the first display panel and the second display panel respectively using the first frame and the second frame. The first frame and the second frame are provided alternately, and a driving frequency of the first display panel and a driving frequency of the second display panel are the same.

10. The display device according to claim 1, wherein: Also includes: The third display panel includes a third pixel and a third data line, is driven by using a plurality of the frames, and is spaced apart from the first display panel and the second display panel. The display driving circuit is also used to drive the third display panel. The signal transmission line is also electrically connected to the third data line. The plurality of frames further include a third frame different from the first frame and the second frame, The display driving circuit transmits a third data signal for driving the third display panel to the signal transmission line during the third frame.

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