Display driving circuit, host, display system including same, and method of operating display driving circuit

Abstract

A display driving circuit, a host, a display system including the same, and a method of operating the display driving circuit are disclosed. The display driving circuit includes an interface configured to receive a synchronization signal and image data corresponding to each of a plurality of frames from an external source; a data processor configured to receive the image data from the interface and convert the image data; and a timing controller configured to generate an internal control signal for driving the driver circuit based on the synchronization signal and the image data. The internal control signal is configured to be output only when the synchronization signal and a signal corresponding to the image data are input simultaneously, and the panel driving signal is configured to be output when the internal control signal is output.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0128529 filed on September 25, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0034716 filed on March 12, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present disclosure relates to a display driving circuit, a host, a display system including the same, and a method for operating the display driving circuit. Background Art

[0003] The display device includes a display panel that displays an image and a display driving circuit that drives the display panel. The display driving circuit can drive the display panel by receiving image data from a host and applying an image signal corresponding to the received image data to a data line of the display panel. The display device can be implemented in various forms such as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, and an active matrix OLED (AMOLED) display. Summary of the invention

[0004] The present disclosure provides a display system that can mitigate severe image defects in a display panel even when an underrun occurs.

[0005] The present invention relates to a display driving circuit, a host, a display system including the same, and a method for operating the display driving circuit, and more particularly, to the operation of the display driving circuit and the host for alleviating screen defects (screen defects, or picture defects) caused by underload in a display system driven in a video mode.

[0006] The display panel can be produced by a low temperature polycrystalline oxide (LTPO) process. The pixel circuit of the LTPO display panel can be maintained for a long time without loss of image data due to charge leakage. Therefore, the display panel can be driven at a low frame rate. When the display panel is driven at a low frame rate, the power consumption of the interface between the host and the display driving circuit can be reduced, and the display device can operate in video mode. In video mode, image data received from the host can be displayed on the display panel without being stored in the memory.

[0007] In video mode, an external synchronization signal may be applied to a display driving circuit for driving a display panel at a variable refresh rate (VRR), and the display driving circuit may generate a panel driving signal based on the external synchronization signal. However, when the external synchronization signal is being input to the display driving circuit and corresponding data is not input to the display driving circuit, an underrun may occur. When an underrun occurs, severe display distortion may occur.

[0008] A display driving circuit operating in a video mode is provided, the display driving circuit comprising: an interface configured to receive a synchronization signal and image data corresponding to each of a plurality of frames from an external source; a data processor configured to receive the image data from the interface and convert the image data to generate converted image data; and a timing controller configured to generate an internal control signal for driving a driver circuit based on the synchronization signal and the image data, wherein the internal control signal is configured to be output to the driver circuit based on the synchronization signal and a signal corresponding to the image data being simultaneously input, and wherein a panel driving signal is configured to be output to the display panel based on the internal control signal being output to the driver circuit.

[0009] In some examples, a host is provided, the host comprising: an interface configured to: send image data corresponding to each of a plurality of frames to a display driving circuit through a first channel, and send a synchronization signal to the display driving circuit through a second channel; a display processor configured to generate image data; and a synchronization generator configured to generate a synchronization signal, wherein the synchronization generator is further configured to generate a first synchronization signal and a second synchronization signal, wherein the second synchronization signal is different from the first synchronization signal, and when a portion of the image data generated from the display processor is not sent normally, the host is configured to operate in at least one of a first mode or a second mode, the first mode delays the output of a first synchronization signal corresponding to a next frame segment of a segment in which a portion of the image data is not normally received by the display device, and the second mode outputs the first synchronization signal corresponding to a next frame segment of a segment in which a portion of the image data is not normally received by the display device.

[0010] In some examples, a display system operating in a video mode is provided, the display system comprising: a host configured to: send image data corresponding to each of a plurality of frames through a first channel, and send a synchronization signal for synchronizing signals of the host and a display driving circuit through a second channel; and a display driving circuit configured to generate a control signal for driving a display panel based on the synchronization signal and the converted image data, wherein the display driving circuit is further configured to: generate a control signal only when the synchronization signal and the image data are normally input, and output a panel driving signal when the control signal is generated.

[0011] In some examples, a method for operating a display driving circuit is provided, the method comprising: receiving image data and a synchronization signal from a host, confirming whether the image data is normal data, and determining whether to output an internal control signal applied to a driver for driving a display panel based on whether the image data is normal data. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0013] Figure 1 is a block diagram of a display system according to some implementations.

[0014] Figure 2 is a block diagram of a partial configuration of a display device according to some embodiments.

[0015] Figure 3 is a block diagram illustrating a display panel according to some embodiments.

[0016] Figure 4 is based on Figure 3 Circuit diagram of a pixel of some embodiments.

[0017] Figure 5A An example of output image data when an underrun occurs is shown.

[0018] Figure 5B is a diagram illustrating signal driving when an underload occurs.

[0019] Figure 5C and 5D is a diagram illustrating data output when an underrun occurs.

[0020] Fig. 6A and 6B is a timing diagram for driving synchronization signals and pixels according to some embodiments.

[0021] Figure 6C is a timing diagram of operations in a display driving circuit according to some embodiments.

[0022] Figure 7 is a timing chart of the operation of the display system according to the first embodiment.

[0023] Figure 8 is a timing chart of the operation of the display system according to the first embodiment.

[0024] Fig.9A is a diagram showing output of a synchronization signal in the host according to the first embodiment.

[0025] Fig. 9Bis a diagram showing output of a synchronization signal in the host according to the first embodiment.

[0026] Fig.10 is a diagram illustrating a delay of a synchronization signal in the host according to the first embodiment.

[0027] Fig.11 is a timing chart of the operation of the display system according to the second embodiment.

[0028] Fig.12 is a timing chart of the operation of the display system according to the second embodiment.

[0029] Fig.13A is a block diagram of a display system according to some implementations.

[0030] Fig. 13B is a block diagram of a display system according to some implementations.

[0031] Fig.14 is a timing chart of control of application block control signals in the first embodiment.

[0032] Fig.15 is a timing chart of control of application block control signals in the second embodiment.

[0033] Fig.16 is a flow chart of a method of operating a display driving circuit according to some embodiments. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments are described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a block diagram of a display system according to some implementations.

[0036] The display system 10 according to some embodiments may be installed on an electronic device having an image display function. For example, the electronic device may include a smart phone, a tablet personal computer (PC), a portable multimedia player (PMP), a camera, a wearable device, an IoT device, a television, a digital video disk (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, a drone, various medical devices, a navigation device, a global positioning system (GPS) receiver, an advanced driver assistance system (ADAS), an automotive device, furniture, or various measuring devices.

[0037] Reference Figure 1, the display system 10 may include a host 100, a display driving circuit 300, and a display panel 400. In some embodiments, the display driving circuit 300 and the display panel 400 may be implemented as one module, and the module may be referred to as a display device 200. For example, the display driving circuit 300 mounted on a circuit film (such as a tape carrier package (TCP), a chip on film (COF), and a flexible printed circuit (FPC)) may be attached to the display panel 400 using a tape-automated bonding (TAB) method, or may be mounted on a non-display area of ​​the display panel 400 using a chip on glass (COG, also known as wafer-on-glass mounting) or a chip on plastic (COP) method.

[0038] The host 100 may control the overall operation of the display system 10. The host 100 may generate image data IDT to be displayed on the display panel 400, and may transmit the image data IDT to the display driving circuit 300.

[0039] The host 100 may include an application processor, but is not limited thereto. The host 100 may be implemented as various types of processors (such as a central processing unit (CPU), a microprocessor, a multimedia processor, and a graphics processor). In some embodiments, the host 100 may be implemented as an integrated circuit (IC), a mobile application processor (AP), or a system on a chip (SoC).

[0040] The host 100 may include a display processor 110, a sync generator 120, and an interface (I / F) 130. The display processor 110 may control the operation of the display device 200. The display processor 110 may transmit image data IDT to be displayed on the display device 200 to the display device 200 through the interface 130.

[0041] The display processor 110 may generate image data IDT to be displayed on the display panel 400, and may send the image data IDT to the display driving circuit 300. The display panel 400 may display an image in units of frames, and the image data IDT may correspond to each of a plurality of frames. In some embodiments, the display processor 110 may send the image data IDT through the main channel 140. The interface 130 may be connected to the display driving circuit 300 through the main channel 140. The interface 130 may send the image data IDT to the display driving circuit 300 through the main channel 140. Here, the main channel 140 may be described with the same meaning as the main link.

[0042] The host 100 may send the image data IDT to the display driving circuit 300. The host 100 may provide the image data IDT to the display device 200 through the main channel 140 according to the high speed serial interface (HSSI). As an example, the host 100 may provide the image data IDT to the display device 200 according to the mobile industry processor interface (MIPI) standard, but this is only an example and is not necessarily limited thereto. The host 100 may send a synchronization packet for timing control to the display driving circuit 300. In some embodiments, the host 100 may send the synchronization packet to the display driving circuit 300 through the main channel 140.

[0043] The synchronization generator 120 may generate a synchronization signal ss for synchronizing the host 100 with the display driving circuit 300. Specifically, the synchronization signal ss may synchronize an internal clock signal of the display driving circuit 300 with a clock signal generated by the host 100. The synchronization generator 120 may generate the synchronization signal ss based on driving information of the display panel 400. The driving information of the display panel 400 may include a pixel resolution of the display panel 400, a vertical back porch, a vertical front porch, a horizontal back porch, a horizontal front porch, and a frame rate of the display panel 400.

[0044] The synchronization generator 120 may generate a first synchronization signal and a second synchronization signal. The first synchronization signal and the second synchronization signal may be included in the synchronization signal ss. The first synchronization signal may represent a signal indicating the start of a frame (for example, the first synchronization signal may correspond to a start signal of each of a plurality of frames), and the second synchronization signal may represent a signal indicating the start of each horizontal line in the frame. For example, the first synchronization signal may be a modulation signal of a vertical synchronization signal, and the second synchronization signal may be a horizontal synchronization signal.

[0045] The synchronization generator 120 may generate the first synchronization signal and the second synchronization signal differently. In some embodiments, at least one of the pulse width, the number of pulses, and the pulse pattern of the first synchronization signal may be different from at least one of the pulse width, the number of pulses, and the pulse pattern of the second synchronization signal. For example, the synchronization generator 120 may set the duty cycle of the first synchronization signal to be different from the duty cycle of the second synchronization signal. For example, the synchronization generator 120 may generate the first synchronization signal and the second synchronization signal so that the pulse width of the first synchronization signal is smaller than the pulse width of the second synchronization signal. As another example, the synchronization generator 120 may generate two pulses of the first synchronization signal during the horizontal period, and generate one pulse of the second synchronization signal during the horizontal period, but is not limited thereto. The first synchronization signal may be generated differently from the second synchronization signal in various ways.

[0046] The synchronization generator 120 may generate a synchronization signal ss and send the synchronization signal ss to the display driving circuit 300. In some embodiments, the host 100 may send the synchronization signal ss to the display driving circuit 300 through the interface 130. The interface 130 may send the synchronization signal ss to the display driving circuit 300 through the auxiliary channel 150. The interface 130 may be connected to the display driving circuit 300 through the auxiliary channel 150. For example, the host 100 may provide the synchronization signal ss to the display device 200 according to the display port (DP) standard, but this is merely an example and is not necessarily limited thereto.

[0047] When the host 100 generates at least one of the first synchronization signal and the second synchronization signal differently and sends it to the display driving circuit 300, the display driving circuit 300 can control the timing of driving the display panel 400 based on the synchronization signal ss. When an underrun occurs, the host 100 (for example, the synchronization generator 120) according to some embodiments may delay the timing of generating the first synchronization signal by "the number of data lines (or line data) in the section corresponding to the underrun". After the underrun occurs, the host 100 according to some embodiments may determine whether the frame can be sent within the time used to determine whether the next frame can be updated. When the frame cannot be sent, the host 100 may stop sending frame data in the section where the frame is updated by the first synchronization signal of the next section. Therefore, even when an underrun occurs, image quality degradation can be prevented.

[0048] The display driving circuit 300 may convert the image data IDT received from the host 100 into an image signal for driving the display panel 400 , and may supply the image signal to the display panel 400 , thereby displaying an image on the display panel 400 .

[0049] The display driving circuit 300 may operate in a video mode in which the image data IDT is received from the host 100. The display device 200 may display moving images and still images in the video mode. The display driving circuit 300 may control the image data IDT received from the host 100 to be displayed on the display panel 400 in the video mode without storing the image data IDT in the internal memory of the display driving circuit 300.

[0050] The display driving circuit 300 may include an interface 310, a display controller 320, and a driver 350. If necessary, the display driving circuit 300 may further include Figure 1 For example, the display driving circuit 300 may further include a memory.

[0051] The display driving circuit 300 may receive the image data IDT through the main channel 140. The interface 310 may be connected to the host 100 through the main channel 140. The interface 310 may receive the image data IDT through the main channel 140. In some embodiments, the interface 130 of the host 100 and the interface 310 of the display driving circuit 300 may include MIPI. The interface 130 of the host 100 and the interface 310 of the display driving circuit 300 may include MIPI and general input / output (GPIO). For example, the synchronization signal ss may be sent from the host 100 to the display driving circuit 300 through the GPIO, but is not limited thereto. The interface 130 of the host 100 and the interface 310 of the display driving circuit 300 may include a display port (DP). In video mode, the image data IDT received through the main channel 140 may be sent to the display controller 320.

[0052] The display controller 320 may control the overall operation of the display driving circuit 300. The display controller 320 may include a data processor (DPU) 330 and a timing controller 340. The data processor 330 may convert the image data IDT and transmit the converted data DATA to the driver 350.

[0053] The display driving circuit 300 may receive the synchronization signal ss through the auxiliary channel 150. The interface 310 may be connected to the host 100 through the auxiliary channel 150. The interface 310 may receive the synchronization signal ss through the auxiliary channel 150. The synchronization signal ss received through the auxiliary channel 150 may be sent to the display controller 320. The synchronization signal ss may be sent to the timing controller 340.

[0054] The timing controller 340 may generate an internal control signal CS for driving the display panel 400 based on the synchronization signal ss received through the auxiliary channel 150. The timing controller 340 may transmit the internal control signal CS to the driver 350.

[0055] The timing controller 340 may generate an internal control signal CS for controlling the driver 350 to drive the display panel 400 based on the synchronization signal ss. The driver 350 may provide voltages to the gate lines and data lines of the display panel 400 in response to the internal control signal CS. Figure 2 and Figure 3 The operations of the timing controller 340 and the driver 350 are described in detail.

[0056] According to some embodiments, the timing controller 340 may control the timing of generating the internal control signal CS based on the synchronization signal ss and the image data IDT. According to some embodiments, the timing controller 340 may control the timing of generating the internal control signal CS so that the internal control signal CS is generated only when the synchronization signal ss and the image data IDT are normally input. According to some embodiments, the timing controller 340 may control the timing of generating the internal control signal CS so that the internal control signal CS is generated only when the synchronization signal ss and the signal corresponding to the image data IDT are received at the same time. Since the start time of the next frame data may change when an underrun occurs, the display driving circuit 300 according to some embodiments may send the corresponding time information to the host 100 so that the frame can be rendered by taking this into consideration.

[0057] The timing controller 340 may receive a synchronization signal ss including a first synchronization signal and a second synchronization signal. The timing controller 340 may distinguish the first synchronization signal from the second synchronization signal. For example, the timing controller 340 may detect a signal having a small pulse width as the first synchronization signal, and detect a signal having a pulse width greater than the first synchronization signal as the second synchronization signal. Since the above description corresponds to an example of distinguishing synchronization signals, the timing controller 340 may distinguish synchronization signals in various ways.

[0058] The display driver circuit 300 may control the components of the display driver circuit 300 based on the synchronization signal ss. In some embodiments, the host 100 may switch the mode of the display system 10, and may send a command for switching the mode of the display driver circuit 300 to the display driver circuit 300. When receiving the command, the display driver circuit 300 may start to switch the mode of the display driver circuit 300, and may control the components of the display driver circuit 300 based on the synchronization signal ss to switch the mode of the display driver circuit 300 from the normal mode to the low power mode or from the low power mode to the normal mode. As another example, the display driver circuit 300 may be turned on or off based on the synchronization signal ss.

[0059] The display panel 400 as a display unit for displaying an actual image may include one of display devices such as a thin film transistor liquid crystal display (TFT-LCD), an organic light emitting diode (OLED) display, a field emission display, and a plasma display panel (PDP) display that receives an electrically transmitted image signal and displays a two-dimensional image. The display panel 400 may be implemented as another type of flat display or a flexible display panel.

[0060] In some embodiments, the display panel 400 may include an LTPO display panel produced by a low temperature polycrystalline oxide (LTPO) process. The display panel 400 may be driven at a low frame rate. In some embodiments, the display panel 400 may be driven at a frame rate of 5 Hz or less. When the display panel 400 is driven at a low frame rate in a video mode, the display system 10 may enter a low power mode. When the display system 10 enters a low power mode, the host 100 and the display driver circuit 300 may also enter a low power mode. When the host 100 enters a low power mode, at least a portion of the components of the host 100 for driving the display panel 400 may be driven at low power or may be disconnected. When the display driver circuit 300 enters a low power mode, at least a portion of the components of the display driver circuit 300 for driving the display panel 400 may be driven at low power or may be disconnected. The low power mode may be maintained for multiple vertical periods. A vertical period may correspond to a frame segment. In the low power mode, the components are driven at low power for multiple vertical periods. Therefore, compared with when driven at low power for multiple horizontal periods, the component can be driven for a longer period of time in the low power mode, thereby reducing power consumption. Although the display system 10 enters the low power mode, the internal clock signal of the display driving circuit 300 and the clock signal generated by the host 100 can be synchronized based on the synchronization signal ss sent through the auxiliary channel 150.

[0061] The display system 10 may include a main channel 140 for transmitting data, and may include an auxiliary channel 150 for transmitting a synchronization signal ss, the synchronization signal ss being used to synchronize the host 100 with the display panel 400. According to some embodiments, the synchronization signal ss may include a modified first synchronization signal notifying the start of a frame, and when an underload occurs, the host 100 may be controlled to change the time of generating the first synchronization signal. According to some embodiments, when an underload occurs and frame data is transmitted within the frame beyond the requested transmission time, the host 100 may be controlled to stop transmitting the frame data in a frame section after the underload (i.e., when updating the next frame data). The display driving circuit 300 may generate an internal control signal CS only when the synchronization signal ss and the frame data are input simultaneously, and may output a panel driving signal DCS based on the internal control signal CS. Although an underload occurs, severe image defects in the panel may be mitigated by queuing the panel driving signal DCS instead of advancing the panel driving signal DCS.

[0062] Figure 2 is a block diagram of a partial configuration of a display device according to some embodiments. Figure 2 The display controller 320, the timing controller (TCON) 340, the data processor 330, the drivers 351 and 352, and the display panel 400 are respectively connected to Figure 1The display controller 320, the timing controller 340, the data processor 330, the driver 350 and the display panel 400 correspond to each other, so their repeated descriptions may be omitted.

[0063] Reference Figure 1 and Figure 2 , the driver 350 may include a scan driver 351 and a data driver 352 (or drivers 351 and 352 ). However, the display driving circuit 300 may not include the scan driver 351 , and the scan driver 351 may be included in the display device 200 as a separate configuration from the display driving circuit 300 .

[0064] The display panel 400 may include a plurality of pixels PX arranged in a matrix form and may display an image in units of frames. The display panel 400 may include scan lines SL1 to SLn arranged in a row direction, data lines DL1 to DLm arranged in a column direction, and pixels PX formed at intersections of the scan lines SL1 to SLn and the data lines DL1 to DLm.

[0065] The scan driver 351 may sequentially select the pixels PX by sequentially applying scan signals to the pixels PX on a line-by-line basis. The scan driver 351 may sequentially select the scan lines SL1 to SLn by sequentially supplying scan-on signals to the scan lines SL1 to SLn in response to the scan control signal CTRL1 provided from the timing controller 340. The scan lines SL1 to SLn may be sequentially selected according to the scan-on signals output from the scan driver 351. When a grayscale voltage corresponding to the pixel PX is applied to the pixel PX connected to the selected scan line through the data lines DL1 to DLm, a display operation may be performed. During a period in which the scan-on signal is not supplied to the scan lines SL1 to SLn, a scan-off signal (e.g., a scan voltage at a logic high level) may be supplied to the scan lines SL1 to SLn.

[0066] The data driver 352 may convert data DATA corresponding to the image data IDT into an image signal as an analog signal in response to the data control signal CTRL2, and may provide the image signal to the data lines DL1 to DLm. The data driver 352 may include a plurality of channel amplifiers, wherein each of the plurality of channel amplifiers may provide the image signal to at least one corresponding data line. According to some embodiments, the signals transmitted through the scan lines SL1 to SLn and the data lines DL1 to DLm may be connected to the image signal. Figure 1 The panel driving signal DCS corresponds to.

[0067] The timing controller 340 may control the overall operation of the display panel 400. The timing controller 340 may be implemented as hardware, software, or a combination of hardware and software. For example, the timing controller 340 may be implemented as a digital logic circuit and register that performs the following various functions.

[0068] The timing controller 340 may receive the synchronization signal ss and may generate internal control signals (e.g., a scan control signal CTRL1, a data control signal CTRL2, and an emission control signal CTRL3) for controlling the data driver 352 and the scan driver 351 to display the image data IDT on the display panel 400. The timing of generating the internal control signals CTRL1, CTRL2, and the emission control signal CTRL3 may be based on Figure 1 It controls whether the synchronization signal ss and image data IDT are supplied normally.

[0069] The data processor 330 may convert the format of the image data IDT received from the outside of the display driving circuit 300 to comply with the interface specification with the data driver 352 , and may transmit the converted data DATA after the conversion to the data driver 352 .

[0070] Figure 3 is a block diagram illustrating a display panel according to some embodiments. Figure 1 The timing controller 340, the driver 350 and the display panel 400 can be respectively Figure 3 The timing controller 340, the drivers 351, 352 and 353 and the display panel 400a correspond to each other. Figure 3 In the OLED panel is described as Figure 1 An example of a display panel 400 having Figure 2 Repeated description of components with the same reference numerals is omitted.

[0071] Reference Figure 3 , the display panel 400a may include a plurality of data lines DL1 to DLm, a plurality of scan lines SL1 to SLn, a plurality of emission control lines EL1 to ELn, and a plurality of pixels PX' located between the lines. Each of the plurality of pixels PX' may be connected to the scan line, the data line, and the emission control line, and each of the plurality of pixels PX' corresponds to the scan line, the data line, and the emission control line.

[0072] The emission control driver 353 may be connected to a plurality of emission control lines EL1 to ELn, and may sequentially apply emission control signals to the pixels PX' to control the emission time of the pixels PX'. Each of the pixels PX' may include a corresponding OLED, and may include a transistor that "supplies a driving current corresponding to an image signal to the OLED or blocks the driving current corresponding to the image signal". The emission control signal provided through each of the plurality of emission control lines EL1 to ELn may control the emission time of the OLED by turning on / off the transistor that "supplies the driving current to the OLED".

[0073] According to some embodiments, signals transmitted through the scan lines SL1 to SLn, the data lines DL1 to DLm, and the emission control lines EL1 to ELn may be connected to Figure 1 The panel driving signal DCS corresponds to.

[0074] The brightness value of each pixel PX' may vary according to the duty cycle of the emission control signal. As the duty cycle of the emission control signal (i.e., the length of the on section of the emission control signal within the cycle of the emission control signal) increases, the time for the pixel PX' to emit light may increase and high brightness may be displayed. In this way, the emission control driver 353 may adjust the brightness of the display panel 400a by adjusting the pulse width modulation (PWM) of the emission control signal under the control of the timing controller 340.

[0075] The timing controller 340 may generate an emission control signal based on the synchronization signal ss to control the emission control driver 353. The timing controller 340 may generate an emission control signal CTRL3 for controlling the emission control driver 353 based on the synchronization signal ss.

[0076] According to some embodiments, the timing of generating the internal control signals CTRL1, CTRL2 and CTRL3 can be based on Figure 1 In some examples, by controlling the generation of the internal control signal only when the synchronization signal ss and the signal corresponding to the image data IDT are input simultaneously, the image quality degradation of the output data is minimized even when underrun occurs.

[0077] Figure 4 is based on Figure 3 Circuit diagram of a pixel of some embodiments. Figure 4 The pixel PX' can be Figure 3 Pixel PX'. In the following, together with Figure 3 and Figure 4 Give a description.

[0078] Reference Figure 4, the pixel PX' may include a switching transistor SX, a driving transistor DX, an emission control transistor EX, a capacitor C and an organic light emitting diode OLED. Figure 4 , but the embodiment is not limited thereto. The number of transistors and the number of capacitors of the pixel PX' may be variously configured.

[0079] A first electrode of the switch transistor SX may be connected to the data line DLm, a gate terminal of the switch transistor SX may be connected to the scan line SLn, and a second electrode of the switch transistor SX may be connected to the first node N 1 The switching transistor SX may be turned on in response to a scan signal Sn transmitted through the scan line SLn to transmit an image signal Dm received through the data line DLm to the first node Nn. 1 .

[0080] The capacitor C may be connected to the first node N 1 The capacitor C can store the first node N in a specific period of time. 1 The organic light emitting diode OLED can utilize the voltage corresponding to the voltage difference between the voltage applied to the first node N by the capacitor C and the first power voltage ELVDD. 1 The organic light emitting diode OLED can be connected between the capacitor C and the ground voltage ELVSS.

[0081] A first electrode of the driving transistor DX may be connected to the emission control transistor EX, and a gate terminal of the driving transistor DX may be connected to a first node N 1 , and the second terminal of the driving transistor DX can be connected to the first power supply voltage ELVDD. Since the gate electrode of the driving transistor DX is connected to the first node N 1 and applied to the first node N 1 The voltage of is maintained by the capacitor C, so the driving transistor DX can be turned on.

[0082] The pixel PX' may include an emission control transistor EX connected between the first electrode of the driving transistor DX and the anode electrode of the organic light emitting diode OLED, and the emission control transistor EX is used to control the time and period when an image is displayed by the light emission of the organic light emitting diode OLED. Specifically, the emission control transistor EX includes a gate electrode connected to the nth emission control line ELn, a second electrode connected to the first electrode of the driving transistor DX, and a first electrode connected to the anode electrode of the organic light emitting diode OLED.

[0083] During a period when the emission control transistor EX is turned on in response to the nth emission control signal En sent through the nth emission control line ELn, a driving current path can be formed between the driving transistor DX and the organic light emitting diode OLED, so that the driving current I flows through the path and the organic light emitting diode OLED can display an image according to the image signal Dm.

[0084] Figure 5A An example of output image data when an underrun occurs is shown.

[0085] Refer to Figure 1 , the host 100 may perform logical operations for computing and system control and various functions (such as multimedia, modem, and memory controller) on a central processing unit (CPU), a graphics processing unit (GPU), and a neural processing unit (NPU). Therefore, various circuit blocks may use common resources (such as memory) through a common bus. When common resources are accessed by different components at the same time, specific components may be queued according to priority. When the DPU is queued, the DPU may not receive data from the memory when the display panel is driven, and may not send image data to the display panel. This may be defined as underload.

[0086] Reference Figure 1 , frame data may be continuously sent from the host 100 to the display driving circuit 300 according to the display timing, but the sending may be temporarily stopped by the internal operation of the host 100, causing underload. When data needs to be sent according to the driving timing of the display panel according to the video mode, serious display distortion may occur from the time when underload occurs. Figure 5A , it can be seen that, since display distortion occurs after under-run occurs, a serious screen defect occurs in which image data is distorted and output for the lower line.

[0087] Figure 5B is a diagram illustrating signal driving when underload occurs.

[0088] Reference Figure 5B After the vertical synchronization signal VSYNC is input, a vertical active section VACTIVE is formed in which data can be substantially input. In the vertical active section VACTIVE, a plurality of horizontal synchronization signals HSYNC can be output at regular intervals, and horizontal line data can be transmitted in a horizontal active section HACT corresponding to the plurality of horizontal synchronization signals HSYNC.

[0089] As in Figure 5BAs in some embodiments of the present invention, when underrun occurs, data may not be transmitted from the time when underrun occurs to the time when data transmission is resumed. Therefore, the horizontal synchronization signal HSYNC and the horizontal line data corresponding to the horizontal synchronization signal HSYNC may not be output.

[0090] Figure 5C and Figure 5D is a diagram illustrating data output when an underrun occurs.

[0091] Figure 5C shows the data output when underrun occurs in the case of data compression processing, and Figure 5D Figure 2 shows the data output when an underrun occurs without data compression processing. Figure 5C and Figure 5D In , the hexagons may indicate that the data has been received normally, and the blanks may indicate that the data has not been received normally. Figure 5C and 5D In the embodiment, a slice (eg, slice 1 to slice 3) may be a compression modulation unit of frame data.

[0092] Reference Figure 5C , when an underrun occurs in the case of a data compression process, data may not be sent at a time when data should be written to a pixel of a corresponding line, and data included in a slice may be pushed back. Therefore, abnormal data may be modulated (or due to an abnormal demodulation process), and a screen defect may be displayed after the underrun occurs. According to some embodiments, unexpected data may be restored during a compression decoding process, and thus an image (such as noise) may appear on the screen.

[0093] Reference Figure 5D , when underrun occurs without data compression processing, data may be pushed back by the corresponding line, causing screen errors (eg, screen tearing or color inversion).

[0094] Fig. 6A and 6B is a timing diagram for driving synchronization signals and pixels according to some embodiments.

[0095] Reference Fig. 6A, discloses a timing diagram of a synchronization signal SS, a data signal of a main link, and a transmission signal. The synchronization signal SS may include a first synchronization signal SS1 and a second synchronization signal SS2. The first synchronization signal SS1 may indicate the start of a frame, or may be generated at a point indicating the time when a light emitting signal starts. According to some embodiments, the second synchronization signal SS2 may be generated at intervals of a horizontal synchronization signal HSYNC between the first synchronization signal SS1 generated in response to a start point of a frame. The second synchronization signal SS2 may be used to generate a panel drive signal. The first synchronization signal SS1 may be obtained by changing a pulse width, a number of pulses, a pulse code, etc. differently from the second synchronization signal SS2.

[0096] exist Fig. 6A and 6B In the disclosure, an example of a synchronization signal SS during normal display operation is disclosed. During normal display operation, a generation period of a vertical synchronization signal VSYNC may be determined by the number of lines of a display and the sum of the number of lines of a preset vertical front VFP segment, a vertical start signal VSS segment, and a vertical back VBP segment. A first synchronization signal SS1 may be modulated according to the time when the vertical synchronization signal VSYNC is generated. The first synchronization signal SS1 may be obtained by modulating the vertical synchronization signal VSYNC.

[0097] Reference Figure 6B For a display panel in which N light emission signals are divided within one frame, the first synchronization signal SS1 may be sent multiple times by dividing the time point of the vertical synchronization signal VSYNC into N equal parts, and emission signals may be generated to correspond to the first synchronization signals SS1 respectively.

[0098] Fig. 6A and 6B The synchronization signal SS shown in can be fixedly transmitted or modulated. Fig. 6A and Figure 6B The synchronization signal SS transmitted from the outside shown in FIG. 1 may be applied to the display driving circuit. In some embodiments, the synchronization signal SS may have the same meaning as the external synchronization signal.

[0099] Figure 6C is a timing diagram of operations in a display driving circuit according to some embodiments.

[0100] exist Figure 6C In the timing diagram of , a hexagon may represent a segment where data corresponding to a line is transmitted. Figure 6C In the timing diagram of , UD may represent an underrun section in which data corresponding to one line is not transmitted.

[0101] In video mode, the line data of the corresponding image should be sent continuously according to the timing of the panel. However, when the DPU is not ready for data at that time, the main link may not send data.

[0102] In the video mode, the display driving circuit may receive an external synchronization signal SS having a cycle level of a horizontal synchronization signal HSYNC to drive the display at a variable refresh rate (VRR), and may generate an internal control signal CS based on the external synchronization signal SS. However, when the external synchronization signal SS is input but is not received due to underrun data, the display panel may cause abnormal screen defects and a very wide screen break.

[0103] Here, in response to a section in which the main link does not transmit data, the internal control signal CS may be queued without generating a clock signal. The timing controller may generate the internal control signal CS only when the start signal of the line data or the line data is completely received from the main link. According to some embodiments, the start signal of the line data may include a horizontal synchronization signal HSYNC or a horizontal start signal HSS. Figure 6C , when the signal corresponding to the data is not applied, the timing controller may control not to generate the internal control signal CS. The synchronization signal may have a default input value, and the control of the generation timing of the internal control signal CS may vary depending on whether the signal corresponding to the data is applied. The control of the generation timing of the synchronization signal to be described below may be intended to easily control the display output after an underload occurs.

[0104] Reference Figure 6C , the internal control signal CS corresponding to the first line data H1 may be output to transition in the next segment of the first line data H1. Here, the next segment of the first line data H1 may be a segment corresponding to the second line data H2 transmitted after the first line data H1.

[0105] Figure 6C The output timing and output waveform of the internal control signal CS shown in FIG. 1 may be examples, and the internal control signal CS may be output to have various waveforms, pulse widths, and pulse numbers in response to the applied line data. According to some embodiments, the internal control signal CS may not be output in a section immediately following the data DATA applied from the data processor 330 and the timing may be delayed. According to some embodiments, as Figure 6C As shown in , the internal control signal CS corresponding to the first line data H1 may be output to transition in the next segment of the first line data H1. Alternatively, the internal control signal CS corresponding to the first line data H1 may be output to transition in a segment delayed longer than the next segment of the first line data H1.

[0106] The timing controller may control the generation of the internal control signal CS only when a signal corresponding to line data and a synchronization signal are simultaneously input. The data driver and the scan driver may operate based on the internal control signal CS, and a normal screen may be output accordingly.

[0107] According to some examples, the display driving circuit may generate a signal for writing data to the panel based only on the synchronization signal. When the signal for writing data to the panel is generated based only on the synchronization signal, the data may not be input due to underload. In this case, the gate signal for the write operation is generated, but the signal that should be stored in the corresponding pixel is not input to the data line. Therefore, unexpected values ​​may be written to the corresponding pixels. When the underload is canceled and the data finally arrives, the data is written behind the corresponding line. Therefore, when underload occurs, a distorted image is displayed on the display. The display driving circuit may control the generation of an internal control signal when the conditions for receiving the synchronization signal and receiving the data through the main link are met at the same time, and control not to generate the internal control signal when the data is not received through the main link even if the synchronization signal is received.

[0108] Figure 7 is a timing chart of the operation of the display system according to the first embodiment.

[0109] Reference Figure 7 , a timing diagram of a synchronization signal SS, data transmitted through a main link, and control signals STV and CLK output from a driver is shown.

[0110] The synchronization signal SS may include a first synchronization signal SS1 and a second synchronization signal SS2. The synchronization signal SS may include an inter-chip interface signal for synchronizing the timing of a host and a display device. According to some embodiments, the synchronization signal SS may be generated in a period of line data (e.g., a period of a horizontal synchronization signal or a fixed period of a similar value). According to some embodiments, the first synchronization signal SS1 may be a modulated signal of a vertical synchronization signal VSYNC, and the second synchronization signal SS2 may be a horizontal synchronization signal HSYNC. According to some embodiments, the first synchronization signal SS1 may be a signal having a modulated waveform that notifies a display driving circuit of a start time of transmitting a signal or scheduling a frame.

[0111] The pulse width W1 of the first synchronization signal SS1 may be smaller than the pulse width W2 of the second synchronization signal SS2. The host may generate the first synchronization signal SS1 and the second synchronization signal SS2 by adjusting the PWM of the synchronization signal SS. The host may set the duty cycle of the first synchronization signal SS1 to be different from the duty cycle of the second synchronization signal SS2. For example, the host may generate the first synchronization signal SS1 and the second synchronization signal SS2 so that the pulse width W1 of the first synchronization signal SS1 is smaller than the pulse width W2 of the second synchronization signal SS2, but is not limited thereto. The host may generate the first synchronization signal SS1 and the second synchronization signal SS2 so that the pulse width W1 of the first synchronization signal SS1 is larger than the pulse width W2 of the second synchronization signal SS2.

[0112] At time point t1, the first synchronization signal SS1 may be changed from a first level to a second level. In some embodiments, the first level may be a logic low level, and the second level may be a logic high level. At each time point t2 to t7, the second synchronization signal SS2 may be changed from a first level to a second level. The second synchronization signal SS2 may be provided with 6 pulses in a first segment corresponding to one frame.

[0113] According to some embodiments, in the first section, one first synchronization signal SS1 and six second synchronization signals SS2 may be provided. The first section may be a section in which image data corresponding to a first frame is received.

[0114] The control signals STV and CLK output from the driver may be generated based on the line image data (or line data) H1, H2, and H3 transmitted through the main link. According to some embodiments, the transition time of the first control signal STV output from the driver may be delayed by a specific time from the input time point t3 of the line image data transmitted through the main link. The transition time of the second control signal CLK output from the driver may be the period of the horizontal synchronization signal HSYNC which is half of the first control signal STV. According to some embodiments, there may be a plurality of horizontal synchronization signals HSYNC between the time when the data is input and the time when the data is actually written to the panel. The first control signal STV may be transformed in consideration of the delay between the time when the data is input and the time when the data is actually written to the panel. The second control signal CLK may be transformed half a period after the first control signal STV. According to some embodiments, the number of pulses of the second control signal CLK in the first segment may correspond to the number of line image data transmitted through the main link. The pulse width, the number of pulses, the pulse period, etc. of the first control signal STV may be different from the pulse width, the number of pulses, the pulse period, etc. of the second control signal CLK. According to some embodiments, the first control signal STV may be a start signal of a shift register included in the driver. According to some embodiments, the second control signal CLK may be a signal for sequentially sending a signal to the next gate. The first control signal STV and the second control signal CLK may be implemented so that the gate signal may be sequentially shifted on a line-by-line basis.

[0115] Reference Figure 7 , the second section may be a section including a case where underrun of image data corresponding to the second frame occurs. When underrun occurs at time point t12 while image data is received through the main link, the third line data H3 may not be transmitted and the third line data H3 may be transmitted at time point t13.

[0116] Reference Figure 7 , the number of pulses of the second synchronization signal SS2 in the second segment may be added to the number of lines where underrun occurs. According to some embodiments, since the number of lines of image data where underrun occurs is 1, the number of pulses of the second synchronization signal SS2 in the second segment may be output as 7. The number of pulses of the second synchronization signal SS2 in the first segment where underrun does not occur may be 6, and the number of pulses of the second synchronization signal SS2 in the second segment where underrun occurs may be 7. By increasing the number of pulses of the second synchronization signal SS2 in the segment where underrun occurs, the start time of the third segment, which is the next frame segment of the second segment, may be delayed by the increased number of pulses of the second synchronization signal SS2. According to some embodiments, the start time of the third segment may be the transition time of the first synchronization signal SS1.

[0117] Reference Figure 7 In the second section of the underloaded section, the second control signal CLK may be controlled not to switch at a time point after the section where the underloaded section occurs. The second control signal CLK may be controlled not to switch at a time point after the section where the underloaded section occurs, thereby preventing the output of the shift register corresponding to the section where the underloaded section occurs from moving to the next stage. In some embodiments (such as, Figure 6C In an embodiment of the present invention, the internal control signal may be controlled not to be output at a time point after the underload section occurs. Since the internal control signal is a control signal for driving the driver, the second control signal CLK corresponding to the internal control signal may not be output at a time point when the internal control signal is not applied.

[0118] Figure 7 The method of controlling the synchronization signal of the host according to the first embodiment is shown. According to the method of controlling the synchronization signal of the host according to the first embodiment, the second synchronization signal SS2 may be additionally output in the segment where the underload occurs "in proportion to the number of line data where the underload occurs". Optionally, the first synchronization signal SS1 (or the modulated VSYNC) of the segment corresponding to the next frame may be delayed by "the number of line data where the underload occurs in the segment where the underload occurs (for example, the number of underload lines)". The method of controlling the synchronization signal of the host according to the first embodiment may be an example of a host operating in the first mode.

[0119] According to the method of controlling the synchronization signal of the host based on the first embodiment, the time point when the start signal of the frame segment after the segment where the underload occurs (i.e., the first synchronization signal SS1) is generated can be delayed by "the number of line data where the underload occurs in the segment where the underload occurs". According to the method of controlling the synchronization signal of the host based on the first embodiment, when a small underload occurs, the frame transmission delay can be small, and the change in screen brightness that may occur due to the underload can be small. In addition, the panel drive signal in the display drive circuit can be implemented to be substantially the same as when the underload does not occur, making the design easier.

[0120] Figure 8 is a timing chart of the operation of the display system according to the first embodiment. Figure 8 The timing diagram of the synchronization signal SS, the main link, the first control signal STV and the second control signal CLK shown in Figure 7 The timing diagrams of the synchronization signal SS, the main link, the first control signal STV, and the second control signal CLK shown in FIG. 1 are similar, so the description of the overlapping configuration is omitted.

[0121] Reference Figure 8 , additional disclosure through Figure 11 is a timing diagram of a plurality of scan signals Sn(0), Sn(1) and Sn(2) applied to a scan line of FIG. 1 . The first scan signal Sn(0) may be changed from a first level to a second level at a time point t4, and may be maintained at the second level from the time point t4 to the time point t5, which is a first transition time of the second control signal CLK. The second scan signal Sn(1) may be changed from a first level to a second level at a time point t5, and may be maintained at the second level from the time point t5 to the time point t6, which is a second transition time of the second control signal CLK. The third scan signal Sn(2) may be changed from a first level to a second level at a time point t6, and may be maintained at the second level from the time point t6 to the time point t7, which is a third transition time of the second control signal CLK. That is, in the first section where the image data is normally applied, the plurality of scan signals Sn(0), Sn(1) and Sn(2) are each activated at the transition time of the second control signal CLK, and the activation may be maintained for a period corresponding to the pulse period of the second control signal CLK.

[0122] Reference Figure 8 In the second section, the second control signal CLK may not switch in the signal section after the section where the underload occurs. In some embodiments (such as, Figure 6C In an embodiment of the present invention, the internal control signal may be controlled not to be output at a time point after the section where the underload occurs. Since the internal control signal is a control signal for driving the driver, when the internal control signal is not applied, the corresponding second control signal CLK may not be output. Therefore, compared with the first section, the activation section t12 to t14 of the corresponding second scan signal Sn(1) may be increased in duration.

[0123] Fig.9A is a diagram showing output of a synchronization signal in the host according to the first embodiment.

[0124] Reference Fig.9A , the synchronization signal SS and image data transmitted on the main link are shown. Fig.9A , the output of the second synchronization signal SS2 can be maintained at the time point t1' when underload occurs. Fig.9A In some embodiments, the second synchronization signal SS2 may be output at the time point t1' when the underrun occurs. The second synchronization signal SS2 may be additionally output in a section corresponding to a frame "in proportion to the number of line data in the section where the underrun occurs".

[0125] Fig. 9B is a diagram showing output of a synchronization signal in the host according to the first embodiment.

[0126] Reference Fig. 9B, showing the synchronization signal SS and image data sent on the main link. Fig. 9B , the second synchronization signal SS2 may not be output at time t2' when underload occurs. Fig. 9B In some embodiments, at time point t2' when underrun occurs, the second synchronization signal SS2 is not output. The second synchronization signal SS2 may be additionally output in a segment corresponding to a frame "in proportion to the number of line data in the segment where underrun occurs". Fig. 9B In some implementations, the number of pulses of the second synchronization signal SS2 in the second segment may be the same as the number of pulses of the second synchronization signal SS2 in the first segment.

[0127] According to some embodiments, the start time of the first synchronization signal SS1 in the next segment may be delayed by the number of line data where underrun occurs, and the “number of the second synchronization signal SS2 in the previous segment” by which the start point of the first synchronization signal SS1 is delayed may be set in various ways.

[0128] Reference Fig.9A and 9B When underload occurs, the line data of the frame and the corresponding horizontal synchronization signal are not sent from the main link. Due to underload, the second synchronization signal SS2 can be continuously sent at the same interval as the non-transmission period of the data ( Fig.9A ), or may not be sent ( Fig. 9B ).

[0129] According to the method for controlling a display system based on the first embodiment, a host and a display driving circuit may include a first channel, a main link, and a second channel, the first channel according to one example being used to send frame data, and the second channel being used to exchange a synchronization signal for timing synchronization between the host and the display driving circuit. When an underrun occurs in image data sent through the first channel and specific line data is not sent, the generation position of the first synchronization signal indicating the start time of a sending segment of the next frame data may be delayed by the number of line segments where the underrun occurs.

[0130] The second synchronization signal at the time when the underrun occurs may be continuously transmitted, or the second synchronization signal at the time when the underrun occurs may not be output.

[0131] Fig.10 is a diagram illustrating a delay of a synchronization signal in the host according to the first embodiment.

[0132] Reference Fig.10 In response to one frame driving section Frame 1 and Frame 2, the synchronization signal SS may include a plurality of first synchronization signals SS1'. The number may be determined according to the number of separate emission signals as driving signals of the display panel, but is not limited thereto.

[0133] Reference Fig.10 , two first synchronization signals SS1' may be implemented in response to one frame driving section Frame 1 and Frame 2. In this case, an example of applying the first embodiment when an under-run occurs is shown.

[0134] Reference Fig.10 When an underload occurs, each first synchronization signal SS1' may be delayed in response to the underload occurrence section. Fig.10 , in response to the first underload occurrence section UD1 (eg, time period T 1 ), the first synchronization signal SS1' may be delayed. In response to the second underload occurrence section UD2 (eg, time period T 2 ), the first synchronization signal SS1' may be delayed. That is, referring to Fig.10 In the case where a plurality of first synchronization signals SS1' are generated in a segment Frame 2 corresponding to one frame, when underrun occurs at several time points during the frame transmission segment, the first synchronization signal SS1' generated immediately after the underrun is immediately delayed in response to the number of lines where the underrun occurs.

[0135] However, according to another embodiment, based on one frame unit, the first synchronization signal SS1 ′ corresponding to the next frame may be immediately delayed in response to a plurality of under-run sections.

[0136] Fig.11 is a timing chart of the operation of the display system according to the second embodiment. Fig.11 The timing diagram of the main link, the first control signal STV and the second control signal CLK shown in FIG. Figure 7 The timing diagrams of the main link, the first control signal STV, and the second control signal CLK shown in FIG. 1 are the same, so the description of the overlapping configuration is omitted.

[0137] In the description Fig.11 In the second embodiment, for convenience of explanation, the description is given by comparison with the first embodiment. Unlike the first embodiment in which the start time of the first synchronization signal corresponding to the next frame segment of the segment UD where the underrun occurs is delayed (i.e., in the first mode), the first synchronization signal SS1 and the second synchronization signal SS2 included in the synchronization signal SS according to the second embodiment can be output at the same interval as the segment where the underrun does not occur (i.e., in the second mode). Fig.11 In some implementations, the synchronization signal SS in the first segment and the synchronization signal SS in the second segment may be the same.

[0138] Reference Fig.11, without delaying the start time point t15 of the first synchronization signal SS1 corresponding to the third segment, the time point T for determining whether the next frame can be updated after the segment where the underrun occurs and before the start of the next frame segment A (i.e., from Fig.11 The time point T12 to the time point t15) can be set, and the third segment is the next frame segment after the segment where the underrun occurs. A , whether the frame data to be sent due to underrun exceeds the permissible time within the frame (e.g., t A ) can be determined to determine whether to send frame data.

[0139] Reference Fig.11 , when the amount of frame data to be transmitted due to underrun is at the time point T for determining whether the next frame can be updated A When the amount of frame data to be transmitted due to underrun is smaller than the allowable time within the frame, data transmission may be allowed in the frame segment (ie, the third segment) after the underrun occurs. A When the time is greater than the allowable time within the frame, data transmission may be stopped in the frame segment (ie, the third segment) after the underrun occurs.

[0140] Compared with the first embodiment, the host control method according to the second embodiment can maintain a fixed display frame timing regardless of underload, thereby improving display quality with an accurate frame rate. In addition, when rendering a frame, it is easy to manage the content creation time point. At this time, for the frame that has been drawn, there may be a possibility of frame delay, and the amount of brightness change may be greater than in the first embodiment according to the amount of underload (for example, the number of lines where underload occurs). The method of controlling the synchronization signal of the host according to the second embodiment may be an example of a host operating in the second mode.

[0141] According to the host control method of the second embodiment, when underload occurs in a very small number of lines, defects caused by the underload can be absorbed within the VFP and VBP sections, and the display driving frequency can be maintained constant, thereby improving display quality.

[0142] Fig.12 is a timing chart of the operation of the display system according to the second embodiment.

[0143] because Fig.12 The timing diagram of the main link, the first control signal STV, the second control signal CLK, the first scanning control signal Sn(0), the second scanning control signal Sn(1) and the third scanning control signal Sn(2) shown in FIG. Figure 8The timing diagrams of the main link, the first control signal STV, the second control signal CLK, the first scanning control signal Sn(0), the second scanning control signal Sn(1), and the third scanning control signal Sn(2) shown in FIG. 1 are the same, so the description of the overlapping configuration is omitted.

[0144] According to the method for controlling a display system based on the second embodiment, a host and a display driving circuit may include a first channel, a main link, and a second channel, the first channel being used to send frame data according to an example, and the second channel being used to exchange synchronization signals for timing synchronization between the host and the display driving circuit. Even when specific line data is not sent due to an underload in the image data sent through the first channel, the first synchronization signal SS1 and the second synchronization signal SS2 may be sent and output at the same interval as when no underload occurs. A determined time point may be set in a segment between the time when the underload occurs and the start time of a segment corresponding to the next frame data. At the determined time point, when the number of line data where the underload occurs is greater than the total number of frame lines, the frame output may be stopped in the next frame segment after the underload occurs. Hereinafter, the stopped frame data may be sent according to the first synchronization signal SS1 that can update the frame data. According to Fig.11 and Fig.12 In some implementations, when the transmission of the frame data is stopped in the third section, the stopped frame data may be transmitted according to the first synchronization signal SS1 of the fourth section.

[0145] According to the second embodiment, software for rendering frame data can be easily synchronized with display hardware timing, thereby reducing the number of resynchronization operations and reducing operation overhead. In addition, the software can more accurately determine the position or state of each object constituting the rendered image over time, thereby improving screen quality degradation.

[0146] exist Fig.9A and Fig. 9B In some implementations, the second synchronization signal SS2 at the time when the underload occurs may be continuously transmitted, or the second synchronization signal SS2 at the time when the underload occurs may not be output.

[0147] The first embodiment and the second embodiment may not be applied at the same time, and either one may be selected and applied.

[0148] Fig.13A is a block diagram of a display system according to some implementations.

[0149] Fig.13A The timing controller 340, the drivers 351, 352 and 353 and the display panel 400a can be respectively Figure 3 The timing controller 340, the drivers 351, 352 and 353 and the display panel 400a correspond to each other. Fig.13AIn the Figure 3 Overlapping descriptions of the same reference numerals.

[0150] Reference Fig.13A , the timing controller 340 may generate a block control signal BS. The block control signal BS may be applied to the scan driver 351. According to some embodiments, the scan driver 351 may include a NAND gate, and the block control signal BS may be applied to the NAND gate as an input. According to some embodiments, the NAND gate included in the scan driver 351 may be a circuit that prevents a gate signal from being output to the display panel.

[0151] Fig. 13B is a block diagram of a display system according to some implementations.

[0152] Fig. 13B The timing controller 340, the drivers 351, 352 and 353 and the display panel 400a can be respectively Figure 3 The timing controller 340, the drivers 351, 352 and 353 and the display panel 400a correspond to each other. Fig. 13B In the Figure 3 Overlapping descriptions of the same reference numerals.

[0153] Reference Fig. 13B , the timing controller 340 may generate a first block control signal BS1 and a second block control signal BS2. The first block control signal BS1 may be applied to the scan driver 351. The second block control signal BS2 may be applied to the emission control driver 353. According to some embodiments, the scan driver 351 and the emission control driver 353 may include a NAND gate, and the first block control signal BS1 and the second block control signal BS2 may be applied to the NAND gate as inputs. According to some embodiments, the NAND gate included in the scan driver 351 and the emission control driver 353 may be a circuit that prevents the gate signal from being output to the display panel. According to some embodiments, when the first block control signal BS1 and the second block control signal BS2 are applied to the scan driver 351 and the emission control driver 353, respectively, the change in screen brightness due to underload may be completely eliminated.

[0154] Fig.14 is a timing chart of control to which the block control signal in the first embodiment is applied. Fig.15 2 is a timing chart of the control using the block control signal in the second embodiment. Fig.14 and Fig.15 The multiple signals shown in Figure 8 and Fig.12The plurality of signals described in are the same, so the timing diagram of the block control signal BS may only be described. According to some embodiments, the timing of the block control signal BS may be equally applicable to the first block control signal BS1 and the second block control signal BS2.

[0155] Reference Fig.14 and Fig.15 , when line data generated at the time of underload is scheduled to be written to the panel, the block control signal BS may be activated to block signals output to the gates (eg, gate (0), gate (1), and gate (2)). Fig.14 and Fig.15 , in the section where the corresponding data line cannot be written due to underload, the data on the panel can be written longer than the writing section of other gates, resulting in brightness fluctuations. Therefore, when the scan driver 351 includes a circuit for turning off the gate output, the data writing operation can be prevented by activating the block control signal BS. By blocking the emission signal, the emission section can be prevented from being extended or shortened due to underload. In addition, the data driver can also determine the output according to the line to be used to prevent display distortion from occurring on the data line of the panel.

[0156] Fig.16 is a flow chart of a method of operating a display driving circuit according to some embodiments.

[0157] Referring to operation S1000, the display driving circuit may receive image data and a synchronization signal from a host. According to some embodiments, the image data may be transmitted in units of frames.

[0158] Referring to operation S2000, the display driving circuit may confirm whether the image data is normal data. According to some embodiments, whether the image data is normal data may be confirmed by confirming whether a horizontal synchronization signal corresponding to the image data or a signal equivalent thereto is input. When a horizontal synchronization signal corresponding to the image data or a signal equivalent thereto is not input, it may be determined that the image data is not normal data. A situation where normal data is not input may be defined as a situation where underload occurs.

[0159] Referring to operation S3000, the display driving circuit may determine whether to output an internal control signal according to whether the image data is normal data.

[0160] Referring to operation S3100, when the image data is normal data, a corresponding horizontal synchronization signal or an equivalent signal may be input. The display driving circuit may control the internal control signal to be output to the driver based on the corresponding horizontal synchronization signal and the external synchronization signal.

[0161] Referring to operation S3200, when the image data is not normal data, underrun may occur and the corresponding horizontal synchronization signal or equivalent signal may not be input. The display driving circuit may control to stop the output of the internal control signal corresponding to the section where the horizontal synchronization signal is not input (ie, the output section of abnormal data).

[0162] When an internal control signal is generated based on an external synchronization signal to synchronize the timing of the host and the display panel, the display driving circuit operating in the video mode can control the internal control signal to be generated only when a signal indicating a line of image data (such as a horizontal synchronization signal, or a similar signal (such as a horizontal start signal)) is received through the main link, otherwise the internal control signal is not generated. In other words, the display driving circuit can control the generation of the internal control signal only when the external synchronization signal and the signal representing the line of image data are input at the same time. The internal control signal can be applied to the driver to generate a signal for driving the panel. According to some embodiments, the signal for driving the panel can be a start signal or a clock signal of the gate line.

[0163] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of possible protection. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the above features may be described as working in a specific combination, one or more features from the combination may be cut out from the combination in some cases, and the combination may point to a sub-combination or a variation of the sub-combination.

[0164] While the present disclosure has particularly shown and described a display driving circuit with reference to the embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A display driving circuit, comprising: an interface configured to receive a synchronization signal and image data corresponding to each of a plurality of frames from an external source; a data processor configured to: receive image data from the interface, and convert the image data to generate converted image data; as well as a timing controller configured to generate an internal control signal for driving a driver circuit based on the synchronization signal and the converted image data, wherein the internal control signal is configured to be output to the driver circuit based on the synchronous signal and the signal corresponding to the image data being simultaneously input, and The panel driving signal is configured to be output to the driver circuit based on the internal control signal and then output to the display panel.

2. The display driving circuit according to claim 1, wherein: The internal control signal is configured to be output to the driver circuit based on the signal corresponding to the image data being applied to the driver circuit, The signal corresponding to the image data includes a horizontal synchronization signal.

3. The display driving circuit according to claim 1 or 2, wherein: The synchronization signal includes a first synchronization signal and a second synchronization signal, the first synchronization signal corresponds to a start signal of each of the plurality of frames, and the second synchronization signal is different from the first synchronization signal.

4. The display driving circuit according to claim 3, wherein: At least one of a pulse width, a number of pulses, and a pulse pattern of the first synchronization signal is different from a corresponding one of a pulse width, a number of pulses, and a pulse pattern of the second synchronization signal.

5. The display driving circuit according to claim 3, in, The first synchronization signal is a start signal of the second segment, the second segment is a next frame segment of the first segment, and The first synchronization signal is configured to be delayed for a period corresponding to the section in which the signal corresponding to the image data is not received based on the fact that the signal corresponding to the image data is not received in the first section.

6. A host, comprising: an interface configured to: send image data corresponding to each of the plurality of frames to a display driving circuit through a first channel, and send a synchronization signal to the display driving circuit through a second channel; a display processor configured to generate image data; as well as a synchronization generator configured to generate a synchronization signal, The synchronization generator is further configured to generate a first synchronization signal and a second synchronization signal, wherein the second synchronization signal is different from the first synchronization signal, and When a portion of image data generated from a display processor is not normally sent to a display device, the synchronization generator is configured to operate in at least one of a first mode and a second mode, wherein the first mode delays the output of a first synchronization signal corresponding to a next frame segment of a segment in which a portion of image data is not normally received by the display device, and the second mode outputs a first synchronization signal corresponding to a next frame segment of a segment in which a portion of image data is not normally received by the display device.

7. The host according to claim 6, wherein: The first synchronization signal corresponds to a start signal of each of the plurality of frames.

8. The host according to claim 7, wherein: At least one of a pulse width, a number of pulses, and a pulse pattern of the first synchronization signal is different from a corresponding one of a pulse width, a number of pulses, and a pulse pattern of the second synchronization signal.

9. The host according to claim 8, wherein: The synchronization generator is further configured to additionally output a second synchronization signal through a signal section in which the image data is not normally transmitted to the display device in the first mode.

10. The host according to claim 9, wherein: The synchronization generator is further configured not to output the second synchronization signal at the beginning of a signal section in which image data is not normally transmitted.

11. The host according to claim 9, wherein: The synchronization generator is further configured to output a second synchronization signal at the beginning of a signal section in which image data is not normally transmitted.

12. The host according to any one of claims 6 to 11, wherein: When a signal segment in which image data is not normally transmitted in one frame includes a first segment and a second segment in the first mode, A delay of the first synchronization signal corresponding to the first segment is output to delay the first synchronization signal generated after the first segment has passed, and The delay of the first synchronization signal corresponding to the second section is output to delay the first synchronization signal generated after the second section has elapsed.

13. The host according to claim 8, wherein: In the second mode, the display processor is further configured to determine whether to transmit the next frame data based on the number of frame lines corresponding to the signal section in which the image data is not normally transmitted and the number of allowable frame lines.

14. The host according to claim 13, wherein: The display processor is configured to: stop sending the next frame data when the number of frame lines corresponding to the signal segment to which the image data is not sent normally exceeds the allowable number of frame lines, and send the next frame data when the number of frame lines corresponding to the signal segment to which the image data is not sent normally does not exceed the allowable number of frame lines.

15. A display system comprising: a host configured to: transmit image data corresponding to each of the plurality of frames through a first channel, and transmit a synchronization signal for synchronizing signals of the host and a display driving circuit through a second channel; as well as The display driving circuit is configured to generate a control signal for driving the display panel based on the synchronization signal and the image data, The display driving circuit is further configured to generate a control signal only when the synchronization signal and the image data are normally input, and output a panel driving signal when the control signal is generated.

16. The display system according to claim 15, wherein: The display driving circuit includes a timing controller configured to generate an internal control signal based on a synchronization signal and image data, the internal control signal being applied to a driver circuit for driving the display panel. The timing controller is further configured to output an internal control signal when a horizontal synchronization signal corresponding to the image data is applied to the driver circuit.

17. The display system according to claim 15, wherein: The synchronization signal includes a first synchronization signal and a second synchronization signal, the first synchronization signal corresponds to the start signal of each of the multiple frames, and at least one of the pulse width, the number of pulses and the pulse mode of the second synchronization signal is different from the corresponding one of the pulse width, the number of pulses and the pulse mode of the first synchronization signal.

18. The display system according to claim 17, wherein: When the image data is not normally transmitted to the display driving circuit, the host controls the synchronization signal to be output in the first mode or the second mode.

19. The display system of claim 18, wherein: The first mode is a mode in which the output of the first synchronization signal is delayed, and the second mode is a mode in which the output of the first synchronization signal is output.

20. The display system of claim 19, wherein: The host is further configured to delay, in the first mode, a first synchronization signal corresponding to a start point of a next frame segment by a segment corresponding to a signal segment in which image data is not normally sent to the display driving circuit, and output it.

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