Pixel circuit and display device

Abstract

The invention relates to a pixel circuit and a display device. The pixel circuit includes: a light emitting element; a first transistor applying a first power supply voltage to a second node in response to a voltage of the first node; a second transistor applying a voltage of a second node to the first node in response to a control signal; a third transistor applying a voltage of a second node to the light emitting element in response to a control signal; and a first capacitor connected to the first node. The first supply voltage has a first voltage level, a second voltage level lower than the first voltage level, or a data voltage.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a pixel circuit and a display device. More particularly, embodiments of the inventive concept relate to a pixel circuit and a display device including the pixel circuit. Background Art

[0002] Typically, a display device may include a display panel and a display panel driver. The display panel may include a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver may include a gate driver that provides a gate signal to the gate line, a data driver that provides a data voltage to the data line, an emission driver that provides an emission signal to the emission line, and a drive controller that controls the gate driver, the data driver, and the emission driver.

[0003] Recently, display devices that provide virtual reality ("VR") or augmented reality ("AR") have become increasingly prominent. For this purpose, the display device is expected to have a small area and a high degree of integration. In this case, since the pitch occupied by the pixel circuit becomes narrower, the number of transistors of the pixel circuit and the number of signals applied to the pixel circuit may be limited. Summary of the invention

[0004] Embodiments of the inventive concept provide a pixel circuit having a relatively small area and a relatively high integration density and reducing leakage current.

[0005] Embodiments of the inventive concept also provide a display device including a pixel circuit.

[0006] In an embodiment of the present disclosure, a pixel circuit includes: a light emitting element; a first transistor, applying a first power supply voltage to a second node in response to a voltage of a first node; a second transistor, applying the voltage of the second node to the first node in response to a control signal; a third transistor, applying the voltage of the second node to the light emitting element in response to the control signal; and a first capacitor connected to the first node. The first power supply voltage has a first voltage level, a second voltage level lower than the first voltage level, or a data voltage.

[0007] In an embodiment, the second transistor is an N-type transistor and the third transistor may be a P-type transistor.

[0008] In an embodiment, in a first period, the first power supply voltage may have the data voltage, the second transistor may be turned on in response to a logic high level of the control signal, and the third transistor may be turned off in response to a logic high level of the control signal.

[0009] In an embodiment, in a second cycle after the first cycle, the first power supply voltage may have a first voltage level, the second transistor may be turned off in response to a logic low level of the control signal, and the third transistor may be turned on in response to a logic low level of the control signal.

[0010] In an embodiment, the pixel circuit may further include: a fourth transistor applying the first power supply voltage to the first transistor in response to the emission signal.

[0011] In an embodiment, in the first period, the first power supply voltage may have a second voltage level, the emission signal may have an inactive level, the second transistor may be turned on in response to a logic high level of the control signal, and the third transistor may be turned off in response to a logic high level of the control signal.

[0012] In an embodiment, in a second period after the first period, the first power supply voltage may have the data voltage, the emission signal may have an activation level, and the fourth transistor may be turned on in response to the activation level of the emission signal.

[0013] In an embodiment, in a third period after the second period, the first power supply voltage may have a second voltage level, the emission signal may have an inactive level, and the fourth transistor may be turned off in response to the inactive level of the emission signal.

[0014] In an embodiment, in a fourth cycle after the third cycle, the first power supply voltage may have a first voltage level, the emission signal may have an activation level, the fourth transistor may be turned on in response to the activation level of the emission signal, the second transistor may be turned off in response to a logic low level of the control signal, and the third transistor may be turned on in response to a logic low level of the control signal.

[0015] In an embodiment, the pixel circuit may further include: a fourth transistor applying the first power supply voltage to the first transistor in response to the emission signal. The second transistor may be a P-type transistor, and the third transistor may be an N-type transistor.

[0016] In an embodiment, in the first period, the first power supply voltage may have a second voltage level, the emission signal may have an inactive level, the second transistor may be turned on in response to a logic low level of the control signal, and the third transistor may be turned off in response to a logic low level of the control signal.

[0017] In an embodiment, in a second period after the first period, the first power supply voltage may have the data voltage, the emission signal may have an activation level, and the fourth transistor may be turned on in response to the activation level of the emission signal.

[0018] In an embodiment, in a third period after the second period, the first power supply voltage may have a second voltage level, the emission signal may have an inactive level, and the fourth transistor may be turned off in response to the inactive level of the emission signal.

[0019] In an embodiment, in a fourth cycle after the third cycle, the first power supply voltage may have a first voltage level, the emission signal may have an activation level, the fourth transistor may be turned on in response to the activation level of the emission signal, the second transistor may be turned off in response to a logic high level of the control signal, and the third transistor may be turned on in response to a logic high level of the control signal.

[0020] In an embodiment of the present invention, a pixel circuit includes: a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode receiving an emission signal, a first electrode receiving a first power supply voltage, and a second electrode connected to the second node; a third transistor including a control electrode receiving a control signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a control electrode receiving a control signal, a first electrode connected to the third node, and a second electrode connected to the fourth node; a first capacitor including a first electrode receiving a second power supply voltage and a second electrode connected to the first node; and a light emitting element including an anode connected to the fourth node and a cathode receiving the third power supply voltage. The first power supply voltage may have a first voltage level, a second voltage level lower than the first voltage level, or a data voltage.

[0021] In an embodiment, the third transistor is an N-type transistor and the fourth transistor is a P-type transistor.

[0022] In an embodiment, the third transistor is a P-type transistor and the fourth transistor is an N-type transistor.

[0023] In an embodiment of the present disclosure, a display device includes: a display panel, the display panel includes: a pixel circuit; a data driver, applying a first power supply voltage to the pixel circuit; a gate driver, applying a control signal to the pixel circuit; an emission driver, applying an emission signal to the pixel circuit; and a driving controller, controlling the data driver, the gate driver and the emission driver. The pixel circuit includes: a light-emitting element; a first transistor, applying the first power supply voltage to the second node in response to the voltage of the first node; a second transistor, applying the first power supply voltage to the first transistor in response to the emission signal; a third transistor, applying the voltage of the second node to the first node in response to the control signal; a fourth transistor, applying the voltage of the second node to the light-emitting element in response to the control signal; and a first capacitor connected to the first node. The first power supply voltage may have a first voltage level, a second voltage level lower than the first voltage level, or a data voltage.

[0024] In an embodiment, the third transistor may be an N-type transistor, and the fourth transistor may be a P-type transistor.

[0025] In an embodiment, the pixel circuit may be formed on a silicon-based substrate.

[0026] As described above, compared with the traditional pixel circuit, the pixel circuit in the embodiment can have a smaller number of transistors and a smaller number of capacitors. Accordingly, the integration of the pixel circuit can be improved, and power consumption can be reduced. In addition, one of the transistors included in the pixel circuit can be an N-type transistor. Accordingly, the leakage current of the pixel circuit can be reduced, thereby improving reliability and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features and advantages of the present inventive concept will become more apparent by describing in detail embodiments of the present inventive concept with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating an embodiment of a display device.

[0029] Figure 2 is a circuit diagram illustrating an embodiment of a pixel circuit.

[0030] Figure 3 is shown applied to Figure 2 A timing diagram of an embodiment of an input signal of a pixel circuit.

[0031] Figure 4 It is shown Figure 2 The pixel circuit is Figure 3 Circuit diagram of the first cycle of operation.

[0032] Figure 5 It is shown Figure 2 The pixel circuit is Figure 3 Circuit diagram of the operation in the second cycle.

[0033] Figure 6 It is shown Figure 2 The pixel circuit is Figure 3 Circuit diagram of the operation in the third cycle.

[0034] Figure 7 It is shown Figure 2 The pixel circuit is Figure 3 Circuit diagram of the operation in the fourth cycle.

[0035] Figure 8 is a circuit diagram illustrating an embodiment of a pixel circuit.

[0036] Fig. 9 is shown applied to Figure 8 A timing diagram of an embodiment of an input signal of a pixel circuit.

[0037] Fig.10 is a circuit diagram illustrating an embodiment of a pixel circuit.

[0038] Fig.11 is shown applied to Fig.10 A timing diagram of an embodiment of an input signal of a pixel circuit.

[0039] Fig.12 is a block diagram illustrating an embodiment of an electronic device according to the inventive concept.

[0040] Fig.13 It is shown Fig.12 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone.

[0041] Fig.14 It is shown Fig.12 FIG. 1 is a diagram of an embodiment of an electronic device implemented as a virtual reality display system. DETAILED DESCRIPTION

[0042] Hereinafter, the inventive concept will be described in more detail with reference to the accompanying drawings.

[0043] It will be understood that when an element is referred to as being "on" another element, the element can be directly on the other element or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0044] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as "second element", "second component", "second region", "second layer" or "second part".

[0045] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the content clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "the (the)" are intended to include plural forms, including "at least one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the terms "include" and / or "comprise" or "contain" and / or "have" illustrate the presence of stated features, regions, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0046] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, relative terms are also intended to cover different orientations of the device. For example, if the device in a figure is turned over, the element described as being on the "lower" side of the other element will then be oriented to be on the "upper" side of the other element. Therefore, depending on the specific orientation of the accompanying drawings, the exemplary term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device in a figure is turned over, the element described as being "below" or "below" the other element will then be oriented to be "above" the other element. Therefore, the exemplary terms "below..." or "below..." can cover both "above..." and "below..." orientations.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formalized sense.

[0048] Figure 1 is a block diagram illustrating an embodiment of a display device.

[0049] Reference Figure 1 The display device may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0050] The display panel 100 may include a display portion displaying an image and a peripheral portion adjacent to the display portion.

[0051] The display panel 100 may include gate lines GL, data lines DL, emission lines EL, and pixel circuits PX electrically connected to the gate lines GL, data lines DL, and emission lines EL, respectively. The gate lines GL may extend in a first direction D1, the data lines DL may extend in a second direction D2 intersecting the first direction D1, and the emission lines EL may extend in the first direction D1.

[0052] The driving controller 200 may receive input image data IMG and an input control signal CONT from an external device. In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0053] The driving controller 200 may generate a gate control signal CONT1 , a data control signal CONT2 , a gamma control signal CONT3 , an emission control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0054] The driving controller 200 may generate a gate control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT to output the generated gate control signal CONT1 to the gate driver 300. The gate control signal CONT1 may include a vertical start signal and a gate clock signal.

[0055] The driving controller 200 may generate a data control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT to output the generated data control signal CONT2 to the data driver 500. The data control signal CONT2 may include a horizontal start signal and a load signal.

[0056] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0057] The driving controller 200 may generate a gamma control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT to output the generated gamma control signal CONT3 to the gamma reference voltage generator 400 .

[0058] The driving controller 200 may generate an emission control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT to output the generated emission control signal CONT4 to the emission driver 600 .

[0059] The gate driver 300 may generate a control signal GC for driving the gate line GL in response to the gate control signal CONT1 received from the driving controller 200. The gate driver 300 may output the control signal GC to the gate line GL.

[0060] In an embodiment, for example, the gate driver 300 may be disposed (eg, mounted) in a peripheral region of the display panel 100. In an embodiment, for example, the gate driver 300 may be integrated in a peripheral region of the display panel 100.

[0061] The gamma reference voltage generator 400 may generate the gamma reference voltage VGREF in response to the gamma control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500.

[0062] In an embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 , or in the data driver 500 .

[0063] The data driver 500 may receive the data control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into an analog data voltage VDATA (see Figure 3 ). The data driver 500 may output the first power voltage ELVDD to the data line DL. In the illustrated embodiment, the first power voltage ELVDD may have the data voltage VDATA. In addition, in the illustrated embodiment, the first power voltage ELVDD may have Figure 3 The first voltage level VGH and below Figure 3 The first voltage level VGH Figure 3 In an embodiment, for example, an operation in which the data voltage VDATA is applied to the pixel circuit PX may be referred to as a data writing operation.

[0064] In an embodiment, for example, the data driver 500 may be disposed (eg, mounted) in a peripheral region of the display panel 100. In an embodiment, for example, the data driver 500 may be integrated in a peripheral region of the display panel 100.

[0065] The emission driver 600 may generate an emission signal EM for driving the emission line EL in response to the emission control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal EM to the emission line EL.

[0066] In an embodiment, for example, the emission driver 600 may be integrated in a peripheral area of ​​the display panel 100. In an embodiment, for example, the emission driver 600 may be disposed (eg, mounted) in a peripheral area of ​​the display panel 100.

[0067] Despite Figure 1 It has been shown that the gate driver 300 is disposed on the first side (eg, Figure 1 ), and the emission driver 600 is disposed on a second side of the display panel 100 opposite to the first side (eg, Figure 1 The gate driver 300 and the emission driver 600 may be disposed on the same side of the display panel 100. In an embodiment, for example, the gate driver 300 and the emission driver 600 may be integrated in a peripheral area of ​​the display panel 100 on the same side of the display area of ​​the display panel 100. In an embodiment, for example, the gate driver 300 and the emission driver 600 may be formed integrally with each other.

[0068] Figure 2is a circuit diagram showing an embodiment of a pixel circuit 110A.

[0069] Reference Figure 2 , the pixel circuit 110A may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1 and a light emitting element EE. The pixel circuit 110A may include four transistors and one capacitor. That is, the pixel circuit 110A may have a 4T1C structure.

[0070] The first transistor T1 may include a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor T1 may apply the voltage of the second node N2 to the third node N3 in response to the voltage of the first node N1. In addition, the first transistor T1 may generate a driving current for driving the light emitting element EE in response to the voltage of the first node N1.

[0071] The second transistor T2 may include a control electrode receiving the emission signal EM, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the second node N2. The second transistor T2 may apply the first power voltage ELVDD to the second node N2 in response to the emission signal EM.

[0072] In an embodiment, for example, the first power supply voltage ELVDD in the illustrated embodiment may have Figure 3 The first voltage level VGH, Figure 3 Accordingly, when the pixel circuits 110A are arranged in a plurality of rows, a different data voltage VDATA may be applied to each row through the second transistor T2 in response to the emission signal EM.

[0073] The third transistor T3 may include a control electrode receiving the control signal GC, a first electrode connected to the third node N3, and a second electrode connected to the first node N1. The third transistor T3 may apply a voltage of the third node N3 to the first node N1 in response to the control signal GC.

[0074] The fourth transistor T4 may include a control electrode receiving the control signal GC, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The fourth transistor T4 may apply a driving current to the light emitting element EE in response to the control signal GC.

[0075] One of the third transistor T3 and the fourth transistor T4 may be an N-type transistor, and the other may be a P-type transistor. In the illustrated embodiment, the third transistor T3 may be an N-type transistor, and the fourth transistor T4 may be a P-type transistor. In addition, the first transistor T1 and the second transistor T2 may be P-type transistors.

[0076] The fourth transistor T4 may be a polysilicon thin film transistor. In an embodiment, for example, the first transistor T1, the second transistor T2 and the fourth transistor T4 may be low temperature polysilicon ("LTPS") thin film transistors. In an embodiment, for example, the third transistor T3 may be an oxide thin film transistor.

[0077] Conventional pixel circuits receive multiple gate signals. In contrast, pixel circuit 110A can operate in response to a gate signal (e.g., control signal GC). Accordingly, unlike conventional pixel circuits, pixel circuit 110A can operate with a relatively small number of signals, so the integration of pixel circuit 110A can be improved. In addition, the absolute value of the threshold voltage of the N-type transistor is lower than the absolute value of the threshold voltage of the P-type transistor, so leakage current can be reduced. One of the third transistor T3 and the fourth transistor T4 included in pixel circuit 110A can be an N-type transistor. Accordingly, the leakage current flowing through pixel circuit 110A can be reduced. Accordingly, the reliability and stability of pixel circuit 110A can be improved.

[0078] The first capacitor C1 may include a first electrode receiving the second power voltage DD2 and a second electrode connected to the first node N1. The first capacitor C1 may store a voltage of the first node N1.

[0079] The light emitting element EE may include an anode connected to the fourth node N4 and a cathode receiving a third power supply voltage ELVSS. The third power supply voltage ELVSS may be lower than the first voltage level VGH. In an embodiment, the light emitting element EE may be an organic light emitting diode. However, the inventive concept is not limited thereto. In other embodiments, the light emitting element EE may be a nano light emitting diode, a quantum dot light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element.

[0080] In an embodiment, the pixel circuit 110A may be formed on a silicon-based substrate. Accordingly, the first voltage level VGH and the second voltage level VGL of the first power supply voltage ELVDD may be stably set. In addition, since the pixel circuit 110A may be formed on a silicon-based substrate, one of the third transistor T3 and the fourth transistor T4 may be stably formed as an N-type transistor.

[0081] Figure 3 is shown applied to Figure 2A timing diagram of an embodiment of an input signal of the pixel circuit 110A. Figure 4 It is shown Figure 2 The pixel circuit 110A is Figure 3 A circuit diagram of the operation during the first cycle TP1A. Figure 5 It is shown Figure 2 The pixel circuit 110A is Figure 3 A circuit diagram of the operation in the second period TP2A. Figure 6 It is shown Figure 2 The pixel circuit 110A is Figure 3 A circuit diagram of the operation in the third cycle TP3A. Figure 7 It is shown Figure 2 The pixel circuit 110A is Figure 3 A circuit diagram of the operation in the fourth cycle TP4A.

[0082] Reference Figure 3 , also refer to Figure 2 For example, the first power supply voltage ELVDD in the illustrated embodiment may have a first voltage level VGH, a second voltage level VGL, and a data voltage VDATA. Accordingly, when the pixel circuits 110A are arranged in multiple rows, different data voltages VDATA may be applied to each row through the second transistor T2 in response to the emission signal EM.

[0083] Reference Figure 3 and Figure 4 , in the first period TP1A, the first power supply voltage ELVDD may have a second voltage level VGL, the control signal GC may have a logic high level, and the emission signal EM may have an inactive level. In an embodiment, for example, the logic high level is a voltage level when the N-type transistor is turned on and the P-type transistor is turned off. In an embodiment, for example, the logic low level is a voltage level when the N-type transistor is turned off and the P-type transistor is turned on.

[0084] In the first period TP1A, the first transistor T1 may maintain a turned-on state. The second transistor T2 may be turned off in response to the inactive level of the emission signal EM. The third transistor T3 may be turned on in response to the logic high level of the control signal GC. The fourth transistor T4 may be turned off in response to the logic high level of the control signal GC. Since the fourth transistor T4 may be turned off, the light emitting element EE may not emit light.

[0085] In an embodiment, for example, when the pixel circuits 110A are arranged in multiple rows, a data write operation may be performed for each row. The second transistor T2 of the pixel circuit row where the data write operation is not performed may be turned off in response to the inactive level of the emission signal EM in the first period TP1A. Accordingly, the data voltage VDATA may be prevented from being applied to the pixel circuit row where the data write operation is not performed. In an embodiment, for example, the first period TP1A may be referred to as a first holding period.

[0086] Reference Figure 3 and Figure 5 , in the second period TP2A, the first power voltage ELVDD may have the data voltage VDATA, the control signal GC may have a logic high level, and the emission signal EM may have an activation level.

[0087] In the second period TP2A, the first transistor T1 may maintain a turned-on state. The second transistor T2 may be turned on in response to the activation level of the emission signal EM. The third transistor T3 may maintain a turned-on state in response to the logic high level of the control signal GC. The fourth transistor T4 may maintain a turned-off state in response to the logic high level of the control signal GC. Since the first transistor T1, the second transistor T2, and the third transistor T3 may be turned on, the data voltage VDATA may be applied to the first node N1.

[0088] In addition, in the second period TP2A, the third transistor T3 may be diode-connected to the first transistor T1 in response to the logic high level of the control signal GC. Accordingly, through the diode connection of the first transistor T1, the voltage of the first node N1 may be the sum of the data voltage VDATA and the threshold voltage of the first transistor T1. In addition, since the first electrode of the first capacitor C1 may be applied with the second power supply voltage DD2, and the voltage of the second electrode of the first capacitor C1 may be the voltage of the first node N1, which is the sum of the threshold voltage of the first transistor T1 and the data voltage VDATA, a voltage with respect to the threshold voltage of the first transistor T1 and the data voltage VDATA may be stored between the first electrode and the second electrode of the first capacitor C1.

[0089] Reference Figure 3 and Figure 6 , in the third period TP3A, the first power voltage ELVDD may have the second voltage level VGL, the control signal GC may have a logic high level, and the emission signal EM may have an inactive level.

[0090] In the third period TP3A, the second transistor T2 may be turned off in response to the inactive level of the emission signal EM. The fourth transistor T4 may be turned off in response to the logic high level of the control signal GC. Since the fourth transistor T4 may be turned off, the light emitting element EE may not emit light.

[0091] In an embodiment, for example, when the pixel circuit 110A is arranged in multiple rows, a data write operation may be performed for each row. The second transistor T2 of the pixel circuit row where the data write operation is not performed may be turned off in response to the inactive level of the emission signal EM in the third period TP3A. Accordingly, the data voltage VDATA may be prevented from being applied to the pixel circuit row where the data write operation is not performed. Accordingly, the voltage of the first node N1 in the third period TP3A may be maintained at the voltage of the first node N1 in the second period TP2A. In an embodiment, for example, the third period TP3A may be referred to as a second holding period.

[0092] Reference Figure 3 and Figure 7 , in the fourth period TP4A, the first power voltage ELVDD may have the first voltage level VGH, the control signal GC may have a logic low level, and the emission signal EM may have an activation level.

[0093] In the fourth period TP4A, the first transistor T1 may generate a driving current based on the voltage of the first node N1 in the third period TP3A. The second transistor T2 may apply the first power supply voltage ELVDD having the first voltage level VGH to the second node N2 in response to the activation level of the emission signal EM. The first transistor T1 may apply the first power supply voltage ELVDD applied to the second node N2 to the third node N3. The third transistor T3 may be turned off in response to the logic low level of the control signal GC. The fourth transistor T4 may be turned on in response to the logic low level of the control signal GC. Since the fourth transistor T4 may be turned on, the voltage of the third node N3 may be applied to the fourth node N4. Accordingly, the light emitting element EE may emit light based on the voltage of the fourth node N4 and the driving current.

[0094] The pixel circuit 110A can be operated with a relatively small number of signals. In addition, the number of transistors and the number of capacitors of the pixel circuit 110A can be reduced. Accordingly, the integration of the pixel circuit 110A can be improved, and power consumption can be reduced.

[0095] Figure 8 is a circuit diagram showing an embodiment of a pixel circuit 110B.

[0096] Reference Figure 8In addition to the first electrode of the first transistor T1 being applied with the first power supply voltage ELVDD, the pixel circuit 110B in the illustrated embodiment is Figure 2 Therefore, the same reference numerals will be used to refer to the same elements, and any repeated description on the above elements will be omitted.

[0097] The pixel circuit 110B may include a first transistor T1, a third transistor T3, a fourth transistor T4, a first capacitor C1, and a light emitting element EE. In an embodiment, for example, the pixel circuit 110B may have a 3T1C structure including three transistors and one capacitor. Accordingly, compared with a conventional pixel circuit, the integration of the pixel circuit 110B may be further improved.

[0098] Fig. 9 is shown applied to Figure 8 A timing diagram of an embodiment of an input signal of the pixel circuit 110B.

[0099] Reference Figure 8 and Fig. 9 , in the first period TP1B, the first power voltage ELVDD may have the data voltage VDATA, and the control signal GC may have a logic high level.

[0100] In the first period TP1B, the first transistor T1 may maintain a turned-on state. The third transistor T3 may have a turned-on state in response to a logic high level of the control signal GC. The fourth transistor T4 may maintain a turned-off state in response to a logic high level of the control signal GC. Since the first transistor T1 and the third transistor T3 may be turned on, the data voltage VDATA may be applied to the first node N1.

[0101] In addition, in the first period TP1B, the third transistor T3 may be diode-connected to the first transistor T1 in response to the logic high level of the control signal GC. Accordingly, through the diode connection of the first transistor T1, the voltage of the first node N1 may be the sum of the data voltage VDATA and the threshold voltage of the first transistor T1. In addition, since the first electrode of the first capacitor C1 may be applied with the second power supply voltage DD2, and the voltage of the second electrode of the first capacitor C1 may be the voltage of the first node N1, which is the sum of the threshold voltage of the first transistor T1 and the data voltage VDATA, a voltage with respect to the threshold voltage of the first transistor T1 and the data voltage VDATA may be stored between the first electrode and the second electrode of the first capacitor C1.

[0102] In the second period TP2B, the first power voltage ELVDD may have the first voltage level VGH, and the control signal GC may have a logic low level.

[0103] In the second period TP2B, the fourth transistor T4 may be turned on in response to the logic low level of the control signal GC. The first transistor T1 may generate a driving current based on the voltage of the first node N1 in the first period TP1B. Accordingly, the light emitting element EE may emit light based on the driving current.

[0104] The pixel circuit 110B can be operated with a relatively small number of signals. In addition, the number of transistors and the number of capacitors of the pixel circuit 110B can be reduced. Accordingly, the integration of the pixel circuit 110B can be improved, and the power consumption can be reduced. In addition, the absolute value of the threshold voltage of the N-type transistor is lower than the absolute value of the threshold voltage of the P-type transistor, so the leakage current can be reduced. One of the third transistor T3 and the fourth transistor T4 included in the pixel circuit 110B can be an N-type transistor. Accordingly, the leakage current flowing through the pixel circuit 110B can be reduced. Accordingly, the reliability and stability of the pixel circuit 110B can be improved.

[0105] Fig.10 is a circuit diagram showing an embodiment of a pixel circuit 110C.

[0106] Reference Fig.10 , except that the third transistor T3 may be a P-type transistor and the fourth transistor T4 may be an N-type transistor, the pixel circuit 110C in the illustrated embodiment is similar to Figure 2 Therefore, the same reference numerals will be used to refer to the same elements, and any repeated description on the above elements will be omitted.

[0107] Reference Fig.10 , one of the third transistor T3 and the fourth transistor T4 may be an N-type transistor, and the other may be a P-type transistor. In the illustrated embodiment, the third transistor T3 may be a P-type transistor, and the fourth transistor T4 may be an N-type transistor. In addition, the first transistor T1 and the second transistor T2 may be P-type transistors.

[0108] Fig.11 is shown applied to Fig.10 A timing diagram of an embodiment of an input signal of the pixel circuit 110C.

[0109] Reference Fig.10 and Fig.11 , Fig.11The timing diagram may include a first period TP1C, a second period TP2C, a third period TP3C, and a fourth period TP4C. In addition to the control signal GC having a logic low level in the first period TP1C, the second period TP2C, and the third period TP3C, and the control signal GC having a logic high level in the fourth period TP4C, Fig.11 The timing diagram and Figure 3 Therefore, the same reference numerals will be used to refer to the same elements, and any repeated description of the above elements will be omitted.

[0110] The pixel circuit 110C can be operated with a relatively small number of signals. In addition, the number of transistors and the number of capacitors of the pixel circuit 110C can be reduced. Accordingly, the integration of the pixel circuit 110C can be improved, and power consumption can be reduced. In addition, the absolute value of the threshold voltage of the N-type transistor is lower than the absolute value of the threshold voltage of the P-type transistor, so the leakage current can be reduced. One of the third transistor T3 and the fourth transistor T4 included in the pixel circuit 110C can be an N-type transistor. Accordingly, the leakage current flowing through the pixel circuit 110C can be reduced. Accordingly, the reliability and stability of the pixel circuit 110C can be improved.

[0111] Fig.12 is a block diagram illustrating an embodiment of an electronic device 1000 according to the inventive concept. Fig.13 It is shown Fig.12 The electronic device 1000 is implemented as a diagram of an embodiment of a smart phone.

[0112] Reference Fig.12 and Fig.13 , also refer to Figure 1 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output ("I / O") device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus ("USB") device, other electronic devices, and the like.

[0113] In an embodiment, Fig.13 As shown in , the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. In an embodiment, for example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer ("PC"), a car navigation system, a computer monitor, a notebook computer, or a head mounted display ("HMD") device, etc.

[0114] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit ("CPU"), an application processor ("AP"), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect ("PCI") bus.

[0115] The processor 1010 can output the input image data IMG and the input control signal CONT to Figure 1 A drive controller 200 is provided.

[0116] The memory device 1020 may store data used for the operation of the electronic device 1000. In an embodiment, for example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory ("EPROM") device, an electrically erasable programmable read-only memory ("EEPROM") device, a flash memory device, a phase change random access memory ("PRAM") device, a resistive random access memory ("RRAM") device, a nano floating gate memory ("NFGM") device, a polymer random access memory ("PoRAM") device, a magnetic random access memory ("MRAM") device, or a ferroelectric random access memory ("FRAM") device, and / or at least one volatile memory device such as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, or a mobile DRAM device.

[0117] The storage device 1030 may include a solid state drive ("SSD") device, a hard disk drive ("HDD") device, or a read-only compact disk memory ("CD-ROM") device, etc. The I / O device 1040 may include an input device such as a keyboard, a keypad, a mouse device, a touch pad, or a touch screen, etc., and an output device such as a printer or a speaker, etc. In some embodiments, the display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.

[0118] Fig.14 It is shown Fig.12 The electronic device 1000 is implemented as a diagram of an embodiment of a virtual reality display system.

[0119] Reference Fig.12 and Fig.14, the virtual reality display system may include a lens unit 10, a display device 20, and a housing 30. The display device 20 is disposed adjacent to the lens unit 10. The housing 30 may accommodate the lens unit 10 and the display device 20. Fig.14 The lens unit 10 and the display device 20 are accommodated in a first side of the housing 30, but the inventive concept may not be limited thereto. In an alternative embodiment, the lens unit 10 may be accommodated in a first side of the housing 30, and the display device 20 may be accommodated in a second side of the housing 30. When the lens unit 10 and the display device 20 are accommodated in the housing 30 in opposite sides, the housing 30 may have a transmission area to transmit light.

[0120] In an embodiment, for example, the virtual reality display system may be a head-mounted (e.g., head-mounted) display system that can be worn on the user's head. Although not shown in the drawings, the virtual reality display system may further include a headband to fix the virtual reality display system on the user's head.

[0121] In an alternative embodiment, the virtual reality display system may be in the form of smart glasses implemented in the shape of glasses.

[0122] In addition, the electronic device may be implemented as an augmented reality display system, a mixed reality display system, or an extended reality display system.

[0123] The display device in the embodiment can be applied to a display device included in a computer (such as a notebook computer), a mobile phone, a smart phone, a smart tablet, a portable multimedia player ("PMP"), a personal digital assistant ("PDA"), or a Moving Picture Experts Group Audio Layer III ("MP3") player, etc.

[0124] The foregoing is an illustration of the inventive concept and will not be construed as limiting the inventive concept. Although some embodiments of the inventive concept have been described, it will be readily understood by those skilled in the art that many modifications in the embodiments are possible without departing substantially from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, method-plus-function clauses are intended to cover structures described herein that perform the functions described, and not only structural equivalents, but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of the inventive concept and will not be construed as being limited to the disclosed exemplary embodiments, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, which include equivalents of the claims.

Claims

1. A pixel circuit, wherein: The pixel circuit comprises: Light emitting element; a first transistor that applies a first power supply voltage to a second node in response to a voltage at the first node; a second transistor, applying the voltage of the second node to the first node in response to a control signal; a third transistor that applies the voltage of the second node to the light emitting element in response to the control signal; and a first capacitor connected to the first node, The first power supply voltage has a first voltage level, a second voltage level lower than the first voltage level, or a data voltage.

2. The pixel circuit according to claim 1, wherein: The second transistor is an N-type transistor, and the third transistor is a P-type transistor.

3. The pixel circuit according to claim 2, wherein: In a first period, the first power supply voltage has the data voltage, the second transistor is turned on in response to a logic high level of the control signal, and the third transistor is turned off in response to the logic high level of the control signal.

4. The pixel circuit according to claim 3, wherein: In a second cycle following the first cycle, the first power supply voltage has the first voltage level, the second transistor is turned off in response to a logic low level of the control signal, and the third transistor is turned on in response to the logic low level of the control signal.

5. The pixel circuit according to claim 2, wherein: The pixel circuit further includes: A fourth transistor applies the first power supply voltage to the first transistor in response to an emission signal.

6. The pixel circuit according to claim 5, wherein: In a first period, the first power supply voltage has the second voltage level, the emission signal has an inactive level, the second transistor is turned on in response to a logic high level of the control signal, and the third transistor is turned off in response to the logic high level of the control signal.

7. The pixel circuit according to claim 6, wherein: In a second period after the first period, the first power supply voltage has the data voltage, the emission signal has an activation level, and the fourth transistor is turned on in response to the activation level of the emission signal.

8. The pixel circuit according to claim 7, wherein: In a third period after the second period, the first power supply voltage has the second voltage level, the emission signal has the inactive level, and the fourth transistor is turned off in response to the inactive level of the emission signal.

9. The pixel circuit according to claim 8, wherein: In a fourth cycle after the third cycle, the first power supply voltage has the first voltage level, the emission signal has the activation level, the fourth transistor is turned on in response to the activation level of the emission signal, the second transistor is turned off in response to a logic low level of the control signal, and the third transistor is turned on in response to the logic low level of the control signal.

10. The pixel circuit according to claim 1, wherein: The pixel circuit further includes: a fourth transistor, applying the first power supply voltage to the first transistor in response to a transmission signal, The second transistor is a P-type transistor, and the third transistor is an N-type transistor.

11. The pixel circuit according to claim 10, wherein: In a first period, the first power supply voltage has the second voltage level, the emission signal has an inactive level, the second transistor is turned on in response to a logic low level of the control signal, and the third transistor is turned off in response to the logic low level of the control signal.

12. The pixel circuit according to claim 11, wherein: In a second period after the first period, the first power supply voltage has the data voltage, the emission signal has an activation level, and the fourth transistor is turned on in response to the activation level of the emission signal.

13. The pixel circuit according to claim 12, wherein: In a third period after the second period, the first power supply voltage has the second voltage level, the emission signal has the inactive level, and the fourth transistor is turned off in response to the inactive level of the emission signal.

14. The pixel circuit according to claim 13, wherein: In a fourth cycle after the third cycle, the first power supply voltage has the first voltage level, the emission signal has the activation level, the fourth transistor is turned on in response to the activation level of the emission signal, the second transistor is turned off in response to a logic high level of the control signal, and the third transistor is turned on in response to the logic high level of the control signal.

15. A display device, wherein: The display device comprises: A display panel, the display panel comprising: A pixel circuit, the pixel circuit comprising: Light emitting element; a first transistor that applies a first power supply voltage to a second node in response to a voltage at the first node; a second transistor that applies the first power supply voltage to the first transistor in response to a transmission signal; a third transistor, applying the voltage of the second node to the first node in response to a control signal; a fourth transistor that applies the voltage of the second node to the light emitting element in response to the control signal; and a first capacitor connected to the first node; a data driver, applying the first power supply voltage to the pixel circuit; a gate driver, applying the control signal to the pixel circuit; an emission driver that applies the emission signal to the pixel circuit; and a driving controller, controlling the data driver, the gate driver and the emission driver, The first power supply voltage has a first voltage level, a second voltage level lower than the first voltage level, or a data voltage.

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