Display device

Abstract

A display device includes: a light emitting element; a driving voltage line transmitting a driving voltage signal having an active level or an inactive level within a preset period; a data line to which a data signal is applied; a first transistor connected between the driving voltage line and the light emitting element; and a second transistor connected to the driving voltage line and the data line, in which a gate electrode of the second transistor is connected to the driving voltage line, and a source electrode of the second transistor is connected to the data line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0127842, filed on September 25, 2023, and all benefits arising from the Korean Patent Application, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device capable of reducing the number of gate lines. Background Art

[0004] A head mounted display (HMD) is an image display device that is worn on a user's head in the form of glasses or a helmet to form a focus at a close distance in front of the user's eyes. The head mounted display can realize virtual reality (VR) or augmented reality (AR).

[0005] The head-mounted display can magnify the image displayed in the small display device by using a plurality of lenses, and display the magnified image. Therefore, it can be expected that the display device applied to the head-mounted display provides a high-resolution image (for example, an image with a resolution of 3000 pixels per inch (PPI) or higher). Therefore, an organic light emitting diode on silicon (OLEDoS), which is a high-resolution small organic light emitting display device, can be used as a display device applied to the head-mounted display. OLEDoS is an image display device in which an organic light emitting diode (OLED) is provided on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device capable of reducing the number of gate lines.

[0007] According to an embodiment of the present disclosure, a display device includes: a light-emitting element; a driving voltage line, which transmits a driving voltage signal having a valid level or an invalid level within a preset period; a data line, to which a data signal is applied; a first transistor, which is connected between the driving voltage line and the light-emitting element; and a second transistor, which is connected to the driving voltage line and the data line, wherein a gate electrode of the second transistor is connected to the driving voltage line, and a source electrode of the second transistor is connected to the data line.

[0008] In an embodiment, the gate electrode of the first transistor can be connected to the first node, the source electrode of the first transistor can be connected to the driving voltage line, and the drain electrode of the first transistor can be connected to the first electrode of the light emitting element through a third node, and the drain electrode of the second transistor can be connected to the second node.

[0009] In an embodiment, the display device may further include: a third transistor including a gate electrode connected to the second gate line to which the second gate signal is applied, a source electrode connected to the third node, and a drain electrode connected to the first node; a fourth transistor including a gate electrode connected to the first gate line to which the first gate signal is applied, a source electrode connected to the first node, and a drain electrode connected to the initialization voltage line; a fifth transistor including a gate electrode connected to the emission control line to which the emission control signal is applied, a source electrode connected to the third node, and a drain electrode connected to the first electrode of the light-emitting element; a first capacitor connected between the first node and the second node; and a second capacitor connected between the initialization voltage line and the second node.

[0010] In an embodiment, the preset period may include an initialization period, a threshold voltage detection period, a data writing period, and an emission period.

[0011] In an embodiment, in the initialization period, each of the driving voltage signal and the first gate signal may have an active level, each of the second gate signal and the emission control signal may have an inactive level, and the data signal may have a level of a reference voltage.

[0012] In an embodiment, the driving voltage signal of an active level, the first gate signal of an active level, the second gate signal of an active level, and the emission control signal of an active level may have the same size as each other.

[0013] In an embodiment, the driving voltage signal of the inactive level, the first gate signal of the inactive level, the second gate signal of the inactive level, and the emission control signal of the inactive level may have the same size as each other.

[0014] In an embodiment, the display device may further include a common voltage line connected to the second electrode of the light emitting element, wherein the common voltage line may transmit a common voltage.

[0015] In an embodiment, the reference voltage may be higher than the driving voltage signal of the inactive level and lower than the common voltage.

[0016] In an embodiment, the initialization voltage line may transmit an initialization voltage, and the initialization voltage may be lower than or equal to the common voltage.

[0017] In an embodiment, each of the driving voltage signal of the effective level, the first gate signal of the effective level, the second gate signal of the effective level, and the emission control signal of the effective level may be a negative voltage, and each of the driving voltage signal of the invalid level, the first gate signal of the invalid level, the second gate signal of the invalid level, and the emission control signal of the invalid level may be a positive voltage.

[0018] In an embodiment, in the threshold voltage detection period, the second gate signal has a valid level, each of the driving voltage signal, the first gate signal, and the emission control signal has an invalid level, and the data signal may have a level of a reference voltage.

[0019] In an embodiment, in the data write period, the driving voltage signal has an active level, each of the first gate signal, the second gate signal, and the emission control signal has an inactive level, and the data signal may have a level of the data voltage.

[0020] In an embodiment, in the emission period, the emission control signal has a valid level, each of the driving voltage signal, the first gate signal, and the second gate signal has an invalid level, and the data signal may have a level of a reference voltage.

[0021] In an embodiment, the first capacitor and the second capacitor may have the same capacitance as each other.

[0022] In an embodiment, each of the first to fifth transistors may be a P-type metal oxide semiconductor field effect transistor (MOSFET).

[0023] In an embodiment, the driving voltage signal of the effective level may be smaller than the driving voltage signal of the ineffective level.

[0024] In an embodiment, the driving voltage signal of the active level may be a positive voltage, and the driving voltage signal of the inactive level may be a negative voltage.

[0025] In an embodiment, the driving voltage signal of the effective level may have a magnitude corresponding to a turn-on voltage of the second transistor.

[0026] In an embodiment, the driving voltage signal of the inactive level may have a magnitude corresponding to a turn-off voltage of the second transistor.

[0027] In an embodiment, the display device may further include: a third transistor including a gate electrode connected to the second gate line to which the second gate signal is applied, a source electrode connected to the third node, and a drain electrode connected to the first node; a fourth transistor including a gate electrode connected to the first gate line to which the first gate signal is applied, a source electrode connected to the first node, and a drain electrode connected to the common voltage line; a fifth transistor including a gate electrode connected to the emission control line to which the emission control signal is applied, a source electrode connected to the third node, and a drain electrode connected to the first electrode of the light-emitting element; a first capacitor connected between the first node and the second node; and a second capacitor connected between the common voltage line and the second node.

[0028] According to an embodiment of the display device according to the present disclosure, a driving voltage signal can be applied in an alternating current manner. Therefore, the on and off of the transistor can be controlled by the driving voltage signal. Therefore, the number of gate lines used to control the on and off of the transistor can be reduced.

[0029] In such an embodiment, since the threshold voltage detection period and the data writing period are separated from each other, the data voltage can be written at high speed. Therefore, high-speed driving of the display device is possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above features and other features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is an exploded perspective view showing a display device according to an embodiment;

[0032] Figure 2 It is shown Figure 1 A schematic plan view of an embodiment of a display panel shown in ;

[0033] Figure 3 is a block diagram showing a display device according to an embodiment;

[0034] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment;

[0035] Figure 5 is a schematic plan view showing a unit pixel of a display area according to an embodiment;

[0036] Figure 6 is a diagram showing an embodiment of a display panel Figure 5 A cross-sectional view taken along line AA';

[0037] Figure 7 yes Figure 4 A signal timing diagram of a driving voltage signal, a first gate signal and a second gate signal, an emission control signal and a data signal;

[0038] Figure 8 It is shown Figure 4 The pixels in Figure 7 A diagram of the operations in the initialization cycle of;

[0039] Fig. 9 It is shown Figure 4 The pixels in Figure 7 A diagram of the operation during a threshold voltage detection cycle;

[0040] Fig.10 It is shown Figure 4 The pixels in Figure 7A diagram of operations in a data write cycle;

[0041] Fig.11 It is shown Figure 4 The pixels in Figure 7 A diagram of the operations in a launch cycle;

[0042] Fig.12 is an equivalent circuit diagram of a pixel according to an embodiment;

[0043] Fig.13 It is shown Fig.12 The pixels in Figure 7 A diagram of the operations in the initialization cycle of;

[0044] Fig.14 It is shown Fig.12 The pixels in Figure 7 A diagram of the operation during a threshold voltage detection cycle;

[0045] Fig.15 It is shown Fig.12 The pixels in Figure 7 A diagram of operations in a data write cycle;

[0046] Fig.16 It is shown Fig.12 The pixels in Figure 7 A diagram of the operations in a launch cycle;

[0047] Fig.17 is shown corresponding to Figure 7 A schematic diagram of a simulation signal of a signal;

[0048] Fig.18 is a perspective view showing a head mounted display device according to an embodiment;

[0049] Fig.19 It is shown Fig.18 An exploded perspective view of an embodiment of a head mounted display device; and

[0050] Fig. 20 is a perspective view showing a head mounted display device according to an embodiment. DETAILED DESCRIPTION

[0051] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments of the present invention are shown. However, the present invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0052] It will also be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers or substrates may be present between the layer or substrate and the other layer or substrate. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0053] It will be understood that, although the terms "first", "second", and "third" may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, without departing from the teachings of the present disclosure, the "first element", "first component", "first region", "first layer", or "first section" discussed below may be referred to as a "second element", "second component", "second region", "second layer", or "second section".

[0054] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be restrictive. Unless the context clearly states otherwise, as used herein, "one", "one (kind / person)", "described (the)" and "at least one (kind / person)" do not represent a limitation on quantity, and are intended to include both singular and plural. Therefore, in the claims subsequently cited as "described" elements, citing "one" elements includes one element and multiple elements. For example, unless the context clearly states otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" is not interpreted as being limited to "one" or "a kind". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that the terms “comprises and / or comprising” or “includes and / or including” when used in this specification specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or combinations thereof.

[0055] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device is turned over in one drawing, then the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in one drawing, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the terms "below..." or "under..." can cover both upper and lower orientations.

[0056] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0058] Embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the zones shown herein, but rather include deviations in shape, for example, caused by manufacturing. For example, a zone shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the zones shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, nor are they intended to limit the scope of the present disclosure.

[0059] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 is an exploded perspective view showing a display device 10 according to an embodiment. Figure 2 It is shown Figure 1A schematic plan view of an embodiment of a display panel 100 is shown in FIG. Figure 3 FIG. 1 is a diagram showing a display device 10 (see FIG. 1 ) according to an embodiment Figure 1 ) block diagram.

[0061] refer to Figure 1 and Figure 2 , the display device 10 according to the embodiment is a device for displaying a moving image or a still image. The display device 10 according to the embodiment can be applied to a portable electronic device (such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation system, or an ultra-mobile PC (UMPC)), etc. For example, the display device 10 can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for realizing virtual reality and augmented reality, etc.

[0062] The display device 10 according to the embodiment includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , and a driving circuit 450 .

[0063] The display panel 100 may have a planar shape similar to a quadrilateral shape. In an embodiment, for example, the display panel 100 may have a planar shape similar to a quadrilateral shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In such an embodiment of the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or a rounded shape having a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangular shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the embodiments of the present disclosure are not limited thereto.

[0064] like Figure 2 As shown in , the display panel 100 includes a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0065] In an embodiment, Figure 3 As shown in FIG. 1 , the display area DAA includes a plurality of pixels PX, a plurality of gate lines GIL and GCL, a plurality of emission control lines EML, and a plurality of data lines DL.

[0066] Each of the plurality of pixels PX includes a light emitting element that emits light. The plurality of pixels PX may be arranged in a first direction DR1 (eg, Figure 1 ) and a second direction DR2 (eg, see Figure 1) are arranged in a matrix form on a first direction DR1. A plurality of gate lines GIL and GCL and a plurality of emission control lines EML may extend in a first direction DR1 while being arranged in a second direction DR2. A plurality of data lines DL may extend in a second direction DR2 while being arranged in a first direction DR1.

[0067] The plurality of gate lines GIL and GCL include a plurality of first gate lines GIL and a plurality of second gate lines GCL. The plurality of emission control lines EML include a plurality of first emission control lines and a plurality of second emission control lines.

[0068] Multiple unit pixels UPX (see Figure 5 ) each includes a plurality of pixels PX1, PX2 and PX3 (in Figure 6 ). The plurality of pixels PX1, PX2, and PX3 may include a plurality of pixel transistors (eg, Figure 4 The first transistor T1 to the fifth transistor T5 in the embodiment of the present invention are provided, and the plurality of pixel transistors are formed by a semiconductor process, and the plurality of pixel transistors can be disposed on a semiconductor substrate (eg, Figure 6 In an embodiment, for example, the plurality of pixel transistors may include or be formed of a complementary metal oxide semiconductor (CMOS).

[0069] Each of the plurality of pixels PX1, PX2, and PX3 may be connected to a corresponding one of the plurality of first gate lines GIL, a corresponding one of the plurality of second gate lines GCL, a corresponding one of the plurality of emission control lines EML, and a corresponding one of the plurality of data lines DL (in Figure 4 ). Each of the plurality of pixels PX1, PX2, and PX3 may receive a data voltage of the data line DL in response to a first gate signal of the first gate line GIL, and the light emitting element may emit light based on the data voltage.

[0070] In an embodiment, Figure 2 As shown in FIG. 1 , the non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0071] The scan driving area SDA may be an area in which the scan driver 610 and the emission driver 620 are disposed. Figure 2 , the scanning driver 610 is arranged on the left side of the display area DAA and the emission driver 620 is arranged on the right side of the display area DAA, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, both the scanning driver 610 and the emission driver 620 may be arranged on either the left side or the right side of the display area DAA.

[0072] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed by a semiconductor process and may be formed on the semiconductor substrate described above. In an embodiment, for example, the plurality of scan transistors and the plurality of light emitting transistors may include or be formed by CMOS.

[0073] refer to Figure 1 , Figure 2 and Figure 3 And combined with Figure 4 and Figure 6 , the scan driver 610 may include a first scan signal output unit 611 and a second scan signal output unit 612. Each of the first scan signal output unit 611 and the second scan signal output unit 612 may receive a scan timing control signal SCS from the timing control circuit (timing controller) 400. The first scan signal output unit 611 may generate a first gate signal GI in response to the scan timing control signal SCS of the timing control circuit 400 and sequentially output the first gate signal GI to the first gate line GIL. The second scan signal output unit 612 may generate a second gate signal GC in response to the scan timing control signal SCS and sequentially output the second gate signal GC to the second gate line GCL.

[0074] The emission driver 620 may receive an emission timing control signal ECS from the timing control circuit 400. The emission driver 620 may generate an emission control signal EM in response to the emission timing control signal ECS and sequentially output the emission control signal EM to the emission control lines EML.

[0075] The data driving area DDA may be an area where the data driver 700 is disposed. The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on the aforementioned semiconductor substrate by a semiconductor process. In an embodiment, for example, the plurality of data transistors may include or be formed of CMOS.

[0076] The data driver 700 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage in response to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 are selected by the first gate signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0077] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may be exposed without being covered by the cover layer CVL (see FIG. Figure 6 ) and a polarizing plate (not shown).

[0078] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface of the display panel 100 (e.g., on the rear surface of the display panel 100). The heat dissipation layer 200 is used to dissipate heat generated by the display panel 100. The heat dissipation layer 200 may include graphite or a metal layer having high thermal conductivity (such as silver (Ag), copper (Cu), or aluminum (Al)).

[0079] The circuit board 300 may be electrically connected to the plurality of pads PD in the pad area PDA of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board having a flexible material, or a flexible film. Figure 1 , the circuit board 300 is shown in an unfolded state, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100. The one end of the circuit board 300 may be an end opposite to the other end of the plurality of pads PD of the circuit board 300 connected to the pad area PDA of the display panel 100 by using a conductive adhesive member.

[0080] The driving circuit 450 may include a timing control circuit 400 and a power supply circuit (power supply unit) 500 .

[0081] The timing control circuit 400 may receive digital video data DATA and a timing signal input from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610, and output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0082] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power supply voltage from the outside. In an embodiment, for example, the power supply circuit 500 may generate a common voltage ELVSS, a driving voltage (driving voltage signal) ELVDD, and an initialization voltage VINT, and supply the common voltage ELVSS, the driving voltage ELVDD, and the initialization voltage VINT to the display panel 100. Figure 4The common voltage ELVSS, the driving voltage ELVDD, and the initialization voltage VINT are described.

[0083] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one side of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. The common voltage ELVSS, the driving voltage signal ELVDD, and the initialization voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0084] Figure 4 is an equivalent circuit diagram of a pixel PX according to an embodiment.

[0085] In an embodiment, Figure 4 As shown in FIG, the pixel PX may be connected to the first gate line GIL, the second gate line GCL, the emission control line EML, the data line DL, the driving voltage line VDL and the common voltage line VSL. Here, the common voltage line VSL may be connected to the common electrode (eg, cathode electrode) of the light emitting element ED.

[0086] The pixel PX may include a pixel circuit PC and a light emitting element ED.

[0087] The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0088] The first transistor T1 (e.g., a driving transistor) may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 may control a source-drain current (hereinafter referred to as a driving current) based on a data voltage applied to its gate electrode. The driving current (Isd) flowing through the channel region of the first transistor T1 may be proportional to the square of the difference between the threshold voltage (Vth) and the voltage (Vsg) between the source electrode and the gate electrode of the first transistor T1 (Isd=k×(Vsg–Vth) 2 ). Here, Isd represents a driving current, k represents a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg represents a source-gate voltage of the first transistor T1, and Vth represents a threshold voltage of the first transistor T1. A gate electrode of the first transistor T1 may be electrically connected to the first node N1, a source electrode of the first transistor T1 may be electrically connected to the driving voltage line VDL, and a drain electrode of the first transistor T1 may be electrically connected to the third node N3.

[0089] The light emitting element ED can emit light by receiving a driving current (Isd). The light emission or brightness of the light emitting element ED can be proportional to the size of the driving current (Isd). In an embodiment, the light emitting element ED can be an organic light emitting diode including a first electrode, a second electrode and an organic light emitting layer disposed between the first electrode and the second electrode. In another embodiment, for example, the light emitting element ED can be an inorganic light emitting element including a first electrode, a second electrode and an inorganic semiconductor disposed between the first electrode and the second electrode. In another embodiment, for example, the light emitting element ED can be a quantum dot light emitting element including a first electrode, a second electrode and a quantum dot light emitting layer disposed between the first electrode and the second electrode. In another embodiment, for example, the light emitting element ED can be a micro light emitting diode. The first electrode of the light emitting element ED can be electrically connected to the drain electrode of the fifth transistor T5. The second electrode of the light emitting element ED can be connected to a common voltage line VSL. The second electrode of the light emitting element ED can receive a common voltage (for example, a low potential voltage) from the common voltage line VSL. The first electrode of the light emitting element can be an anode electrode and the second electrode of the light emitting element can be a cathode electrode.

[0090] The second transistor T2 may be turned on by the driving voltage signal ELVDD from the driving voltage line VDL to electrically connect the data line DL to the second node N2. The gate electrode of the second transistor T2 may be electrically connected to the driving voltage line VDL, the source electrode of the second transistor T2 may be electrically connected to the data line DL, and the drain electrode of the second transistor T2 may be electrically connected to the second node N2. In this case, the data line DL may transmit (at Figure 7 ) data voltage Vdat or reference voltage Vref shown in .

[0091] The third transistor T3 may be turned on by a second gate signal GC from the second gate line GCL to electrically connect the first node N1 to the third node N3. A gate electrode of the third transistor T3 may be electrically connected to the second gate line GCL, a source electrode of the third transistor T3 may be electrically connected to the third node N3, and a drain electrode of the third transistor T3 may be electrically connected to the first node N1.

[0092] The fourth transistor T4 may be turned on by the first gate signal GI from the first gate line GIL and may electrically connect the first node N1 to the initialization voltage line VIL. The gate electrode of the fourth transistor T4 may be electrically connected to the first gate line GIL, the source electrode of the fourth transistor T4 may be electrically connected to the first node N1, and the drain electrode of the fourth transistor T4 may be electrically connected to the initialization voltage line VIL. The initialization voltage line VIL may transmit an initialization voltage VINT as a DC voltage. In an embodiment, a different DC voltage may be applied to the drain electrode of the fourth transistor T4 instead of the initialization voltage.

[0093] The fifth transistor T5 may be turned on by the emission control signal EM received through the emission control line EML to electrically connect the third node N3 to the first electrode of the light emitting element ED. A gate electrode of the fifth transistor T5 may be electrically connected to the emission control line EML, a source electrode of the fifth transistor T5 may be electrically connected to the third node N3, and a drain electrode of the fifth transistor T5 may be electrically connected to the first electrode of the light emitting element ED.

[0094] The first capacitor C1 may be electrically connected between the first node N1 and the second node N2. In an embodiment, for example, a first electrode of the first capacitor C1 may be electrically connected to the first node N1, and a second electrode of the first capacitor C1 may be electrically connected to the second node N2.

[0095] The second capacitor C2 may be electrically connected between the initialization voltage line VIL and the second node N2. In an embodiment, for example, a first electrode of the second capacitor C2 may be electrically connected to the initialization voltage line VIL, and a second electrode of the second capacitor C2 may be electrically connected to the second node N2.

[0096] At least one selected from the first to fifth transistors T1 to T5 may be a metal oxide semiconductor field effect transistor (MOSFET). In an embodiment, for example, each of the first to fifth transistors T1 to T5 may be a P-type MOSFET. In another embodiment, for example, each of the first to fifth transistors T1 to T5 may be an N-type MOSFET. In another embodiment, for example, some of the first to fifth transistors T1 to T5 may be P-type MOSFETs, and the other transistors of the first to fifth transistors T1 to T5 may be N-type MOSFETs.

[0097] Figure 5 is a schematic plan view showing a unit pixel UPX of the display area DAA according to the embodiment.

[0098] refer to Figure 5 And combined with Figure 6 , each of the plurality of unit pixels UPX may include a first emission area EA1 as an emission area of ​​a first pixel PX1, a second emission area EA2 as an emission area of ​​a second pixel PX2, and a third emission area EA3 as an emission area of ​​a third pixel PX3.

[0099] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape (such as a rectangle, a square, or a rhombus) in a plan view. In an embodiment, for example, in a plan view, the first emission area EA1 may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. In an embodiment, in a plan view, each of the second emission area EA2 and the third emission area EA3 may have a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2.

[0100] The length of the first emission area EA1 in the first direction DR1 may be smaller than the length of the second emission area EA2 in the first direction DR1, and may be smaller than the length of the third emission area EA3 in the first direction DR1. The length of the second emission area EA2 in the first direction DR1 may be substantially the same as the length of the third emission area EA3 in the first direction DR1.

[0101] The length of the first emission region EA1 in the second direction DR2 may be greater than the sum of the length of the second emission region EA2 in the second direction DR2 and the length of the third emission region EA3 in the second direction DR2.

[0102] Despite Figure 5 , an embodiment in which each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 has a rectangular shape in a plan view is shown, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, in a plan view, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a quadrilateral, a circular shape, or an elliptical shape.

[0103] In each of the plurality of unit pixels UPX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first emission region EA1, the area of ​​the second emission region EA2, and the area of ​​the third emission region EA3 may be different from each other.

[0104] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the first color light may be light of a blue wavelength band, the second color light may be light of a green wavelength band, and the third color light may be light of a red wavelength band. In an embodiment, for example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in a range of about 370 nanometers (nm) to about 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in a range of about 480 nm to about 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in a range of about 600 nm to about 750 nm.

[0105] In an embodiment, Figure 5 As shown in FIG. 1 , each of the plurality of unit pixels UPX includes three emission areas EA1 , EA2 , and EA3 , but the embodiments of the present disclosure are not limited thereto. In another embodiment, for example, each of the plurality of unit pixels UPX may include four emission areas.

[0106] In addition, the arrangement of the emission regions of the plurality of unit pixels UPX is not limited to Figure 5 In an embodiment, for example, the emission regions of the plurality of unit pixels UPX may be arranged in a stripe structure in which the plurality of emission regions are arranged in a first direction DR1, in which the plurality of emission regions are arranged in a diamond shape, or in which the plurality of emission regions are arranged in a stripe structure in which the plurality of emission regions are arranged in a first direction DR2. structure, or a hexagonal structure in which a plurality of emission regions having a hexagonal shape in a plan view are arranged side by side.

[0107] Figure 6 is a diagram showing an embodiment of the display panel 100 Figure 5 A cross-sectional view taken along line AA'.

[0108] refer to Figure 6 , the display panel 100 (see Figure 1 ) includes a semiconductor base plate SBP, a light emitting element base plate EBP, a light emitting element layer EMTL, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate (not shown).

[0109] The semiconductor base plate SBP includes: a semiconductor substrate SSUB including a plurality of pixel transistors TRS; a semiconductor insulating layer SINS covering the plurality of pixel transistors TRS; and a plurality of first through holes VA1 electrically connected to the plurality of pixel transistors TRS. The plurality of pixel transistors TRS may be reference Figure 4 The first transistor T1 to the fourth transistor T4 are described.

[0110] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well areas WA may be defined on the top surface of the semiconductor substrate SSUB. A plurality of well areas WA may be areas doped with a second type of impurity. The second type of impurity may be different from the aforementioned first type of impurity. In an embodiment, for example, in the case where the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, in an embodiment where the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0111] Each well region WA includes a source S (corresponding to the source of the pixel transistor TRS), a drain D (corresponding to the drain of the pixel transistor TRS), and a channel region CH disposed between the source S and the drain D.

[0112] Each of the source S and the drain D may be a region doped with a first type impurity. The gate G of the pixel transistor TRS may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate G in the third direction DR3. The source S may be disposed on one side of the gate G, and the drain D may be disposed on the other side of the gate G.

[0113] Each of the plurality of well regions WA further includes a first low-concentration impurity region disposed between the channel region CH and the source S, and a second low-concentration impurity region disposed between the channel region CH and the drain D. The first low-concentration impurity region may be a region having an impurity concentration lower than that of the source S. The second low-concentration impurity region may be a region having an impurity concentration lower than that of the drain D. Due to the presence of the first low-concentration impurity region and the second low-concentration impurity region, the distance between the source S and the drain D may be increased. Therefore, the length of the channel region CH of each pixel transistor TRS may be increased, so that punch-through and hot carrier phenomena that may be caused by a short channel may be prevented.

[0114] The semiconductor insulating layer SINS may be disposed on the semiconductor substrate SSUB. The semiconductor insulating layer SINS may include silicon carbonitride (SiCN) or silicon oxide (SiO x ) type inorganic layer or silicon carbonitride (SiCN) or silicon oxide (SiO x )-type inorganic layer is formed, but the embodiments of the present disclosure are not limited thereto.

[0115] A plurality of first through holes VA1 may be provided on the pixel transistor TRS. The plurality of first through holes VA1 may be connected to at least one selected from the gate G, the source S, and the drain D of each pixel transistor TRS through a hole defined in the semiconductor insulating layer SINS. The plurality of first through holes VA1 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0116] A first interlayer insulating layer INS1 may be disposed on the semiconductor insulating layer SINS.

[0117] In an embodiment, the semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin (such as polyimide) substrate. In such an embodiment, the thin film transistor may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that can be bent or curved.

[0118] The light emitting element backplane EBP includes first to ninth metal layers ML1 to ML9 , reflective electrodes RL1 to RL4 , a plurality of vias VA2 to VA11 , a plurality of interlayer insulating layers INS1 to INS11 , and a step layer STPL.

[0119] The first metal layer ML1 to the ninth metal layer ML9 are connected to the pixel transistor TRS of the semiconductor substrate SBP to realize the first pixel PX1. Figure 4 That is, the first transistor T1 to the fourth transistor T4 are formed only in the semiconductor base plate SBP, and the connection between the first transistor T1 to the fourth transistor T4 and the first capacitor C1 and the second capacitor C2 is realized through the first metal layer ML1 to the ninth metal layer ML9. In addition, the connection between the drain of the first transistor T1, the source of the fourth transistor T4 and the first electrode of the light emitting element ED is realized through the first metal layer ML1 to the ninth metal layer ML9.

[0120] The first interlayer insulating layer INS1 may be disposed on the semiconductor base plate SBP. In an embodiment, for example, the first interlayer insulating layer INS1 may be disposed on the semiconductor insulating layer SINS. The first via VA1 may be disposed through the semiconductor insulating layer SINS and correspondingly connected to the exposed gate G, source S, and drain D of the pixel transistor TRS. Each of the plurality of first metal layers ML1 may be disposed on the semiconductor insulating layer SINS and may be connected to the first via VA1.

[0121] The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1 and the first metal layer ML1. Each of the plurality of second vias VA2 may penetrate the second interlayer insulating layer INS2 and be connected to the exposed first metal layer ML1. Each of the plurality of second metal layers ML2 may be disposed on the second interlayer insulating layer INS2 and may be connected to the second vias VA2.

[0122] The third interlayer insulating layer INS3 may be disposed on the second interlayer insulating layer INS2 and the second metal layer ML2. Each of the plurality of third vias VA3 may be disposed through the third interlayer insulating layer INS3 and connected to the exposed second metal layer ML2. Each of the plurality of third metal layers ML3 may be disposed on the third interlayer insulating layer INS3 and may be connected to the third vias VA3.

[0123] The fourth interlayer insulating layer INS4 may be disposed on the third interlayer insulating layer INS3 and the third metal layer ML3. Each of the plurality of fourth vias VA4 may be disposed through the fourth interlayer insulating layer INS4 and connected to the exposed third metal layer ML3. Each of the plurality of fourth metal layers ML4 may be disposed on the fourth interlayer insulating layer INS4 and may be connected to the fourth via VA4.

[0124] A fifth interlayer insulating layer INS5 may be disposed on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. Each of a plurality of fifth vias VA5 may be disposed through the fifth interlayer insulating layer INS5 and connected to the exposed fourth metal layer ML4. Each of a plurality of fifth metal layers ML5 may be disposed on the fifth interlayer insulating layer INS5 and may be connected to the fifth via VA5.

[0125] The sixth interlayer insulating layer INS6 may be disposed on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. Each of the plurality of sixth vias VA6 may be disposed through the sixth interlayer insulating layer INS6 and connected to the exposed fifth metal layer ML5. Each of the plurality of sixth metal layers ML6 may be disposed on the sixth interlayer insulating layer INS6 and may be connected to the sixth via VA6.

[0126] The seventh interlayer insulating layer INS7 may be disposed on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. Each of the plurality of seventh vias VA7 may be disposed through the seventh interlayer insulating layer INS7 and connected to the exposed sixth metal layer ML6. Each of the plurality of seventh metal layers ML7 may be disposed on the seventh interlayer insulating layer INS7 and may be connected to the seventh via VA7.

[0127] The eighth interlayer insulating layer INS8 may be disposed on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. Each of the plurality of eighth vias VA8 may be disposed through the eighth interlayer insulating layer INS8 and connected to the exposed seventh metal layer ML7. Each of the plurality of eighth metal layers ML8 may be disposed on the eighth interlayer insulating layer INS8 and may be connected to the eighth via VA8.

[0128] A ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. Each of a plurality of ninth vias VA9 may be disposed through the ninth interlayer insulating layer INS9 and connected to the exposed eighth metal layer ML8. Each of a plurality of ninth metal layers ML9 may be disposed on the ninth interlayer insulating layer INS9 and may be connected to the ninth via VA9.

[0129] The first metal layer ML1 to the ninth metal layer ML9 may be made of substantially the same material as the first through hole VA1 to the ninth through hole VA9. The first metal layer ML1 to the ninth metal layer ML9 and the first through hole VA1 to the ninth through hole VA9 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy thereof (i.e., an alloy of at least two selected therefrom), or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy thereof (i.e., an alloy of at least two selected therefrom). The first through hole VA1 to the ninth through hole VA9 may include or be made of substantially the same material as each other. In an embodiment, for example, the first interlayer insulating layer INS1 to the ninth interlayer insulating layer INS9 may include silicon oxide (SiO x ) inorganic layer or silicon oxide (SiO x )-type inorganic layer is formed, but the embodiments of the present disclosure are not limited thereto.

[0130] The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, and the seventh metal layer ML7 may be greater than the thickness of each of the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, and the seventh through hole VA7. The thickness of each of the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, and the seventh metal layer ML7 may be greater than the thickness of the second metal layer ML2. The thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, the thickness of the sixth metal layer ML6, and the thickness of the seventh metal layer ML7 may be substantially the same as each other. In an embodiment, for example, the thickness of the second metal layer ML2 may be approximately 1360 angstroms. The thickness of each of the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, and the seventh metal layer ML7 may be approximately The thickness of each of the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, and the seventh through hole VA7 may be approximately

[0131] The thickness of each of the eighth metal layer ML8 and the ninth metal layer ML9 may be greater than the thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, and the seventh metal layer ML7. The thickness of each of the eighth metal layer ML8 and the ninth metal layer ML9 may be greater than the thickness of each of the eighth through-hole VA8 and the ninth through-hole VA9. The thickness of each of the eighth through-hole VA8 and the ninth through-hole VA9 may be greater than the thickness of each of the second through-hole VA2, the third through-hole VA3, the fourth through-hole VA4, the fifth through-hole VA5, the sixth through-hole VA6, and the seventh through-hole VA7. The thickness of the eighth metal layer ML8 and the thickness of the ninth metal layer ML9 may be substantially the same as each other. In an embodiment, for example, the thickness of each of the eighth metal layer ML8 and the ninth metal layer ML9 may be approximately In an embodiment, for example, the thickness of each of the eighth through-hole VA8 and the ninth through-hole VA9 may be approximately

[0132] The tenth interlayer insulating layer INS10 may be disposed on the ninth interlayer insulating layer INS9 and the ninth metal layer ML9. In an embodiment, for example, the tenth interlayer insulating layer INS10 may include silicon oxide (SiO x ) inorganic layer or silicon oxide (SiO x )-type inorganic layer is formed, but the embodiments of the present disclosure are not limited thereto.

[0133] Each of the plurality of tenth vias VA10 may penetrate the tenth interlayer insulating layer INS10 and be connected to the exposed ninth metal layer ML9. The tenth via VA10 may include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The thickness of the tenth via VA10 may be approximately 100 Å.

[0134]

[0135] Each of the plurality of first reflective electrodes RL1 may be disposed on the tenth interlayer insulating layer INS10 and may be connected to the tenth via hole VA10. The first reflective electrode RL1 may include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0136] Each of the plurality of second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. In an embodiment, for example, the second reflective electrode RL2 may be made of titanium nitride (TiN).

[0137] In the first pixel PX1, the step layer STPL may be disposed on the second reflective electrode RL2. The step layer STPL may not be disposed in each of the second pixel PX2 and the third pixel PX3. In order to effectively reflect the light of the first color emitted from the intermediate layer IL of the first pixel PX1, the thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the intermediate layer IL to the fourth reflective electrode RL4. The step layer STPL may include silicon carbon nitride (SiCN) or silicon oxide (SiO x ) type inorganic layer or silicon carbonitride (SiCN) or silicon oxide (SiO x) type inorganic layer is formed, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the thickness of the step layer STPL may be about

[0138] In the first pixel PX1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second pixel PX2 and the third pixel PX3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0139] In an embodiment, at least one selected from the first reflective electrode RL1 , the second reflective electrode RL2 , and the third reflective electrode RL3 may be omitted.

[0140] A plurality of fourth reflective electrodes RL4 may be disposed on the plurality of third reflective electrodes RL3, respectively. The fourth reflective electrode RL4 may reflect light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to advantageously reflect light. The fourth reflective electrode RL4 may include aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy (the APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu)), and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), or may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy (the APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu)), and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, each fourth reflective electrode RL4 may have approximately Thickness.

[0141] The eleventh interlayer insulating layer INS11 may be disposed on the tenth interlayer insulating layer INS10 and the fourth reflective electrode RL4. The eleventh interlayer insulating layer INS11 may include silicon oxide (SiO x ) inorganic layer or silicon oxide (SiO x )-type inorganic layer is formed, but the embodiments of the present disclosure are not limited thereto.

[0142] Each of the plurality of eleventh through holes VA11 may penetrate the eleventh interlayer insulating layer INS11 and be connected to the exposed tenth metal layer ML10. The eleventh through hole VA11 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. Due to the presence of the step layer STPL, the thickness of the eleventh through hole VA11 in the first pixel PX1 may be less than the thickness of the eleventh through hole VA11 in each of the second pixel PX2 and the third pixel PX3. In an embodiment, for example, the thickness of the eleventh through hole VA11 in the first pixel PX1 may be approximately And the thickness of the eleventh through hole VA11 in each of the second pixel PX2 and the third pixel PX3 may be approximately

[0143] The light emitting element layer EMTL may be disposed on the light emitting element backplane EBP. The light emitting element layer EMTL may include a light emitting element ED, a pixel defining layer PDL, and a plurality of trenches TRC, each of the plurality of light emitting elements ED including a first electrode AND, an intermediate layer IL, and a second electrode CAT.

[0144] The first electrode AND of each of the plurality of light emitting elements ED may be disposed on the eleventh interlayer insulating layer INS11 and connected to the eleventh through hole VA11. The first electrode AND of each of the plurality of light emitting elements ED may be connected to the drain D or the source S of the pixel transistor TRS through the eleventh through hole VA11, the first to fourth reflective electrodes RL1 to RL4, the first to tenth through holes VA10, and the first to ninth metal layers ML1 to ML9. The first electrode AND of each of the plurality of light emitting elements ED may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. In an embodiment, for example, the first electrode AND of each of the plurality of light emitting elements ED may be titanium nitride (TiN).

[0145] The pixel defining layer PDL may be disposed on a portion of the first electrode AND of each of the plurality of light emitting elements ED. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the plurality of light emitting elements ED. The pixel defining layer PDL may be used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0146] The first emission area EA1 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second emission area EA2 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third emission area EA3 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0147] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be disposed on an edge of the first electrode AND of each light emitting element ED, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may include silicon oxide (SiO x ) inorganic layer or silicon oxide (SiO x ) type inorganic layer is formed, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have approximately Thickness.

[0148] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1 , the second pixel defining layer PDL2 , and the third pixel defining layer PDL3 . The eleventh interlayer insulating layer INS11 may be partially recessed at each of the plurality of trenches TRC.

[0149] At least one trench TRC may be provided or defined between adjacent pixels PX1, PX2, and PX3. Figure 6 An embodiment in which two trenches TRC are defined between adjacent pixels PX1 , PX2 , and PX3 is illustrated, but embodiments of the present disclosure are not limited thereto.

[0150] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0151] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 emitting different lights. In an embodiment, for example, the intermediate layer IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked.

[0152] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting a first color light, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting a third color light, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting a second color light, and a third electron transport layer are sequentially stacked.

[0153] A first charge generation layer for supplying holes to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be provided between the first intermediate layer IL1 and the second intermediate layer IL2. A second charge generation layer for supplying holes to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be provided between the second intermediate layer IL2 and the third intermediate layer IL3.

[0154] The first intermediate layer IL1 may be disposed on the first electrode AND and the pixel defining layer PDL, and may be disposed on the bottom surface of each groove TRC. Due to the groove TRC, the first intermediate layer IL1 may be separated or disconnected at the boundary between adjacent pixels PX1, PX2, and PX3. The second intermediate layer IL2 may be disposed on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 may be separated or disconnected at the boundary between adjacent pixels PX1, PX2, and PX3. The third intermediate layer IL3 may be disposed on the second intermediate layer IL2. Due to the groove TRC, the third intermediate layer IL3 may be separated or disconnected at the boundary between adjacent pixels PX1, PX2, and PX3. That is, each of the plurality of grooves TRC may be a structure for separating the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2, and PX3.

[0155] In order to stably separate the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2 and PX3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3.

[0156] In order to cut off the first, second and third intermediate layers IL1, IL2 and IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2 and PX3, another structure may exist instead of the trench TRC. In an embodiment, for example, a reverse tapered partition wall may be provided on the pixel defining layer PDL instead of the trench TRC.

[0157] The number of the intermediate layers IL1, IL2 and IL3 emitting different light is not limited to Figure 6 In the embodiment, for example, the intermediate layer IL may include two intermediate layers. In such an embodiment, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In such an embodiment, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be provided between the two intermediate layers.

[0158] in addition, Figure 6 An embodiment in which the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all disposed in the first emission area EA1, the second emission area EA2, and the third emission area EA3 is shown, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the first intermediate layer IL1 may be disposed in the first emission area EA1 and may not be disposed in the second emission area EA2 and the third emission area EA3. In an embodiment, the second intermediate layer IL2 may be disposed in the second emission area EA2 and may not be disposed in the first emission area EA1 and the third emission area EA3. In an embodiment, the third intermediate layer IL3 may be disposed in the third emission area EA3 and may not be disposed in the first emission area EA1 and the second emission area EA2. In such an embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0159] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may include a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag) or an alloy of Mg and Ag), or may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag) or an alloy of Mg and Ag). In an embodiment in which the second electrode CAT is formed of a semi-transmissive conductive material, the light emitting efficiency may be improved in each of the first pixel PX1, the second pixel PX2 and the third pixel PX3 due to the microcavity effect.

[0160] The encapsulation layer TFE may be disposed on the light emitting element layer EMTL. The encapsulation layer TFE may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer EMTL from foreign substances such as dust. In an embodiment, for example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0161] The first encapsulation inorganic layer TFE1 may be disposed on the second electrode CAT, the encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ) and aluminum oxide (AlO x ) layer, or a multilayer in which one or more inorganic layers are alternately stacked, or a multilayer in which silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ) and aluminum oxide (AlO x ) layer is formed by alternately stacking one or more inorganic layers in the encapsulation organic layer TFE2. The encapsulation organic layer TFE2 may include a monomer. Alternatively, the encapsulation organic layer TFE2 may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0162] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member (such as a transparent adhesive resin member).

[0163] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0164] The first color filter CF1 may overlap with the first emission area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of the first color (i.e., light of the blue wavelength band). The blue wavelength band may be approximately 370nm to 460nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0165] The second color filter CF2 may overlap with the second emission area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of the second color (i.e., light of the green wavelength band). The green wavelength band may be approximately 480nm to 560nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0166] The third color filter CF3 may overlap with the third emission area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color (i.e., light of a red wavelength band). The red wavelength band may be approximately 600nm to 750nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third emission area EA3.

[0167] A plurality of lenses LNS may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing a ratio of light directed to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0168] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index so that light travels in the third direction DR3 at an interface between the filling layer FIL and the plurality of lenses LNS. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0169] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. In an embodiment where the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In such an embodiment, the filling layer FIL may be used to bond the cover layer CVL. In an embodiment where the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. In an embodiment where the cover layer CVL is a polymer resin, the cover layer CVL may be directly applied to the filling layer FIL.

[0170] A polarizing plate (not shown) may be provided on one surface of the cover layer CVL. The polarizing plate may be a structure for preventing visibility reduction caused by reflection of external light. The polarizing plate may include a linear polarizing plate and a phase delay film. In an embodiment, for example, the phase delay film may be a λ / 4 plate (quarter wave plate), but the embodiments of the present disclosure are not limited thereto. However, in an embodiment where the visibility reduction caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may be omitted.

[0171] Figure 7 yes Figure 4 Signal timing diagram of the driving voltage signal ELVDD, the first gate signal GI and the second gate signal GC, the emission control signal EM and the data signal data.

[0172] In an embodiment, Figure 7 As shown in FIG. 1 , the display device 10 (see Figure 1 ) can be based on the initialization period P1, the threshold voltage detection period P2, the data writing period P3 and the emission period P4 operation. Here, the threshold voltage detection period P2 can represent the detection of the first transistor T1 (see Figure 4 )'s threshold voltage (Vth).

[0173] The initialization period P1, the threshold voltage detection period P2, the data writing period P3 and the emission period P4 may be repeated sequentially and cyclically. In an embodiment, for example, the threshold voltage detection period P2 may be performed after the initialization period P1, the data writing period P3 may be performed after the threshold voltage detection period P2, the emission period P4 may be performed after the data writing period P3, and the initialization period P1 may be performed again after the emission period P4. After the initialization period P1, the previous period may be repeated again.

[0174] In an embodiment, the initialization period P1, the threshold voltage detection period P2, and the data writing period P3 adjacent to each other may correspond to one horizontal period (1H). In other words, one horizontal period (1H) may include the initialization period P1, the threshold voltage detection period P2, or the data writing period P3. Here, the horizontal period (1H) may refer to a period during which pixels arranged in a horizontal direction (e.g., a first direction) (e.g., pixels in a row) are driven. Here, pixels in a row may refer to pixels commonly connected to a gate line (e.g., a first gate line GIL (see Figure 4 )) and are accordingly connected to a plurality of different data lines DL (see Figure 4 ) of multiple pixels.

[0175] Each of the driving voltage signal ELVDD, the first gate signal GI, the second gate signal GC, and the emission control signal EM may have an effective level or an ineffective level based on each of the periods P1 to P4 described above. Here, the effective level of each signal ELVDD, GI, GC, EM may represent a voltage at a turn-on voltage level (i.e., a level capable of being turned on) of the corresponding transistor to which the corresponding signal is applied. In other words, the effective level signal may have a value greater than the threshold voltage of the corresponding transistor. In an embodiment, for example, Figure 4 As shown in , in the case where each transistor is a P-type transistor, the effective level of each signal may represent a low level (e.g., a negative voltage). In such embodiments, the ineffective level of each signal may represent a voltage at a cut-off voltage level (i.e., a level capable of being cut off) of the corresponding transistor. In other words, the ineffective level signal may have a value smaller than the threshold voltage of the corresponding transistor. In an embodiment, for example, as Figure 4 As shown in , when each transistor is a P-type transistor, the invalid level of each signal can represent a high level (e.g., a positive voltage). In another embodiment, when each transistor is an N-type transistor, the valid level of each signal can represent a high level (e.g., a positive voltage), and the invalid level of each signal can represent a low level (e.g., a negative voltage).

[0176] The driving voltage signal ELVDD of an effective level, the first gate signal GI of an effective level, the second gate signal GC of an effective level, and the emission control signal EM of an effective level may have the same size (or the same voltage level) as each other.

[0177] The driving voltage signal ELVDD of an inactive level, the first gate signal GI of an inactive level, the second gate signal GC of an inactive level, and the emission control signal EM of an inactive level may have the same size as each other.

[0178] The driving voltage signal ELVDD of the effective level may be lower than the driving voltage signal ELVDD of the ineffective level.

[0179] The reference voltage Vref may be lower than or equal to the common voltage ELVSS (see Figure 4 ).

[0180] In an embodiment, in the initialization period P1, each of the driving voltage signal ELVDD and the first gate signal GI may have an effective level, and each of the second gate signal GC and the emission control signal EM may have an ineffective level. In such an embodiment, in the initialization period P1, the data signal data may have a level of the reference voltage Vref. In other words, the data signal data in the initialization period P1 may be the reference voltage Vref. In an embodiment, for example, the reference voltage Vref may be higher than the driving voltage signal ELVDD of the effective level (e.g., a negative voltage) and lower than the common voltage ELVSS.

[0181] In the threshold voltage detection period P2, the second gate signal GC may have an active level, and each of the driving voltage signal ELVDD, the first gate signal GI, and the emission control signal EM may have an inactive level. In the threshold voltage detection period P2, the data signal data may have a level of the reference voltage Vref.

[0182] In the data writing period P3, the driving voltage signal ELVDD may have an effective level, but each of the first gate signal GI, the second gate signal GC, and the emission control signal EM may have an ineffective level. In the data writing period P3, the data signal data may have a level of the data voltage Vdat. In other words, the data signal data in the data writing period P3 may be a data voltage Vdat having a value corresponding to a specific gray level of an image to be displayed in the screen.

[0183] In the emission period P4, the emission control signal EM may have an active level, and each of the driving voltage signal ELVDD, the first gate signal GI, and the second gate signal GC may have an inactive level. In the emission period P4, the data signal data may be maintained at the level of the reference voltage Vref.

[0184] Reference Figures 7 to 11 The operation of the display device according to the embodiment of the present disclosure is described. Figures 8 to 11 , the transistor surrounded by the circular dotted line is a transistor in an on state, and the transistor not surrounded by the circular dotted line is a transistor in an off state.

[0185] First, refer to Figure 7 and Figure 8Description of the display device 10 (see Figure 1 ) Operation in initialization period P1.

[0186] Figure 8 It is shown Figure 4 The pixel PX is Figure 7 FIG. 5 is a diagram of the operations during the initialization cycle P1.

[0187] like Figure 7 As shown in , each of the driving voltage signal ELVDD and the first gate signal GI may have an active level, and each of the second gate signal GC and the emission control signal EM may have an inactive level. In the initialization period P1, the data signal data may have a level of the reference voltage Vref.

[0188] like Figure 8 As shown in FIG. 1 , the first gate signal GI of the effective level may be applied to the gate electrode of the fourth transistor T4 through the first gate line GIL. Therefore, the fourth transistor T4 may be turned on.

[0189] like Figure 8 As shown in FIG. 1 , a driving voltage signal ELVDD of an effective level (eg, a negative voltage L) may be applied to a gate electrode of the second transistor T2 through the driving voltage line VDL. Therefore, the second transistor T2 may be turned on.

[0190] like Figure 8 As shown in FIG. 1 , the second gate signal GC of the inactive level may be applied to the gate electrode of the third transistor T3 through the second gate line GCL. Therefore, the third transistor T3 may be turned off.

[0191] like Figure 8 As shown in FIG. 1 , the emission control signal EM of the inactive level may be applied to the gate electrode of the fifth transistor T5 through the emission control line EML. Therefore, the fifth transistor T5 may be turned off.

[0192] like Figure 8 As shown in FIG. 1 , the initialization voltage VINT from the initialization voltage line VIL may be applied to the first node N1 through the turned-on fourth transistor T4. Therefore, the first transistor T1 connected to the first node N1 through the gate electrode may be turned off.

[0193] like Figure 8 As shown in , a driving voltage signal ELVDD of an active level from a driving voltage line VDL may be applied to a source electrode of the first transistor T1 .

[0194] like Figure 8 As shown in FIG. 1 , the reference voltage Vref from the data line DL may be applied to the second node N2 through the turned-on second transistor T2 .

[0195] Therefore, in the initialization period P1, each of the first node N1, the second node N2, and the source electrode of the first transistor T1 may be initialized.

[0196] In the initialization period P1, the voltage of the second node N2 can be kept stable by the initialization voltage VINT as a DC voltage and the second capacitor C2 receiving the initialization voltage VINT. Therefore, the voltage of the drain electrode of the second transistor T2 connected to the second node N2 can be kept stable. Therefore, the data voltage can be stably applied in the data writing period P3.

[0197] Next, the display device 10 (see Figure 1 ) The operation in the threshold voltage detection period P2 will refer to Figure 7 and Fig. 9 Description is as follows.

[0198] Fig. 9 It is shown Figure 4 The pixel PX is Figure 7 FIG. 1 is a diagram of the operation of the threshold voltage detection period P2.

[0199] like Figure 7 As shown in , in the threshold voltage detection period P2, the second gate signal GC may have a valid level, and each of the driving voltage signal ELVDD, the first gate signal GI, and the emission control signal EM may have an invalid level. In the threshold voltage detection period P2, the data signal data may have a level of the reference voltage Vref.

[0200] like Fig. 9 As shown in , the second gate signal GC of the effective level can be applied to the gate electrode of the third transistor T3 through the second gate line GCL. Therefore, the third transistor T3 can be turned on. The initialization voltage VINT of the first node N1 can be applied to the drain electrode of the first transistor T1 through the turned-on third transistor T3. Therefore, the drain electrode of the first transistor T1 can be initialized.

[0201] like Fig. 9 As shown in FIG. 1 , the driving voltage signal ELVDD of an inactive level (eg, a positive voltage H) may be applied to the gate electrode of the second transistor T2 through the driving voltage line VDL. Therefore, the second transistor T2 may be turned off.

[0202] like Fig. 9 As shown in FIG. 1 , the first gate signal GI of the inactive level may be applied to the gate electrode of the fourth transistor T4 through the first gate line GIL. Therefore, the fourth transistor T4 may be turned off.

[0203] like Fig. 9As shown in FIG. 1 , the emission control signal EM of the inactive level may be applied to the gate electrode of the fifth transistor T5 through the emission control line EML. Therefore, the fifth transistor T5 may be turned off.

[0204] In the threshold voltage detection period P2, the gate electrode and the drain electrode of the first transistor T1 are connected to each other through the turned-on third transistor T3, so that the first transistor T1 can be operated as a diode. In other words, the first transistor T1 configured to operate as a diode in the threshold voltage detection period P2 can be turned on by the initialization voltage VINT applied to its gate electrode and the driving voltage signal ELVDD of the invalid level (e.g., high level) applied to its source electrode. In this case, the initialization voltage VINT applied to the gate electrode of the first transistor T1 can be lower than the driving voltage signal ELVDD (e.g., positive voltage H) of the invalid level applied to the source electrode of the first transistor T1. Therefore, the P-type first transistor T1 can be turned on. The first capacitor C1 can be charged by the turned-on first transistor T1. At the same time, when the first capacitor C1 starts to charge and the voltage across the first capacitor C1 reaches the threshold voltage (Vth) of the first transistor T1, the first transistor T1 is turned off. In other words, as the first capacitor C1 is charged, the voltage of the first node N1 as one electrode of the first capacitor C1 gradually increases. When the voltage of the first node N1 reaches the sum of the inactive level driving voltage signal ELVDD and the threshold voltage of the first transistor T1 (i.e., the inactive level driving voltage signal ELVDD+the threshold voltage (Vth) of the first transistor T1), the first transistor T1 is turned off. Therefore, when the first transistor T1 is turned off, the threshold voltage (Vth) of the first transistor T1 can be stored in the first capacitor C1.

[0205] Thus, in the threshold voltage detection period P2 , the threshold voltage (Vth) of the first transistor T1 may be detected and may be maintained by the first capacitor C1 .

[0206] Next, we will refer to Figure 7 and Fig.10 Description of the display device 10 (see Figure 1 ) Operation in the data write cycle P3.

[0207] Fig.10 It is shown Figure 4 The pixel PX is Figure 7 FIG. 1 is a diagram of the operation in the data write cycle P3.

[0208] like Figure 7As shown in , in the data write period P3, the driving voltage signal ELVDD may have an effective level, and each of the first gate signal GI, the second gate signal GC, and the emission control signal EM may have an invalid level. In the data write period P3, the data signal data may have a level of the data voltage Vdat. In other words, the data signal data in the data write period P3 may be a data voltage Vdat having a value corresponding to a specific gray level of an image to be displayed in the screen.

[0209] like Fig.10 As shown in FIG. 1 , the driving voltage signal ELVDD of an effective level may be applied to the gate electrode of the second transistor T2 through the driving voltage line VDL. Therefore, the second transistor T2 may be turned on.

[0210] like Fig.10 As shown in FIG. 1 , the first gate signal GI of the inactive level may be applied to the gate electrode of the fourth transistor T4 through the first gate line GIL. Therefore, the fourth transistor T4 may be turned off.

[0211] like Fig.10 As shown in FIG. 1 , the second gate signal GC of the inactive level may be applied to the gate electrode of the third transistor T3 through the second gate line GCL. Therefore, the third transistor T3 may be turned off.

[0212] like Fig.10 As shown in FIG. 1 , the emission control signal EM of the inactive level may be applied to the gate electrode of the fifth transistor T5 through the emission control line EML. Therefore, the fifth transistor T5 may be turned off.

[0213] like Fig.10 As shown in , the data voltage Vdat can be applied to the second node N2 through the data line DL and the turned-on second transistor T2. Here, since the first node N1 is in a floating state, the voltage of the first node N1 can also increase the voltage coupled by the second capacitor C2 (e.g., the data voltage Vdat). In particular, the size of the data voltage Vdat added to the voltage of the first node N1 can be determined by the ratio between the capacitance of the second capacitor C2 and the capacitance of the first capacitor C1. In an embodiment, for example, the voltage added to the first node N1 can have a value corresponding to "data voltage × (capacitance of C2 / (capacitance of C1+capacitance of C2))". In this case, since the data voltage Vdat is divided by the first capacitor C1 and the second capacitor C2, the range of the data voltage Vdat (e.g., grayscale expression range) can be extended. In an embodiment, the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 may be the same. However, it is not limited thereto, and the capacitance of the first capacitor C1 may be greater than the capacitance of the second capacitor C2. Alternatively, the capacitance of the second capacitor C2 may be greater than the capacitance of the first capacitor C1.

[0214] During the data write period P3, the difference voltage (e.g., gate-source voltage) between the first node N1 as the gate electrode of the first transistor T1 and the source electrode of the first transistor T1 may be maintained by the first capacitor C1. The gate-source voltage may include a threshold voltage (Vth) of the first transistor T1 and a data voltage Vdat. In the data write period P3, the voltage of the first node N1 is higher than the effective level of the driving voltage signal ELVDD (e.g., negative voltage L), and thus the first transistor T1 may be turned off.

[0215] In this way, during the data writing period P3, the voltage of the first node N1 which is the gate electrode of the first transistor T1 can have a value obtained by adding the data voltage Vdat to the voltage of the threshold voltage detection period P2 (eg, the threshold voltage of the first transistor T1).

[0216] Next, we will refer to Figure 7 and Fig.11 Description of the display device 10 (see Figure 1 )Operation in transmission cycle P4.

[0217] Fig.11 It is shown Figure 4 The pixel PX is Figure 7 FIG. 4 is a diagram of the operation during the emission cycle P4.

[0218] like Figure 7 As shown in , in the emission period P4, the emission control signal EM may have an effective level, and each of the driving voltage signal ELVDD, the first gate signal GI, and the second gate signal GC may have an inactive level. In the emission period P4, the data signal data may be maintained at the level of the reference voltage Vref.

[0219] like Fig.11 As shown in FIG. 1 , the emission control signal EM of an effective level may be applied to the gate electrode of the fifth transistor T5 through the emission control line EML. Therefore, the fifth transistor T5 may be turned on.

[0220] like Fig.11 As shown in FIG. 1 , an inactive level driving voltage signal ELVDD (eg, a positive voltage H) may be applied to a source electrode of the first transistor T1 and a gate electrode of the second transistor T2 through a driving voltage line VDL. Thus, the first transistor T1 may be turned on and the second transistor T2 may be turned off.

[0221] like Fig.11 As shown in FIG. 1 , the first gate signal GI of the inactive level may be applied to the gate electrode of the fourth transistor T4 through the first gate line GIL. Therefore, the fourth transistor T4 may be turned off.

[0222] like Fig.11 As shown in FIG. 1 , the second gate signal GC of the inactive level may be applied to the gate electrode of the third transistor T3 through the second gate line GCL. Therefore, the third transistor T3 may be turned off.

[0223] Meanwhile, in the emission period P4 , the first transistor T1 may be maintained in a turned-on state by the gate-source voltage maintained by the first capacitor C1 .

[0224] Thus, in the emission period P4, since the first transistor T1 and the fifth transistor T5 are turned on, the driving voltage ELVDD of the invalid level (e.g., the positive voltage H) can be applied to the first electrode (e.g., N3) of the light emitting element ED through the turned-on first transistor T1 and the fifth transistor T5. At this time, since the gate-source voltage maintained by the first capacitor C1 includes the threshold voltage (Vth) of the first transistor T1, the magnitude of the driving current flowing to the light emitting element ED through the turned-on first transistor T1 can be determined based on the data voltage Vdat and the threshold voltage (Vth) of the first transistor T1. Therefore, the driving current supplied to the light emitting element ED can accurately reflect the magnitude of the data voltage Vdat. In other words, the aforementioned driving current can have an accurate value in which the threshold voltage (Vth) of the first transistor T1 is compensated. Thus, since the threshold voltage (Vth) of the first transistor T1 of each pixel PX is compensated to determine the driving current of each pixel, the brightness deviation between the pixels PX according to the deviation of the threshold voltage (Vth) between the first transistors T1 of the pixels PX can be minimized. Therefore, the image quality of the display device 10 can be improved.

[0225] According to the display device 10 of the embodiment, the driving voltage signal ELVDD can be applied in an alternating manner (e.g., an effective level and an inactive level). Therefore, the conduction and cutoff of the second transistor T2 can be controlled by the driving voltage signal ELVDD. Therefore, a separate gate line is not used to control the conduction and cutoff of the second transistor T2. Therefore, the number of gate lines used to drive the display device 10 can be reduced.

[0226] In such an embodiment, since the threshold voltage detection period P2 and the data writing period P3 are separated, the data voltage Vdat can be written at high speed. Therefore, high-speed driving of the display device 10 is possible.

[0227] Fig.12 is an equivalent circuit diagram of a pixel PX according to an embodiment.

[0228] In addition to the connection relationship between the fourth transistor T4 and the second capacitor C2, Fig.12 The pixel PX is the same as described above. Figure 4 The pixels PX are substantially the same. This difference will be mainly described as follows.

[0229] Fig.12 The fourth transistor T4 may be turned on by the first gate signal GI from the first gate line GIL to electrically connect the first node N1 to the common voltage line VSL. A gate electrode of the fourth transistor T4 may be electrically connected to the first gate line GIL, a source electrode of the fourth transistor T4 may be electrically connected to the first node N1, and a drain electrode of the fourth transistor T4 may be electrically connected to the common voltage line VSL.

[0230] Fig.12 The second capacitor C2 may be electrically connected between the common voltage line VSL and the second node N2. In an embodiment, for example, a first electrode of the second capacitor C2 may be electrically connected to the common voltage line VSL, and a second electrode of the second capacitor C2 may be electrically connected to the second node N2.

[0231] In such an embodiment, the driving voltage signal ELVDD applied to the driving voltage line VDL, the first gate signal GI applied to the first gate line GIL, the second gate signal GC applied to the second gate line GCL, the emission control signal EM applied to the emission control line EML, and the emission control signal EM applied to the gate line GCL are applied to the gate line GCL. Fig.12 The data signal data of the data line DL can be the same as described above. Figure 7 The driving voltage signal ELVDD, the first gate signal GI, the second gate signal GC, the emission control signal EM and the data signal data are the same. In other words, Fig.12 The pixel PX can be based on the above described Figure 7 The driving voltage signal ELVDD, the first gate signal GI, the second gate signal GC, the emission control signal EM and the data signal data are operated.

[0232] According to the display device 10 (see Figure 1 ) will refer to Figure 7 and Figures 13 to 16 The description is as follows. Figure 13 to Figure 16 , the transistor surrounded by the circular dotted line is a transistor in an on state, and the transistor not surrounded by the circular dotted line is a transistor in an off state.

[0233] First, the operation of the display device 10 in the initialization period P1 will refer to Figure 7 and Fig.13 Description is as follows.

[0234] Fig.13 It is shown Fig.12 The pixel PX is Figure 7 FIG. 5 is a diagram of the operations during the initialization cycle P1.

[0235] Fig.13 The operation of the pixel PX in the initialization period P1 is the same as described above. Figure 8 The operation of the pixel PX in the initialization period P1 is substantially the same. Fig.13 As shown in FIG. , the common voltage ELVSS can be replaced by the fourth transistor T4 that is turned on. Figure 8 In other words, the initialization voltage VINT in is applied to the first node N1. Fig.13 As shown in FIG. 1 , the common voltage ELVSS from the common voltage line VSL may be applied to the first node N1 through the turned-on fourth transistor T4 .

[0236] Next, the display device 10 (see Figure 1 ) The operation in the threshold voltage detection period P2 will refer to Figure 7 and Fig.14 Description is as follows.

[0237] Fig.14 It is shown Fig.12 The pixel PX is Figure 7 FIG. 1 is a diagram of the operation of the threshold voltage detection period P2.

[0238] Fig.14 The operation of the pixel PX in the threshold voltage detection period P2 is the same as described above. Fig. 9 The operation of the pixel PX in the threshold voltage detection period P2 is substantially the same. Therefore, in the embodiment, Fig.14 As shown in the figure, the common voltage ELVSS replaces Fig. 9 The initialization voltage VINT is applied to the first node N1.

[0239] Next, the display device 10 (see Figure 1 ) The operation in the data write cycle P3 will refer to Figure 7 and Fig.15 Description is as follows.

[0240] Fig.15 It is shown Fig.12 The pixel PX is Figure 7 FIG. 1 is a diagram of the operation in the data write cycle P3.

[0241] Fig.15 The operation of the pixel PX in the data writing period P3 is the same as described above. Fig.10 The operation of the pixel PX in the data writing period P3 is substantially the same. Therefore, in the embodiment, Fig.15 As shown in the figure, the common voltage ELVSS replaces Fig.10 The initialization voltage VINT is applied to the first node N1.

[0242] Next, the display device 10 (see Figure 1 ) The operation in the transmission cycle P4 will refer to Figure 7 and Fig.16 Description is as follows.

[0243] Fig.16 It is shown Fig.12 The pixel PX is Figure 7 FIG. 4 is a diagram of the operation during the emission cycle P4.

[0244] Fig.16 The operation of the pixel PX in the emission period P4 is the same as described above. Fig.11 The operation of the pixel PX in the emission period P4 is substantially the same. Therefore, in the embodiment, Fig.16 As shown in the figure, the common voltage ELVSS replaces Fig.11 The initialization voltage VINT is applied to the first node N1.

[0245] Fig.17 is shown corresponding to Figure 7 Schematic diagram of the simulation signal of the signal.

[0246] Fig.17 Shows Figure 7 1 and 2 are simulation waveforms of the first gate signal GI, the second gate signal GC, the emission control signal EM, the driving voltage signal ELVDD, and the data signal data in each of the periods P1 to P4 shown in FIG.

[0247] in addition, Fig.17 Waveforms of the first node voltage V_N1 and the initialization voltage VINT in each of the periods P1 to P4 are shown.

[0248] Fig.18 is a perspective view showing a head mounted display device 1000 according to an embodiment. Fig.19 It is shown Fig.18 1000 is an exploded perspective view of an embodiment of a head mounted display device 1000.

[0249] refer to Fig.18 and Fig.19 , a head mounted display device 1000 as an optical device according to an embodiment includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, optical path conversion members 1210, 1220, 1510 and 1520, a head mounted band 1300, an intermediate frame 1400, a control circuit board 1600 and a connector.

[0250] The optical path converting members 1210 , 1220 , 1510 , and 1520 may include a first eyepiece 1210 , a second eyepiece 1220 , a first optical member 1510 , and a second optical member 1520 .

[0251] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 6 The described display devices 10 are substantially the same, and thus any repeated detailed description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0252] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0253] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0254] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (see Figure 3 ), and transmits the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0255] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0256] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 is provided to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 provided for the left eye of the user and a second eyepiece 1220 provided for the right eye of the user. Fig.18 and Fig.19 An embodiment in which the first eyepiece 1210 and the second eyepiece 1220 are separately provided is shown, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0257] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may observe the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may observe the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0258] The headband 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain disposed on the user's left eye and right eye, respectively. In an embodiment where the display device housing 1100 is desired to be lightweight and compact, as shown in FIG. Fig. 20 As shown in , the head mounted display device 1000_1 may be provided with a glasses frame instead of the head mounted band 1300 .

[0259] In addition, the head mounted display device 1000 may further include a battery for power supply, an external memory slot for receiving an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0260] Fig. 20 is a perspective view showing a head mounted display device 1000_1 according to an embodiment.

[0261] refer to Fig. 20The head mounted display device 1000_1 according to the embodiment may be a glasses type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head mounted display device 1000_1 according to the embodiment may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1100_1.

[0262] The display device housing 1100_1 may house the display device 10_3, the optical member 1060, and the optical path conversion member 1070. The image displayed in the display device 10_3 may be magnified by the optical member 1060, and may be provided to the right eye of the user through the right eye lens 1020 after its optical path is converted by the optical path conversion member 1070. Thus, the user may observe an augmented reality image through the right eye, in which the virtual image displayed in the display device 10_3 and the real image viewed through the right eye lens 1020 are combined.

[0263] Fig. 20 An embodiment in which the display device housing 1100_1 is provided at the right end of the support frame 1030 is shown, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the display device housing 1100_1 may be provided on the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the display device housing 1100_1 may be provided at the left and right ends of the support frame 1030, and in this case, the user may observe the image displayed in the display device 10_3 through both the left eye and the right eye.

[0264] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0265] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, wherein: The display device comprises: Light emitting element; A driving voltage line, wherein the driving voltage line transmits a driving voltage signal having a valid level or an invalid level within a preset period; a data line to which a data signal is applied; A first transistor connected between the driving voltage line and the light emitting element; and a second transistor connected to the driving voltage line and the data line, The gate electrode of the second transistor is connected to the driving voltage line, and the source electrode of the second transistor is connected to the data line.

2. The display device according to claim 1, wherein: The gate electrode of the first transistor is connected to the first node, the source electrode of the first transistor is connected to the driving voltage line, and the drain electrode of the first transistor is connected to the first electrode of the light emitting element through a third node, and A drain electrode of the second transistor is connected to a second node.

3. The display device according to claim 2, wherein: The display device further includes: a third transistor including a gate electrode connected to a second gate line to which a second gate signal is applied, a source electrode connected to the third node, and a drain electrode connected to the first node; a fourth transistor including a gate electrode connected to a first gate line to which a first gate signal is applied, a source electrode connected to the first node, and a drain electrode connected to an initialization voltage line; a fifth transistor including a gate electrode connected to an emission control line to which an emission control signal is applied, a source electrode connected to the third node, and a drain electrode connected to the first electrode of the light emitting element; a first capacitor connected between the first node and the second node; and The second capacitor is connected between the initialization voltage line and the second node.

4. The display device according to claim 3, wherein: The preset period includes an initialization period, a threshold voltage detection period, a data writing period and an emission period.

5. The display device according to claim 4, wherein: During the initialization cycle, Each of the driving voltage signal and the first gate signal has an effective level, Each of the second gate signal and the emission control signal has an inactive level, and The data signal has a level of a reference voltage.

6. The display device according to claim 5, wherein: The driving voltage signal of the active level, the first gate signal of the active level, the second gate signal of the active level, and the emission control signal of the active level have the same size as each other.

7. The display device according to claim 5, wherein: The driving voltage signal of the inactive level, the first gate signal of the inactive level, the second gate signal of the inactive level, and the emission control signal of the inactive level have the same size as each other.

8. The display device according to claim 5, wherein: The display device further includes: A common voltage line is connected to the second electrode of the light emitting element, wherein the common voltage line transmits a common voltage.

9. The display device according to claim 8, wherein: The reference voltage is higher than the driving voltage signal of the inactive level and lower than the common voltage.

10. The display device according to claim 8, wherein: The initialization voltage line transmits an initialization voltage, and The initialization voltage is lower than or equal to the common voltage.

11. The display device according to claim 5, wherein: Each of the driving voltage signal of the effective level, the first gate signal of the effective level, the second gate signal of the effective level, and the emission control signal of the effective level is a negative voltage, and Each of the driving voltage signal of the inactive level, the first gate signal of the inactive level, the second gate signal of the inactive level, and the emission control signal of the inactive level is a positive voltage.

12. The display device according to claim 4, wherein: In the threshold voltage detection cycle, The second gate signal has an effective level, Each of the driving voltage signal, the first gate signal, and the emission control signal has an inactive level, and The data signal has a level of a reference voltage.

13. The display device according to claim 4, wherein: In the data writing cycle, The driving voltage signal has an effective level, Each of the first gate signal, the second gate signal, and the emission control signal has an inactive level, and The data signal has a level of a data voltage.

14. The display device according to claim 4, wherein: During the transmission cycle, The emission control signal has an effective level, Each of the driving voltage signal, the first gate signal, and the second gate signal has an inactive level, and The data signal has a level of a reference voltage.

15. The display device according to claim 3, wherein: The first capacitor and the second capacitor have the same capacitance as each other.

16. The display device according to claim 3, wherein: Each of the first to fifth transistors is a P-type metal oxide semiconductor field effect transistor.

17. The display device according to claim 15, wherein: The driving voltage signal at the effective level is smaller than the driving voltage signal at the ineffective level.

18. The display device according to claim 17, wherein: The driving voltage signal of the active level is a positive voltage, and the driving voltage signal of the inactive level is a negative voltage.

19. The display device according to claim 1, wherein: The driving voltage signal of the effective level has a magnitude corresponding to a turn-on voltage of the second transistor.

20. The display device according to claim 1, wherein: The driving voltage signal of the inactive level has a magnitude corresponding to a cut-off voltage of the second transistor.

Images