Storage devices and their fabrication methods

Abstract

This application is a divisional application of application number 2021111607840. This application discloses a storage device and its fabrication method, belonging to the field of storage technology. The storage device includes a first chip and a second chip. The first chip includes a storage array, which includes at least one storage block. The second chip includes a logic control circuit, which includes a global bit-line decoder. The global bit-line decoder is electrically connected to at least one storage block. By constructing the global bit-line decoder block to be located within the top-view projection area of ​​the storage block in the second chip, the area of ​​the first and second chips stacked together can be reduced, thereby reducing the occupied area of ​​the storage device and helping to achieve a minimized size of the storage device.

Description

[0001] This application is a divisional application of the invention patent with application number "2021111607840", application date "2021.09.30", and title "Storage device and preparation method thereof". Technical Field

[0002] This application relates to the field of storage technology, specifically to a storage device and its fabrication method. Background Technology

[0003] like Figure 1 As shown, the storage device in the conventional technical solution includes multiple storage blocks 510, multiple local bit-line decoders 520, multiple word-line decoders 540, multiple global bit-line decoders 530, and other circuits 550. The construction regions of the storage blocks 510, the local bit-line decoders 520, the word-line decoders 540, the global bit-line decoders 530, and the other circuits 550 do not overlap. For example, the construction region of the local bit-line decoder 520 is located on one side of the construction region of the corresponding storage block 510, the word-line decoder 540 is located on the other side of the construction region of the corresponding local bit-line decoder 520 and / or the construction region of the storage block 510, and the construction region of the global bit-line decoder 530 is located between the construction regions of the corresponding local bit-line decoders 520 and the global bit-line decoder 530.

[0004] Specifically, such as Figure 2 As shown, along a certain direction, memory blocks 510 and local bit-line decoders 520 are arranged alternately. Following the last local bit-line decoder 520 are a global bit-line decoder 530 and multiple sense amplifiers 551. A word-line decoder 540 is located on the other side of each memory block 510. Each local bit-line decoder 520 is electrically connected to its corresponding memory block 510 and global bit-line decoder 530. The output of the global bit-line decoder 530 is electrically connected to its corresponding multiple sense amplifiers 551. Similarly, Figure 2 The construction regions of each memory block 510, each local bit line decoder 520, each global bit line decoder 530, each sense amplifier 551, and each word line decoder 540 do not overlap.

[0005] Thus, the storage devices in the aforementioned traditional technical solutions require a large space to integrate the various structural components, which is not conducive to minimizing the size of the storage devices.

[0006] It should be noted that the above description of the background technology is merely for the purpose of facilitating a clear and complete understanding of the technical solutions of this application. Therefore, it should not be assumed that the technical solutions mentioned above are known to those skilled in the art simply because they appear in the background technology of this application. Summary of the Invention

[0007] This application provides a storage device and a method for manufacturing the same, in order to alleviate the technical problem that storage devices require a large amount of space.

[0008] In a first aspect, this application provides a memory device comprising a first chip and a second chip. The first chip includes a memory array, which includes at least one memory block. The memory block includes multiple word lines extending along a first direction and multiple bit lines extending along a second direction. The second chip is stacked above the first chip along a third direction. The second chip has a top-view projection area of ​​a memory block. The second chip includes a logic control circuit, which includes a global bit line decoder. The global bit line decoder is electrically connected to at least one memory block, and the global bit line decoder block formed by the global bit line decoder is located within the top-view projection area.

[0009] In some embodiments, the logic control circuit further includes a local bit line decoder, which includes a first local bit line sub-decoder. The first local bit line sub-decoder is electrically connected to the memory block and the global bit line decoder. The first local bit line sub-decoder block formed by the first local bit line sub-decoder is located within the top-view projection area. In a first direction, the projection of the first local bit line sub-decoder block does not overlap with the projection of the global bit line decoder block.

[0010] In some embodiments, the first local bitline decoder includes a first local bitline decoder unit and a second local bitline decoder unit. The first local bitline decoder unit is electrically connected to a portion of the bitline and a global bitline decoder. The second local bitline decoder unit is electrically connected to another portion of the bitline and a global bitline decoder unit. In a first direction, the projection of the first local bitline decoder unit block formed by the first local bitline decoder unit and the projection of the second local bitline decoder unit block formed by the second local bitline decoder unit do not overlap. In a second direction, the global bitline decoder block is located between the first local bitline decoder unit block and the second local bitline decoder unit block.

[0011] In some embodiments, in the first direction, the length of the global bit line decoder block, the length of the first local bit line sub-decoding unit block, and the length of the second local bit line sub-decoding unit block are all less than or equal to the length of the top-view projection area; and in the second direction, the sum of the width of the global bit line decoder block, the width of the first local bit line sub-decoding unit block, and the width of the second local bit line sub-decoding unit block is less than or equal to the width of the top-view projection area.

[0012] In some embodiments, the logic control circuit further includes a word line decoding circuit, which includes a first word line sub-decoder electrically connected to the word line. The first word line sub-decoder block formed by the first word line sub-decoder is located within the top-view projection area, and in a second direction, the first word line sub-decoder block is located between the global bit line decoder block and the second local bit line sub-decoder unit block.

[0013] In some embodiments, the first word line decoder includes a first word line decoding unit and a second word line decoding unit, wherein the first word line decoding unit is electrically connected to a portion of the word lines; and the second word line decoding unit is electrically connected to another portion of the word lines; wherein, in a first direction, the projection of the first word line decoding unit block formed by the first word line decoding unit at least partially overlaps with the projection of the second word line decoding unit block formed by the second word line decoding unit; and in a second direction, the projections of the first word line decoding unit block and the second word line decoding unit block do not overlap.

[0014] In some embodiments, the logic control circuit further includes a sensing amplifier circuit electrically connected to the global bit line decoder, wherein the sensing amplifier circuit block is located within the top-view projection area; in a first direction, the sensing amplifier circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in a second direction, the sensing amplifier circuit block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

[0015] In some embodiments, the inductive amplifier circuit includes a first group of inductive amplifiers and a second group of inductive amplifiers. The first group of inductive amplifiers is electrically connected to a global bit line decoder and includes a plurality of inductive amplifiers arranged sequentially along a first direction. The second group of inductive amplifiers is also electrically connected to the global bit line decoder and includes a plurality of inductive amplifiers arranged sequentially along the first direction. In the first direction, the projection of the first group of inductive amplifier blocks formed by the first group of inductive amplifiers and the projection of the second group of inductive amplifier blocks formed by the second group of inductive amplifiers at least partially overlap. In the second direction, the projections of the first group of inductive amplifier blocks and the projections of the second group of inductive amplifier blocks do not overlap.

[0016] In some embodiments, in a first direction, a first word line decoding unit block, a first group of inductive amplifier blocks, a second group of inductive amplifier blocks, and a second word line decoding unit block are arranged sequentially; in the first direction, the distance from the first group of inductive amplifier blocks to the first word line decoding unit block is less than the distance from the first group of inductive amplifier blocks to the second word line decoding unit block, and the distance from the second group of inductive amplifier blocks to the first word line decoding unit block is greater than the distance from the second group of inductive amplifier blocks to the second word line decoding unit block.

[0017] In some embodiments, in a first direction, the projection of the first group of inductive amplifier blocks coincides with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block, and the projection of the second group of inductive amplifier blocks coincides with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

[0018] In some embodiments, the logic control circuit further includes multiple first traces electrically connected to the output of a global bit-line decoder and the input of multiple inductive amplifiers; in a second direction, the multiple first traces are located between the global bit-line decoder block and the inductive amplifier circuit block; and the multiple first traces are arranged sequentially along the first direction.

[0019] In some embodiments, the logic control circuit further includes a plurality of second traces electrically connected to the input of a global bit-line decoder and the output of a local bit-line decoder; the plurality of second traces are arranged sequentially in a first direction; and the plurality of second traces are located in at least one top-view projection area.

[0020] In some embodiments, the first local bit line decoding unit and the second local bit line decoding unit each have multiple first transmission terminals, and a first transmission terminal is electrically connected to a bit line through a first silicon via or a pair of first bonding pads.

[0021] In some embodiments, the first word line decoding unit and the second word line decoding unit each have multiple second transmission terminals, and a second transmission terminal is electrically connected to a word line through a second through-silicon via or a pair of second bonding pads.

[0022] In some embodiments, the first chip includes a first bonding layer, the first bonding layer including at least one first bonding pad and / or a second bonding pad; the second chip includes a second bonding layer, the second bonding layer including at least one first bonding pad and / or a second bonding pad; the first bonding pad located on the first bonding layer is bonded to the first bonding pad located on the second bonding layer, and / or, the second bonding pad located on the first bonding layer is bonded to the second bonding pad located on the second bonding layer.

[0023] In some embodiments, at least one memory block includes a first memory block to an Nth memory block arranged sequentially along a second direction; when N is odd, the global bit line decoder block is located in the top-view projection area of ​​the (N+1) / 2th memory block in the second chip; when N is even, the global bit line decoder block is located in the top-view projection area of ​​the second chip in either the N / 2th memory block or the 1+N / 2th memory block; wherein N is an integer greater than or equal to 1.

[0024] Secondly, this application provides a method for fabricating a memory device, comprising: constructing a memory array on a first chip, the memory array including at least one memory block, the memory block including a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; constructing a logic control circuit on a second chip, the second chip having a top-view projection area of ​​a memory block, the logic control circuit including a global bit line decoder electrically connected to at least one memory block, the global bit line decoder block formed by the global bit line decoder being located within the top-view projection area; and stacking the second chip on top of the first chip along a third direction.

[0025] In some embodiments, the fabrication method further includes: configuring a local bit-line decoder in a logic control circuit, the local bit-line decoder including a first local bit-line sub-decoder; configuring the first local bit-line sub-decoder electrically connected to a bit line and a global bit-line decoder; and constructing a first local bit-line sub-decoder block formed by the first local bit-line sub-decoder located in a top-view projection region, and in a first direction, the projection of the first local bit-line sub-decoder block does not overlap with the projection of the global bit-line decoder block.

[0026] In some embodiments, the fabrication method further includes: configuring a first local bitline decoder including a first local bitline decoder unit and a second local bitline decoder unit; electrically connecting the first local bitline decoder unit to a portion of the bitline and a global bitline decoder, and electrically connecting the second local bitline decoder unit to another portion of the bitline and the global bitline decoder; and constructing a first local bitline decoder unit block formed by the first local bitline decoder unit and a second local bitline decoder unit block formed by the second local bitline decoder unit in a top-view projection area; wherein, in a first direction, the projections of the first local bitline decoder unit block and the second local bitline decoder unit block do not overlap; and in a second direction, the global bitline decoder block is located between the first local bitline decoder unit block and the second local bitline decoder unit block.

[0027] In some embodiments, the fabrication method further includes: configuring a word line decoding circuit in a logic control circuit, the word line decoding circuit including a first word line sub-decoder; electrically connecting the first word line sub-decoder to a word line; and constructing a first word line sub-decoder block formed by the first word line sub-decoder in a top-view projection area; wherein, in a second direction, the first word line sub-decoder block is located between a global bit line decoder block and a second local bit line sub-decoder unit block.

[0028] In some embodiments, the fabrication method further includes: configuring a first word line decoder including a first word line decoding unit and a second word line decoding unit; electrically connecting the first word line decoding unit to a portion of a word line, and electrically connecting the second word line decoding unit to another portion of a word line; and constructing a projection of the first word line decoding unit block formed by the first word line decoding unit and a projection of the second word line decoding unit block formed by the second word line decoding unit to at least partially overlap in a first direction; and the projections of the first word line decoding unit block and the second word line decoding unit block do not overlap in a second direction.

[0029] The storage device and its fabrication method provided in this application reduce the area of ​​the stacked first and second chips by constructing a global bit-line decoder block located in the top-view projection area of ​​the storage block in the second chip, thereby reducing the area occupied by the storage device and helping to achieve the minimum size of the storage device.

[0030] Based on the fact that the decoder is set entirely within the projection range and the stacked structure of the two chips, the decoder can be vertically connected to the memory array without the need for additional lateral traces. Therefore, no trace space is required between the two sub-modules, which can further reduce the area of ​​the first and second chips. Attached Figure Description

[0031] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0032] Figure 1 A schematic diagram showing the distribution of various parts of a storage device provided by a conventional technical solution.

[0033] Figure 2 A schematic diagram showing another distribution of the various parts of the storage device provided by a conventional technical solution.

[0034] Figure 3 This is a schematic diagram of the structural distribution of a storage device provided in an embodiment of this application.

[0035] Figure 4 for Figure 3 A schematic diagram of the structure of the induction amplifier circuit.

[0036] Figure 5 This is a schematic diagram of another structural distribution of the storage device provided in an embodiment of this application.

[0037] Figure 6 This is a schematic flowchart illustrating the fabrication method of the storage device provided in the embodiments of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0039] In the description of this disclosure, word line decoders are also described as X-DECs, and bit line decoders can be described as bit line selectors, bit line multiplexers, or Y-MUXs for locating a majority of memory cells in a memory array for further read and write operations on the memory cells.

[0040] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description of this disclosure. They do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this disclosure. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0042] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through a third feature other than themselves. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0043] See also Figures 3 to 6 ,like Figure 3 As shown, this embodiment provides a storage device including a first chip 100 and a second chip 200. The first chip 100 includes a storage array 10, which includes at least one storage block, such as a first storage block 11, a second storage block 12, or an Nth storage block 13. The storage block includes multiple word lines extending along a first direction DR1 and multiple bit lines extending along a second direction DR2. The second chip 200 is stacked above the first chip 100 along a third direction DR3. The second chip 200 has a top-view projection area of ​​a storage block. The second chip 200 includes a logic control circuit, which includes a global bit line decoder 20. The global bit line decoder 20 is electrically connected to at least one storage block, and the global bit line decoder block formed by the global bit line decoder 20 is located within the top-view projection area.

[0044] It is understood that the memory device provided in this embodiment, by constructing a global bit-line decoder block formed by the global bit-line decoder 20 located within the top-view projection area of ​​the memory block in the second chip 200, can reduce the area of ​​the first chip 100 and the second chip 200 after stacking, thereby reducing the occupied area of ​​the memory device and helping to achieve a minimized size of the memory device. Furthermore, this stacking structure helps to reduce the wiring distance between the logic control circuit and the memory cell.

[0045] The first chip 100 can be a wafer, and the second chip 200 can be another wafer.

[0046] It should be noted that each block in this application can be understood as the wafer space required to construct the corresponding structure. For example, the top-view projection area can be understood as the space occupied by the memory block, that is, the top-view projection area is formed by the memory block. As another example, the global bit-line decoder block can also be understood as the space required to construct the global bit-line decoder 20, that is, the global bit-line decoder block is formed by the global bit-line decoder 20.

[0047] Furthermore, the storage block in this embodiment can be an independent entity, and it can be any one of at least one storage block. For example, the storage block can be the first storage block 11, the second storage block 12, or the Nth storage block 13, where N can be any positive integer.

[0048] Therefore, in this embodiment, the global bit line decoder block formed by the global bit line decoder 20 can partially or completely overlap with the construction area of ​​any memory block, which can also reduce the area occupied by the first chip 100 and the second chip 200 after stacking, thereby reducing the space occupied by the memory device and helping to achieve the minimum size of the memory device.

[0049] In one embodiment, the length of the top-view projection region along the first direction DR1 is greater than or equal to the length of the global bit-line decoder block. This is understood to maximize the overlap between the top-view projection region and the global bit-line decoder block. The first direction DR1 can be the bit-line arrangement direction of the memory array 10.

[0050] In one embodiment, the width of the top-view projection region in the second direction DR2 is greater than the width of the global bit-line decoder block. It is understood that this further increases the overlap area between the top-view projection region and the global bit-line decoder block. The second direction DR2 can be the word line arrangement direction of the memory array 10.

[0051] In one embodiment, the logic control circuit further includes a local bit line decoder 30, which includes a first local bit line sub-decoder 30A. The first local bit line sub-decoder 30A is electrically connected to the memory block and the global bit line decoder 20. The first local bit line sub-decoder block formed by the first local bit line sub-decoder 30A is located in the top-view projection area. On the first direction DR1, the projection of the first local bit line sub-decoder block does not overlap with the projection of the global bit line decoder block.

[0052] It is understandable that by at least partially overlapping the top-view projection area with the first local bit line decoder block, the area occupied by the stacked first chip 100 and second chip 200 can be further reduced, thereby reducing the space occupied by the memory device and helping to achieve the minimum size of the memory device.

[0053] In this application, the first direction DR1 can also be the horizontal axis direction, the second direction DR2 can also be the vertical axis direction, and the third direction DR3 can also be the thickness direction of the storage device.

[0054] It should be noted that in this embodiment, each memory block is configured with a local bit line sub-decoder, and each memory block includes corresponding bit lines. The local bit line sub-decoder is connected to the bit lines of the corresponding memory block and can be used to simultaneously or time-divisionally control the corresponding bit lines to be in the on or off state.

[0055] For example, the first storage block 11 is configured with a first local bit line decoder 30A, the second storage block 12 is configured with a second local bit line decoder 30B, and the Nth storage block 13 is configured with an Nth local bit line decoder 30C.

[0056] In one embodiment, the first local bitline decoder 30A includes a first local bitline decoder unit 31 and a second local bitline decoder unit 32. The first local bitline decoder unit 31 is electrically connected to a portion of the bitline and the global bitline decoder 20; the second local bitline decoder unit 32 is electrically connected to another portion of the bitline and the global bitline decoder 20; in the first direction DR1, the projection of the first local bitline decoder unit block formed by the first local bitline decoder unit 31 and the projection of the second local bitline decoder unit block formed by the second local bitline decoder unit 32 do not overlap; and in the second direction DR2, the global bitline decoder block is located between the first local bitline decoder unit block and the second local bitline decoder unit block.

[0057] The first local bit-line sub-decoding unit block can be formed by any one of the first local bit-line sub-decoding unit 31, the third local bit-line sub-decoding unit 33, and the 2N-1th local bit-line sub-decoding unit 35. The second local bit-line sub-decoding unit block can be formed by any one of the second local bit-line sub-decoding unit 32, the fourth local bit-line sub-decoding unit 34, and the 2Nth local bit-line sub-decoding unit 36.

[0058] It should be noted that, in this embodiment, the first local bit-line decoder 30A can be divided into a first local bit-line decoder unit 31 and a second local bit-line decoder unit 32. This is beneficial for minimizing the size of each local bit-line decoder, making full use of the fragmented area of ​​the second chip 200, and thus minimizing the area of ​​the second chip 200. At the same time, this division is more conducive to the layout of the word-line decoders, allowing them to be placed within the projection area without affecting the wiring, thereby further saving area.

[0059] Similarly, the second local bit line decoder 30B configured in the second storage block 12 can be divided into a third local bit line decoder unit 33 and a fourth local bit line decoder unit 34, so that they can be placed in different positions respectively. The Nth local bit line decoder 30C configured in the Nth storage block 13 can also be divided into a 2N-1th local bit line decoder unit 35 and a 2Nth local bit line decoder unit 36, so that they can be placed in different positions respectively.

[0060] In one embodiment, the global bit-line decoder block may be adjacent to the first local bit-line sub-decoding unit block and far from the second local bit-line sub-decoding unit block.

[0061] In one embodiment, the top-view projection area or blocks can have a specific shape, such as a rectangle, or a square, circle, or ellipse, etc.

[0062] In some embodiments, in the first direction DR1, the length of the global bit line decoder block, the length of the first local bit line sub-decoding unit block, and the length of the second local bit line sub-decoding unit block are all less than or equal to the length of the top-view projection area; and in the second direction DR2, the sum of the width of the global bit line decoder block, the width of the first local bit line sub-decoding unit block, and the width of the second local bit line sub-decoding unit block is less than or equal to the width of the top-view projection area.

[0063] In one embodiment, the logic control circuit further includes a word line decoding circuit 40, which includes a first word line sub-decoder 40A. The first word line sub-decoder 40A is electrically connected to the word line. The first word line sub-decoder block formed by the first word line sub-decoder 40A is located in the top-view projection area and on the second direction DR2. The first word line sub-decoder block is located between the global bit line decoder block and the second local bit line sub-decoder unit block.

[0064] It is understandable that by at least partially overlapping the top-view projection area with the first word line decoder block formed by the first word line decoder 40A, the area occupied by the first chip 100 and the second chip 200 after stacking can be further reduced, thereby reducing the space occupied by the memory device and helping to achieve the minimum size of the memory device.

[0065] It should be noted that in this embodiment, each memory block is equipped with a word line decoder, and each memory block includes a corresponding word line. The word line decoder is electrically connected to the word line of the corresponding memory block.

[0066] For example, the first storage block 11 is equipped with a first word line decoder 40A, the second storage block 12 is equipped with a second word line decoder 40B, and the Nth storage block 13 is equipped with an Nth word line decoder 40C.

[0067] In one embodiment, the first word line decoder 40A includes a first word line decoding unit 41 and a second word line decoding unit 42. The first word line decoding unit 41 is electrically connected to a portion of the word lines, and the second word line decoding unit 42 is electrically connected to another portion of the word lines. In the first direction DR1, the projection of the first word line decoding unit block formed by the first word line decoding unit 41 and the projection of the second word line decoding unit block formed by the second word line decoding unit 42 at least partially overlap; and in the second direction DR2, the projections of the first word line decoding unit block and the second word line decoding unit block do not overlap.

[0068] It should be noted that in this embodiment, the first word line decoder 40A can be divided into a first word line decoding unit 41 and a second word line decoding unit 42, which is beneficial to minimizing each word line decoder and making full use of the fragmented area of ​​the second chip 200, thereby minimizing the area of ​​the second chip 200.

[0069] Similarly, the second word line decoder 40B configured in the second storage block 12 can be divided into a third word line decoding unit 43 and a fourth word line decoding unit 44, so that they can be placed in different positions respectively. The Nth word line decoder 40C configured in the Nth storage block 13 can also be divided into a 2N-1 word line decoding unit 45 and a 2N word line decoding unit 46, so that they can be placed in different positions respectively.

[0070] In one embodiment, the logic control circuit further includes a sensing amplifier circuit 50, which is electrically connected to the global bit line decoder 20. The sensing amplifier circuit block formed by the sensing amplifier circuit 50 is located within the top-view projection area. In the first direction DR1, the sensing amplifier circuit block is located between the first word line decoding unit block and the second word line decoding unit block, and in the second direction DR2, the sensing amplifier circuit block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

[0071] It is understandable that by at least partially overlapping the top-view projection area and the inductive amplifier circuit block formed by the inductive amplifier circuit 50, the area occupied by the first chip 100 and the second chip 200 after stacking can be further reduced, thereby reducing the space occupied by the memory device and helping to achieve the minimum size of the memory device.

[0072] like Figure 3 and Figure 4As shown, in one embodiment, the inductive amplifier circuit 50 includes a first group of inductive amplifiers 51 and a second group of inductive amplifiers 52. The first group of inductive amplifiers 51 is electrically connected to the global bit line decoder 20. The first group of inductive amplifiers 51 includes a plurality of inductive amplifiers arranged sequentially along the first direction DR1, such as inductive amplifiers 51A, 51B, 51C, 51D, etc. The second group of inductive amplifiers 52 is electrically connected to the global bit line decoder 20. The second group of inductive amplifiers 52 includes a plurality of inductive amplifiers arranged sequentially along the first direction DR1, such as inductive amplifiers 52A, 52B, 52C, 52D, etc. In the first direction DR1, the projection of the first group of inductive amplifier blocks formed by the first group of inductive amplifiers 51 and the projection of the second group of inductive amplifier blocks formed by the second group of inductive amplifiers 52 at least partially overlap; and in the second direction DR2, the projections of the first group of inductive amplifier blocks and the projections of the second group of inductive amplifier blocks do not overlap.

[0073] In one embodiment, in the first direction DR1, a first word line decoding unit block, a first group of inductive amplifier blocks, a second group of inductive amplifier blocks, and a second word line decoding unit block are arranged sequentially; in the first direction DR1, the distance from the first group of inductive amplifier blocks to the first word line decoding unit block is less than the distance from the first group of inductive amplifier blocks to the second word line decoding unit block, and the distance from the second group of inductive amplifier blocks to the first word line decoding unit block is greater than the distance from the second group of inductive amplifier blocks to the second word line decoding unit block.

[0074] In one embodiment, in the first direction DR1, the projection of the first group of induction amplifier blocks coincides with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block, and the projection of the second group of induction amplifier blocks coincides with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

[0075] In one embodiment, the logic control circuit further includes multiple first traces 70, which are electrically connected to the output of the global bit line decoder 20 and the input of multiple induction amplifiers. On the second direction DR2, the multiple first traces 70 are located between the global bit line decoder block and the induction amplifier circuit block; and the multiple first traces 70 are arranged sequentially along the first direction DR1.

[0076] It should be noted that multiple first traces 70 can be located on the same wafer layer as the logic control circuit, which can avoid the need for multiple first traces 70 to occupy an additional wafer layer, thereby increasing the required thickness of the second chip 200.

[0077] In one embodiment, the logic control circuit further includes multiple second traces 60, which are electrically connected to the input of the global bit-line decoder 20 and the output of the local bit-line decoder 30. The multiple second traces 60 are arranged sequentially along the first direction DR1, and are located in at least one top-view projection region. It is understood that one memory block can correspond to one top-view projection region.

[0078] It should be noted that multiple second traces 60 can be located on different wafer layers from the logic control circuit to achieve partial stacking of the two, which can save the area required for the second chip 200.

[0079] Among them, the second routing line 60 can be a global bit line.

[0080] In one embodiment, it should be noted that, Figure 3 The structural diagram shown is consistent with Figure 5 The difference between the structural diagrams shown is that: Figure 3 In the middle, the construction regions of the global bit-line decoder 20, the inductive amplifier circuit 50, and multiple first traces 70 all overlap with the construction region of the Nth memory block 13; while Figure 5 In this configuration, the construction regions of the global bit-line decoder 20, the inductive amplifier circuit 50, and the multiple first traces 70 all overlap or coincide with the construction region of the second memory block 12. Furthermore, these two different configurations also require corresponding changes to the positions of the connection nodes between the multiple second traces 60 and each local bit-line sub-decoder and the global bit-line decoder 20, as well as the trace paths of the multiple second traces 60.

[0081] In one embodiment, at least one memory block includes a first memory block 11 to an Nth memory block 13 arranged sequentially along the second direction DR2; when N is odd, the global bit line decoder block is located in the top-view projection area of ​​the (N+1) / 2th memory block in the second chip 200; when N is even, the global bit line decoder block is located in the top-view projection area of ​​the N / 2th or 1+N / 2th memory block in the second chip 200; wherein N is an integer greater than or equal to 1. It is understood that this configuration allows for the central position of the global bit line decoder block memory array 10.

[0082] In summary, the global bit-line decoder block can be located in any top-view projection area. When the global decoder block is located in the top-view projection area of ​​the intermediate memory block, the overall distance between the global decoder block and other local decoders can be reduced, thereby shortening the traces and reducing the delay.

[0083] In one embodiment, the first local bit line decoding unit 31 and the second local bit line decoding unit 32 each have a plurality of first transmission ends, and a first transmission end is electrically connected to a bit line through a first silicon via or a pair of first bonding pads.

[0084] In one embodiment, both the first word line decoding unit 41 and the second word line decoding unit 42 have multiple second transmission terminals, and each second transmission terminal is electrically connected to a word line through a second through-silicon via or a pair of second bonding pads.

[0085] In one embodiment, the first chip 100 includes a first bonding layer, the first bonding layer including at least one first bonding pad and / or a second bonding pad; the second chip 200 includes a second bonding layer, the second bonding layer including at least one first bonding pad and / or a second bonding pad; the first bonding pad located on the first bonding layer is bonded to the first bonding pad located on the second bonding layer, and / or the second bonding pad located on the first bonding layer is bonded to the second bonding pad located on the second bonding layer.

[0086] like Figure 6 As shown, in one embodiment, this embodiment provides a method for fabricating a storage device, the method comprising the following steps:

[0087] Step S10: Construct a memory array on the first chip. The memory array includes at least one memory block. The memory block includes multiple word lines extending along a first direction and multiple bit lines extending along a second direction.

[0088] Step S20: Construct a logic control circuit on a second chip. The second chip has a top-view projection area of ​​a memory block. The logic control circuit includes a global bit-line decoder electrically connected to at least one memory block. The global bit-line decoder block formed by the global bit-line decoder is located within the top-view projection area.

[0089] And step S30: stack the second chip on top of the first chip along the third direction.

[0090] It is understood that the method for fabricating the memory device provided in this embodiment reduces the area of ​​the stacked first and second chips by constructing a global bit-line decoder block located in the top-view projection area of ​​the memory block in the second chip, thereby reducing the area occupied by the memory device and helping to achieve the minimum size of the memory device.

[0091] In one embodiment, the fabrication method further includes: configuring a local bit-line decoder in a logic control circuit, the local bit-line decoder including a first local bit-line sub-decoder; configuring the first local bit-line sub-decoder electrically connected to a bit line and a global bit-line decoder; and constructing a first local bit-line sub-decoder block formed by the first local bit-line sub-decoder located in a top-view projection region, and in a first direction, the projection of the first local bit-line sub-decoder block and the projection of the global bit-line decoder block do not overlap.

[0092] It should be noted that, in the first direction, the projection of the first local bit-line decoder block and the projection of the global bit-line decoder block do not overlap. This means that, along the first direction, the first local bit-line decoder block can have the projection of the first local bit-line decoder block, and the global bit-line decoder block can have the projection of the global bit-line decoder block; furthermore, in the first direction, the projection of the first local bit-line decoder block and the projection of the global bit-line decoder block do not overlap on any plane perpendicular to the first direction.

[0093] In one embodiment, the fabrication method further includes: configuring a first local bitline decoder including a first local bitline decoder unit and a second local bitline decoder unit; electrically connecting the first local bitline decoder unit to a portion of the bitline and a global bitline decoder, and electrically connecting the second local bitline decoder unit to another portion of the bitline and the global bitline decoder; and constructing a first local bitline decoder unit block formed by the first local bitline decoder unit and a second local bitline decoder unit block formed by the second local bitline decoder unit in a top-view projection area; wherein, in a first direction, the projections of the first local bitline decoder unit block and the second local bitline decoder unit block do not overlap; and in a second direction, the global bitline decoder block is located between the first local bitline decoder unit block and the second local bitline decoder unit block.

[0094] In one embodiment, the fabrication method further includes: configuring a word line decoding circuit in a logic control circuit, the word line decoding circuit including a first word line sub-decoder; electrically connecting the first word line sub-decoder to a word line; and constructing a first word line sub-decoder block formed by the first word line sub-decoder in a top-view projection area; wherein, in a second direction, the first word line sub-decoder block is located between a global bit line decoder block and a second local bit line sub-decoder unit block.

[0095] In one embodiment, the fabrication method further includes: configuring a first word line decoder including a first word line decoding unit and a second word line decoding unit; electrically connecting the first word line decoding unit to a portion of a word line, and electrically connecting the second word line decoding unit to another portion of a word line; and constructing a projection of the first word line decoding unit block formed by the first word line decoding unit and a projection of the second word line decoding unit block formed by the second word line decoding unit to at least partially overlap in a first direction; and the projections of the first word line decoding unit block and the second word line decoding unit block do not overlap in a second direction.

[0096] It should be noted that the projections of the first word line decoding unit block and the second word line decoding unit block do not overlap in the second direction. This means that along the second direction, the first word line decoding unit block can have its own projection, and the second word line decoding unit block can have its own projection; furthermore, in the second direction, the projections of the first and second word line decoding unit blocks do not overlap on any plane perpendicular to the second direction.

[0097] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0098] The storage devices and their manufacturing methods provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A storage device, characterized in that, include: A first chip, the first chip including a memory array, the memory array including at least one memory block, the memory block including a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; The second chip is stacked on top of the first chip along a third direction. The second chip has a top-view projection area of ​​the memory block. The second chip includes a logic control circuit, which includes a global bit-line decoder, a local bit-line decoder, and a word-line decoder. The local bit-line decoder includes a first local bit-line sub-decoder, which includes a first local bit-line sub-decoder unit and a second local bit-line sub-decoder unit. The word line decoding circuit includes a first word line sub-decoder, which is electrically connected to the word line. The first word line sub-decoder block formed by the first word line sub-decoder is located within the top-view projection area, and in the second direction, the first word line sub-decoder block is located between the global bit line decoder block formed by the global bit line decoder and the second local bit line sub-decoder unit block formed by the second local bit line sub-decoder unit.

2. The storage device according to claim 1, characterized in that, In the first direction, the projection of the first local bit line sub-decoding unit block formed by the first local bit line sub-decoding unit does not overlap with the projection of the second local bit line sub-decoding unit block; and in the second direction, the global bit line decoder block is located between the first local bit line sub-decoding unit block and the second local bit line sub-decoding unit block.

3. The storage device according to claim 2, characterized in that, In the first direction, the length of the global bitline decoder block, the length of the first local bitline sub-decoding unit block, and the length of the second local bitline sub-decoding unit block are all less than or equal to the length of the top-view projection area; and in the second direction, the sum of the width of the global bitline decoder block, the width of the first local bitline sub-decoding unit block, and the width of the second local bitline sub-decoding unit block is less than or equal to the width of the top-view projection area.

4. The storage device according to claim 3, characterized in that, The first word line decoder includes: The first word line decoding unit is electrically connected to a portion of the word lines; The second word line decoding unit is electrically connected to another part of the word line; In the first direction, the projection of the first word line decoding unit block formed by the first word line decoding unit at least partially overlaps with the projection of the second word line decoding unit block formed by the second word line decoding unit; and in the second direction, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block do not overlap.

5. The storage device according to claim 4, characterized in that, The logic control circuit also includes: An inductive amplifier circuit is electrically connected to the global bit line decoder, and the inductive amplifier circuit block formed by the inductive amplifier circuit is located within the top-view projection area; in the first direction, the inductive amplifier circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in the second direction, the inductive amplifier circuit block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

6. The storage device according to claim 5, characterized in that, The inductive amplifier circuit includes: A first group of inductive amplifiers is electrically connected to the global bit-line decoder, and the first group of inductive amplifiers includes a plurality of inductive amplifiers arranged sequentially along the first direction; and The second group of inductive amplifiers is electrically connected to the global bit line decoder, and the second group of inductive amplifiers includes a plurality of inductive amplifiers arranged sequentially along the first direction; In the first direction, the projection of the first group of inductive amplifier blocks formed by the first group of inductive amplifiers and the projection of the second group of inductive amplifier blocks formed by the second group of inductive amplifiers at least partially overlap; and in the second direction, the projections of the first group of inductive amplifier blocks and the projections of the second group of inductive amplifier blocks do not overlap.

7. The storage device according to claim 6, characterized in that, In the first direction, the first word line decoding unit block, the first group of inductive amplifier blocks, the second group of inductive amplifier blocks, and the second word line decoding unit block are arranged sequentially; in the first direction, the distance from the first group of inductive amplifier blocks to the first word line decoding unit block is less than the distance from the first group of inductive amplifier blocks to the second word line decoding unit block, and the distance from the second group of inductive amplifier blocks to the first word line decoding unit block is greater than the distance from the second group of inductive amplifier blocks to the second word line decoding unit block.

8. The storage device according to claim 6, characterized in that, In the first direction, the projection of the first group of inductive amplifier blocks coincides with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block, and the projection of the second group of inductive amplifier blocks coincides with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

9. The storage device according to claim 6, characterized in that, The logic control circuit also includes: Multiple first traces are electrically connected to the output of the global bit line decoder and the input of the multiple inductive amplifiers; in the second direction, the multiple first traces are located between the global bit line decoder block and the inductive amplifier circuit block; and the multiple first traces are arranged sequentially along the first direction.

10. The storage device according to claim 9, characterized in that, The logic control circuit also includes: Multiple second traces are electrically connected to the input of the global bit line decoder and the output of the local bit line decoder; the multiple second traces are arranged sequentially in the first direction; and the multiple second traces are located in at least one of the top-view projection regions.

11. The storage device according to claim 4, characterized in that, The first local bit line decoding unit and the second local bit line decoding unit each have multiple first transmission terminals. Each first transmission terminal is electrically connected to a bit line through a first through-silicon via or a pair of first bonding pads. Both the first word line decoding unit and the second word line decoding unit have multiple second transmission terminals. Each second transmission terminal is electrically connected to a word line through a second through-silicon via or a pair of second bonding pads.

12. The storage device according to any one of claims 1 to 11, characterized in that, The at least one storage block includes a first storage block to an Nth storage block arranged sequentially along the second direction; When N is odd, the global bit line decoder block is located in the top-view projection area of ​​the (N+1) / 2th memory block in the second chip; When N is even, the global bit line decoder block is located in the N / 2th memory block or the 1+N / 2th memory block is located in the top-view projection area of ​​the second chip; Where N is an integer greater than or equal to 1.

13. A method for manufacturing a storage device, characterized in that, include: A memory array is constructed on a first chip, the memory array including at least one memory block, the memory block including multiple word lines extending along a first direction and multiple bit lines extending along a second direction; A logic control circuit is constructed on a second chip, the second chip having a top-view projection area of ​​the memory block. The logic control circuit includes a global bit-line decoder, a local bit-line decoder, and a word-line decoder circuit. The local bit-line decoder includes a first local bit-line sub-decoder, the first local bit-line sub-decoder including a first local bit-line sub-decoder unit and a second local bit-line sub-decoder unit. The word-line decoder circuit includes a first word-line sub-decoder. as well as The second chip is stacked on top of the first chip along a third direction; Wherein, the first word line decoder block formed by the first word line decoder is located within the top-view projection area; in the second direction, the first word line decoder block is located between the global bit line decoder block formed by the global bit line decoder and the second local bit line decoder unit block formed by the second local bit line decoder unit.

14. The preparation method according to claim 13, characterized in that, The preparation method further includes: The first local bit line decoder is configured to be electrically connected to the bit line and the global bit line decoder; and The first local bit line decoder block formed by constructing the first local bit line decoder is located within the top-view projection area, and in the first direction, the projection of the first local bit line decoder block does not overlap with the projection of the global bit line decoder block.

15. The preparation method according to claim 14, characterized in that, The preparation method further includes: Electrically connected to the first local bit line sub-decoding unit and a portion of the bit lines, the global bit line decoder; and electrically connected to the second local bit line sub-decoding unit and the other portion of the bit lines, the global bit line decoder; and Construct the first local bit line sub-decoding unit block formed by the first local bit line sub-decoding unit and the second local bit line sub-decoding unit block formed by the second local bit line sub-decoding unit within the top-view projection area; In the first direction, the projection of the first local bit line sub-decoding unit block and the projection of the second local bit line sub-decoding unit block do not overlap; and in the second direction, the global bit line decoder block is located between the first local bit line sub-decoding unit block and the second local bit line sub-decoding unit block.

16. The preparation method according to claim 15, characterized in that, The preparation method further includes: The first word line decoder is configured to include a first word line decoding unit and a second word line decoding unit. Electrically connect the first word line decoding unit to a portion of the word line, and electrically connect the second word line decoding unit to the other portion of the word line; and The projection of the first word line decoding unit block formed by the first word line decoding unit and the projection of the second word line decoding unit block formed by the second word line decoding unit overlap at least partially in the first direction; and the projection of the first word line decoding unit block and the projection of the second word line decoding unit block do not overlap in the second direction.

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