Abnormity processing method and device for semiconductor test data, equipment and medium

Abstract

The invention discloses an exception handling method, device and equipment for semiconductor test data and a medium. The method comprises the following steps: acquiring to-be-processed semiconductor test data; according to test stages corresponding to the semiconductor test data, an adaptive target detection algorithm is selected from a plurality of anomaly detection algorithms, the semiconductor test data is detected to obtain an anomaly detection result, and data characteristics of different test stages are different; and under the condition that the anomaly detection result indicates that abnormal data exists in the semiconductor test data, selecting an adaptive target repair algorithm from a plurality of anomaly repair algorithms according to an anomaly type corresponding to the abnormal data and a repair verification degree, and repairing the abnormal data to obtain an anomaly repair result. The target detection algorithm selected through the scheme is more adaptive to the data characteristics of the semiconductor test data, and the target repair algorithm is more adaptive to the data characteristics of the abnormal data, so that the accuracy of performing anomaly detection and repair on the semiconductor test data is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of semiconductor test analysis, and in particular to a method, device, equipment and medium for handling semiconductor test data exceptions. Background Art

[0002] Semiconductor testing is a key link in ensuring the quality of integrated circuits and semiconductor devices, covering the entire process from design verification, wafer detection to final product testing. During the semiconductor testing process, a large amount of semiconductor test data will be generated. By performing abnormal processing on semiconductor test data, it is helpful to reveal potential problems of semiconductor devices and repair abnormal parts, further ensuring the quality of semiconductor devices.

[0003] In the prior art, semiconductor test data obtained from the entire process of semiconductor testing may be processed in the same manner, such as using any method based on statistical principles or machine learning technology. The processing results obtained by processing semiconductor test data in the above manner may be inaccurate. Summary of the invention

[0004] The present invention provides a method, device, equipment and medium for abnormal processing of semiconductor test data, which can improve the accuracy of abnormal processing of semiconductor test data.

[0005] In a first aspect, an embodiment of the present invention provides a method for handling semiconductor test data exceptions, comprising:

[0006] Acquiring semiconductor test data to be processed;

[0007] According to the test phase corresponding to the semiconductor test data, an adapted target detection algorithm is selected from a plurality of anomaly detection algorithms, and the semiconductor test data is detected to obtain an anomaly detection result, wherein data characteristics of different test phases are different;

[0008] When the abnormality detection result indicates that abnormal data exists in the semiconductor test data, an adapted target repair algorithm is selected from multiple abnormality repair algorithms according to the abnormality type corresponding to the abnormal data and the degree of verification of the repair, and the abnormal data is repaired to obtain an abnormality repair result.

[0009] In a second aspect, an embodiment of the present invention provides a semiconductor test data exception processing device, comprising:

[0010] An acquisition module, used for acquiring semiconductor test data to be processed;

[0011] A detection module, configured to select an adapted target detection algorithm from a plurality of anomaly detection algorithms according to a test phase corresponding to the semiconductor test data, and detect the semiconductor test data to obtain an anomaly detection result, wherein data characteristics of different test phases are different;

[0012] A repair module is used to select an adapted target repair algorithm from a plurality of abnormal repair algorithms according to the abnormal type corresponding to the abnormal data and the degree of verification of the repair when the abnormal detection result indicates that abnormal data exists in the semiconductor test data, and repair the abnormal data to obtain an abnormal repair result.

[0013] In a third aspect, an embodiment of the present invention provides an electronic device, including:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the method according to the first aspect.

[0017] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0018] The technical solution of the embodiment of the present invention can select an adapted target detection algorithm from multiple anomaly detection algorithms to perform anomaly detection according to the test stage corresponding to the semiconductor test data, and select an adapted target repair algorithm from multiple anomaly repair algorithms to perform anomaly repair according to the anomaly type corresponding to the anomaly data and the degree of verification of the repair. The target detection algorithm selected by this solution is more adapted to the data characteristics of the semiconductor test data, and the target repair algorithm selected by this solution is more adapted to the data characteristics of the abnormal data in the semiconductor test data, thereby improving the accuracy of anomaly detection and repair of semiconductor test data.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flowchart of a method for handling semiconductor test data exceptions provided in accordance with a first embodiment of the present invention;

[0022] Figure 2 is a flow chart of a method for handling semiconductor test data exceptions provided in accordance with a second embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of the structure of a semiconductor test data exception processing device provided according to a fourth embodiment of the present invention;

[0024] Figure 4 It is a schematic diagram of the structure of an electronic device implementing an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] Embodiment 1

[0028] Figure 1This is a flowchart of a method for handling semiconductor test data exceptions according to Embodiment 1 of the present invention. This embodiment is applicable to the case of detecting and repairing semiconductor test data exceptions. The method can be performed by a semiconductor test data exception handling device, which can be implemented in the form of software and / or hardware and integrated in an electronic device. Further, the electronic device includes but is not limited to: computers, laptops, servers, etc.

[0029] like Figure 1 As shown, the method includes:

[0030] S110, obtaining semiconductor test data to be processed.

[0031] Semiconductor test data may be data generated during semiconductor testing, including various data collected during the design verification, production process, and finished product testing of semiconductor devices. Semiconductor test data to be processed may be semiconductor test data to be subjected to anomaly detection and anomaly repair.

[0032] In this step, semiconductor test data can be acquired in real time from semiconductor test equipment, and semiconductor test data can also be acquired in real time from sensors involved in semiconductor testing. After acquiring the semiconductor test data, the acquired data can be preprocessed, including data cleaning and data standardization. Data cleaning is used to eliminate invalid or erroneous data, and data standardization is used to ensure that the data format is unified for subsequent analysis. The preprocessed semiconductor test data is used as the semiconductor test data to be processed.

[0033] The semiconductor testing equipment may be equipment for implementing semiconductor testing, such as electrical performance testing of semiconductors. The sensor may be a sensor for real-time detection and collection of parameters involved in the semiconductor production process. The specific implementation of the semiconductor testing equipment and the sensor is not limited here.

[0034] S120. Select an adapted target detection algorithm from a plurality of anomaly detection algorithms according to the test phase corresponding to the semiconductor test data, and detect the semiconductor test data to obtain an anomaly detection result, wherein data characteristics in different test phases are different.

[0035] In the embodiment of the present invention, there may be multiple different test phases for semiconductor testing, and the data characteristics of the semiconductor test data obtained in each test phase are different, and the semiconductor test data may include at least the following three test phases:

[0036] Wafer Acceptance Test (WAT):

[0037] In the WAT test phase, the focus can be on detecting anomalies between test points in the wafer, such as deviations in electrical parameters, connections, and other issues. The data characteristics of the semiconductor test data obtained can be high-dimensional, low-noise data, and the electrical parameters present a multi-dimensional normal distribution. Among them, electrical parameters can be a series of specific indicators used to quantify the characteristics of semiconductor devices, such as voltage, current, etc., which are not limited here.

[0038] Wafer test (Chip Probe, CP):

[0039] In the CP test phase, each chip on the wafer can be probed to perform functional testing and obtain electrical parameters of the chip. The data characteristics of the obtained semiconductor test data can be complex electrical parameters in multi-dimensional space, such as power consumption, leakage current, etc. Among them, the functional test can be a test that simulates the working environment of the chip to test the functional logic of the chip and confirm whether the basic function of the chip is abnormal.

[0040] Chip testing, also known as final test (FT), is the testing of finished chips:

[0041] In the FT test phase, the functional integrity and durability of the packaged finished chips can be tested, which includes a number of complex tests, such as functional testing, environmental testing, and performance verification. Environmental testing is to evaluate the performance and reliability of finished chips under various extreme or typical environmental conditions. Performance verification is to verify whether the electrical characteristic data of the final finished chip is abnormal. The data characteristics of the semiconductor test data obtained in the FT test phase can be that if abnormal data appears in the semiconductor test data, the abnormal data may appear in the form of clusters, such as a batch of finished chips is abnormal as a whole.

[0042] The anomaly detection algorithm may be an algorithm for anomaly detection of semiconductor test data, which is not limited here, as long as it can realize anomaly detection of semiconductor test data. For example, the anomaly detection algorithm may include but is not limited to: an algorithm based on a multidimensional Gaussian model, an isolation forest algorithm, and a density-based clustering algorithm.

[0043] Among them, the multidimensional Gaussian model can be used to detect electrical defects in semiconductor devices. This method is based on the assumption that the data follows a multidimensional normal distribution and can effectively identify outliers that deviate from the normal range. The isolation forest algorithm can be used to detect anomalies in data sets, especially when processing test data containing complex electrical parameters. The density-based clustering algorithm can effectively detect abnormal clusters formed in data sets, and is particularly suitable for processing data sets with complex parameters.

[0044] In this step, multiple anomaly detection algorithms can be pre-determined, and based on the data characteristics of different test phases of the semiconductor test data and combined with the characteristics of each anomaly detection algorithm, an adaptive anomaly detection algorithm can be pre-assigned to the semiconductor test data of each test phase.

[0045] In practical applications, the data characteristics of the semiconductor test data can be determined based on the test phase of the semiconductor test data, and an anomaly detection algorithm adapted to the data characteristics is further selected from multiple anomaly detection algorithms as a target detection algorithm, and the anomaly detection of the semiconductor test data is implemented by the target detection algorithm to obtain an anomaly detection result. Among them, the target detection algorithm can be an anomaly detection algorithm adapted to the semiconductor test data of the embodiment of the present invention. The anomaly detection result can be the result of anomaly detection of the semiconductor test data, such as indicating whether there is abnormal data in the semiconductor test data, and further indicating what the abnormal data is, which is not limited here.

[0046] S130. When the abnormality detection result indicates that abnormal data exists in the semiconductor test data, an adapted target repair algorithm is selected from a plurality of abnormality repair algorithms according to the abnormality type corresponding to the abnormal data and the degree of verification of the repair, and the abnormal data is repaired to obtain an abnormality repair result.

[0047] When the abnormal detection result indicates that there is abnormal data in the semiconductor test data, the data repair mechanism can be automatically triggered to repair the abnormal data to ensure the reliability of the data and the accuracy of the test results.

[0048] The abnormality type corresponding to the abnormal data may be a type of data indicating an abnormality in the semiconductor test data. The abnormality type may be related to the test phase corresponding to the semiconductor test data and the abnormality that may occur in each test phase, which is not limited here.

[0049] In the WAT test phase, possible anomalies may include parameter value anomalies, such as a parameter value in this phase deviating from the standard parameter value or parameter range, such as abnormal thickness at a certain location on the wafer. In the CP test phase, possible anomalies may include functional test anomalies, such as data with large deviations in functional tests, and electrical parameter anomalies, such as locally abnormal electrical parameters. In the FT test phase, possible anomalies may include functional test anomalies, such as abnormal values ​​in functional tests that deviate from the normal range but are repairable, and environmental test anomalies, i.e. abnormal conditions in environmental tests.

[0050] The abnormality repair algorithm can be an algorithm for performing abnormality repair on abnormal data in semiconductor test data. It is not limited here, as long as it can achieve abnormality repair. For example, the abnormality repair algorithm can include but is not limited to: interpolation method, algorithm based on regression model implementation, and statistical correction algorithm based on historical data. The degree of verification of the repair can be understood as an evaluation method that reflects the effect of abnormality repair achieved by a certain abnormality repair algorithm to determine whether to select the repair result of the abnormality repair algorithm as the final repair result.

[0051] Among them, interpolation can be understood as a way to estimate the value of unknown data points through the value of known data points. The degree of verification of the repair can be measured by the rationality of the selection of data involved in the interpolation and the rationality of the data after interpolation. The regression model can predict and repair possible outliers. The degree of verification of the repair can be measured by the fit of the regression model, prediction accuracy, prediction error, prediction stability, generalization ability, etc. The statistical correction algorithm based on historical data can correct the anomalies of the current data through the statistics of historical data. The degree of verification of the repair can be measured by historical data distribution verification and statistical significance test.

[0052] In this step, one or more abnormal repair algorithms can be preliminarily assigned to each abnormal type based on the abnormal type corresponding to the abnormal data that may appear, and the verification method of each abnormal repair algorithm can be preliminarily set. In practical applications, one or more abnormal repair algorithms can be preliminarily selected based on the abnormal type corresponding to the abnormal data, and then, based on the degree of verification of the repair by the selected abnormal repair algorithm, an abnormal repair algorithm can be finally selected as the target repair algorithm adapted for the abnormal data, and the result of the target repair algorithm repairing the abnormal data can be used as the abnormal repair result of the abnormal data. Among them, the target repair algorithm can be an abnormal repair algorithm adapted to the abnormal data of the embodiment of the present invention. The abnormal repair result can be the result of abnormal repair of the abnormal data, which is not limited here.

[0053] The technical solution of the embodiment of the present invention can select an adapted target detection algorithm from multiple anomaly detection algorithms to perform anomaly detection according to the test stage corresponding to the semiconductor test data, and select an adapted target repair algorithm from multiple anomaly repair algorithms to perform anomaly repair according to the anomaly type corresponding to the anomaly data and the degree of verification of the repair. The target detection algorithm selected by this solution is more adapted to the data characteristics of the semiconductor test data, and the target repair algorithm selected by this solution is more adapted to the data characteristics of the abnormal data in the semiconductor test data, thereby improving the accuracy of anomaly detection and repair of semiconductor test data.

[0054] Embodiment 2

[0055] Figure 2It is a flowchart of a semiconductor test data exception processing method provided according to the second embodiment of the present invention. This embodiment is based on the above-mentioned embodiment one, and further refines the selection of an adapted target detection algorithm from multiple exception detection algorithms according to the test phase corresponding to the semiconductor test data; and further refines the selection of an adapted target repair algorithm from multiple exception repair algorithms according to the exception type corresponding to the exception data and the degree of verification of the repair.

[0056] like Figure 2 As shown, the method includes:

[0057] S110, obtaining semiconductor test data to be processed.

[0058] S121. When the test phase corresponding to the semiconductor test data is wafer acceptance test, determine that the target detection algorithm is an algorithm based on a multidimensional Gaussian model; when the test phase is wafer test, determine that the target detection algorithm is an isolation forest algorithm; when the test phase is chip test, determine that the target detection algorithm is a density-based clustering algorithm.

[0059] In the WAT test phase, the algorithm based on the multidimensional Gaussian model can be used as a target detection algorithm to analyze the correlation between the parameters of the semiconductor test data in this phase and identify electrical defect points.

[0060] In the CP testing stage, the isolation forest algorithm can be used as a target detection algorithm. The isolation forest algorithm can detect anomalies based on the differentiation of data sets in semiconductor test data and can handle complex electrical parameters.

[0061] In the FT test phase, the density-based clustering algorithm can be used as a target detection algorithm. The density-based clustering algorithm can effectively detect abnormal clusters formed in the data set in the semiconductor test data. It is suitable for processing complex environmental test data and identifying abnormal performance under certain extreme conditions.

[0062] S122: Detect the semiconductor test data based on the determined target detection algorithm to obtain an abnormality detection result.

[0063] S131. Determine that the abnormality detection result indicates that abnormal data exists in the semiconductor test data; execute S132; or execute S133; or execute S134.

[0064] S132. When the abnormal type corresponding to the abnormal data is an abnormal parameter value in a wafer acceptance test, if the verification level is a first verification level, the target repair algorithm is determined to be an interpolation method; if the verification level is a second verification level, the target repair algorithm is determined to be an algorithm implemented based on a first regression model.

[0065] Among them, the first verification degree includes that the neighboring data points of the abnormal parameter value are normal and the number of the neighboring data points exceeds a first threshold, and the repair value corresponding to the abnormal parameter value is within a first range; the second verification degree includes that the fit of the first regression model exceeds a second threshold and the prediction accuracy exceeds a third threshold.

[0066] For the anomaly repair of abnormal data in the WAT test phase, such as the case of abnormal parameter values ​​in the WAT test phase, two methods may be used, namely, interpolation method and algorithm based on the first regression model implementation.

[0067] By repairing the abnormal data through interpolation, the abnormal data can be repaired to the average value of the adjacent normal parameters. If the neighboring data points involved in the interpolation in the interpolation method are normal and the number of neighboring data points exceeds the first threshold, and when the repair value obtained by repairing the abnormal parameter value through the interpolation method is compared with the historical data, the repair value is within the first range, then the first verification degree is met, and the interpolation method is determined as the target repair algorithm. Among them, the neighboring data points can be data points adjacent to the abnormal parameter value. There is no limit on the first threshold, and it is sufficient to ensure that the number of neighboring data points meets the interpolation requirements. There is no limit on the first range, and it is sufficient to ensure the rationality of the repair value.

[0068] By repairing abnormal data with an algorithm based on the first regression model, abnormal parameter values ​​can be predicted and repaired based on test data of similar wafers. If the fit of the first regression model exceeds the second threshold, and the prediction accuracy of the first regression model evaluated using the cross-validation method exceeds the third threshold, the second verification degree is met, and the algorithm based on the first regression model is determined as the target repair algorithm. The second threshold and the third threshold are not limited.

[0069] S133. When the abnormality type corresponding to the abnormal data is a functional test abnormality or an electrical parameter abnormality in wafer testing, if the verification level is the third verification level, the target repair algorithm is determined to be an algorithm implemented based on the second regression model; if the verification level is the fourth verification level, the target repair algorithm is determined to be an interpolation repair implemented based on a classification algorithm.

[0070] Among them, the third verification level includes that the stability verification of the second regression model is passed and the prediction error is within a second range; the fourth verification level includes that the similarity between the data involved in the interpolation repair and the abnormal data is higher than a fourth threshold and the accuracy of the repair is higher than a fifth threshold.

[0071] For the abnormal repair of abnormal data in the CP test phase, such as the repair of functional test abnormalities or electrical parameter abnormalities, two methods may be used, namely, an algorithm based on the second regression model and an interpolation repair based on the classification algorithm.

[0072] By repairing abnormal data through an algorithm based on the second regression model, it is possible to model multi-dimensional electrical parameters, predict chip performance under normal conditions, repair abnormal points, and replace abnormal values ​​with the predicted values ​​of the second regression model. If the performance of the second regression model on different data sets is stable, that is, the stability verification of the second regression model is passed, and the prediction error of the second regression model is verified to be within the second range through residual analysis, then the third verification level is met, and the algorithm based on the second regression model is determined as the target repair algorithm. Among them, the second range is not limited, and it is sufficient to ensure that the prediction error is within a reasonable range.

[0073] The abnormal data is repaired by interpolation repair based on the classification algorithm, which can be to use the K-Nearest Neighbors (KNN) algorithm to find K data involved in the interpolation repair, which can be the data of similar chips, and interpolation repair is performed based on the data of similar chips. If the similarity between the K data involved in the interpolation repair and the abnormal data is higher than the fourth threshold, and the accuracy of the repair evaluated by the cross-validation method is higher than the fifth threshold, the fourth verification degree is met, and the interpolation repair based on the classification algorithm is determined as the target repair algorithm. Among them, the KNN algorithm can be a kind of classification algorithm. There is no limitation on the fourth threshold and the fifth threshold.

[0074] S134. When the abnormality type corresponding to the abnormal data is a functional test abnormality or an environmental test abnormality in chip testing, if the verification level is the fifth verification level, the target repair algorithm is determined to be a statistical correction algorithm based on historical data; if the verification level is the sixth verification level, the target repair algorithm is determined to be an algorithm implemented based on the third regression model.

[0075] Among them, the fifth verification level includes that the distribution of the historical data is consistent with the distribution of the current data and the rationality of the corresponding repair value is verified; the sixth verification level includes that the generalization ability of the third regression model is verified and the prediction error is within the third range.

[0076] There are two possible ways to repair abnormal data in the FT test phase, such as the repair of functional test anomalies or environmental test anomalies in chip testing, namely, a statistical correction algorithm based on historical data or an algorithm based on the third regression model.

[0077] By repairing abnormal data with a statistical correction algorithm based on historical data, the abnormal values ​​in the current data can be judged and corrected based on the patterns and rules contained in the historical data. If the distribution of the historical data is consistent with the distribution of the current data, and the rationality verification of the corresponding repair value is determined by the statistical significance test, the fifth verification level is met, and the statistical correction algorithm based on historical data is determined as the target repair algorithm.

[0078] By repairing abnormal data through an algorithm based on the third regression model, possible outliers can be predicted and repaired by training historical data. For example, if some current or power consumption data is abnormal in the humidity test, the model can correct these data based on environmental conditions. If it is determined that the third regression model has strong generalization ability on different data sets, the generalization ability of the third regression model is verified, and the prediction error of the third regression model is verified to be within the third range through prediction error analysis, then the sixth verification level is met, and the algorithm based on the third regression model is determined as the target repair algorithm. Among them, the third range is not limited, and it is sufficient to ensure that the prediction error is within a reasonable range.

[0079] S135. Repair the abnormal data based on the determined target repair algorithm to obtain an abnormal repair result.

[0080] It should be noted that the anomaly detection algorithm involved in the embodiments of the present invention can improve the detection accuracy and efficiency of the algorithm and reduce false positives and negatives through adaptive learning and adjustment; the anomaly repair algorithm involved in the embodiments of the present invention can continuously optimize the repair strategy and improve the overall performance of the system through feedback learning of the repair results.

[0081] The technical solution of the embodiment of the present invention adopts different target detection algorithms to perform anomaly detection on semiconductor test data in different test stages, which can adapt to different test scenarios and data characteristics and improve the accuracy of anomaly detection; automatically runs the data repair mechanism when abnormal data is detected, and determines the target repair algorithm according to the type of abnormal data and the degree of verification of the repair, which can improve the efficiency and accuracy of data repair and ensure the integrity and availability of the data.

[0082] In one embodiment, the method further comprises:

[0083] When the abnormality detection result indicates that the semiconductor test data has no abnormality and the test stage is a wafer test or a chip test, detecting whether the test process identifier corresponding to the semiconductor test data is abnormal by a test process detection algorithm, and obtaining an identifier abnormality detection result;

[0084] The test process identifier at least includes: an off-chip retest identifier, an interrupt identifier, a whole batch retest identifier, and a batch split identifier.

[0085] For anomaly detection in the CP test phase or the FT test phase, if the anomaly detection result indicates that there is no anomaly in the semiconductor test data, it is necessary to further perform anomaly detection on the test process identifier based on the semiconductor test data. Specifically, it is possible to detect whether the value of the field included in the test process identifier is missing or abnormal.

[0086] The test process identifier can be an identifier indicating the process of semiconductor testing, which is used to track and manage the test process. The test process identifier can be composed of at least the following four fields: an off-chip retest identifier (also known as offlineRetest), which is used to indicate whether the test process is in an off-chip retest, that is, the chip is temporarily taken out of the assembly line for additional offline retesting; an interrupt identifier (also known as interrupt), which is used to indicate whether the test process is in an interrupt state, that is, an unexpected stop or pause; a batch retest identifier (also known as dupRetest), which is used to indicate whether the test process is in a batch retest, that is, a second test of a batch of chips; a batch split identifier (also known as batchNum), which is used to indicate whether the test process is in a batch split test, that is, a larger batch is divided into several smaller sub-batches for independent testing.

[0087] Through the test process detection algorithm, it is possible to detect whether the value of the field included in the test process identifier corresponding to the semiconductor test data is missing or abnormal, and determine the identifier abnormality detection result. Among them, the test process detection algorithm can be any algorithm that can realize the test process detection, which is not limited here. The identifier abnormality detection result can be the result of abnormality detection of the test process identifier.

[0088] In one embodiment, the method further comprises:

[0089] When the identification anomaly detection result indicates that the test process identification is abnormal, the test process identification is repaired based on the test start time, test end time, all tested chips, test failed chips, and test passed chips corresponding to the test files of the same batch as the semiconductor test data.

[0090] When the identification anomaly detection result indicates that the test process identification is abnormal, extract the relevant field values ​​of the test files of the same batch as the semiconductor test data, such as but not limited to: the field corresponding to the test start time, the field corresponding to the test end time, the test ECID field, the chip test pass mark field, and the known values ​​of the offlineRetest, interrupt, dupRetest, and batchNum fields. Through the relevant field values ​​extracted above, the test start time, test end time, full test chips, test failed chips, and test passed chips corresponding to each test file can be determined. Among them, ECID stands for Electronic Chip Identification, which can be understood as an electronic label unique to semiconductor devices.

[0091] According to the correlation between the test start time, test end time, all tested chips, chips that failed the test, and chips that passed the test corresponding to each test file, the initial test, retest, interruption, batch split test, and whole batch retest are inferred and restored, and the values ​​of the abnormal fields included in the test process identifier corresponding to the semiconductor test data are repaired.

[0092] After the test process identifier is repaired, logical consistency verification can be performed to ensure that the inferred test process is logically consistent and conforms to the actual test process; data integrity verification can also be performed to ensure that the field values ​​included in the repaired test process identifier are complete, without missing or abnormalities.

[0093] Exemplarily, the above-mentioned inference steps may include the following:

[0094] 1. Sort all test files in the same batch as the semiconductor test data by the test start time.

[0095] 2. The first test file after sorting is defined as the initial test: offlineRetest=0, interrupt=0, dupRetest=0, batchNum=0.

[0096] 3. If the test start time of the sorted test file 2 is less than the test end time of the test file 1, it is defined as the batch splitting of the test file 1: offlineRetest = 0, interrupt = 0, dupRetest = 0, batchNum = 1. Otherwise, proceed to step 4.

[0097] 4. If the test start time of the sorted test file 2 is greater than the test end time of the test file 1, determine whether the test chips of test file 2 and the test chips of test file 1 have an intersection. If there is no intersection, define test file 2 as a split batch of test file 1: offlineRetest = 0, interrupt = 0, dupRetest = 0, batchNum = 1. Otherwise, go to step 5 for judgment.

[0098] 5. If the test chip of test file 2 is consistent with the test chip of test file 1, then positioning test file 2 is the whole batch retest of test file 1: offlineRetest = 0, interrupt = 0, dupRetest = 1, batchNum = 0. Otherwise, go to step 6 for judgment.

[0099] 6. If the test chip of test file 2 is the chip that failed the test in test file 1, then define test file 2 as the retest of test file 1: offlineRetest = 1, interrupt = 0, dupRetest = 0, batchNum = 0. Otherwise, go to step 7 for judgment.

[0100] 7. If the test chip of test file 2 intersects with the test chip of test file 1, and if the test chip of test file 2 is not the chip that failed the test in test file 1, then define test file 2 as an interrupt of test file 1: offlineRetest=0, interrupt=1, dupRetest=0, batchNum=0.

[0101] By adopting a method similar to steps 1-7 above, continuous speculation can be performed based on multiple test files until the value of the abnormal field included in the test flow identifier corresponding to the semiconductor test data is repaired.

[0102] Embodiment 3

[0103] The embodiments of the present invention are illustrative descriptions of the above embodiments.

[0104] In an embodiment of the present invention, the anomaly detection and repair of semiconductor test data can be implemented in a semiconductor production factory. In the factory, hardware facilities are equipped, including but not limited to: semiconductor test equipment for implementing electrical performance testing of semiconductors; sensors for real-time detection and collection of parameters involved in the semiconductor production process; electronic equipment for executing a semiconductor test data anomaly processing method provided by the present invention. In the factory, a software environment is equipped, including but not limited to: a data acquisition system for collecting data from sensors or semiconductor test equipment and transmitting it to electronic equipment; data analysis software for executing anomaly detection algorithms and anomaly repair algorithms; a user interface is an interface provided to operators for monitoring and operation.

[0105] In an embodiment of the present invention, the abnormality detection and repair of semiconductor test data can be realized by specifically including the following steps:

[0106] Step 1: Data Collection

[0107] In practical applications, semiconductor test data can be acquired in real time from semiconductor test equipment, and semiconductor test data can also be acquired in real time from sensors involved in semiconductor testing.

[0108] Step 2: Data preprocessing

[0109] After the semiconductor test data is acquired, the acquired data may be preprocessed, including data cleaning and data standardization, to obtain semiconductor test data to be subjected to anomaly detection and repair.

[0110] Step 3: Anomaly Detection

[0111] According to the test phase corresponding to the semiconductor test data, an adapted target detection algorithm is selected from multiple anomaly detection algorithms, and the semiconductor test data is detected to obtain an anomaly detection result. The anomaly detection result can indicate whether there is an abnormal data in the semiconductor test data, and further indicate the type, location and possible cause of the abnormal data.

[0112] Step 4: Problem location

[0113] Based on the anomaly detection results, further analysis is performed to determine the specific links and causes of the problem. In-depth analysis of anomalies is performed using historical data and expert knowledge base.

[0114] Step 5: Abnormal alarm and repair

[0115] When the anomaly detection result indicates that there is abnormal data in the semiconductor test data, an alarm is immediately issued to notify relevant personnel, and the data repair mechanism is automatically run. That is, according to the anomaly type corresponding to the abnormal data and the degree of verification of the repair, an adapted target repair algorithm is selected from multiple anomaly repair algorithms, and the abnormal data is repaired to obtain the anomaly repair result.

[0116] The abnormal type corresponding to the abnormal data can be determined according to the result of problem location in step 4.

[0117] Among them, repairs can be achieved while ensuring safety and without affecting production. The repair process may involve adjustment of equipment parameters, replacement of materials or optimization of processes, etc. The repair process can also be monitored to ensure that the problem is effectively solved.

[0118] Step 6: Evaluation of repair effect

[0119] After the repair is completed, data collection and analysis are performed again to evaluate the repair effect. If the anomaly is not eliminated, the problem is relocated and the anomaly is repaired.

[0120] Step 7: Knowledge Base Update

[0121] The experience of this anomaly detection and repair is recorded in the knowledge base to provide reference for similar problems in the future. The knowledge base is regularly updated and maintained to ensure its effectiveness and accuracy.

[0122] The technical solution of the embodiment of the present invention may include the following advantages:

[0123] Automated testing process: It can automatically receive and analyze semiconductor test data without manual intervention, reducing waiting and processing time;

[0124] Real-time detection capability: Using efficient anomaly detection algorithms, data streams can be detected in real time to detect anomalies in a timely manner and avoid potential delays;

[0125] Intelligent repair algorithm: using the abnormality type of abnormal data and the degree of verification of the repair, automatically select the most appropriate abnormality repair algorithm to improve the accuracy of the repair;

[0126] Adaptive learning mechanism: Through adaptive learning, the anomaly detection algorithm can be continuously optimized, anomalies can be identified more quickly, and the response speed of anomaly detection can be improved. Through adaptive learning, the anomaly repair algorithm can be learned and optimized from the repair process, further improving the effect of anomaly repair.

[0127] Multi-dimensional data analysis: It can analyze semiconductor test data from multiple dimensions, identify complex abnormal data, and perform precise repairs, reducing the possibility of false positives and false negatives.

[0128] Embodiment 4

[0129] Figure 3 1 is a schematic diagram of a structure of a semiconductor test data exception processing device according to a fourth embodiment of the present invention. This embodiment is applicable to the case of performing anomaly detection and repair on semiconductor test data. Figure 3 As shown, the specific structure of the device includes:

[0130] An acquisition module 31 is used to acquire semiconductor test data to be processed;

[0131] A detection module 32, configured to select an adapted target detection algorithm from a plurality of anomaly detection algorithms according to a test phase corresponding to the semiconductor test data, and detect the semiconductor test data to obtain an anomaly detection result, wherein data characteristics of different test phases are different;

[0132] The repair module 33 is used to select an adapted target repair algorithm from a plurality of abnormal repair algorithms according to the abnormal type corresponding to the abnormal data and the degree of verification of the repair when the abnormal detection result indicates that abnormal data exists in the semiconductor test data, and repair the abnormal data to obtain an abnormal repair result.

[0133] The semiconductor test data exception processing device provided in this embodiment acquires the semiconductor test data to be processed through an acquisition module; selects an adapted target detection algorithm from a plurality of anomaly detection algorithms according to the test phase corresponding to the semiconductor test data through a detection module, and detects the semiconductor test data to obtain an anomaly detection result, wherein the data characteristics of different test phases are different; and selects an adapted target repair algorithm from a plurality of anomaly repair algorithms according to the anomaly type corresponding to the anomaly data and the degree of verification of the repair when the anomaly detection result indicates that there is abnormal data in the semiconductor test data through a repair module, and repairs the abnormal data to obtain an abnormal repair result. The target detection algorithm selected by this scheme is more adapted to the data characteristics of the semiconductor test data, and the target repair algorithm selected by this scheme is more adapted to the data characteristics of the abnormal data in the semiconductor test data, thereby improving the accuracy of anomaly detection and repair of semiconductor test data.

[0134] Furthermore, the detection module 32 is specifically used for:

[0135] In a case where the test phase corresponding to the semiconductor test data is a wafer acceptance test, determining that the target detection algorithm is an algorithm implemented based on a multidimensional Gaussian model;

[0136] In a case where the testing phase is a wafer test, determining that the target detection algorithm is an isolation forest algorithm;

[0137] When the test phase is a chip test, the target detection algorithm is determined to be a density-based clustering algorithm.

[0138] Furthermore, the repair module 33 is specifically used for:

[0139] In the case where the abnormal type corresponding to the abnormal data is an abnormal parameter value in a wafer acceptance test, if the verification level is a first verification level, determining that the target repair algorithm is an interpolation method, and if the verification level is a second verification level, determining that the target repair algorithm is an algorithm implemented based on a first regression model;

[0140] Among them, the first verification degree includes that the neighboring data points of the abnormal parameter value are normal and the number of the neighboring data points exceeds a first threshold, and the repair value corresponding to the abnormal parameter value is within a first range; the second verification degree includes that the fit of the first regression model exceeds a second threshold and the prediction accuracy exceeds a third threshold.

[0141] Furthermore, the repair module 33 is specifically used for:

[0142] In the case where the abnormal type corresponding to the abnormal data is a functional test abnormality or an electrical parameter abnormality in a wafer test, if the verification level is the third verification level, it is determined that the target repair algorithm is an algorithm implemented based on the second regression model; if the verification level is the fourth verification level, it is determined that the target repair algorithm is an interpolation repair implemented based on a classification algorithm;

[0143] Among them, the third verification level includes that the stability verification of the second regression model is passed and the prediction error is within a second range; the fourth verification level includes that the similarity between the data involved in the interpolation repair and the abnormal data is higher than a fourth threshold and the accuracy of the repair is higher than a fifth threshold.

[0144] Furthermore, the repair module 33 is specifically used for:

[0145] In the case where the abnormal type corresponding to the abnormal data is a functional test abnormality or an environmental test abnormality in chip testing, if the verification level is the fifth verification level, the target repair algorithm is determined to be a statistical correction algorithm based on historical data; if the verification level is the sixth verification level, the target repair algorithm is determined to be an algorithm implemented based on the third regression model;

[0146] Among them, the fifth verification level includes that the distribution of the historical data is consistent with the distribution of the current data and the rationality of the corresponding repair value is verified; the sixth verification level includes that the generalization ability of the third regression model is verified and the prediction error is within the third range.

[0147] Furthermore, the device also includes a test process detection module, which is used to:

[0148] When the abnormality detection result indicates that the semiconductor test data has no abnormality and the test stage is a wafer test or a chip test, detecting whether the test process identifier corresponding to the semiconductor test data is abnormal by a test process detection algorithm, and obtaining an identifier abnormality detection result;

[0149] The test process identifier at least includes: an off-chip retest identifier, an interrupt identifier, a whole batch retest identifier, and a batch split identifier.

[0150] Furthermore, the device also includes a test process repair module, which is used to:

[0151] When the identification anomaly detection result indicates that the test process identification is abnormal, the test process identification is repaired based on the test start time, test end time, all tested chips, test failed chips, and test passed chips corresponding to the test files of the same batch as the semiconductor test data.

[0152] The semiconductor test data exception processing device provided in the embodiment of the present invention can execute the semiconductor test data exception processing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0153] Embodiment 5

[0154] Figure 4 Schematic diagram of the structure of the electronic device implementing the embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0155] like Figure 4As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0156] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0157] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as an exception processing method for semiconductor test data.

[0158] In some embodiments, the semiconductor test data exception handling method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the semiconductor test data exception handling method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the semiconductor test data exception handling method in any other appropriate manner (e.g., by means of firmware).

[0159] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0160] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0161] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0162] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input from the user can be received in any form.

[0163] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0164] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0165] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0166] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for handling abnormality of semiconductor test data, characterized in that: include: Acquiring semiconductor test data to be processed; According to the test phase corresponding to the semiconductor test data, an adapted target detection algorithm is selected from a plurality of anomaly detection algorithms, and the semiconductor test data is detected to obtain an anomaly detection result, wherein data characteristics of different test phases are different; When the abnormality detection result indicates that abnormal data exists in the semiconductor test data, an adapted target repair algorithm is selected from multiple abnormality repair algorithms according to the abnormality type corresponding to the abnormal data and the degree of verification of the repair, and the abnormal data is repaired to obtain an abnormality repair result.

2. The method according to claim 1, characterized in that According to the test phase corresponding to the semiconductor test data, an adapted target detection algorithm is selected from a plurality of anomaly detection algorithms, including: In a case where the test phase corresponding to the semiconductor test data is a wafer acceptance test, determining that the target detection algorithm is an algorithm implemented based on a multidimensional Gaussian model; In a case where the testing phase is a wafer test, determining that the target detection algorithm is an isolation forest algorithm; When the test phase is a chip test, the target detection algorithm is determined to be a density-based clustering algorithm.

3. The method according to claim 1, characterized in that: According to the abnormality type corresponding to the abnormal data and the degree of verification of the repair, an adapted target repair algorithm is selected from a plurality of abnormality repair algorithms, including: In the case where the abnormal type corresponding to the abnormal data is an abnormal parameter value in a wafer acceptance test, if the verification level is a first verification level, determining that the target repair algorithm is an interpolation method, and if the verification level is a second verification level, determining that the target repair algorithm is an algorithm implemented based on a first regression model; Among them, the first verification degree includes that the neighboring data points of the abnormal parameter value are normal and the number of the neighboring data points exceeds a first threshold, and the repair value corresponding to the abnormal parameter value is within a first range; the second verification degree includes that the fit of the first regression model exceeds a second threshold and the prediction accuracy exceeds a third threshold.

4. The method according to claim 1, characterized in that According to the abnormality type corresponding to the abnormal data and the degree of verification of the repair, an adapted target repair algorithm is selected from a plurality of abnormality repair algorithms, including: In the case where the abnormal type corresponding to the abnormal data is a functional test abnormality or an electrical parameter abnormality in a wafer test, if the verification level is the third verification level, it is determined that the target repair algorithm is an algorithm implemented based on the second regression model; if the verification level is the fourth verification level, it is determined that the target repair algorithm is an interpolation repair implemented based on a classification algorithm; Among them, the third verification level includes that the stability verification of the second regression model is passed and the prediction error is within a second range; the fourth verification level includes that the similarity between the data involved in the interpolation repair and the abnormal data is higher than a fourth threshold and the accuracy of the repair is higher than a fifth threshold.

5. The method according to claim 1, characterized in that According to the abnormality type corresponding to the abnormal data and the degree of verification of the repair, an adapted target repair algorithm is selected from a plurality of abnormality repair algorithms, including: In the case where the abnormal type corresponding to the abnormal data is a functional test abnormality or an environmental test abnormality in chip testing, if the verification level is the fifth verification level, the target repair algorithm is determined to be a statistical correction algorithm based on historical data; if the verification level is the sixth verification level, the target repair algorithm is determined to be an algorithm implemented based on the third regression model; Among them, the fifth verification level includes that the distribution of the historical data is consistent with the distribution of the current data and the rationality of the corresponding repair value is verified; the sixth verification level includes that the generalization ability of the third regression model is verified and the prediction error is within the third range.

6. The method according to claim 1, characterized in that Also includes: When the abnormality detection result indicates that the semiconductor test data has no abnormality and the test stage is a wafer test or a chip test, detecting whether the test flow identifier corresponding to the semiconductor test data is abnormal by a test flow detection algorithm, and obtaining an identifier abnormality detection result; The test process identifier at least includes: an off-chip retest identifier, an interrupt identifier, a whole batch retest identifier, and a batch split identifier.

7. The method according to claim 6, characterized in that Also includes: When the identification anomaly detection result indicates that the test process identification is abnormal, the test process identification is repaired based on the test start time, test end time, all tested chips, test failed chips, and test passed chips corresponding to the test files of the same batch as the semiconductor test data.

8. A semiconductor test data exception processing device, characterized in that: include: An acquisition module, used for acquiring semiconductor test data to be processed; A detection module, configured to select an adapted target detection algorithm from a plurality of anomaly detection algorithms according to a test phase corresponding to the semiconductor test data, and detect the semiconductor test data to obtain an anomaly detection result, wherein data characteristics of different test phases are different; A repair module is used to select an adapted target repair algorithm from a plurality of abnormal repair algorithms according to the abnormal type corresponding to the abnormal data and the degree of verification of the repair when the abnormal detection result indicates that abnormal data exists in the semiconductor test data, and repair the abnormal data to obtain an abnormal repair result.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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