Wafer-level bonding method and bonding structure of III-V group semiconductor material and silicon wafer

Abstract

The invention discloses a wafer-level bonding method and a wafer-level bonding structure of a III-V group semiconductor material and a silicon wafer, and the wafer-level bonding method comprises the steps: providing a silicon substrate, forming a groove structure on the silicon substrate, and growing a heteroepitaxial layer of the III-V group semiconductor material on the silicon substrate through the groove structure; manufacturing a mesa structure of the photoelectric device by using the heteroepitaxial layer; forming a first metal bonding structure on the mesa structure of the photoelectric device; providing a silicon wafer, and forming a second metal bonding structure corresponding to the first metal bonding structure on the surface of the silicon wafer; and the silicon substrate on which the mesa structure of the photoelectric device is formed and the silicon wafer are subjected to counterpoint pressing, and the first metal bonding structure and the second metal bonding structure are subjected to counterpoint bonding. According to the wafer-level bonding method and the wafer-level bonding structure of the III-V group semiconductor material and the silicon wafer, wafer-level bonding of the III-V group semiconductor material and the silicon wafer can be realized, and the packaging efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a wafer-level bonding method and a bonding structure for a III-V semiconductor material and a silicon wafer. Background Art

[0002] Group III-V semiconductor materials generally have excellent optoelectronic properties and high-frequency performance, while silicon materials have good integrated circuit compatibility. Therefore, the combination of the two helps to achieve high-efficiency heterogeneous integrated circuits (Heterogeneous Integration).

[0003] The wafer-to-wafer (W2W) packaging method of III-V semiconductor material wafers and silicon wafers combines the respective advantages of III-V semiconductor materials, such as gallium arsenide (GaAs), indium phosphide (InP), etc., with silicon materials, and can realize high-performance optoelectronic devices, radio frequency devices or other heterogeneous integrated applications. However, the direct bonding of III-V semiconductor material wafers and silicon wafers also has certain technical challenges, mainly manifested in material mismatch, large differences in lattice constants, stress, dislocations and crystal defects, which affect device performance. At the same time, the difference in thermal expansion coefficients between the two may cause thermal stress in high-temperature processes, affecting the reliability of the package.

[0004] The current mainstream packaging method of III-V semiconductor material devices and silicon wafers is chip to chip or chip to wafer. The III-V semiconductor material wafer is first cut into semiconductor material device chips, and then packaged on a silicon wafer or silicon chip by flip-chip bonding.

[0005] The above packaging method has low efficiency and complex process.

[0006] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0007] The object of the present invention is to provide a wafer-level bonding method and bonding structure for III-V semiconductor materials and silicon wafers, which can achieve wafer-level bonding of III-V semiconductor materials and silicon wafers and improve packaging efficiency.

[0008] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0009] A wafer-level bonding method for a III-V semiconductor material and a silicon wafer, comprising:

[0010] Providing a silicon substrate, forming a groove structure on the silicon substrate, and growing a heteroepitaxial layer of a III-V semiconductor material on the silicon substrate using the groove structure;

[0011] Using the heteroepitaxial layer to manufacture a mesa structure of an optoelectronic device;

[0012] forming a first metal bonding structure on the optoelectronic device mesa structure;

[0013] Providing a silicon wafer, and forming a second metal bonding structure corresponding to the first metal bonding structure on a surface of the silicon wafer;

[0014] The silicon substrate formed with the mesa structure of the optoelectronic device is aligned and pressed with the silicon wafer, and the first metal bonding structure is aligned and bonded with the second metal bonding structure.

[0015] In one or more embodiments of the present invention, a silicon substrate is provided, and a groove structure is formed on the silicon substrate, including:

[0016] Providing a silicon substrate, wherein the silicon substrate has a first surface, wherein the first surface is a non-{111} crystal plane;

[0017] Forming a photoresist layer on the first surface of the silicon substrate, and forming a groove on the photoresist layer, wherein the groove has at least one inclined surface with a desired inclination angle;

[0018] The photoresist layer is used as a mask layer, and the silicon substrate is obliquely etched along the inclined surface of the groove to form a groove structure having at least one {111} crystal plane on the silicon substrate.

[0019] In one or more embodiments of the present invention, the first surface is a {100} crystal plane, and the inclined surface of the groove has an inclination angle of 54.7° relative to the first surface; and / or,

[0020] A groove having an inverted trapezoidal radial cross section is formed on the photoresist layer by using an exposure and development technology, wherein the inclination angles of two side surfaces of the groove relative to the first surface are both 54.7°; and / or,

[0021] By using the inclined etching technology of ion beam etching, a groove structure with a {111} crystal plane is etched on the silicon substrate along the inclined direction parallel to the groove. The radial cross section of the groove structure is a parallelogram and the groove structure has two {111} crystal planes arranged opposite to each other.

[0022] In one or more embodiments of the present invention, growing a heteroepitaxial layer of a III-V semiconductor material on the silicon substrate using the trench structure includes:

[0023] Depositing an oxide layer on the silicon substrate, wherein the oxide layer exposes at least one {111} crystal plane of the groove structure;

[0024] epitaxially growing a flat layer on the {111} crystal plane exposed by the groove structure, wherein the flat layer at least covers the groove structure and a top surface of the flat layer is parallel to the first surface of the silicon substrate;

[0025] A functional layer of group III-V semiconductor material is epitaxially grown on the flat layer.

[0026] In one or more embodiments of the present invention, the method of using the heteroepitaxial layer to manufacture a mesa structure of an optoelectronic device includes:

[0027] The heteroepitaxial layer is patterned and etched to form a mesa structure of an optoelectronic device.

[0028] In one or more embodiments of the present invention, forming a first metal bonding structure on the optoelectronic device mesa structure includes:

[0029] forming a first barrier layer on the heteroepitaxial layer, wherein the first barrier layer covers the optoelectronic device mesa structure;

[0030] forming a first window on the first barrier layer to expose the mesa structure of the optoelectronic device;

[0031] A first metal bonding structure is formed in the first window.

[0032] In one or more embodiments of the present invention, forming a first metal bonding structure in the first window includes:

[0033] forming a first seed layer on the inner wall of the first window and on the surface of the first barrier layer;

[0034] forming a first metal bonding layer on the first seed layer;

[0035] The first metal bonding layer is thinned and polished to form a first metal bonding structure located in the first window, wherein the surface roughness of the first metal bonding structure is less than 1 nm.

[0036] In one or more embodiments of the present invention, forming a second metal bonding structure corresponding to the first metal bonding structure on the surface of the silicon wafer includes:

[0037] forming a second barrier layer on the surface of the silicon wafer;

[0038] A second window corresponding to the first window is formed on the second barrier layer, and a second metal bonding structure is formed in the second window.

[0039] In one or more embodiments of the present invention, forming a second metal bonding structure in the second window includes:

[0040] forming a second seed layer on the inner wall of the second window and on the surface of the second barrier layer;

[0041] forming a second metal bonding layer on the second seed layer;

[0042] The second metal bonding layer is thinned and polished to form a second metal bonding structure located in the second window, and the surface roughness of the second metal bonding structure is less than 1 nm.

[0043] A bonding structure of a III-V semiconductor material and a silicon wafer is formed by bonding the III-V semiconductor material and the silicon wafer using the wafer-level bonding method described above.

[0044] Compared with the prior art, the wafer-level bonding method and bonding structure of the III-V semiconductor material and the silicon wafer of the present invention achieves wafer-to-wafer bonding of the III-V semiconductor material optoelectronic device and the silicon wafer by heteroepitaxially growing the III-V semiconductor material on a patterned silicon substrate and utilizing the advantages of heteroepitaxial growth on a patterned substrate.

[0045] The wafer-level bonding method and bonding structure of the III-V semiconductor material and silicon wafer of the present invention, and the wafer-to-wafer packaging technology enable the III-V semiconductor material and silicon material to be combined in the same system, thereby optimizing the overall performance and achieving higher integration and functional density. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 The process flow chart of a wafer-level bonding method of a III-V semiconductor material and a silicon wafer in one embodiment of the present invention;

[0048] Figure 2a-2i Schematic diagram of the steps of a wafer-level bonding method for a III-V semiconductor material and a silicon wafer in one embodiment of the present invention (selected from a partial cross section of a whole wafer);

[0049] Figure 3 for Figure 2b Top view of the silicon substrate. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0051] As mentioned in the background technology, the wafer-to-wafer (W2W) packaging method of III-V semiconductor material wafers and silicon wafers can combine the respective advantages of III-V semiconductor materials and silicon materials, and can realize high-performance optoelectronic devices, radio frequency devices or other heterogeneous integrated applications. However, the direct bonding of III-V semiconductor material wafers and silicon wafers also has certain technical challenges, which are mainly manifested in material mismatch, large differences in lattice constants, stress, dislocations and crystal defects, which affect device performance. At the same time, the difference in thermal expansion coefficients between the two may cause thermal stress in high-temperature processes, affecting the reliability of packaging.

[0052] In order to solve the above technical problems, the present invention provides a wafer-level bonding method and bonding structure for III-V semiconductor materials and silicon wafers, by heteroepitaxially growing III-V semiconductor materials on a patterned silicon substrate and utilizing the advantages of heteroepitaxial growth on a patterned substrate, wafer-to-wafer bonding of III-V semiconductor material optoelectronic devices and silicon wafers is achieved.

[0053] like Figure 1 As shown, a wafer-level bonding method of a III-V semiconductor material and a silicon wafer in an embodiment of the present invention specifically includes the following steps:

[0054] S1, providing a silicon substrate, forming a groove structure on the silicon substrate, and growing a heteroepitaxial layer of a III-V semiconductor material on the silicon substrate using the groove structure.

[0055] S2, using heteroepitaxial layers to fabricate mesa structures of optoelectronic devices.

[0056] S3, forming a first metal bonding structure on the optoelectronic device mesa structure.

[0057] S4, providing a silicon wafer, and forming a second metal bonding structure corresponding to the first metal bonding structure on a surface of the silicon wafer.

[0058] S5, aligning and pressing the silicon substrate formed with the mesa structure of the optoelectronic device and the silicon wafer, aligning and bonding the first metal bonding structure and the second metal bonding structure, so as to achieve wafer-level bonding between the III-V semiconductor material and the silicon wafer.

[0059] In step S1, the silicon substrate provided has a first surface, and the first surface is a non-{111} crystal plane. The groove structure has at least one {111} crystal plane. The specific steps of forming the groove structure on the silicon substrate are as follows: first, a photoresist layer is formed on the first surface of the silicon substrate; second, a groove is formed on the photoresist layer, and the groove has at least one inclined surface with a desired inclination angle; then, the photoresist layer is used as a mask layer, and the silicon substrate is obliquely etched along the inclined surface of the groove to form a groove structure with at least one {111} crystal plane on the silicon substrate.

[0060] The specific steps of growing a heteroepitaxial layer of a III-V semiconductor material on a silicon substrate using a groove structure are as follows: depositing an oxide layer on the silicon substrate, the oxide layer exposing at least one {111} crystal plane of the groove structure; epitaxially growing a flat layer on the {111} crystal plane exposed by the groove structure, the flat layer at least covering the groove structure and the top surface of the flat layer being parallel to the first surface of the silicon substrate; epitaxially growing a functional layer of a III-V semiconductor material on the flat layer. The flat layer and the functional layer together constitute a heteroepitaxial layer of a III-V semiconductor material.

[0061] In step S2, the heteroepitaxial layer is patterned and etched to produce a mesa structure of an optoelectronic device.

[0062] In step S3, a first metal bonding structure may be formed on the mesa structure of the optoelectronic device in the following specific manner. A first barrier layer is formed on the heteroepitaxial layer, the first barrier layer covers the mesa structure of the optoelectronic device; a first window is formed on the first barrier layer to expose the mesa structure of the optoelectronic device; a first seed layer is formed on the inner wall of the first window and on the surface of the first barrier layer; a first metal bonding layer is formed on the first seed layer; and the first metal bonding layer is thinned and polished to form a first metal bonding structure located in the first window. The surface roughness of the first metal bonding structure is less than 1 nm, preferably 0.5 nm-1 nm.

[0063] In step S4, a second metal bonding structure may be formed on the surface of the silicon wafer in the following specific manner: forming a second barrier layer on the surface of the silicon wafer; forming a second window corresponding to the first window on the second barrier layer; forming a second seed layer on the inner wall of the second window and on the surface of the second barrier layer; forming a second metal bonding layer on the second seed layer; and thinning and polishing the second metal bonding layer to form a second metal bonding structure located in the second window, wherein the surface roughness of the second metal bonding structure is less than 1 nm, preferably 0.5 nm-1 nm.

[0064] Figure 2a-2i The schematic diagram of the steps of the wafer-level bonding method of the III-V semiconductor material and the silicon wafer of the present invention is as follows. Figure 2a-2i, the wafer-level bonding method of the III-V semiconductor material and the silicon wafer of the present invention is elaborated in detail to facilitate a further understanding of the technical solution of the present invention.

[0065] refer to Figure 2a As shown, a silicon substrate 10 is provided, the silicon substrate 10 has a first surface 10a, and the first surface 10a is a non-{111} crystal plane. A photoresist layer 20 is formed on the first surface 10a of the silicon substrate 10, and a groove 21 is formed on the photoresist layer 20, and the groove 21 has an inclined surface 211 with at least one desired tilt angle.

[0066] In a specific embodiment, the first surface 10a is a {100} crystal plane; the inclined surface 211 of the groove 21 has an inclination angle of 54.7° relative to the first surface 10a. There may be a plurality of grooves 21 arranged in an array on the photoresist layer 20.

[0067] Exemplarily, a suitable positive photoresist is selected to be spin-coated on the first surface 10a of the silicon substrate 10 to form a positive photoresist layer. Positive photoresist is usually more likely to form a cross section with a positive slope surface after exposure (the slope is upward and is positive), which helps to adjust the exposure light source angle in order to obtain the required tilt angle of 54.7 ° in the future. Design and provide a mask, a pattern with a required bevel angle is formed on the mask, the mask is covered on the surface of the positive photoresist layer, and the pattern formed on the positive photoresist layer is arranged according to the shape of the mask. The angle of the exposure light source is adjusted on the lithography machine so that it is not perpendicular to the surface of the positive photoresist layer, but presents a certain angle with the surface, preferably 54.7 °, the positive photoresist layer is exposed, and the pattern of the required first groove structure is obtained by optimizing the exposure parameters, and then developed to form a positive trapezoidal pattern with a 54.7 ° bevel.

[0068] refer to Figure 2b As shown, the photoresist layer 20 is used as a mask layer, and the silicon substrate 10 is obliquely etched along the inclined surface 211 of the groove 21 to form a groove structure 11 having at least one {111} crystal plane 111 on the silicon substrate 10 .

[0069] Exemplarily, by using the oblique etching technology of ion beam etching (IBE), a groove structure 11 having two oppositely disposed {111} crystal planes 111 is etched on the silicon substrate 10 along a direction parallel to one of the inclined surfaces 211 of the groove 21 .

[0070] It can be understood that the silicon substrate of the present application can form a plurality of groove structures arranged in an array through the above scheme, which is conducive to the subsequent growth of the heteroepitaxial layer and improves the quality of the heteroepitaxial layer. Figure 3 shown.

[0071] The present application applies IBE technology to the etching of silicon substrates. The direction of the ion beam source of the equipment can be adjusted. The etching direction is controlled by changing the incident angle θ of the ion beam to complete the etching of the silicon substrate 10 along the direction of the inclined surface 211 parallel to the groove 21, and a parallelogram structure with two {111} crystal planes 111 is formed on the silicon substrate 10.

[0072] refer to Figure 2c As shown, the photoresist layer 20 is removed, and an oxide layer 30 is deposited on the silicon substrate 10, wherein the oxide layer 30 exposes at least one {111} crystal plane 111 of the groove structure 11. A planar layer 40 of a group III-V semiconductor material is epitaxially grown on the silicon substrate 10 using the {111} crystal plane 111 exposed by the groove structure 11. The planar layer 40 at least covers the groove structure 11, and the top surface of the planar layer 40 is parallel to the first surface 10a of the silicon substrate 10.

[0073] Exemplarily, the oxide layer 30 is deposited on the first surface 10a of the silicon substrate 10 and the inner wall of the groove structure 11. If the radial structure of the groove structure 11 is a parallelogram, the oxide layer 30 is deposited on the bottom wall of the groove structure 11 and the {111} crystal plane 111 with a positive slope (the slope facing upward is positive), and the {111} crystal plane 111 with a negative slope is completely exposed, which can be used for epitaxial growth of the flat layer 40 of the III-V semiconductor material; if the radial structure of the groove structure 11 is a triangle, the oxide layer 30 is deposited on the two {111} crystal planes 111 of the groove structure 11, and the oxide layer on the two {111} crystal planes of the groove structure is etched to expose the {111} crystal plane. If the radial structure of the groove structure 11 is a right-angled trapezoid, the oxide layer 30 is deposited on the inner wall of the groove structure 11, and the oxide layer on one {111} crystal plane (slope) of the groove structure is etched to expose the {111} crystal plane.

[0074] Since the groove structure 11 is exposed as a {111} crystal plane 111, the epitaxially grown flat layer 40 can be well lattice-matched with the silicon substrate 10, so that the flat layer 40 has a high quality. It should be understood that the thickness of the flat layer 40 is at least greater than or equal to the depth of the groove structure 11, so that the flat layer 40 can cover the groove structure 11, so that the top surface of the flat layer 40 is in the same plane and parallel to the first surface 10a of the silicon substrate 10, thereby obtaining a substrate structure with a relatively flat top surface, so as to provide a high-quality substrate structure for the heteroepitaxial functional layer of III-V semiconductor materials that is subsequently epitaxially grown.

[0075] In some embodiments, the material of the planar layer 40 may be InP or GaAs.

[0076] refer to Figure 2dAs shown, a heteroepitaxial functional layer of a III-V semiconductor material is epitaxially grown on the planar layer 40. The planar layer and the functional layer together constitute the heteroepitaxial layer of the III-V semiconductor material.

[0077] The heteroepitaxial functional layer of the III-V group semiconductor material includes an N-type InP layer 51 , an InGaAs intrinsic layer 52 , a P-type InP layer 53 and an InGaAs contact layer 54 which are sequentially formed on the flat layer 40 .

[0078] refer to Figure 2e As shown, a mesa structure array is formed on a heteroepitaxial functional layer of a III-V semiconductor material by dry etching process, wherein the size of the mesa structure ranges from 5 μm to 30 μm, preferably 13 μm×13 μm, and the period ranges from 10 μm to 20 μm, preferably 15 μm.

[0079] A first barrier layer 61 is deposited on the heteroepitaxial functional layer. The first barrier layer 61 is preferably a silicon oxide layer with a thickness of 2 μm-10 μm. The first barrier layer 61 completely covers the mesa structure array.

[0080] By photolithography and etching technology, a first window 611 is etched at the center of the mesa structure on the first barrier layer 61. The first window 611 is preferably a circular hole with a diameter ranging from 2 μm to 10 μm. The first window 611 exposes the mesa structure.

[0081] refer to Figure 2f As shown, a first seed layer 612 is formed by sputtering on the inner wall of the first window 611 and on the surface of the first barrier layer 61. The first seed layer 612 is made of Ta / TaN / Cu, and the thicknesses are 50nm / 50nm / 500nm respectively.

[0082] A first metal bonding layer is formed on the first seed layer 612 by electroplating. The first metal bonding layer is thinned and polished by CMP technology to form a first metal bonding structure 613 located in the first window 611. The height of the first metal bonding structure is equal to the thickness of the first barrier layer 61. The surface roughness of the first metal bonding structure is less than 1nm, preferably 0.5nm-1nm. The material of the first metal bonding structure is preferably Cu.

[0083] refer to Figure 2g As shown, a silicon wafer 70 is provided, and a second barrier layer 81 is formed on the surface of the silicon wafer 70. The second barrier layer 81 is preferably a silicon oxide layer with a thickness of 2 μm-10 μm. The silicon wafer 70 is preferably a functional silicon integrated wafer.

[0084] By photolithography and etching technology, a second window 811 corresponding to the first window 611 is etched on the second barrier layer 81. The second window 811 is preferably a circular hole with a diameter ranging from 2 μm to 10 μm. The second window 811 exposes the silicon wafer 70.

[0085] refer to Figure 2h As shown, a second seed layer 812 is formed by sputtering on the inner wall of the second window 811 and on the surface of the second barrier layer 81. The second seed layer 812 is made of Ta / TaN / Cu, and the thicknesses thereof are 50nm / 50nm / 500nm, respectively.

[0086] A second metal bonding layer is formed on the second seed layer 812 by electroplating. The second metal bonding layer is thinned and polished by CMP technology to form a second metal bonding structure 813 located in the second window 811. The height of the second metal bonding structure is equal to the thickness of the second barrier layer 81. The surface roughness of the second metal bonding structure is less than 1nm, preferably 0.5nm-1nm. The material of the second metal bonding structure is preferably Cu.

[0087] refer to Figure 2i As shown, the silicon substrate 10 formed with the mesa structure of the optoelectronic device is aligned and pressed with the silicon wafer 70, and the first metal bonding structure 613 and the second metal bonding structure 813 are aligned and bonded, and are in an interconnected state, thereby realizing wafer-level bonding between the III-V semiconductor material and the silicon wafer.

[0088] The present invention also provides a bonding structure of a III-V semiconductor material and a silicon wafer, which is formed by bonding using the above-mentioned wafer-level bonding method of the III-V semiconductor material and the silicon wafer.

[0089] The bonding structure of the III-V group semiconductor material and the silicon wafer includes a silicon substrate 10 , a heteroepitaxial structure, a barrier layer, a metal bonding structure and a silicon wafer 70 .

[0090] The silicon substrate 10 has a first surface 10 a which is not a {111} crystal plane. A plurality of groove structures 11 arranged in an array are formed on the first surface 10 a . Each groove structure 11 exposes at least one {111} crystal plane 111 of the silicon substrate 10 .

[0091] Preferably, the radial cross-section of the groove structure 11 can be a parallelogram, exposing two {111} crystal planes 111 of the silicon substrate 10; the radial cross-section of the groove structure 11 can be a triangle, exposing two {111} crystal planes 111 of the silicon substrate 10; or the radial cross-section of the groove structure 11 can be an inverted right-angled trapezoid, exposing one {111} crystal plane 111 of the silicon substrate 10.

[0092] A heteroepitaxial structure is formed on the first surface 10a of the silicon substrate 10, and the heteroepitaxial structure includes a flat layer 40 formed in the groove structure 11 and one or more optoelectronic devices formed on the flat layer 40. An oxide layer 30 is also formed between the flat layer 40 and the first surface 10a. The oxide layer 30 does not cover at least one {111} crystal plane 111 of the groove structure 11.

[0093] The barrier layer is formed on the heteroepitaxial structure, a window exposing the optoelectronic device is formed in the barrier layer, and a metal bonding structure is arranged in the window.

[0094] The silicon wafer 70 is disposed on the surface of the barrier layer facing away from the silicon substrate 10 , and the silicon wafer 70 is electrically bonded to the optoelectronic device through a metal bonding structure.

[0095] Compared with the prior art, the wafer-level bonding method and bonding structure of the III-V semiconductor material and the silicon wafer of the present invention achieves wafer-to-wafer bonding of the III-V semiconductor material optoelectronic device and the silicon wafer by heteroepitaxially growing the III-V semiconductor material on a patterned silicon substrate and utilizing the advantages of heteroepitaxial growth on a patterned substrate.

[0096] The wafer-level bonding method and bonding structure of the III-V semiconductor material and silicon wafer of the present invention, and the wafer-to-wafer packaging technology enable the III-V semiconductor material and silicon material to be combined in the same system, thereby optimizing the overall performance and achieving higher integration and functional density.

[0097] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0098] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A wafer-level bonding method for a III-V semiconductor material and a silicon wafer, characterized in that: include: Providing a silicon substrate, forming a groove structure on the silicon substrate, and growing a heteroepitaxial layer of a III-V semiconductor material on the silicon substrate using the groove structure; Using the heteroepitaxial layer to manufacture a mesa structure of an optoelectronic device; forming a first metal bonding structure on the optoelectronic device mesa structure; Providing a silicon wafer, and forming a second metal bonding structure corresponding to the first metal bonding structure on a surface of the silicon wafer; The silicon substrate formed with the mesa structure of the optoelectronic device is aligned and pressed with the silicon wafer, and the first metal bonding structure is aligned and bonded with the second metal bonding structure.

2. The wafer-level bonding method of a III-V semiconductor material and a silicon wafer according to claim 1, characterized in that: Providing a silicon substrate, and forming a groove structure on the silicon substrate, comprising: Providing a silicon substrate, wherein the silicon substrate has a first surface, wherein the first surface is a non-{111} crystal plane; Forming a photoresist layer on the first surface of the silicon substrate, and forming a groove on the photoresist layer, wherein the groove has at least one inclined surface with a desired inclination angle; The photoresist layer is used as a mask layer, and the silicon substrate is obliquely etched along the inclined surface of the groove to form a groove structure having at least one {111} crystal plane on the silicon substrate.

3. The wafer-level bonding method of a III-V semiconductor material and a silicon wafer according to claim 2, characterized in that: The first surface is a {100} crystal plane, and the inclined surface of the groove has an inclination angle of 54.7° relative to the first surface; and / or, A groove having an inverted trapezoidal radial cross section is formed on the photoresist layer by using an exposure and development technology, wherein the inclination angles of two side surfaces of the groove relative to the first surface are both 54.7°; and / or, By using the inclined etching technology of ion beam etching, a groove structure with a {111} crystal plane is etched on the silicon substrate along the inclined direction parallel to the groove. The radial cross section of the groove structure is a parallelogram and the groove structure has two {111} crystal planes arranged opposite to each other.

4. The wafer-level bonding method of a III-V semiconductor material and a silicon wafer according to claim 2, characterized in that: Growing a heteroepitaxial layer of a III-V semiconductor material on the silicon substrate using the groove structure comprises: Depositing an oxide layer on the silicon substrate, wherein the oxide layer exposes at least one {111} crystal plane of the groove structure; epitaxially growing a flat layer on the {111} crystal plane exposed by the groove structure, wherein the flat layer at least covers the groove structure and a top surface of the flat layer is parallel to the first surface of the silicon substrate; A functional layer of group III-V semiconductor material is epitaxially grown on the flat layer.

5. The wafer-level bonding method of a III-V semiconductor material and a silicon wafer according to claim 1, characterized in that: The method of using the heteroepitaxial layer to manufacture a mesa structure of an optoelectronic device comprises: The heteroepitaxial layer is patterned and etched to form a mesa structure of an optoelectronic device.

6. The wafer-level bonding method of a III-V semiconductor material and a silicon wafer according to claim 1, characterized in that: Forming a first metal bonding structure on the optoelectronic device mesa structure, comprising: forming a first barrier layer on the heteroepitaxial layer, wherein the first barrier layer covers the optoelectronic device mesa structure; forming a first window on the first barrier layer to expose the mesa structure of the optoelectronic device; A first metal bonding structure is formed in the first window.

7. The wafer-level bonding method of a III-V semiconductor material and a silicon wafer according to claim 6, characterized in that: forming a first metal bonding structure in the first window, comprising: forming a first seed layer on the inner wall of the first window and on the surface of the first barrier layer; forming a first metal bonding layer on the first seed layer; The first metal bonding layer is thinned and polished to form a first metal bonding structure located in the first window, wherein the surface roughness of the first metal bonding structure is less than 1 nm.

8. The wafer-level bonding method of a III-V semiconductor material and a silicon wafer according to claim 6, characterized in that: Forming a second metal bonding structure corresponding to the first metal bonding structure on the surface of the silicon wafer, comprising: forming a second barrier layer on the surface of the silicon wafer; A second window corresponding to the first window is formed on the second barrier layer, and a second metal bonding structure is formed in the second window.

9. The wafer-level bonding method of a III-V semiconductor material and a silicon wafer according to claim 8, characterized in that: forming a second metal bonding structure in the second window, comprising: forming a second seed layer on the inner wall of the second window and on the surface of the second barrier layer; forming a second metal bonding layer on the second seed layer; The second metal bonding layer is thinned and polished to form a second metal bonding structure located in the second window, and the surface roughness of the second metal bonding structure is less than 1 nm.

10. A bonding structure of a III-V semiconductor material and a silicon wafer, formed by bonding using the wafer-level bonding method of a III-V semiconductor material and a silicon wafer as described in any one of claims 1 to 9.

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