Packaging structure and preparation method thereof

Abstract

The invention provides a packaging structure and a preparation method thereof, the packaging structure comprises a recombination structure, a first rewiring layer and at least one stacked chip group which are stacked, and the at least one stacked chip group is electrically connected with the first rewiring layer; the recombination structure comprises a first chip and a plurality of conductive columns, and the bottom surface of the stacked chip set and the bottom surface of the first chip are located on different planes; the first redistribution layer is electrically connected with the plurality of conductive columns; the packaging structure further comprises a heat dissipation structure, and the heat dissipation structure is adjacent to the stacked chip set and / or the first chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a packaging structure and a preparation method thereof. Background Art

[0002] With the continuous advancement of semiconductor processes and technologies, chips and electronic products are developing in the direction of miniaturization, high density, and high performance. Integrating chips with higher performance and more functions in a limited area has become an inevitable trend. At the same time, as the development of Moore's Law gradually slows down, chip stacking and packaging technology can not only make up for the limitations of the slowdown of Moore's Law to a certain extent, but also show significant advantages in some aspects. Therefore, the position of chip stacking and packaging technology in the electronic product industry chain is becoming more and more important.

[0003] However, in the direction of chip stacking, there is a risk of heat sources of multiple chips being concentrated, resulting in poor heat dissipation effect of the packaging structure. Summary of the invention

[0004] Embodiments of the present disclosure provide a packaging structure and a method for preparing the same.

[0005] In a first aspect, an embodiment of the present disclosure provides a packaging structure, the packaging structure comprising: a stacked reorganization structure, a first redistribution layer, and at least one stacked chipset, the at least one stacked chipset being electrically connected to the first redistribution layer; the reorganization structure comprising a first chip and a plurality of conductive pillars, the bottom surface of the stacked chipset being located in a different plane from the bottom surface of the first chip; the first redistribution layer being electrically connected to the plurality of conductive pillars;

[0006] The packaging structure further includes a heat dissipation structure, and the heat dissipation structure is adjacent to the stacked chipset and / or the first chip.

[0007] In some embodiments, the stacked chipset includes at least one layer of second chips, and the bottom surface of the stacked chipset is the bottom surface of the second chip at the bottom layer.

[0008] In some embodiments, the heat dissipation structure includes at least one microfluidic chip, and the at least one microfluidic chip includes a plurality of flow channels, an input port, and an output port;

[0009] The heat dissipation liquid enters the plurality of flow channels from the input port, passes through the plurality of flow channels, and is discharged from the output port.

[0010] In some embodiments, the package structure further includes a second redistribution layer, the second redistribution layer being electrically connected to the plurality of conductive pillars;

[0011] The first redistribution layer and the second redistribution layer are respectively located on a first surface and a second surface of the reorganization structure, and the first surface of the reorganization structure is opposite to the second surface of the reorganization structure.

[0012] In some embodiments, the package structure further includes a plurality of first bonding structures and a plurality of second bonding structures;

[0013] The plurality of first bonding structures are close to the first surface of the reorganization structure, and the at least one stacked chipset is electrically connected to the first redistribution layer through the plurality of first bonding structures;

[0014] The plurality of second bonding structures are close to the second surface of the reorganization structure and are electrically connected to the second redistribution layer.

[0015] In some embodiments, the packaging structure includes two stacked chipsets, the heat dissipation structure is T-shaped, and the heat dissipation structure includes a first microfluidic chip and a second microfluidic chip connected to each other;

[0016] The first microfluidic chip is located between the two stacked chip groups and above the first chip; the second microfluidic chip is located above the two stacked chip groups and the first microfluidic chip.

[0017] In some embodiments, the packaging structure further includes a packaging material, and the packaging material is filled in the gap of the packaging structure.

[0018] In a second aspect, an embodiment of the present disclosure provides a method for preparing a packaging structure, the method comprising:

[0019] Providing a carrier chip, and forming a recombinant structure above the carrier chip; the recombinant structure includes a first chip and a plurality of conductive pillars;

[0020] forming a first redistribution layer electrically connected to the plurality of conductive pillars above the reorganization structure;

[0021] Placing at least one stacked chipset above the first redistribution layer, and electrically connecting the at least one stacked chipset to the first redistribution layer; a bottom surface of the stacked chipset and a bottom surface of the first chip are located in different planes;

[0022] A heat dissipation structure is placed adjacent to the stacked chipset and / or the first chip.

[0023] In some embodiments, forming a recombinant structure on the carrier chip comprises:

[0024] Providing the recombinant structure, and performing bonding processing on the recombinant structure and the carrier chip;

[0025] The first redistribution layer is located on a first surface of the reorganization structure, and the method further comprises:

[0026] performing a debonding process on the recombinant structure and the carrier chip;

[0027] A second redistribution layer electrically connected to the plurality of conductive pillars is formed on the second surface of the recombination structure; the first surface of the recombination structure is opposite to the second surface of the recombination structure.

[0028] In some embodiments, electrically connecting the at least one stacked chipset to the first redistribution layer includes:

[0029] A plurality of first bonding structures are formed above the first redistribution layer, and the at least one stacked chip group is electrically connected to the plurality of first bonding structures.

[0030] In some embodiments, the method further comprises:

[0031] A plurality of second bonding structures are formed, and the second redistribution layer is electrically connected to the plurality of second bonding structures.

[0032] In some embodiments, the heat dissipation structure includes at least one microfluidic chip, the at least one microfluidic chip includes a plurality of flow channels, and the method further includes:

[0033] An input port and an output port are formed on the at least one microfluidic chip; the heat dissipation liquid enters the plurality of flow channels from the input port, passes through the plurality of flow channels, and is discharged from the output port.

[0034] In some embodiments, forming a recombinant structure on the carrier chip comprises:

[0035] placing at least one channel chip and the first chip above the carrier chip; the at least one channel chip comprising the plurality of conductive pillars;

[0036] forming a first dielectric layer, wherein the first dielectric layer covers the at least one channel chip and the exposed surface of the first chip;

[0037] Parts of the first dielectric layer and the at least one channel chip are removed to expose the plurality of conductive pillars.

[0038] In some embodiments, forming a recombinant structure on the carrier chip comprises:

[0039] placing the first chip above the carrier chip;

[0040] placing the plurality of conductive pillars on at least one side of the first chip;

[0041] forming a second dielectric layer, wherein the second dielectric layer covers the plurality of conductive pillars and an exposed surface of the first chip;

[0042] A portion of the second dielectric layer is removed to expose the plurality of conductive pillars.

[0043] The present disclosure provides a packaging structure and a preparation method thereof, wherein the packaging structure includes stacked: a reorganization structure, a first redistribution layer and at least one stacked chipset, wherein at least one stacked chipset is electrically connected to the first redistribution layer; the reorganization structure includes a first chip and a plurality of conductive pillars, wherein the bottom surface of the stacked chipset and the bottom surface of the first chip are located in different planes; the first redistribution layer is electrically connected to the plurality of conductive pillars; the packaging structure also includes a heat dissipation structure, wherein the heat dissipation structure is adjacent to the stacked chipset and / or the first chip. In this way, the bottom surface of the stacked chipset and the bottom surface of the first chip are misaligned in the first direction, thereby avoiding the risk of heat concentration. In addition, the heat dissipation performance can be improved and the cost can be reduced by dissipating the heat from the stacked chipset and the first chip through the heat dissipation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0045] Figure 1 A schematic diagram of the composition of a packaging structure Figure 1 ;

[0046] Figure 2 A schematic diagram of the composition of a packaging structure Figure 2 ;

[0047] Figure 3 A schematic diagram of a packaging structure provided in an embodiment of the present disclosure Figure 1 ;

[0048] Figure 4 A schematic diagram of a packaging structure provided in an embodiment of the present disclosure Figure 2 ;

[0049] Figure 5 A schematic diagram of the composition structure of a first chip provided in an embodiment of the present disclosure;

[0050] Figure 6 A schematic diagram of a packaging structure provided in an embodiment of the present disclosure Figure 3 ;

[0051] Figure 7A schematic diagram of a process for preparing a packaging structure provided by an embodiment of the present disclosure;

[0052] Figure 8 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 1 ;

[0053] Fig. 9 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 2 ;

[0054] Fig.10 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 3 ;

[0055] Fig.11 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 4 ;

[0056] Fig.12 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 5 ;

[0057] Fig.13 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 6 ;

[0058] Fig.14 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 7 ;

[0059] Fig.15 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 8 ;

[0060] Fig.16 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 9 ;

[0061] Fig.17 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 10 . DETAILED DESCRIPTION

[0062] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0063] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0064] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0065] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] In today's advanced packaging processes, fan-out processes and interposer processes are often used to package multiple identical or different dies into one unit to achieve better performance.

[0068] See also Figure 1, which shows a schematic diagram of the composition structure of a packaging structure Figure 1 , specifically, a schematic diagram of the architecture of a two-dimensional (2D) stacked high-performance storage and computing integrated chip (storage and computing chip for short). Figure 1 As shown, in the related art, the package structure 10 includes a substrate 11, a plurality of bonding structures 12 (only one number is shown in the figure) and a plurality of chips 13 (only one number is shown in the figure). Here, the substrate 11 can be a printed circuit board (PCB); the bonding structure 12 can be a bump or a hybrid bonding structure; the plurality of chips 13 can include chips with different functions, such as a logic chip (Logic Die) and a dynamic random access memory chip (Dynamic Random Access Memory Die; DRAM Die, DRAM chip for short).

[0069] In the packaging structure 10, the heat sources of multiple high-performance chips can be separated in the X direction or the Y direction, but in the Z direction, there is a problem of heat source concentration, which creates more unfavorable factors for the subsequent chip thermal effect. Among them, the chip thermal effect refers to the effect caused by the heat generated during the working process. Therefore, when multiple chips 13 with different functions are co-packaged and stacked, they are misaligned in the Z direction to effectively achieve heat dissipation.

[0070] See also Figure 2 , which shows a schematic diagram of the composition structure of a packaging structure Figure 2 , specifically a schematic diagram of the composition structure of a three-dimensional (3D) packaging structure. Figure 2 As shown, the package structure 20 includes an interposer 21, a logic chip 22, and two stacked chipsets 23 (only one number is shown in the figure). The interposer 21 includes a conductive pillar (e.g., a copper pillar) 211; the stacked chipset 23 may include at least one DRAM chip, and illustratively, the stacked chipset 23 includes four DRAM chips stacked in sequence.

[0071] Here, the packaging structure 20 adopts an interposer process.

[0072] It should be noted that the logic chip 22 and the stacked chipset 23 are at the same height in the first direction (the direction of chip stacking, i.e. the aforementioned Z direction), specifically, the bottom surface of the stacked chipset 23 (i.e. the bottom surface of the bottom DRAM chip) and the bottom surface of the logic chip 22 are located in the same plane. The main heat source of the chip is located on the bottom surface of the chip, so there is a risk of heat concentration in the package structure 20, resulting in poor heat dissipation effect of the package structure 20.

[0073] Based on this, the present disclosure provides a packaging structure, which includes stacked: a reorganization structure, a first redistribution layer and at least one stacked chipset, at least one stacked chipset is electrically connected to the first redistribution layer; the reorganization structure includes a first chip and a plurality of conductive pillars, the bottom surface of the stacked chipset and the bottom surface of the first chip are located in different planes; the first redistribution layer is electrically connected to the plurality of conductive pillars; the packaging structure also includes a heat dissipation structure, the heat dissipation structure is adjacent to the stacked chipset and / or the first chip. In this way, the bottom surface of the stacked chipset and the bottom surface of the first chip are misaligned in the first direction, which can avoid the risk of heat concentration. In addition, the heat dissipation performance can be improved and the cost can be reduced by dissipating the heat of the stacked chipset and the first chip through the heat dissipation structure.

[0074] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0075] In one embodiment of the present disclosure, see Figure 3 , which shows a schematic diagram of the composition structure of a packaging structure provided by an embodiment of the present disclosure Figure 1 .like Figure 3 As shown, the package structure 30 may include a reorganization structure 31, a first redistribution layer 32 and at least one stacked chipset 33 stacked in sequence along a first direction, and at least one stacked chipset 33 is electrically connected to the first redistribution layer 32; the reorganization structure 31 includes a first chip 311 and a plurality of conductive pillars 312 (only one number is shown in the figure), and the bottom surface of the stacked chipset 33 and the bottom surface of the first chip 311 are located in different planes; the first redistribution layer 32 is electrically connected to the plurality of conductive pillars 312;

[0076] The package structure 30 may further include a heat dissipation structure 34 , which is adjacent to the stacked chipset 33 and / or the first chip 311 .

[0077] The present disclosure provides a packaging structure 30, specifically a three-dimensional system-in-package (SIP) stacking structure. The packaging structure 30 can form a high bandwidth memory (HBM), which stacks multiple memory devices together in three dimensions to achieve a large-capacity, high-bandwidth storage array.

[0078] It should be noted that the first direction (i.e., the aforementioned Z direction) is the direction of chip stacking in the package structure 30. On the surface (top surface or bottom surface) of the semiconductor chip (e.g., the first chip 311), two mutually perpendicular directions are defined, namely, the second direction (i.e., the aforementioned X direction) and the third direction (i.e., the aforementioned Y direction), and the second direction is perpendicular to one edge of the semiconductor chip, and the third direction is perpendicular to the other edge of the semiconductor chip. In addition, the semiconductor chip may include a top surface at the front side and a bottom surface at the back side opposite to the front side.

[0079] It should also be noted that the number and position of the stacked chipset 33 are not specifically limited. There may be only one stacked chipset 33, or there may be two or more stacked chipsets 33, as long as the bottom surface of the stacked chipset 33 and the bottom surface of the first chip 311 are not located in the same plane. Along the second direction, the stacked chipset 33 may be completely misaligned with the first chip 311, or partially misaligned, or completely overlapped without misalignment (i.e., the projection of the stacked chipset 33 along the first direction completely overlaps the projection of the first chip 311 along the first direction). By way of example, the specific implementation of the embodiment of the present disclosure is described in detail by taking the example that the packaging structure 30 includes two stacked chipsets 33 located on both sides of the first chip 311, and the stacked chipset 33 is completely misaligned with the first chip 311 along the second direction.

[0080] Here, the positional relationship between the first chip 311 and the stacked chipset 33 can also be referred to Figure 4 Understand. Figure 2 In the related art shown, the bottom surface of the stacked chipset 33 and the bottom surface of the first chip 311 are not located in the same plane, and the first chip 311 and the stacked chipset 33 are not at the same height in the first direction.

[0081] It should also be noted that the number and position of the conductive pillars 312 are not specifically limited, and the plurality of conductive pillars 312 can be located on one side or both sides of the first chip 311. When the package structure 30 includes a stacked chipset 33 located on either side of the first chip 311, the plurality of conductive pillars 312 can be located on the same side or both sides of the stacked chipset 33; when the package structure 30 includes two stacked chipsets 33 located on the same side of the first chip 311, the plurality of conductive pillars 312 can be located on the same side or both sides of the stacked chipset 33; when the package structure 30 includes two stacked chipsets 33 located on both sides of the first chip 311, the plurality of conductive pillars 312 can be located on both sides of the first chip 311. The stacked chipset 33 needs to be electrically connected to the plurality of conductive pillars 312 through the first redistribution layer 32. By way of example, the specific implementation of the embodiment of the present disclosure is described in detail by taking the package structure 30 including 13 conductive pillars 312 located on both sides of the first chip 311 as an example.

[0082] It should also be noted that the conductive pillar 312 may be a copper pillar, but this is not specifically limited.

[0083] like Figure 3 As shown, the reorganization structure 31 may also include a dielectric layer 313, and the material of the dielectric layer 313 may be a packaging material, silicon dioxide (SiO2) or ABF (Ajinomoto Build-up Film) material, which is not specifically limited. Among them, ABF material (Ajinomoto Build-up Film) is mainly used in semiconductor packaging and printed circuit board manufacturing. The packaging structure 30 may also include a first oxide layer (Oxide, OX) u1, and the first redistribution layer 32 is formed in the first oxide layer u1.

[0084] In this embodiment, the first chip 311 may be a logic chip, which is a storage and computing chip and generates heat during operation. Figure 5 As shown, the first chip 311 may include a silicon material a1, a dielectric layer a2 and a circuit a3.

[0085] In this embodiment, the main heat source of the chip is located on the bottom surface of the chip. The bottom surface of the stacked chipset 33 and the bottom surface of the first chip 311 are located in different planes and are staggered in the first direction, so that the heat sources of the chips can be staggered to avoid the risk of heat concentration. In addition, the heat dissipation structure 34 is located adjacent to the stacked chipset 33 and / or the first chip 311, so that the heat dissipation of the stacked chipset 33 and the first chip 311 can be better performed.

[0086] In some embodiments, Figure 3 As shown, the stacked chipset 33 may include at least one layer of second chips 331 , and the bottom surface of the stacked chipset 33 is the bottom surface of the second chips 331 at the bottom layer.

[0087] In this embodiment, the number of layers of the second chip 331 is not specifically limited and can be set according to actual conditions. When the package structure 30 includes multiple layers of second chips 331, the multiple layers of second chips 331 are stacked and electrically connected to each other. Exemplarily, the stacked chip group 33 in this embodiment each includes 4 layers of second chips 331.

[0088] It should be noted that the second chip 331 may be a storage chip, such as a DRAM chip. The DRAM chip is also a storage and computing chip, which will also generate heat during operation.

[0089] In some embodiments, Figure 3 As shown, the heat dissipation structure 34 may include at least one microfluidic chip 341, and the at least one microfluidic chip 341 includes a plurality of flow channels b1, an input port b2, and an output port b3;

[0090] The heat dissipating liquid enters the plurality of flow channels b1 from the input port b2 and is discharged from the output port b3 after passing through the plurality of flow channels b1.

[0091] Exemplarily, the heat dissipation structure 34 includes two microfluidic chips 341 . Part of the flow channels b1 in the two microfluidic chips 341 are connected to each other, so that the two microfluidic chips 341 are connected to each other.

[0092] Specifically, in some embodiments, Figure 3 As shown, the packaging structure 30 may include two stacked chip groups 33, the heat dissipation structure 34 is T-shaped, and the heat dissipation structure 34 includes a first microfluidic chip 341-1 and a second microfluidic chip 341-2 (not shown in the numbers) connected to each other;

[0093] The first microfluidic chip 341 - 1 is located in the middle of the two stacked chip groups 33 and above the first chip 311 ; the second microfluidic chip 341 - 2 is located above the two stacked chip groups 33 and the first microfluidic chip 341 - 1 .

[0094] It should be noted that the heat dissipation liquid can be an insulating low-boiling-point coolant such as water, mineral oil or fluorinated liquid, which is not specifically limited; the heat generated by the chip is quickly discharged through heat exchange by utilizing the high heat capacity and high thermal conductivity of the heat dissipation liquid. The cavity structure in the heat dissipation structure 34 is the flow channel b1 for subsequent heat dissipation of the heat dissipation liquid. Multiple flow channels b1 are used to transmit the heat dissipation liquid to dissipate heat from the first chip 311 and the second chip 331.

[0095] It should also be noted that the microfluidic chip 341 is not a storage and computing chip and hardly generates heat.

[0096] In some embodiments, Figure 6 As shown, the heat dissipation structure 34 may include only one microfluidic chip 341 , which is located between the two stacked chip groups 33 and above the first chip 311 .

[0097] In this embodiment, two stacked chip groups 33 and one first chip 311 form a concave structure, and the microfluidic chip 341 is inserted into the storage and computing chip.

[0098] Understandably, in Figure 6 On the basis of the formed SIP chip, a microfluidic chip 341 is packaged, that is, the heat dissipation structure includes two microfluidic chips 341 (a first microfluidic chip 341-1 and a second microfluidic chip 341-2), so as to form Figure 3 The heat dissipation structure 34 and the packaging structure 30 shown can achieve better heat dissipation.

[0099] In some embodiments, according to actual conditions, Figure 3 The microfluidic chip 341 is packaged on top of the second microfluidic chip 341-2, and no specific limitation is given to this.

[0100] In some embodiments, Figure 3 or Figure 6 As shown, the package structure 30 may further include a second redistribution layer 35 , and the second redistribution layer 35 is electrically connected to the plurality of conductive pillars 312 ;

[0101] The first redistribution layer 32 and the second redistribution layer 35 are respectively located on the first surface and the second surface of the reorganization structure 31 , and the first surface of the reorganization structure 31 is opposite to the second surface of the reorganization structure 31 .

[0102] It can be understood that the first surface of the reorganization structure 31 faces upward, and the second surface of the reorganization structure 31 faces downward.

[0103] like Figure 3 or Figure 6 As shown, the package structure 30 may further include a second oxide layer u2 , and the second redistribution layer 35 is formed in the second oxide layer u2 .

[0104] It should be noted that in the packaging structure 30, the shape and number of layers of each redistribution layer (RDL), that is, the first redistribution layer 32 and the second redistribution layer 35 are not limited, and each redistribution layer can include 1 layer, 3 layers, 5 layers and other different layers according to actual needs; when each redistribution layer includes multiple layers, the structure of each layer can be the same or different, and there is no specific limitation on this. Exemplarily, taking each redistribution layer including 1 layer as an example, the specific implementation of the embodiment of the present disclosure is described in detail. In addition, each redistribution layer plays the role of electrical extension and interconnection of the XY plane (i.e., the plane composed of the second direction and the third direction).

[0105] In some embodiments, Figure 3 or Figure 6 As shown, the package structure 30 may further include a plurality of first bonding structures 36 and a plurality of second bonding structures 37 (only one number is shown in the figure);

[0106] A plurality of first bonding structures 36 are close to the first surface of the reorganization structure 31 , and at least one stacked chip group 33 is electrically connected to the first redistribution layer 32 through the plurality of first bonding structures 36 ;

[0107] The plurality of second bonding structures 37 are close to the second surface of the reorganization structure 31 and are electrically connected to the second redistribution layer 35 .

[0108] It should be noted that the first bonding structure 36 and the second bonding structure 37 can be a bump or a hybrid bonding structure, and there is no specific limitation on this. In other words, multiple first bonding structures 36 can be bonded to the first redistribution layer 32, and multiple second bonding structures 37 can be bonded to the second redistribution layer 35 by any bonding technology, and there is no specific limitation on this. Exemplarily, hybrid bonding technology or fusion bonding technology can be used. Among them, hybrid bonding technology is a method that combines physical bonding and chemical bonding, which can make different types of bonding materials form bonds. This bonding method can overcome the limitations of a single bonding method, while greatly reducing the bonding spacing and improving the bonding density. Melt bonding technology can combine polished semiconductor wafers together without the use of adhesives. Currently, hydrophilic melt bonding schemes are mostly used. After the clean polished wafers are hydrophilically cleaned, a hydrophilic surface with a high hydroxyl (-OH) density is formed. Water molecules in the atmospheric environment are easily adsorbed on the hydrophilic surface. Then, at room temperature, the two wafers with hydrophilic surfaces are bonded together. During the high-temperature annealing process, the weak intermolecular forces (van der Waals forces and hydrogen bonds) between the interfaces will be converted into stronger Si-O-Si covalent bonds, thereby obtaining a strong bonding interface.

[0109] In some embodiments, Figure 3 or Figure 6 As shown, the package structure 30 may further include a package material 38 , and the package material 38 is filled in the gaps of the package structure 30 .

[0110] It should be noted that the packaging material 38 can be plastic, but there is no specific limitation to this.

[0111] The disclosed embodiment provides a packaging structure 30, in which the DRAM chip (second chip 331) and the logic chip (first chip 311) are staggered in the Z direction (first direction), which can avoid the problem of excessive heat concentration; and the microfluidic chip 341 can be inserted into the storage chip, which has better heat dissipation performance in the Z direction. In other words, the packaging structure 30 can solve the problem of poor heat dissipation effect of high-performance storage chips when the stack height is thick, so that different chips can not only achieve good staggering in the X direction (second direction) or the Y direction (third direction), but also achieve effective staggering in the Z direction to avoid the risk of heat concentration.

[0112] In another embodiment of the present disclosure, see Figure 7 , which shows a schematic flow chart of a method for preparing a packaging structure provided by an embodiment of the present disclosure. Figure 7 As shown, the method may include:

[0113] S401, providing a carrier chip, and forming a recombinant structure above the carrier chip.

[0114] The reorganization structure 31 includes a first chip 311 and a plurality of conductive pillars 312 .

[0115] It should be noted that the preparation method provided in the embodiment of the present disclosure is applied to prepare the aforementioned packaging structure 30 .

[0116] See also Figure 8 , which shows a schematic diagram of a preparation process of a packaging structure provided by an embodiment of the present disclosure Figure 1 .like Figure 8 As shown, when preparing the transfer plate structure 30 , a carrier chip 51 is first provided, and a reconstructed structure 31 is formed above the carrier chip 51 .

[0117] It should be noted that the carrier chip can also be called a carrier chip. Among them, the carrier chip is an indispensable component in the manufacture of semiconductor chips, which is mainly used to support and transmit the signal and energy of the chip. The carrier chip can be made of materials such as silicon carbide and aluminum nitride.

[0118] It should also be noted that the carrier chip 51 has a temporary bonding adhesive layer 52 and a debonding layer 53 to bond the reconstructed structure 31 and the carrier chip 51 to each other. The debonding layer 53 may include a temporary bonding adhesive and a release layer.

[0119] In this embodiment, different processes may be used to form the reconstructed structure 31 on the carrier chip 51 .

[0120] In one possibility, forming a recombinant structure on a carrier chip includes:

[0121] Placing at least one channel chip and a first chip above the carrier chip; at least one channel chip includes a plurality of conductive pillars;

[0122] forming a first dielectric layer, the first dielectric layer covering at least one channel chip and an exposed surface of the first chip;

[0123] Parts of the first dielectric layer and at least one channel chip are removed to expose a plurality of conductive pillars.

[0124] like Fig. 9 As shown, firstly, the first chip 311 and at least one channel chip 54 are reassembled onto a carrier chip 51 having a temporary bonding glue layer 52 and a debonding layer 53 .

[0125] It should be noted that the channel chip may also be referred to as a dummy channel die, which is a chip including conductive pillars 312. Exemplarily, two channel chips 54 are placed on both sides of the first chip 311, and each channel chip 54 includes 13 conductive pillars 312.

[0126] It should also be noted that the manufacturing process of the channel chip 54 is the common silicon interposer process in the related art, and the channel chip 54 has a conduction function, that is, electrically connecting the subsequently placed stacked chip group 33 with the first chip 311.

[0127] In addition, the channel chip 54 includes a conductive column 312, but other structures are not specifically limited. Fig. 9 As shown, the channel chip 54 may further include a substrate 541, and the substrate 541 may be silicon-based. In addition, the channel chip 54 is not a storage and computing chip and hardly generates heat.

[0128] It should also be noted that a through silicon via (TSV) technology can be used to form a conductive structure (i.e., a conductive column 312); wherein the TSV technology is a technology for interconnecting chips by making a vertical conductive structure between chips and between wafers. Specifically, etching can be performed in the substrate 541 to form a plurality of deep holes, and after forming the plurality of deep holes, a conductive material is filled in the deep holes to form a plurality of conductive columns 312. The conductive material may include copper, tungsten, polysilicon, etc., which is not specifically limited; illustratively, the conductive column 312 is a copper column. The process of filling the conductive material may include a deposition process, such as an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, etc., or may also include an electroplating process, which is not specifically limited in the embodiments of the present disclosure.

[0129] like Fig.10 As shown, after placing at least one channel chip 54 and the first chip 311 above the carrier chip 51 , a first dielectric layer 55 is filled on the exposed surfaces of the at least one channel chip 54 and the first chip 311 .

[0130] It should be noted that the first dielectric layer 55 may be formed by a CVD process, but this is not specifically limited.

[0131] It should also be noted that the material of the first dielectric layer 55 can be a packaging material, silicon dioxide or ABF material, which is not specifically limited.

[0132] like Fig.11 As shown, after forming the first dielectric layer 55 , a portion of the first dielectric layer 55 and a portion of each channel chip 54 are removed to expose the plurality of conductive pillars 312 .

[0133] It should be noted that before placing at least one channel chip 54 on the carrier chip 51 , the channel chip 54 has been thinned, and the conductive pillars 312 are exposed or nearly exposed.

[0134] It should also be noted that a variety of processes can be used to expose the conductive pillars 312 in the channel chip 54. For example, a chemical mechanical polish (CMP) process and an etching process are used. Among them, etching can be a dry etching process or a wet etching process. The gas used for dry etching can be one or any combination of trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2) or sulfur hexafluoride (SF6). Wet etching can be carried out using strong acids such as concentrated sulfuric acid, hydrofluoric acid, and concentrated nitric acid.

[0135] It should also be noted that when multiple processes are used to expose the conductive pillars 312, attention must be paid to the height of the first chip 311 and the appropriate selection ratio of various processes to ensure that while the conductive pillars 312 are exposed, the entire plane of the reconstructed structure 31 is flat and the performance of the first chip 311 is not damaged.

[0136] In another possibility, forming a recombinant structure on a carrier chip includes:

[0137] placing a first chip above the carrier chip;

[0138] Placing a plurality of conductive pillars on at least one side of the first chip;

[0139] forming a second dielectric layer, wherein the second dielectric layer covers the plurality of conductive pillars and the exposed surface of the first chip;

[0140] A portion of the second dielectric layer is removed to expose the plurality of conductive pillars.

[0141] like Fig.12 As shown, the fan-out process is used to place (also referred to as mounting) the first chip 311 on a carrier chip 51 having a temporary bonding layer 52 and a debonding layer 53; and a packaging method is used to place a plurality of conductive pillars 312 on the carrier chip 51. Exemplarily, 13 conductive pillars 312 are placed on both sides of the first chip 311.

[0142] It should be noted that after the first chip 311 and the plurality of conductive pillars 312 are placed above the carrier chip 51 , the second dielectric layer 56 is filled on the exposed surfaces of the plurality of conductive pillars 312 and the first chip 311 .

[0143] like Fig.13As shown, after forming the second dielectric layer 56 , a portion of the second dielectric layer 56 is removed to expose the plurality of conductive pillars 312 and to make the entire surface of the reconstructed structure 31 flat without damaging the performance of the first chip 311 .

[0144] It should also be noted that the process and material for forming the second dielectric layer 56 can be consistent with the process and material for forming the first dielectric layer 55, and the process for removing the second dielectric layer 56 can also be consistent with the process for removing the first dielectric layer 55. Please refer to the process steps of other embodiments for understanding, which will not be repeated here. Here, the first dielectric layer 55 or the second dielectric layer 56 is the aforementioned dielectric layer 313.

[0145] Exemplarily, the specific implementation of the embodiment of the present disclosure is described in detail by taking the example that the recombinant structure 31 includes at least one channel chip 54 and a first chip 311 , and the channel chip 54 includes a plurality of conductive pillars 312 .

[0146] S402 , forming a first redistribution layer electrically connected to the plurality of conductive pillars above the reorganization structure.

[0147] like Fig.14 As shown, after the reorganization structure 31 is formed, a first redistribution layer 32 is formed on the reorganization structure 31, and the first redistribution layer 32 is electrically connected to the plurality of conductive pillars 312; that is, an RDL process is performed on the reorganization structure 31 to facilitate subsequent lead-out. In addition, the size of the conductive pillar 312 can be set to match the lead-out process, for example, the size of the conductive pillar 312 can be set larger so that the first redistribution layer 32 is electrically connected to the plurality of conductive pillars 312.

[0148] It should be noted that the material of the first redistribution layer 32 can be the same as the conductive material of the conductive pillar 312, and illustratively, both are copper. In addition, the first redistribution layer 32 can be formed by a damascene process.

[0149] It should also be noted that the first oxide layer u1 may be formed by a CVD process first, and then the first redistribution layer 32 may be formed by processes such as photolithography, etching, filling, and CMP.

[0150] S403, placing at least one stacked chipset on the first redistribution layer, and electrically connecting the at least one stacked chipset to the first redistribution layer.

[0151] The bottom surface of the stacked chipset and the bottom surface of the first chip are located in different planes.

[0152] like Fig.15 As shown, after the first redistribution layer 32 is formed, at least one stacked chip group 33 is placed above the first redistribution layer 32 , and the at least one stacked chip group 33 is electrically connected to the first redistribution layer 32 .

[0153] It should be noted that the number and position of the stacked chipset 33 are not specifically limited. There may be only one stacked chipset 33, or there may be two or more stacked chipsets 33, as long as the bottom surface of the stacked chipset 33 and the bottom surface of the first chip 311 are not located in the same plane. Along the second direction, the stacked chipset 33 may be completely misaligned with the first chip 311, or partially misaligned, or completely overlapped without misalignment. Exemplarily, the specific implementation of the embodiment of the present disclosure is described in detail by taking the example that the package structure 30 includes two stacked chipsets 33 located on both sides of the first chip 311, and along the second direction, the stacked chipset 33 is completely misaligned with the first chip 311.

[0154] It should also be noted that the stacked chipset 33 may include at least one layer of second chips 331, and the bottom surface of the stacked chipset 33 is the bottom surface of the bottom second chip 331. By way of example, the stacked chipset 33 in this embodiment includes four layers of second chips 331 each.

[0155] S404, placing a heat dissipation structure adjacent to the stacked chipset and / or the first chip.

[0156] like Fig.15 As shown, after placing at least one stacked chipset 33 above the first redistribution layer 32 , a heat dissipation structure 34 is placed adjacent to the stacked chipset 33 and / or the first chip 311 . The heat dissipation structure 34 may include at least one microfluidic chip 341 .

[0157] For example, considering good heat dissipation performance, a microfluidic chip 341 is placed above the first chip 311 and in the middle of the two stacked chip groups 33. The process can be implemented using the common micro-electro-mechanical system (MEMS) process or wafer on wafer (WoW) stacking process in the relevant technology, and the embodiments of the present disclosure are not described in detail here.

[0158] In some embodiments, electrically connecting at least one stacked chipset to a first redistribution layer includes:

[0159] A plurality of first bonding structures are formed above the first redistribution layer, and at least one stacked chip group is electrically connected to the plurality of first bonding structures.

[0160] like Fig.15 As shown, a plurality of first bonding structures 36 are formed above the first redistribution layer 32 , ie, close to the first surface of the reorganization structure 31 , and at least one stacked chip group 33 is electrically connected to the first redistribution layer 32 via the plurality of first bonding structures 36 .

[0161] In some embodiments, Fig.16 As shown, after placing the heat dissipation structure 34, the obtained structure is packaged, that is, the packaging material 38 is filled in the gaps of the obtained structure.

[0162] In some embodiments, forming a recombinant structure on a carrier chip includes:

[0163] Providing a recombinant structure, and performing bonding processing on the recombinant structure and the carrier chip;

[0164] The first redistribution layer is located on the first surface of the reorganization structure, and the method further comprises:

[0165] Debonding the recombinant structure and the carrier chip;

[0166] A second redistribution layer electrically connected to a plurality of conductive pillars is formed on the second surface of the reorganization structure; the first surface of the reorganization structure is opposite to the second surface of the reorganization structure.

[0167] Specifically, the reconstructed structure 31 and the carrier chip 51 are bonded via a temporary bonding adhesive layer 52 and a debonding layer 53. Fig.17 As shown, the reconstructed structure 31 and the carrier chip 51 are subjected to a debonding process.

[0168] It should be noted that after the carrier chip 51 and the reconstructed structure 31 are debonded, the reconstructed structure 31 is turned upside down with the second surface facing upwards for front processing. After the front processing, the reconstructed structure 31 is turned back.

[0169] like Figure 6 As shown, a second redistribution layer 35 is formed on the second surface of the reorganization structure 31, and the second redistribution layer 35 is electrically connected to the plurality of conductive pillars 312. The second redistribution layer 35 can be electrically connected to the circuit a3 in the first chip 311.

[0170] It should be noted that the material of the second redistribution layer 35 can be the same as the conductive material of the conductive pillar 312, and illustratively, both are copper. In addition, the second redistribution layer 35 can be formed by a damascene process.

[0171] It should also be noted that the second oxide layer u2 can be first formed by a CVD process, and then the second redistribution layer 35 can be formed by processes such as photolithography, etching, filling, and CMP.

[0172] In some embodiments, the method further comprises:

[0173] A plurality of second bonding structures are formed, and the second redistribution layer is electrically connected to the plurality of second bonding structures.

[0174] like Figure 6As shown, a plurality of second bonding structures 37 are formed on the second surface close to the reorganization structure 31 , and the plurality of second bonding structures 37 are electrically connected to the second redistribution layer 35 .

[0175] It should be noted that after the reorganization structure 31 is turned upside down, a second redistribution layer 35 is formed on the second surface of the reorganization structure 31 , and a plurality of second bonding structures 37 are formed above the second redistribution layer 35 .

[0176] It should also be noted that the plurality of first bonding structures 36 and the plurality of second bonding structures 37 may be formed by using a bump process, a hybrid bonding process, etc., and no specific limitation is made to this.

[0177] In some embodiments, the heat dissipation structure includes at least one microfluidic chip, and the at least one microfluidic chip includes a plurality of flow channels. The method may further include:

[0178] An input port and an output port are formed on at least one microfluidic chip; the heat dissipation liquid enters into the multiple flow channels from the input port, and is discharged from the output port after passing through the multiple flow channels.

[0179] like Figure 6 As shown, the heat dissipation structure 34 includes a microfluidic chip 341, and the microfluidic chip 341 includes multiple flow channels b1. Laser and other methods can be used to form an input port b2 and an output port b3 on the microfluidic chip 341 to realize flow channel grooving and then pass heat dissipation liquid into it to achieve heat dissipation.

[0180] exist Figure 6 In the figure, the package structure 30 includes a first chip 311 (logic chip), two stacked chipsets 33 formed by stacking DRAM chips, two channel chips 54 and a microfluidic chip 341. The package structure 30 adopts different combination processes to avoid the logic chip and the DRAM chip in the Z direction to achieve staggered heat sources. At the same time, different process methods are adopted, which reduces a lot of costs compared with the interposer process of related technologies. In addition, in addition to the silicon in the channel chip 54 that can dissipate heat for the package structure 30, the heat dissipation structure 34 can also dissipate heat for the package structure 30. In other words, compared with the related technology, the heat dissipation performance of the package structure 30 is better.

[0181] In some embodiments, Figure 6 On the basis of the package structure 30 shown in FIG. 1 , a microfluidic chip (i.e., the second microfluidic chip 341 - 2) is packaged on the microfluidic chip 341 (i.e., the first microfluidic chip 341 - 1) to form Figure 3 The packaging structure 30 shown can achieve better heat dissipation.

[0182] In some embodiments, Figure 3On the basis of the packaging structure 30 shown, a microfluidic chip 341 may be packaged above the second microfluidic chip 341 - 2 .

[0183] It should be noted that the present embodiment is a wafer-level packaging process, that is, in the actual preparation process, a channel wafer and a logic wafer are placed on a carrier wafer (or a bearing wafer), and then a subsequent preparation process is performed (forming a first redistribution layer 32, placing at least one stacked chipset 33, placing a heat dissipation structure 34, etc.), and the wafer-level packaging structure finally obtained includes a plurality of identical packaging structures 30, which can be cut to obtain a plurality of packaging structures 30. In addition, the preparation method of each packaging structure 30 is the same, and the specific implementation of the disclosed embodiment is described in detail by taking the preparation method of one packaging structure 30 as an example.

[0184] The embodiment of the present disclosure provides a method for preparing a packaging structure 30. The packaging structure 30 prepared by the method can realize the staggered placement of the first chip 311 and the second chip 331 in the first direction to avoid the problem of excessive heat concentration; the microfluidic chip 341 enables the packaging structure 30 to have better heat dissipation performance in the first direction; and a silicon interposer can be used as a channel chip 54, and silicon grains can be used for fan-out, introducing the good heat dissipation performance of silicon, while the fan-out packaging of the related art uses an inorganic dielectric layer or an organic dielectric layer for fan-out, and its heat dissipation performance is poor. Compared with the related art, the present disclosure can improve the heat dissipation performance. In addition, compared with the interposer in the related art, the fan-out packaging process used by the packaging structure 30 can reduce costs.

[0185] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0186] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0187] The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0188] The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A packaging structure, characterized in that: The packaging structure comprises stacked: a reorganization structure, a first redistribution layer and at least one stacked chipset, wherein the at least one stacked chipset is electrically connected to the first redistribution layer; the reorganization structure comprises a first chip and a plurality of conductive pillars, wherein the bottom surface of the stacked chipset is located in a different plane from the bottom surface of the first chip; and the first redistribution layer is electrically connected to the plurality of conductive pillars; The packaging structure further includes a heat dissipation structure, and the heat dissipation structure is adjacent to the stacked chipset and / or the first chip.

2. The packaging structure according to claim 1, characterized in that: The stacked chipset includes at least one layer of second chips, and the bottom surface of the stacked chipset is the bottom surface of the second chip at the bottom layer.

3. The packaging structure according to claim 2, characterized in that: The heat dissipation structure includes at least one microfluidic chip, and the at least one microfluidic chip includes a plurality of flow channels, an input port, and an output port; The heat dissipation liquid enters the plurality of flow channels from the input port, passes through the plurality of flow channels, and is discharged from the output port.

4. The packaging structure according to claim 1, characterized in that: The packaging structure further includes a second redistribution layer, wherein the second redistribution layer is electrically connected to the plurality of conductive pillars; The first redistribution layer and the second redistribution layer are respectively located on a first surface and a second surface of the reorganization structure, and the first surface of the reorganization structure is opposite to the second surface of the reorganization structure.

5. The packaging structure according to claim 4, characterized in that: The packaging structure further includes a plurality of first bonding structures and a plurality of second bonding structures; The plurality of first bonding structures are close to the first surface of the reorganization structure, and the at least one stacked chipset is electrically connected to the first redistribution layer through the plurality of first bonding structures; The plurality of second bonding structures are close to the second surface of the reorganization structure and are electrically connected to the second redistribution layer.

6. The packaging structure according to claim 3, characterized in that: The packaging structure includes two stacked chip groups, the heat dissipation structure is T-shaped, and the heat dissipation structure includes a first microfluidic chip and a second microfluidic chip connected to each other; The first microfluidic chip is located between the two stacked chip groups and above the first chip; the second microfluidic chip is located above the two stacked chip groups and the first microfluidic chip.

7. The packaging structure according to claim 1, characterized in that: The packaging structure further includes a packaging material, and the packaging material is filled in the gap of the packaging structure.

8. A method for preparing a packaging structure, characterized in that: The method comprises: Providing a carrier chip, and forming a recombinant structure above the carrier chip; the recombinant structure includes a first chip and a plurality of conductive pillars; forming a first redistribution layer electrically connected to the plurality of conductive pillars above the reorganization structure; Placing at least one stacked chipset above the first redistribution layer, and electrically connecting the at least one stacked chipset to the first redistribution layer; a bottom surface of the stacked chipset and a bottom surface of the first chip are located in different planes; A heat dissipation structure is placed adjacent to the stacked chipset and / or the first chip.

9. The method according to claim 8, characterized in that The forming of a recombinant structure above the carrier chip comprises: Providing the recombinant structure, and performing bonding processing on the recombinant structure and the carrier chip; The first redistribution layer is located on a first surface of the reorganization structure, and the method further comprises: performing a debonding process on the recombinant structure and the carrier chip; A second redistribution layer electrically connected to the plurality of conductive pillars is formed on the second surface of the recombination structure; the first surface of the recombination structure is opposite to the second surface of the recombination structure.

10. The method according to claim 8, characterized in that The step of electrically connecting the at least one stacked chipset to the first redistribution layer comprises: A plurality of first bonding structures are formed above the first redistribution layer, and the at least one stacked chip group is electrically connected to the plurality of first bonding structures.

11. The method according to claim 9, characterized in that The method further comprises: A plurality of second bonding structures are formed, and the second redistribution layer is electrically connected to the plurality of second bonding structures.

12. The method according to claim 8, characterized in that The heat dissipation structure includes at least one microfluidic chip, and the at least one microfluidic chip includes a plurality of flow channels. The method further includes: An input port and an output port are formed on the at least one microfluidic chip; the heat dissipation liquid enters the plurality of flow channels from the input port, passes through the plurality of flow channels, and is discharged from the output port.

13. The method according to claim 8, characterized in that The forming of a recombinant structure above the carrier chip comprises: placing at least one channel chip and the first chip above the carrier chip; the at least one channel chip comprising the plurality of conductive pillars; forming a first dielectric layer, wherein the first dielectric layer covers the at least one channel chip and the exposed surface of the first chip; Parts of the first dielectric layer and the at least one channel chip are removed to expose the plurality of conductive pillars.

14. The method according to claim 8, characterized in that The forming of a recombinant structure above the carrier chip comprises: placing the first chip above the carrier chip; placing the plurality of conductive pillars on at least one side of the first chip; forming a second dielectric layer, wherein the second dielectric layer covers the plurality of conductive pillars and an exposed surface of the first chip; A portion of the second dielectric layer is removed to expose the plurality of conductive pillars.

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