Semiconductor device and preparation method thereof
By forming an oxide layer on the side wall of the redistribution layer (RDL) of the semiconductor device and depositing a passivation layer thereon, the pore and crack problems caused by stress migration are solved, and the thermal cycle reliability and electrical contact stability of the semiconductor device are improved.
Patent Information
- Application Number
- CN202411394303.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-21
- Filing Date
- 2024-10-08
- Publication Date
- 2025-03-25
AI Technical Summary
In semiconductor manufacturing processes, as the size of semiconductor devices decreases, stress migration becomes more serious, resulting in pores and cracks in the conductors, reducing the efficiency of the integrated circuit.
An oxide layer of metal material is formed on the side walls of the redistribution layer (RDL), and a passivation layer is deposited thereon, forming an oxide layer between the RDL and the passivation layer to improve the interface adhesion between the RDL and the passivation layer and prevent the formation of pores and cracks.
By forming an oxide layer on the side walls of the RDL, pores and cracks caused by stress migration are reduced, thermal cycling reliability and electrical contact stability of the semiconductor device are improved, and the service life of the device is extended.
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Figure CN119695025A_ABST
Abstract
Description
Technical Field
[0001] Some embodiments of the present disclosure provide semiconductor devices and methods for making the same. Background Art
[0002] The electronics industry has experienced an increasing demand for smaller and faster electronic devices that are capable of simultaneously supporting more and more complex and sophisticated functions. Therefore, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking semiconductor IC dimensions (e.g., minimum feature size) and thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies. Summary of the invention
[0003] Some embodiments of the present disclosure provide a semiconductor device, including a redistribution layer, a passivation layer, and an oxide layer of a metal material. The redistribution layer includes a metal material, and the metal material is formed above a substrate. The passivation layer is formed above the redistribution layer. The oxide layer of the metal material is formed on a plurality of sidewalls of the redistribution layer between the redistribution layer and the passivation layer.
[0004] Some embodiments of the present disclosure provide a method for preparing a semiconductor device, including forming a redistribution layer including a metal material above a substrate; forming an oxide layer of the metal material on multiple sidewalls of the redistribution layer; and depositing a passivation layer above the redistribution layer and the oxide layer, wherein the oxide layer is formed between the redistribution layer and the passivation layer.
[0005] Some embodiments of the present disclosure provide a method for preparing a semiconductor device, including: forming a redistribution layer including aluminum-copper over a substrate; oxidizing multiple sidewalls of the redistribution layer to form an aluminum oxide layer on these sidewalls of the redistribution layer; depositing a passivation layer over the redistribution layer and the aluminum oxide layer, wherein the aluminum oxide layer is formed between the redistribution layer and the passivation layer; and performing a hydrogen plasma annealing process without hydrogen-induced porosity in multiple top corners or multiple bottom corners of the redistribution layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] When read in conjunction with the accompanying drawings, aspects of some embodiments of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.
[0007] Figure 1is a cross-sectional view of a section of an example semiconductor device at one stage of an integrated circuit fabrication process according to an embodiment;
[0008] Figure 2 According to one embodiment, Figure 1 A cross-sectional view of a section of an example semiconductor device around a boundary between a redistribution layer (RDL) and a passivation layer at the same stage in the integrated circuit fabrication process depicted in FIG.
[0009] Figure 3 is a top view of an example RDL showing an oxide layer not formed on the sidewalls of the RDL;
[0010] Figure 4 is a perspective view of an RDL region showing apertures formed in the top corners of the RDL;
[0011] Figure 5 is a top view illustrating an example RDL having an oxide layer formed on the sidewalls of the RDL according to some embodiments;
[0012] Figure 6 A process flow diagram depicting an example method of semiconductor fabrication including forming an oxide layer between an RDL and a passivation layer according to some embodiments;
[0013] 7A to 7F Schematic diagrams showing semiconductor structures at various stages of manufacture according to some embodiments;
[0014] Figure 8 To illustrate the interface between the RDL and the passivation layer having aluminum oxide (Al x O y ) schematic diagram of an aluminum-copper (AlCu) RDL at an interface;
[0015] Fig. 9 To illustrate the surrounding Al according to some embodiments x O y Example EDS line scan results of an interface.
[0016]
Explanation of symbols
[0017] 100:Semiconductor device
[0018] 102: Redistribution Layer / RDL
[0019] 104: Pattern film
[0020] 106: passivation layer
[0021] 108: Etch stop layer / ESL
[0022] 110: Gap filling layer
[0023] 112: Oxide layer
[0024] 114: Segment
[0025] 302: Redistribution Layer / RDL
[0026] 304: Porosity
[0027] 306: Area
[0028] 502: Redistribution Layer / RDL
[0029] 600: Method
[0030] 602: Block
[0031] 604: Block
[0032] 606: Block
[0033] 608: Block
[0034] 610: Block
[0035] 612: Block
[0036] 614: Block
[0037] 616: Block
[0038] 618: Block
[0039] 620: Block
[0040] 702: Redistribution Layer / RDL
[0041] 704: Patterned film
[0042] 706: Oxide layer
[0043] 708: passivation layer
[0044] 710: Etching stop layer / ESL
[0045] 712: Gap filling layer
[0046] 802: Redistribution Layer / RDL
[0047] 804:Al x O y interface
[0048] 806: passivation layer
[0049] 902: Energy Dispersive X-ray Scanning / EDS Line Scanning DETAILED DESCRIPTION
[0050] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The specific examples of the components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.
[0051] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, elements, regions, layers, parts, and / or sections, these components, elements, regions, layers, parts, and / or sections should not be limited by these terms. These terms are only used to distinguish one component, element, region, layer, part, or section from another region, layer, or section. Therefore, without departing from the teachings of some embodiments of the present disclosure, the first component, element, region, layer, part, or section discussed below may be referred to as a second component, element, region, layer, part, or section.
[0052] For the sake of brevity, conventional techniques related to conventional semiconductor device manufacturing may not be described in detail herein. In addition, the various tasks and processes described herein may be incorporated into a more comprehensive program or process with additional functionality not described in detail herein. In particular, various processes in the manufacture of semiconductor devices are well known, and therefore, for the sake of brevity, many conventional processes will only be briefly mentioned here or will be omitted entirely without providing well-known process details. As will be apparent to those skilled in the art after a thorough reading of this disclosure, the structures disclosed herein can be used with various technologies and can be incorporated into various semiconductor devices and products. In addition, it should be noted that semiconductor device structures include different numbers of elements, and a single element shown in the figure can represent multiple elements.
[0053] In addition, for ease of description, spatially relative terms such as "above," "overlying," "on," "upper," "top," "below," "underlying," "under," "lower," "bottom," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. When spatially relative terms such as those listed above are used to describe a first component relative to a second component, the first component may be directly on the other component, or there may be intervening components or layers. When a component or layer is referred to as being "on" another component or layer, it is directly on and in contact with the other component or layer.
[0054] It should be noted that references in this specification to "one embodiment," "an embodiment," "an example embodiment," "illustrative," "example," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment does not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.
[0055] In certain embodiments herein, a "material layer" is a layer comprising at least 50 weight percent (wt%) of the identified material, such as at least 60 weight percent of the identified material, at least 75 weight percent of the identified material, at least 90 weight percent of the identified material, at least 95 weight percent of the identified material, or at least 99 weight percent of the identified material; and as a layer of "material" comprising at least 50 weight percent of the identified material, such as at least 60 weight percent of the identified material, at least 75 weight percent of the identified material, at least 90 weight percent of the identified material, at least 95 weight percent of the identified material, or at least 99 weight percent of the identified material. For example, in certain embodiments, each of the aluminum layer and the layer of aluminum is a layer of at least 50 weight percent, at least 60 weight percent, at least 75 weight percent, at least 90 weight percent, at least 95 weight percent, or at least 99 weight percent of aluminum.
[0056] Some embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein like reference numerals are generally used throughout to refer to like parts. In the following description, for purposes of explanation, in order to provide a comprehensive understanding of the claimed subject matter, many specific details are set forth. However, it is apparent that the claimed subject matter may be practiced without these specific details. In other cases, structures and devices are depicted in block diagram form to facilitate description of the claimed subject matter.
[0057] Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated for different embodiments. Additional features may be added to the semiconductor device structure. Some of the stages described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.
[0058] As used herein, a "layer" is a region, such as a zone, including any boundaries, and not necessarily including a uniform thickness. For example, a layer may be a region that includes at least some thickness variation.
[0059] Stress migration (SM) is a phenomenon that can occur in integrated circuits (ICs). SM can cause voids and / or cracks to form in conductors, which can reduce the performance of the IC. For example, with SM, voids can form due to vacancy migration and hydrostatic stress gradients. Voids or cracks in conductors can cause open circuits or increased resistance, which can hamper the performance of the IC.
[0060] When various materials with different thermal expansion coefficients are formed in an interconnect structure, SM may occur due to the stress formed between the different materials. Various thermal treatments during semiconductor processing, such as high pressure annealing, may cause plastic deformation vacancies (e.g., small pores) or cracks to form in the interconnect structure. These small pores can be driven by stress migration due to hydrostatic stress gradients to gather in high stress gradient areas in the interconnect structure, thereby nucleating or forming large pores. Large pores may reduce or eliminate electrical contact between metal layers. Therefore, SM may cause reduced electrical contact between conductive materials, resulting in increased resistivity, and may cause device failure.
[0061] As semiconductor device geometries continue to shrink, SM reliability issues may become more severe. The SM effect may be minimized, thereby forming an oxide layer at the interface between the RDL (e.g., AlCu RDL) and the overlying passivation layer. Forming an oxide layer on the sidewalls of the RDL may further improve film adhesion and provide pad well protection by preventing void formation due to SM. Embodiments of semiconductor structures and methods for forming semiconductor structures with oxide layers on the sidewalls of the RDL are provided herein.
[0062] Figure 1 1 is a cross-sectional view of a section of an example semiconductor device 100 at a stage of an integrated circuit manufacturing process according to an embodiment. Sections of a redistribution layer (RDL) 102 including a metal material and formed over a substrate (not shown), a pattern film 104 over a top surface of the RDL 102, a passivation layer 106 over the pattern film 104 and the top surface of the RDL 102, an etch stop layer (ESL) 108 over the passivation layer 106, and a gap fill layer 110 over the ESL 108 are shown. The example semiconductor section also includes an oxide layer 112 of a metal material formed on a sidewall of the RDL 102 between the RDL 102 and the passivation layer 106. The oxide layer 112 can enhance the bonding between the RDL 102 and the passivation layer 106 to prevent hydrogen-induced voids from forming in the RDL 102.
[0063] Figure 2 According to one embodiment, Figure 1 1 is a cross-sectional view of a section 114 of an example semiconductor device 100 around a boundary between an RDL 102 and a passivation layer 106 at the same stage in the integrated circuit manufacturing process depicted in . The following are depicted: the RDL 102, including a metal material, formed over a substrate; the passivation layer 106, formed over the RDL; and an oxide layer 112 of the metal material, formed on the sidewalls of the RDL 102 between the RDL 102 and the passivation layer 106.
[0064] The semiconductor substrate (not shown) may be any configuration including semiconductor materials, including but not limited to bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials may be used, including Group III, Group IV, and / or Group V semiconductors. Although not shown, it should be appreciated that the substrate may further include a plurality of isolation features, such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation features may isolate various microelectronic components formed in and / or on the substrate. Examples of types of microelectronic components that may be formed in the substrate include, but are not limited to, transistors such as metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), resistors, diodes, capacitors, inductors, fuses, and / or other suitable components. Various processes are performed to form the various microelectronic components, including, but not limited to, one or more of deposition, etching, implantation, lithography, annealing, and other suitable processes. The microelectronic components are interconnected to form an integrated circuit device, which may include one or more of a logic device, a memory device (e.g., a static random-access memory (SRAM)), a radio frequency (RF) device, an input / output (I / O) device, a system-on-chip (SoC) device, and other suitable types of devices.
[0065] The RDL 102 is formed over an interconnect structure on a substrate to reroute electrical connections at the top metal pad of the interconnect structure to a desired location, such as an under-bump metallization (UBM) structure, a solder bump, and / or a copper pillar bump, for external electrical connections. The ability to redistribute points can achieve higher contact density. A portion of the RDL 102 is coupled to the top metal pad of the interconnect structure on the substrate. In various embodiments, the RDL 102 is formed of aluminum and / or aluminum copper (AlCu) and can include multiple layers.
[0066] The pattern film 104 is patterned and used as a mask for patterning the RDL 102. In various embodiments, the pattern film 104 is formed of an oxynitride material.
[0067] After patterning the RDL 102, an oxide layer 112 is formed on the sidewalls of the RDL 102. In various embodiments, the oxide layer includes aluminum oxide (Al x O y , where x>0 and y>0). In various embodiments, Al x O y The Al metal of the RDL pad is formed by a plasma oxidation process in a plasma chamber. In the plasma chamber, the surface of the Al metal of the RDL pad can be oxidized by a plasma containing N2O or O2, such as oxygen (O2) plasma, nitrous oxide (N2O) plasma, or nitrogen oxide (NO) plasma. This may lead to the formation of Al y O x In other embodiments, Al x O y It can be formed by a deposition process. For example, Al y O x The film can be deposited by an ALD or CVD process using an Al precursor and an oxidant.
[0068] The passivation layer 106 may be formed on a substrate with Al x O y The passivation layer 106 may be grown and made of a non-organic material, such as un-doped silicate glass (USG), silicon oxide (SiO2), or other materials. The passivation layer 106 may be formed by any suitable method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other methods.
[0069] The etch stop layer (ESL) 108 may be formed by deposition such as CVD. In various embodiments, the ESL is formed of silicon oxynitride (SiON).
[0070] The gap filling layer 110 may include an inorganic material (e.g., silicon dioxide (SiO2), SiON, silicon carbonitride (SiCN), silicon oxycarbide (SiCO), etc.), an organic material (e.g., epoxy resin, polyimide (PI), polybenzoxazole (PBO), etc.), or a mixture of inorganic and organic materials (e.g., a mixture of silicon dioxide and epoxy resin, etc.). The gap filling layer 110 may be formed by chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable techniques.
[0071] Further manufacturing operations may include forming a nitride layer over the gap fill layer 110 and performing a hydrogen plasma annealing process. Without an oxide layer, voids may be formed at the top and bottom corners of the RDL 302 .
[0072] Figure 3 FIG. 3 is a top view of an example RDL 302 showing no oxide layer formed on the sidewalls of the RDL. The example RDL 302 includes a plurality of apertures 304 formed after performing a hydrogen plasma annealing process. Figure 4 is a perspective view of a region 306 of an RDL 302 illustrating one of the apertures 304 formed in a top corner of the RDL 302 . Figure 5 is a top view illustrating an example RDL 502 formed with an oxide layer formed on the sidewalls of the RDL 502. In this example, the RDL 502 exhibits no voids in the RDL 502 after performing a hydrogen plasma annealing process.
[0073] Figure 6 A process flow diagram is depicted for an example semiconductor manufacturing method 600 that includes forming an oxide layer between an RDL and a passivation layer to enhance bonding between the RDL and the passivation layer to prevent formation of hydrogen-induced voids. Figure 6 and 7A to 7FTogether, semiconductor structures at different stages of fabrication are depicted in accordance with some embodiments. Method 600 is merely an example and is not intended to limit the present disclosure beyond that expressly recited in the claims. Additional steps may be provided before, during, and after method 600, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of method 600. Additional features may be added to the semiconductor structures depicted in the figures, and some of the features described below may be replaced, modified, or eliminated in other embodiments.
[0074] As with other method embodiments and exemplary devices discussed herein, it should be understood that portions of the semiconductor structure can be manufactured by typical semiconductor technology process flows, and therefore only some processes are briefly described herein. In addition, the exemplary semiconductor structure can include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, dials, fuses and / or other logic devices, etc., but are simplified for a better understanding of the concepts of the present disclosure.
[0075] At block 602, example method 600 includes providing a substrate. In various embodiments, the substrate includes an interconnect structure in a dielectric layer above the substrate.
[0076] At block 604, the example method 600 includes forming a redistribution layer (RDL) over the interconnect structure on the substrate. In various embodiments, the RDL is coupled to the top metal pad of the interconnect structure on the substrate to reroute electrical connections at the top metal pad to a desired location. In various embodiments, the RDL 102 is formed of aluminum (Al), aluminum copper (AlCu), Cu, or some other metal.
[0077] At block 606, the example method 600 includes forming a pattern film over the RDL. In various embodiments, the pattern film 104 is formed of an oxynitride material. Fig. 7A In the example of blocks 604 and 606 , a pattern film 704 formed over the RDL 702 is depicted.
[0078] At block 608, the example method 600 includes patterning the RDL. The patterning the RDL includes patterning the pattern film and etching the RDL using the pattern film as an etch mask. The RDL may be etched using an anisotropic etching operation. Figure 7B In the example of block 608, the pattern film 704 and the RDL 702 have been patterned.
[0079] At block 610, example method 600 includes forming an oxide layer on the sidewalls of the RDL. In various embodiments, the oxide layer includes an oxide layer of a metal material of the RDL. In various embodiments, the oxide layer includes aluminum oxide (Al x O y ). In various embodiments, Al x O y The Al2O3 layer is formed to have a thickness between about 20 angstroms and about 100 angstroms. In various embodiments, this thickness level is sufficient to prevent voids from forming in the RDL due to SM. In various embodiments, the Al2O3 layer is formed to have a thickness between about 20 angstroms and about 100 angstroms ... x O y is formed by a plasma oxidation process in a plasma chamber. x O y The plasma oxidation process includes oxygen (O2) plasma, nitrous oxide (N2O) plasma, or nitrogen oxide (NO) plasma and / or a mixture thereof. Figure 7C In the example of block 610 , an oxide layer 706 has been formed on the sidewalls of the RDL 702 .
[0080] At block 612, the example method 600 includes forming a passivation layer over the pattern film and the oxide layer. The passivation layer may be grown and made of a non-organic material such as un-doped silicate glass (USG), silicon oxide (SiO2), or other materials.
[0081] refer to Fig.7D In the embodiment of block 612, the passivation layer 708 is formed on the pattern film 704 and the oxide layer 706. The passivation layer 708 can be formed by CVD, high-density plasma CVD (HDPCVD), plasma-enhanced CVD (PECVD), sub-atmospheric CVD (SACVD), other suitable methods or combinations thereof.
[0082] In the present embodiment, the RDL 702 has an oxide layer 706 on the sidewalls of the RDL 702 at its interface with the passivation layer 708, thereby alleviating stress concentration between the RDL 702 and the passivation layer 708 due to any potential mismatched thermal expansion. Without forming an oxide layer on the sidewalls of the RDL, any stress experienced by the passivation layer may be concentrated at the corners of the RDL between the RDL and the passivation layer, resulting in structural defects, including cracks, delamination and / or other defects. In some cases, such stress may be caused by uneven thermal expansion between the passivation layer and a subsequently formed protective layer. To address these challenges, some embodiments of the present disclosure provide a method for forming an oxide layer on the sidewalls of the RDL. By forming an oxide layer on the sidewalls of the RDL, improved interfacial adhesion between the RDL and the passivation layer can be achieved to prevent cracks, delamination and / or other defects. By forming an oxide layer on the sidewalls of the RDL, AlCu pores can be reduced to obtain better thermal cycling reliability. By forming an oxide layer on the sidewall of the RDL, AlCu / Al x O y interface to prevent hydrogen-induced porosity.
[0083] At block 614, the example method 600 includes forming an ESL over the passivation layer. The ESL may be formed by deposition such as CVD. In various embodiments, the ESL is formed of silicon oxynitride (SiON). Fig.7D In the example of block 614 , the ESL layer 710 has been formed over the passivation layer 708 .
[0084] At block 616, the example method 600 includes forming a gap fill layer above the ESL layer. The gap fill layer may be formed by a suitable deposition technique. In some embodiments, the material of the gap fill layer includes silicon oxide (SiO x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0), silicon nitride (SiN x , where x>0) or other suitable dielectric materials. In some alternative embodiments, the packaging material of the gap filling layer is formed by a film deposition process. For example, the film deposition process may include CVD, HDPCVD, PECVD, atomic layer deposition (ALD) or a combination thereof. Fig. 7E In the example of block 616 , a gap fill layer 712 is formed over the ESL 710 .
[0085] At block 618, the example method 600 includes forming a nitride layer over the gapfill layer. At block 620, the example method 600 includes performing a hydrogen plasma anneal process.
[0086] Since the RDL 702 has an oxide layer 706 on the sidewalls of the RDL 702 at its interface with the passivation layer 708, stress concentrations between the RDL 702 and the passivation layer 708 due to any potential mismatched thermal expansion are mitigated. By forming an oxide layer on the sidewalls of the RDL, improved interfacial adhesion between the RDL and the passivation layer can be achieved to prevent cracks, delamination, and / or other defects. By forming an oxide layer on the sidewalls of the RDL, AlCu porosity can be reduced for better thermal cycling reliability. By forming an oxide layer on the sidewalls of the RDL, AlCu / Al x O y interface to prevent hydrogen-induced porosity.
[0087] Transmission electron microscopy (TEM), energy dispersive X-Ray (EDX / EDS) mapping, and line scans can be used to show evidence of successful plasma oxidation on AlCu. Figure 8 To illustrate the interface between the RDL 802 and the passivation layer 806 above the RDL 802, an Al x O y Schematic diagram of the AlCu RDL 802 at the interface 804 . Fig. 9 To illustrate the x O y The example EDS line scan 902 of the interface 804 shows the result of the Al x O y The concentrations of Si, Al, and O around the interface 804. Specifically, the example EDS line scan 902 shows the concentration of Si, Al, and O around the interface 804. x O y At interface 804, the concentration of aluminum (Al) decreases from about 40% to about 15%, the concentration of oxygen (O) increases from about 40% to about 55%, and the concentration of silicon (Si) increases from about 0% to about 10%. This shows that oxygen penetrates into Al from the bottom interface of passivation layer 806.
[0088] Here, embodiments provide improved resistance to problems associated with stress migration (SM). The technology described herein can be used for multi-chip stacking in 3DIC ( / SoIC (Small-Outline Integrated Circuit)) packaging, face-to-face multi-chip module (MCM), CoWoS (Chipon Wafer on Substrte) and integrated fan-out (InFO) packaging and other packaging technologies. The embodiments of the present disclosure provide advantages over existing technologies, although it should be understood that other embodiments can provide different advantages, but not all advantages need to be discussed here, and the specific advantages of all embodiments are not required.
[0089] In some aspects, the technology described herein relates to a semiconductor device comprising: a redistribution layer (RDL) comprising a metal material formed above a substrate; a passivation layer formed above the RDL; and an oxide layer of the metal material formed on a sidewall of the RDL between the RDL and the passivation layer.
[0090] In some aspects, the technology described herein relates to a semiconductor device, wherein the metal material comprises aluminum (Al), and the oxide layer comprises aluminum oxide.
[0091] In some aspects, the technology described herein relates to a semiconductor device wherein the passivation layer comprises silicon oxide (SiO 2 ).
[0092] In some aspects, technology described herein relates to a semiconductor device wherein an RDL does not have voids formed in top or bottom corners of the RDL.
[0093] In some aspects, the technology described herein relates to a semiconductor device in which an oxide layer of a metal material is formed in a plasma chamber using one or more of oxygen (O2) plasma, nitrous oxide (N2O) plasma, or nitride oxide (NO) plasma.
[0094] In some aspects, the technology described herein relates to a semiconductor device wherein an oxide layer of a metal material is formed of an aluminum oxide film deposited by an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process using an Al precursor and an oxidant.
[0095] In some aspects, the technology described herein relates to a semiconductor device, wherein the metal material comprises copper (Cu), and the oxide layer comprises copper oxide.
[0096] In some aspects, the technology described herein relates to a semiconductor device wherein an oxide layer has a thickness between about 20 angstroms and about 100 angstroms.
[0097] In some embodiments, the technology described herein relates to a method for preparing a semiconductor device, comprising: forming a redistribution layer (RDL) comprising a metal material above a substrate; forming an oxide layer of the metal material on a sidewall of the RDL; and depositing a passivation layer above the RDL and the oxide layer, wherein the oxide layer is formed between the RDL and the passivation layer.
[0098] In some aspects, the technology described herein relates to a method wherein forming an oxide layer includes performing a plasma oxidation process to form an oxide layer on sidewalls of an RDL.
[0099] In some aspects, the technology described herein is directed to a method wherein performing a plasma oxidation process includes forming an oxide layer using a plasma including one or more of an oxygen (O2) plasma, a nitrous oxide (N2O) plasma, and a nitride oxide (NO) plasma.
[0100] In some aspects, the technology described herein is directed to a method wherein forming an oxide layer includes depositing an aluminum oxide film by an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process using an Al precursor and an oxidant.
[0101] In some aspects, the technology described herein is directed to a method wherein forming an oxide layer includes forming an oxide layer having a thickness between about 20 angstroms and about 100 angstroms.
[0102] In some aspects, the technology described herein is directed to a method wherein the metal material comprises aluminum (Al) and the oxide layer comprises aluminum oxide.
[0103] In some aspects, techniques described herein relate to a method wherein depositing a passivation layer includes depositing the passivation layer in a plasma chamber after performing a plasma oxidation process in the plasma chamber.
[0104] In some embodiments, the technology described herein is related to a method of preparing a semiconductor device, comprising: forming a redistribution layer (RDL) including aluminum copper (AlCu) over a substrate; oxidizing a sidewall of the RDL to form an aluminum oxide layer on the sidewall of the RDL; depositing a passivation layer over the RDL and the aluminum oxide layer, wherein the aluminum oxide layer is formed between the RDL and the passivation layer; and performing a hydrogen plasma annealing process without hydrogen-induced porosity in a top corner or a bottom corner of the RDL.
[0105] In some aspects, the technology described herein is directed to a method wherein oxidizing a sidewall of an RDL to form an aluminum oxide layer includes performing a plasma oxidation process to form an aluminum oxide layer on the sidewall of the RDL.
[0106] In some aspects, the technology described herein relates to a method wherein performing a plasma oxidation process includes oxidizing the sidewalls of the RDL to form an aluminum oxide layer using a plasma including one or more of an oxygen (O2) plasma, a nitrous oxide (N2O) plasma, and a nitride oxide (NO) plasma.
[0107] In some aspects, techniques described herein relate to a method wherein depositing a passivation layer includes depositing the passivation layer in a plasma chamber after performing a plasma oxidation process in the plasma chamber.
[0108] In some aspects, technology described herein relates to a method wherein oxidizing a sidewall of the RDL to form an aluminum oxide layer includes forming the aluminum oxide layer to a thickness between about 20 angstroms and about 100 angstroms.
[0109] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and alterations may be made herein without departing from the spirit and scope of the present disclosure.
Claims
1. A semiconductor device, characterized in that: include: a redistribution layer, comprising a metal material formed on a substrate; a passivation layer formed above the redistribution layer; and An oxide layer of the metal material is formed on a plurality of side walls of the redistribution layer between the redistribution layer and the passivation layer.
2. The semiconductor device according to claim 1, wherein The metal material includes aluminum, and the oxide layer includes aluminum oxide.
3. The semiconductor device according to claim 1, wherein: The metal material includes copper, and the oxide layer includes copper oxide.
4. The semiconductor device according to claim 1, wherein: The oxide layer has a thickness between 20 angstroms and 100 angstroms.
5. A method for preparing a semiconductor device, characterized in that: include: forming a redistribution layer including a metal material over a substrate; forming an oxide layer of the metal material on a plurality of sidewalls of the redistribution layer; and A passivation layer is deposited over the redistribution layer and the oxide layer, wherein the oxide layer is formed between the redistribution layer and the passivation layer.
6. The method according to claim 5, characterized in that The step of forming the oxide layer includes: performing a plasma oxidation process to form the oxide layer on a plurality of sidewalls of the redistribution layer.
7. The method according to claim 5, characterized in that The step of forming the oxide layer includes: depositing an aluminum oxide film by an atomic layer deposition or chemical vapor deposition process using an aluminum precursor and an oxidant.
8. A method for preparing a semiconductor device, characterized in that: include: forming a redistribution layer including aluminum and copper over a substrate; oxidizing a plurality of sidewalls of the redistribution layer to form an aluminum oxide layer on the plurality of sidewalls of the redistribution layer; depositing a passivation layer over the redistribution layer and the aluminum oxide layer, wherein the aluminum oxide layer is formed between the redistribution layer and the passivation layer; and A hydrogen plasma annealing process without hydrogen-induced porosity is performed in top corners or bottom corners of the redistribution layer.
9. The method according to claim 8, characterized in that The step of oxidizing the plurality of sidewalls of the redistribution layer to form the aluminum oxide layer includes: performing a plasma oxidation process to form the aluminum oxide layer on the plurality of sidewalls of the redistribution layer.
10. The method according to claim 8, characterized in that The step of oxidizing the sidewalls of the redistribution layer to form the aluminum oxide layer includes: forming the aluminum oxide layer to a thickness between 20 angstroms and 100 angstroms.