Self-cleaning over-current protection circuit

Abstract

The invention discloses a self-cleaning over-current protection circuit, and belongs to the technical field of power electronics. Comprising a sampling circuit, a reference circuit, a comparator, a D trigger, a control module, a gate driver, a shunt resistor, a first MOS tube, a second MOS tube and a third MOS tube. A self-cleaning mechanism is introduced into the overcurrent protection circuit. After over-current protection, the control module can automatically clear an over-current state through a preset strategy without external intervention, so that the circuit recovers normal work, and meanwhile, the circuit has the characteristics of simple structure, adjustable protection threshold and the like, so that the safety and the stability of the system are improved, and the requirements of modern electrical equipment on high reliability and continuous operation can be met.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, and in particular to a self-clearing overcurrent protection circuit. Background Art

[0002] Power management and safety protection are vital components of modern electronic devices, among which overcurrent protection is one of the key measures to ensure the normal operation of the equipment. The current overcurrent protection mechanism has the following problems: external intervention is required to restore system operation after the overcurrent protection is triggered; the threshold parameters of the protection device are fixed and cannot be dynamically adjusted according to the actual working conditions; the circuit is complex and contains multiple components and redundant paths. These problems increase manufacturing costs and may also introduce more failure points, resulting in reduced overall system reliability and slow response speed, and the inability to quickly cut off the power supply at the moment when the current rises sharply.

[0003] In order to solve the above problems, it is urgent to develop a more intelligent and efficient overcurrent protection circuit to improve the safety and stability of the system and meet the requirements of modern electrical equipment for high reliability and continuous operation. Summary of the invention

[0004] In view of the defects of the prior art, the present invention provides a self-clearing overcurrent protection circuit with an automatic reset function, which can automatically restore system operation after the overcurrent event is handled, reducing the need for external intervention. The protection threshold can be dynamically adjusted, which improves the flexibility and reliability of the system.

[0005] In order to achieve the above object, the present invention provides a self-clearing overcurrent protection circuit, comprising: a sampling circuit, a reference circuit, a comparator, a D trigger, a control module, a gate driver, a shunt resistor, a first MOS tube, a second MOS tube and a third MOS tube;

[0006] One end of the shunt resistor is connected to the input end of the overcurrent protection circuit, and the other end is connected to the source of the second MOS tube; the drain of the second MOS tube is connected to the drain of the third MOS tube, and the source of the third MOS tube is connected to the output end of the overcurrent protection circuit;

[0007] The input ends of the sampling circuit and the reference circuit are respectively connected to the two ends of the shunt resistor, and are used to detect the voltage at the two ends of the shunt resistor. The output ends of the reference circuit and the sampling circuit are respectively connected to the inverting input end and the non-inverting input end of the comparator, and the output end of the comparator is connected to the data input end of the D flip-flop; the gate of the first MOS tube is connected to the positive output end of the D flip-flop, its source is grounded, and its drain is connected to the enable end of the gate driver, and is also connected to the input end of the control module; the output end of the control module is connected to the CLK port of the D flip-flop and the enable end of the gate driver; the output end of the gate driver is connected to the gates of the second MOS tube and the third MOS tube.

[0008] Furthermore, the shunt resistor is connected to the circuit using a Kelvin four-wire connection method.

[0009] Furthermore, the reference circuit includes a first resistor R1 and a second resistor R2, which are connected in series and connected between the input end of the overcurrent protection circuit and the ground; the connection point between the first resistor R1 and the second resistor R2 serves as the output end of the reference circuit and is connected to the inverting input end of the D trigger.

[0010] Furthermore, the sampling circuit includes a third resistor R3 and a fourth resistor R4; the third resistor R3 and the fourth resistor R4 are connected in series and connected between the connection point of the shunt resistor R and the source of the second MOS tube and the ground; the connection point of the third resistor R3 and the fourth resistor R4 serves as the output end of the sampling circuit and is connected to the in-phase input end of the D trigger.

[0011] Furthermore, when a short power failure does not occur at the output end of the overcurrent protection circuit, the comparator outputs a high level, the D trigger controls the first MOS tube to be in a disconnected state, the drain of the first MOS tube is at a high level, so that the gate driver enable end is at a high level, and the gate driver sets the gates of the second MOS tube and the third MOS tube to a high level, so that the second MOS tube and the third MOS tube are turned on;

[0012] When a short power failure occurs at the output end of the overcurrent protection circuit, the comparator outputs a low level, the D trigger controls the first MOS tube to be in a conducting state, the drain of the first MOS tube is at a low level, so that the gate driver enable end is at a low level, and the gate driver sets the gates of the second MOS tube and the third MOS tube to a low level, so that the second MOS tube and the third MOS tube cut-off system stop working, thereby realizing overcurrent protection;

[0013] After the overcurrent protection is triggered, the control module detects the low level of the drain of the first MOS tube, sends a rising edge signal and maintains a high level through a preset strategy, so that the D trigger clears the overcurrent latch signal and enables the gate driver at the same time, so that the second MOS tube and the third MOS tube are turned on again, completing the self-clearing of the overcurrent protection.

[0014] Furthermore, the control module is an MCU.

[0015] Furthermore, the resistance of the shunt resistor is set according to a triggering threshold of the overcurrent protection.

[0016] Beneficial effects of the present invention:

[0017] The present invention creatively introduces a self-clearing mechanism after overcurrent protection, which can automatically clear the overcurrent state without external intervention, so that the circuit can resume normal operation. At the same time, the circuit has the characteristics of simple structure and adjustable protection threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of a self-clearing overcurrent protection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0020] like Figure 1 As shown, an embodiment of the present invention provides a self-clearing overcurrent protection circuit, including: a sampling circuit, a reference circuit, a comparator, a D trigger, a control module (MCU), a gate driver, a shunt resistor R, a first MOS tube Q1, a second MOS tube Q2 and a third MOS tube Q3.

[0021] One end of the shunt resistor R is connected to the input end of the overcurrent protection circuit, and the other end is connected to the source of the second MOS tube Q2; the drain Q2 of the second MOS tube is connected to the drain of the third MOS tube Q3, and the source of the third MOS tube Q3 is connected to the output end of the overcurrent protection circuit; the input ends of the sampling circuit and the reference circuit are respectively connected to the two ends of the shunt resistor R, and are used to detect the voltages at the two ends of the shunt resistor R, and the output ends of the reference circuit and the sampling circuit are respectively connected to the inverting input end and the non-inverting input end of the comparator; the output end of the comparator is connected to the data input end of the D trigger; the gate of the first MOS tube Q1 is connected to the positive output end of the D trigger, its source is grounded, and its drain is connected to the enable end of the gate driver, and is also connected to the input end of the control module; the output end of the control module is connected to the CLK port of the D trigger and the enable end of the gate driver; the output end of the gate driver is connected to the gates of the second MOS tube and the third MOS tube.

[0022] The shunt resistor is connected to the circuit using the Kelvin four-wire method to achieve high-precision and high-stability benchmark and sampling.

[0023] The reference circuit includes a first resistor R1 and a second resistor R2; the first resistor R1 and the second resistor R2 are connected in series and connected between the input end of the overcurrent protection circuit and the ground; the connection point between the first resistor R1 and the second resistor R2 serves as the output end of the reference circuit and is connected to the inverting input end of the D trigger.

[0024] The sampling circuit includes a third resistor R3 and a fourth resistor R4; the third resistor R3 and the fourth resistor R4 are connected in series and connected between the connection point of the shunt resistor R and the source of the second MOS tube and the ground; the connection point of the third resistor R3 and the fourth resistor R4 is connected to the non-inverting input terminal of the D trigger as the output terminal of the sampling circuit.

[0025] When there is no short power failure at the output of the overcurrent protection circuit (normal working state), the reference value of the inverting input is always lower than the sampling value of the non-inverting input, so the comparator outputs a high level. The PRE_L pin of the D flip-flop is continuously pulled high, while the output pin of the D flip-flop is continuously pulled low, so that the latch maintains a low output state, thereby controlling the first MOS tube Q1 to be in a disconnected state. Therefore, the drain of the first MOS tube is at a high level, so that the gate driver enable terminal is also at a high level, and the gate driver sets the gates of the second MOS tube and the third MOS tube to a high level, so that the second MOS tube Q2 and the third MOS tube Q3 are turned on and work.

[0026] When a short power failure occurs at the output end of the overcurrent protection circuit (overcurrent working state), the reference value of the inverting input end is higher than the sampling value of the non-inverting input end, so the comparator outputs a low level. The PRE_L pin of the D flip-flop is pulled low, while the output pin of the D flip-flop is continuously pulled high, and the latch enters a high-level output state, controlling the first MOS tube Q1 to turn on. Therefore, the drain of the first MOS tube is at a low level, so that the gate driver enable end is also at a low level, and the gate driver sets the gates of the second MOS tube and the third MOS tube to a low level, so that the second MOS tube and the third MOS tube cutoff system stop working, and overcurrent protection is achieved.

[0027] After the overcurrent protection is triggered, that is, the control module detects the low level of the drain of the first MOS tube, then the control module determines whether it is necessary to send a clear overcurrent latch signal according to the preset strategy. If clearing is required, a rising edge signal can be sent through the GPIO pin (MOS_CTR) and the high level (rising edge instruction) can be maintained to perform self-clearing of the overcurrent protection. This rising edge instruction is given to the overcurrent latch signal of the D flip-flop. After clearing the latch signal, the D flip-flop returns to the initial state, the latch outputs a low level, and controls the first MOS tube Q1 to turn off. At the same time, this rising edge instruction is also given to the EN enable terminal of the gate driver GATE_driver to restore it to a normal high level. The gate driver controls the second MOS tube Q2 and the third MOS tube Q3 to turn on again, and the system resumes normal operation, completing the self-clearing mechanism of the overcurrent protection. If clearing is not required, the overcurrent protection state is maintained to prevent the system from repeatedly entering the overcurrent state.

[0028] The trigger threshold can be adjusted according to the resistance value of the voltage divider resistor R.

[0029] The above is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solution and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A self-clearing overcurrent protection circuit, characterized in that: include: A sampling circuit, a reference circuit, a comparator, a D trigger, a control module, a gate driver, a shunt resistor, a first MOS tube, a second MOS tube and a third MOS tube; One end of the shunt resistor is connected to the input end of the overcurrent protection circuit, and the other end is connected to the source of the second MOS tube; The drain of the second MOS tube is connected to the drain of the third MOS tube, and the source of the third MOS tube is connected to the output end of the overcurrent protection circuit; The input ends of the sampling circuit and the reference circuit are respectively connected to the two ends of the shunt resistor, and are used to detect the voltage at the two ends of the shunt resistor. The output ends of the reference circuit and the sampling circuit are respectively connected to the inverting input end and the non-inverting input end of the comparator, and the output end of the comparator is connected to the data input end of the D flip-flop; the gate of the first MOS tube is connected to the positive output end of the D flip-flop, its source is grounded, and its drain is connected to the enable end of the gate driver, and is also connected to the input end of the control module; the output end of the control module is connected to the CLK port of the D flip-flop and the enable end of the gate driver; the output end of the gate driver is connected to the gates of the second MOS tube and the third MOS tube.

2. The self-clearing overcurrent protection circuit according to claim 1, characterized in that: The shunt resistor is connected to the circuit using a Kelvin four-wire connection method.

3. The self-clearing overcurrent protection circuit according to claim 1, characterized in that: The reference circuit includes a first resistor R1 and a second resistor R2, which are connected in series and connected between the input end of the overcurrent protection circuit and the ground; the connection point between the first resistor R1 and the second resistor R2 serves as the output end of the reference circuit and is connected to the inverting input end of the D trigger.

4. The self-clearing overcurrent protection circuit according to claim 1, characterized in that: The sampling circuit includes a third resistor R3 and a fourth resistor R4; the third resistor R3 and the fourth resistor R4 are connected in series and connected between the connection point of the shunt resistor R and the source of the second MOS tube and the ground; the connection point of the third resistor R3 and the fourth resistor R4 serves as the output end of the sampling circuit and is connected to the non-inverting input end of the D trigger.

5. The self-clearing overcurrent protection circuit according to claim 1, characterized in that: When a short power failure does not occur at the output end of the overcurrent protection circuit, the comparator outputs a high level, the D trigger controls the first MOS tube to be in a disconnected state, the drain of the first MOS tube is at a high level, so that the gate driver enable end is at a high level, and the gate driver sets the gates of the second MOS tube and the third MOS tube to a high level, so that the second MOS tube and the third MOS tube are turned on; When a short power failure occurs at the output end of the overcurrent protection circuit, the comparator outputs a low level, the D trigger controls the first MOS tube to be in a conducting state, the drain of the first MOS tube is at a low level, so that the gate driver enable end is at a low level, and the gate driver sets the gates of the second MOS tube and the third MOS tube to a low level, so that the second MOS tube and the third MOS tube cutoff system stop working, thereby realizing overcurrent protection; after the overcurrent protection is triggered, the control module detects the low level of the drain of the first MOS tube, sends a rising edge signal through a preset strategy and maintains a high level, so that the D trigger clears the overcurrent latch signal, and enables the gate driver at the same time, so that the second MOS tube and the third MOS tube are turned on again, thereby completing the self-clearing of the overcurrent protection.

6. The self-clearing overcurrent protection circuit according to claim 1, characterized in that: The control module is MCU.

7. The self-clearing overcurrent protection circuit according to claim 1, characterized in that: The resistance value of the shunt resistor is set according to the triggering threshold of the overcurrent protection.

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