A single-stage adjustable voltage rectifier system with multi-output full-wave rectification

Abstract

This application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification, including: a rectifier and a control module; the rectifier includes: a generation module, a free-slip switch assembly, a first transistor assembly, a second transistor assembly, a first load assembly, a second load assembly, and a third transistor assembly, all electrically connected; the generation module is used to generate an AC input voltage; the first transistor assembly and the second transistor assembly are configured to generate a DC output voltage based on the AC input voltage; the load is configured to acquire the DC output voltage; the control module is configured to: if the DC output voltage is not within a target voltage range, control the free-slip switch assembly, the first transistor assembly, the second transistor assembly, and the third transistor assembly to turn on or off according to the DC output voltage and a DC output voltage reference level, so that the DC output voltage is within the target voltage range, thereby realizing the simultaneous adjustment of the output voltage values ​​of multiple output ports in the multi-output rectifier circuit.

Description

Technical Field

[0001] This application relates to the field of rectifier circuit technology, and in particular to a single-stage adjustable voltage rectifier system with multi-output full-wave rectification. Background Technology

[0002] Wireless power transfer technology has been widely used in current implantable biomedical devices, including cochlear implants, retinal implants, and neural prostheses. In wireless power transfer systems, a power receiver of tens of milliwatts is typically preferred to power multiple regulated power rails supporting various functions. To achieve efficient power transfer in implantable devices, wireless charging systems are generally used.

[0003] Currently, wireless charging systems use a single-input multiple-output rectifier circuit, which uses time-division multiplexing to supply power to different power output ports. When the supply voltage of a power output port reaches the required voltage of the load, the load connected to the power output port is charged. This achieves efficient power supply and can supply power to multiple power output ports.

[0004] However, during application, when the supply voltage of some loads at multiple power output ports does not reach the required voltage, while the supply voltage of other loads does reach the required voltage, the PMOS transistors corresponding to the partial output DC voltage in the rectifier circuit will not conduct. If the subsequent rectifier circuit is still in charging mode, the input voltage of the rectifier circuit will exceed the output voltage and the gate voltage of the PMOS transistor, causing the body diode of the PMOS transistor to conduct, thereby causing the voltage regulation function of the rectifier circuit to fail or even be damaged. If the rectifier circuit switches to idling mode, it cannot normally supply power to the power output ports corresponding to loads whose supply voltage does not reach the required voltage, thus limiting the output power and voltage regulation freedom of the rectifier circuit. Summary of the Invention

[0005] This application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification to solve the technical problem that the output power of each power output port cannot be adjusted in existing multi-output rectifier circuits.

[0006] This application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification, comprising:

[0007] A rectifier and a control module, wherein the rectifier is communicatively connected to the control module;

[0008] The rectifier includes: an electrically connected generation module, an idle switch assembly, a first transistor assembly, a second transistor assembly, a first load assembly, a second load assembly, and a third transistor assembly;

[0009] The generating module includes: an electrically connected tapped coil, a first resonant capacitor, and a second resonant capacitor, wherein the first and second resonant capacitors are connected in series and then connected in parallel with the tapped coil; the tapped end of the tapped coil is connected to the series connection point of the first and second resonant capacitors; the idle switch assembly includes: an electrically connected first idle switch and a second idle switch, wherein the first and second idle switches are connected in series, the first idle switch is connected in parallel with the first resonant capacitor, and the second idle switch is connected in parallel with the second resonant capacitor;

[0010] The two input terminals of the first transistor assembly are respectively connected to one end of the first resonant capacitor and one end of the second resonant capacitor; the output terminal of the first transistor assembly is connected to one end of the first load assembly; the input terminal of the third transistor assembly is connected to one end of the first resonant capacitor and the series connection point of the second resonant capacitor, and the output terminal of the third transistor assembly is connected to the second load assembly; the two input terminals of the second transistor assembly are respectively connected to one end of the first resonant capacitor and one end of the second resonant capacitor; the output terminal of the second transistor assembly is connected to the common terminal of the first load assembly and the second load assembly.

[0011] The generation module is used to generate AC input voltage;

[0012] The first transistor assembly, the second transistor assembly, and the third transistor assembly are configured as follows:

[0013] Based on the AC input voltage, a DC output voltage is generated;

[0014] The first load component and the second load component are configured as follows:

[0015] Obtain the DC output voltage;

[0016] The control module is configured as follows:

[0017] Determine the DC output voltage reference level;

[0018] The target voltage range is obtained based on the DC output voltage reference level;

[0019] If the DC output voltage is not within the target voltage range, then the idle switch assembly, the first transistor assembly, the second transistor assembly, and the third transistor assembly are controlled to turn on or off according to the DC output voltage and the DC output voltage reference level, so that the DC output voltage is within the target voltage range.

[0020] The third transistor assembly is configured with at least one PMOS transistor or NMOS transistor; the number of the PMOS transistor or the NMOS transistor is determined by the number of the second load assembly.

[0021] In some embodiments, the first transistor component includes:

[0022] The first PMOS transistor and the second PMOS transistor are electrically connected;

[0023] The first PMOS transistor and the second PMOS transistor are cross-connected.

[0024] In some embodiments, the second transistor component includes:

[0025] The first NMOS transistor, the second NMOS transistor, the first comparator, and the second comparator are electrically connected. The non-inverting input of the first comparator is connected to the drain of the first NMOS transistor as one input of the second transistor assembly. The inverting input of the first comparator is connected to the source of the first NMOS transistor and then to the common terminal of the first load assembly and the second load assembly. The non-inverting input of the second comparator is connected to the drain of the second NMOS transistor as the other input of the second transistor assembly. The inverting input of the second comparator is connected to the source of the second NMOS transistor and then to the common terminal of the first load assembly and the second load assembly.

[0026] The first NMOS transistor and the second NMOS transistor are active diode structures.

[0027] In some embodiments, the first load component includes a first load stabilizing capacitor and a first load resistor connected in parallel, and the second load component is configured with a plurality of load stabilizing capacitors and load resistors;

[0028] The first load voltage regulator capacitor is configured as follows:

[0029] Obtain the first DC output voltage;

[0030] The second load component is configured as follows:

[0031] Obtain the second DC output voltage.

[0032] In some embodiments, the control module is further configured to:

[0033] Based on the second DC output voltage, obtain the load current of the second load component;

[0034] Based on the load current, the load state of the load current is obtained; the load state includes: light load state and heavy load state;

[0035] If the load current is under light load, control the idling switch assembly, the first transistor assembly, the second transistor assembly, and the third transistor assembly to turn on or off, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range;

[0036] If the load current is under heavy load, control the first PMOS transistor and the third transistor assembly to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range.

[0037] In some embodiments, the control module is further configured to:

[0038] When the load current is under light load, if the first DC output voltage is less than the first DC output voltage reference level and the second DC output voltage is less than the second DC output voltage reference level, then the first PMOS transistor, the second NMOS transistor, and the third transistor assembly are controlled to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range.

[0039] If the first DC output voltage is less than the first DC output voltage reference level and the second DC output voltage is greater than the second DC output voltage reference level, then control the first PMOS transistor and the second NMOS transistor to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range.

[0040] If the first DC output voltage is greater than the first DC output voltage reference level and the second DC output voltage is greater than the second DC output voltage reference level, then the idle switch assembly is controlled to open, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range.

[0041] In some embodiments, the control module includes:

[0042] The electrical connections include a first hysteresis comparator, a second hysteresis comparator, a third hysteresis comparator, a D flip-flop assembly, a logic gate assembly, an inverter chain delay circuit, and an inverter assembly.

[0043] The first hysteresis comparator is used to obtain a first comparison result based on the first DC output voltage and the first DC output voltage reference level;

[0044] The second hysteresis comparator is used to obtain a second comparison result based on the second DC output voltage and the second DC output voltage reference level;

[0045] The third hysteresis comparator is configured as follows:

[0046] The reference voltage is obtained based on the second DC output voltage reference level;

[0047] Based on the second DC output voltage and the reference voltage, a third comparison result is obtained;

[0048] The logic gate component is used to generate a trigger signal based on the first comparison result, the second comparison result, and the third comparison result; the trigger signal is used to control the idle switch component, the first transistor component, the second transistor component, and the third transistor component to turn on or off, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range.

[0049] In some embodiments, the control module is further configured to:

[0050] If the load current is under heavy load, the first PMOS transistor and the third transistor assembly are turned on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the third target voltage range; the third target voltage range is obtained by the reference voltage and the reference level of the second DC output voltage.

[0051] In some embodiments, the first comparator and the second comparator include:

[0052] Electrically connected PMOS transistor components and NMOS transistor components;

[0053] Specifically, when the value of the signal to be compared input to the first comparator or the second comparator is greater than the positive value of the power supply voltage of the first comparator or the second comparator, the first comparator or the second comparator outputs a low level; when the value of the signal to be compared input to the first comparator or the second comparator is less than or equal to the positive value of the power supply voltage of the first comparator or the second comparator, the first comparator or the second comparator outputs a high level.

[0054] This application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification, comprising: a rectifier and a control module, wherein the rectifier is communicatively connected to the control module; the rectifier includes: a generation module, an idle switch assembly, a first transistor assembly, a second transistor assembly, a first load assembly, a second load assembly, and a third transistor assembly, all electrically connected; the generation module is connected in parallel with the idle switch assembly, and the idle switch assembly and the load are connected in parallel with the first transistor assembly and the second transistor assembly; the first transistor assembly and the second transistor assembly are connected in parallel; the generation module is used to generate an AC input voltage; the first transistor assembly and the second transistor assembly... The component is configured to generate a DC output voltage based on the AC input voltage; the load is configured to acquire the DC output voltage; the control module is configured to acquire a DC output voltage reference level; acquire a target voltage range based on the DC output voltage reference level; if the DC output voltage is not within the target voltage range, control the idle switch assembly, the first transistor assembly, the second transistor assembly, and the third transistor assembly to turn on or off based on the DC output voltage and the DC output voltage reference level, so that the DC output voltage is within the target voltage range, thereby enabling simultaneous adjustment of the output voltage values ​​of multiple output ports in a multi-output rectifier circuit. Attached Figure Description

[0055] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a first schematic diagram of the structure of the single-stage adjustable voltage rectifier system with multi-output full-wave rectification in this application;

[0057] Figure 2 This is a second schematic diagram of the structure of the single-stage adjustable voltage rectifier system with multi-output full-wave rectification in this application;

[0058] Figure 3 This is a schematic diagram of the control module in this application;

[0059] Figure 4 This is a schematic diagram of the structure of the first comparator and the second comparator in this application;

[0060] Figure 5 This is a schematic diagram of the current wireless charging system.

[0061] Figure 6 This is a schematic diagram of the current single-input multiple-output rectifier circuit.

[0062] Figure 7This is a schematic diagram of the rectifier circuit in this application when it is in dual-sided charging mode.

[0063] Figure 8 This is a schematic diagram of the rectifier circuit in this application when it is in high-side charging mode.

[0064] Figure 9 This is a schematic diagram of the rectifier circuit in the idling mode in this application;

[0065] Figure 10 This is a schematic diagram of the rectifier circuit in charge distribution mode in this application;

[0066] Figure 11 This is a schematic diagram of the transient switching performance of the rectifier circuit in the no-charge-distribution mode of this application.

[0067] Figure 12 This is a schematic diagram of the transient switching performance of the rectifier circuit in charge distribution mode in this application;

[0068] Figure 13 The schematic waveforms of the input and output voltages of the rectifier circuit in this application when it is in dual-sided charging mode are shown.

[0069] Figure 14 The waveforms of the input and output voltages and the NMOS gate voltage of the rectifier circuit under the first load condition in this application are shown.

[0070] Figure 15 The test waveforms of the rectifier circuit input and output voltages and NMOS gate voltage under the second load condition in this application are shown.

[0071] Figure 16 The test waveforms of the rectifier circuit input and output voltages and NMOS gate voltage under the third load condition in this application are shown.

[0072] Figure 17 The waveforms of the rectifier circuit input and output voltages and NMOS gate voltage under the fourth load condition in this application are shown.

[0073] Figure 18 This is a first schematic diagram of the two output voltage waveforms and load switching signal of the rectifier circuit in this application when the load current changes abruptly;

[0074] Figure 19 This is a second schematic diagram of the two output voltage waveforms and load switching signal of the rectifier circuit in this application when the load current changes abruptly;

[0075] Figure 20 The diagram shows the efficiency test results of the rectifier circuit in this application under different load conditions.

[0076] Explanation of reference numerals in the attached figures:

[0077] 1-Control module; 11-First hysteresis comparator; 12-Second hysteresis comparator; 13-Third hysteresis comparator; 14-D flip-flop assembly; 15-Logic gate assembly; 16-Inverter chain delay circuit; 17-Inverter assembly; 2-Generation module; 21-Tap coil; 22-First resonant capacitor; 23-Second resonant capacitor; 3-Free-running switch assembly; 31-First free-running switch; 32-Second free-running switch; 4-First transistor assembly; 41-First PMOS transistor; 42-Second PMOS transistor; 5-Second transistor assembly; 51-First NMOS transistor; 52-Second NMOS transistor; 53-First comparator; 54-Second comparator; 541-PMOS transistor assembly; 542-NMOS transistor assembly; 6-First load assembly; 61-First load voltage regulator capacitor; 62-First load resistor; 7-Third transistor assembly; 8-Second load assembly. Detailed Implementation

[0078] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0079] Because in some technologies, the output power of each power output port cannot be adjusted in a multi-output rectifier circuit, this application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification to solve this technical problem. The structure of each part of the single-stage adjustable voltage rectifier system with multi-output full-wave rectification is described below:

[0080] For example, the basic structure of currently used wireless charging systems is as follows: Figure 5 As shown, the transmitting end generates an alternating magnetic field through the alternating current in coil L1, and the receiving end coil L2 generates an alternating current through this alternating magnetic field. The alternating current flows through capacitor C2 to generate an alternating voltage V. AC1 V AC2 Since all electrical equipment requires DC power, the AC voltage needs to be converted to DC voltage by a rectifier circuit. The DC voltage V obtained by the rectifier is... REC The voltage level will change with the input voltage level, so it cannot be used directly. It needs to be converted into multiple stable DC voltages that do not change with the input voltage level through a subsequent single-input multiple-output DC-DC circuit.

[0081] For example, the following requirements currently exist in rectifier circuits:

[0082] Voltage regulation requirement: In biomedical wireless power transmission systems, changes in the relative positions of the transmitting coil (TX) and receiving coil (RX) often cause fluctuations in the coupling coefficient. This fluctuation directly affects the voltage conversion ratio of the entire power transmission link, leading to instability in the RX terminal voltage. Since the RX circuit needs to continuously provide a stable DC power supply voltage to various functional modules in biomedical devices, the rectifier circuit needs to have voltage regulation and stabilization capabilities.

[0083] Multiple Output Requirements: With advancements in biomedical device technology, these devices typically require multiple independent power supply voltages to drive different functional modules, such as analog amplifiers, digital logic units, and memory. This requirement further increases the complexity of RX circuit design. Traditional RX circuit designs include a rectifier and multiple DC-DC converters responsible for converting AC to DC to meet the device's requirements for power stability and multiple voltage outputs. DC-DC converters provide adjustable DC outputs.

[0084] To achieve the aforementioned voltage regulation and multi-output requirements, the current approach combines a full-bridge rectifier (FBR) with multiple low-dropout regulators (LDOs). This necessitates outputting a high-power voltage from the TX terminal to compensate for varying link conditions. However, the required multi-stage structure and additional components inevitably lead to cascading power losses and increase system size and cost. To address the limitations of this multi-stage structure, a single-stage multi-output regulating rectifier can be introduced for voltage rectification and regulation, thus avoiding cascading efficiency losses.

[0085] For example, current single-input multiple-output rectifier circuits such as Figure 6 As shown, V SS The negative terminal of the comparator's supply voltage is selectively connected to V via a cross-coupled NMOS transistor. AC1 or V AC2 (Voltage across the inductor), and different output terminals V OUT1 and V OUT2 Then, a PMOS with an active diode structure driven by a comparator is connected to V at different times. AC2 or V AC1 When V AC1 When M is high, N2 On, V AC2 Connected to V SS Controlled by logic circuits, M can be selected at this time. P1 Or M P3 Enabled (cannot be enabled simultaneously), if M is selected. P1 If enabled, then VAC1 Connect to V OUT1 At this time, the rectifier circuit controls the inductor current to supply V. OUT1 Charging; if M is selected P3 If enabled, then V AC1 Connect to V OUT2 At this time, the rectifier circuit controls the inductor current to supply V. OUT2 Charging; if V at this time OUT1 and V OUT2 If the equalization charge reaches the specified voltage, then M P1 and M P3 Neither of them is turned on. At this time, the switch connected in parallel across the inductor will close, turning V... AC1 and V AC2 When short-circuited, the system enters idling mode to achieve the voltage regulation function of the rectifier circuit.

[0086] Current single-input multiple-output rectifier circuits have the following problems:

[0087] 1. In rectifier circuits, NMOS transistors use a cross-connection structure, while PMOS transistors use an active diode structure. Cross-connected NMOS transistors have very low drive losses. Because PMOS transistors have lower electron mobility than NMOS transistors, for the same on-resistance, the size and gate parasitic capacitance of NMOS transistors are much smaller than those of PMOS transistors.

[0088] 2. The rectifier circuit uses a multiplexing method to supply power to different power output ports. When the supply voltage of a power output port reaches the required voltage of the load, it charges the load connected to that power output port, thus achieving efficient power supply and powering multiple power output ports. However, during application, when the supply voltage of some loads in the multiple power output ports does not reach the required voltage, while the supply voltage of other loads does, the PMOS transistors corresponding to some output DC voltages in the rectifier circuit will not conduct. If the rectifier circuit is still in charging mode, the input voltage of the rectifier circuit will exceed the output voltage and the gate voltage of the PMOS transistor, causing the body diode of the PMOS transistor to conduct, thereby causing the voltage regulation function of the rectifier circuit to fail or even be damaged. If the rectifier circuit switches to idle mode, it cannot normally supply power to the power output ports corresponding to loads whose supply voltage does not reach the required voltage, limiting the output power and voltage regulation flexibility of the rectifier circuit.

[0089] 3. A rectifier circuit can only charge once per cycle, which is called half-wave rectification. Under the same conditions, the output ripple of half-wave rectification is twice that of full-wave rectification. Full-wave rectification and half-wave rectification are two basic methods for converting alternating current (AC) to direct current (DC). Half-wave rectification is a simple rectification method that uses only one diode to rectify the positive half-cycle of the AC current, ignoring the negative half-cycle. This means that only half the time in each AC cycle is the output voltage generated, resulting in a large ripple component in the output DC voltage. Half-wave rectification is less efficient because it does not fully utilize all cycles of the AC current. Full-wave rectification uses two or four diodes to rectify both the positive and negative half-cycles of the AC current. In full-wave rectification, the output is a positive DC voltage regardless of whether the AC current is in the positive or negative half-cycle, making more efficient use of the AC power supply. Full-wave rectification has less output DC voltage ripple, making it more stable and efficient than half-wave rectification. In summary, full-wave rectification offers the following advantages over half-wave rectification: higher rectification efficiency because it utilizes the entire cycle of the alternating current; less output DC voltage ripple, resulting in better power quality, making it suitable for high-power applications and providing a more stable DC power supply.

[0090] Depend on Figure 1 As can be seen, to address the above problems, this application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification, comprising: a rectifier and a control module 1, wherein the rectifier is communicatively connected to the control module 1; the control module 1 can receive the charging voltage V of the rectifier in real time. out1 and V out2 The rectifier is used to convert AC voltage to DC voltage. The rectifier includes: a generation module 2, an idler switch assembly 3, a first transistor assembly 4, a second transistor assembly 5, a first load assembly 6, a second load assembly 8, and a third transistor assembly 7, all electrically connected. The generation module 2 generates an AC input voltage. The specific method of generating the AC input voltage can be found in the above-described wireless charging system embodiment, and will not be repeated here. The first transistor assembly 4, the second transistor assembly 5, and the third transistor assembly 7 are configured to generate a DC output voltage based on the AC input voltage. The first transistor assembly 4 includes several PMOS transistors, and the second transistor assembly 5 includes several NMOS transistors. The first load assembly 6 and the second load assembly 8 are configured to acquire the DC output voltage. The control module 1 is configured to determine the DC output voltage reference level. The DC output voltage reference level is input from the user's external environment. For example, if the user wants to charge one of the first load assembly 6 or the second load assembly 8 to 1.5V, they can input the value to be charged (1.5V), i.e., the DC output voltage reference level, to the control module 1. Figure 3 Chinese V REF1 and V REF2The target voltage range is obtained based on the DC output voltage reference level. The target voltage range is defined as the range in which the corresponding load in the first load component 6 and the second load component 8 is charged, indicating that charging is complete. The target voltage range is obtained based on the charge capture capability of the load, meaning that the charging voltage requirement of the load can be met when the voltage is within the target voltage range. If the DC output voltage is not within the target voltage range, the idle switch component 3, the first transistor component 4, the second transistor component 5, and the third transistor component 7 are controlled to open or close based on the DC output voltage and the DC output voltage reference level, so that the DC output voltage is within the target voltage range. The third transistor component 7 is configured with at least one PMOS transistor or NMOS transistor. The number of PMOS transistors or NMOS transistors is determined by the number of the second load components 8.

[0091] For example, for each PMOS or NMOS transistor configured in the third transistor component 7, an additional load is configured in the first load component 6 and the second load component 8 of the system to be connected to the corresponding PMOS or NMOS transistor. It can be understood that the multi-output full-wave rectifier single-stage adjustable voltage rectifier system provided in this application can be connected to several loads.

[0092] This application provides a single-stage adjustable voltage rectifier system with multi-output full-wave rectification. The control module 1 acquires the load voltage (i.e., DC output voltage) in real time. By judging the relationship between the load's DC output voltage and the load's charging voltage (i.e., the reference level of DC output voltage), the system controls which components of the idle switch assembly 3, the first transistor assembly 4, and the second transistor assembly 5 are turned on. This enables the rectifier circuit to select which components in the rectifier are turned on according to each load voltage, so that each load voltage is within the target voltage range, thus completing the power supply work of multiple power output ports of the rectifier circuit.

[0093] Depend on Figure 2 It is known that the generating module 2 includes: an electrically connected tap coil 21, a first resonant capacitor 22, and a second resonant capacitor 23. The first resonant capacitor 22 and the second resonant capacitor 23 are connected in series and then connected in parallel with the tap coil 21. The tap end of the tap coil 21 is connected to the series connection point of the first resonant capacitor 22 and the second resonant capacitor 23. The idle switch assembly 3 includes: an electrically connected first idle switch 31 and a second idle switch 32. The first idle switch 31 and the second idle switch 32 are connected in series. The first idle switch 31 is connected in parallel with the first resonant capacitor 22, and the second idle switch 32 is connected in parallel with the second resonant capacitor 23.

[0094] The two input terminals of the first transistor assembly 4 are respectively connected to one end of the first resonant capacitor 22 and one end of the second resonant capacitor 23; the output terminal of the first transistor assembly 4 is connected to one end of the first load assembly; the input terminal of the third transistor assembly 7 is connected to one end of the first resonant capacitor 22 and the series connection point of the second resonant capacitor 23, and the output terminal of the third transistor assembly 7 is connected to the second load assembly; the two input terminals of the second transistor assembly 5 are respectively connected to one end of the first resonant capacitor 22 and one end of the second resonant capacitor 23; the output terminal of the second transistor assembly 5 is connected to the common terminal of the first load assembly and the second load assembly; the tap coil 21, the first resonant capacitor 22, and the second resonant capacitor 23 correspond to... Figure 2 Center tap coil L R First resonant capacitor C R1 Second resonant capacitor C R2 The tap coil 21 is connected to the first resonant capacitor 22 and the second resonant capacitor 23 in series. The current is drawn out through the coil tap to charge the lower voltage side, which avoids different outputs crowding out each other's charging time, improves the maximum output power while ensuring a low cross-regulation rate.

[0095] The idler switch assembly 3 includes: a first idler switch 31 and a second idler switch 32 electrically connected. The first idler switch 31 and the second idler switch 32 are connected in series. The first idler switch 31 is connected in parallel with the first resonant capacitor 22, and the second idler switch 32 is connected in parallel with the second resonant capacitor 23. The first idler switch 31 and the second idler switch 32 correspond to... Figure 2 First idling switch S 1. Second idle switch S 2.

[0096] Depend on Figure 2 It can be seen that the first transistor assembly 4 includes: a first PMOS transistor 41 and a second PMOS transistor 42 electrically connected; the first PMOS transistor 41 and the second PMOS transistor 42 are cross-connected. The first PMOS transistor 41 and the second PMOS transistor 42 correspond to... Figure 2 The first PMOS transistor M P1 The second PMOS transistor M P2 In rectifier circuits, PMOS circuits using a cross-regulating structure have lower overall drive losses and higher overall efficiency.

[0097] Depend on Figure 2It is known that the second transistor assembly 5 includes: a first NMOS transistor 51, a second NMOS transistor 52, a first comparator 53, and a second comparator 54 electrically connected. The non-inverting input terminal of the first comparator 53 is connected to the drain terminal of the first NMOS transistor 51 as one input terminal of the second transistor assembly 5. The inverting input terminal of the first comparator 53 is connected to the source terminal of the first NMOS transistor 51 and then connected to the common terminal of the first load assembly and the second load assembly. The non-inverting input terminal of the second comparator 54 is connected to the drain terminal of the second NMOS transistor 52 as the other input terminal of the second transistor assembly 5. The inverting input terminal of the second comparator is connected to the source terminal of the second NMOS transistor and then connected to the common terminal of the first load assembly and the second load assembly. The first NMOS transistor 51 and the second NMOS transistor 52 correspond to... Figure 2 The first NMOS transistor M in N1 The second NMOS transistor M N2 The first NMOS transistor 51 and the second NMOS transistor 52 are active diode structures. In the rectifier circuit, the overall circuit using an active diode structure for NMOS transistors has lower drive losses and higher overall efficiency.

[0098] Depend on Figure 2 As can be seen, the first load component 6 includes a first load voltage regulator capacitor 61 and a first load resistor 62 connected in parallel, and the second load component 8 is configured with a plurality of load voltage regulator capacitors and load resistors; the first load voltage regulator capacitor 61 is configured to obtain a first DC output voltage; the second load component is configured to obtain a second DC output voltage. It is worth noting that this embodiment uses two load components for illustration, but the rectifier provided in this application can connect multiple load components and a corresponding number of NMOS transistors and PMOS transistors.

[0099] In this embodiment, the control module 1 is further configured to: obtain the load current of the second load component 8 based on the second DC output voltage; obtain the load state of the load current based on the load current; the load state includes: light load state and heavy load state; the light load state and heavy load state represent the load-carrying capacity of the rectifier circuit, wherein the light load state represents that the load rate of the circuit is less than the load rate of the circuit under full load, and the heavy load state represents that the load rate of the circuit is greater than the load rate of the circuit under full load; if the load current is in a light load state, control the idling switch component 3, the first transistor component 4, the second transistor component 5, and the third transistor component 7 to turn on or off, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range; if the load current is in a heavy load state, control the first PMOS transistor 41 and the third transistor component 7 to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range, corresponding to Figure 10 The operating mode of the rectifier is: charge distribution mode.

[0100] In this embodiment, the control module 1 is further configured to: when the load current is under light load, if the first DC output voltage is less than the first DC output voltage reference level and the second DC output voltage is less than the second DC output voltage reference level, then control the first PMOS transistor 41, the second NMOS transistor 52, and the third transistor assembly 7 to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range; correspondingly Figure 7 The rectifier operates in a dual-sided charging mode. If the first DC output voltage is lower than the first DC output voltage reference level, and the second DC output voltage is higher than the second DC output voltage reference level, then the first PMOS transistor 41 and the second NMOS transistor 52 are turned on, so that the first DC output voltage is within the first target voltage range, and the second DC output voltage is within the second target voltage range. Figure 8 The rectifier operates in high-side charging mode. If the first DC output voltage is greater than the first DC output voltage reference level, and the second DC output voltage is greater than the second DC output voltage reference level, then the idle switch assembly 3 is controlled to open, so that the first DC output voltage is within the first target voltage range, and the second DC output voltage is within the second target voltage range. Figure 9 The operating mode of the intermediate rectifier is: idle mode.

[0101] For example, the rectifier can be configured to four operating modes: dual-side charging mode, high-side charging mode, idling mode, and charge distribution mode. The selectable mode depends on the load current at V. OUT2 (I2) conditions. When I2 is under light load, the rectifier operates in dual-side charging mode, high-side charging mode, and idling mode.

[0102] Taking half a cycle as an example, in dual-sided charging mode, M N2 M N3 and M P1 It is currently on. OUT1 and V OUT2 It can be passed through current I respectively AC1 / I AC2 and I AC3 Simultaneous charging within a half-cycle results in an increase in the load voltage for both loads. In high-side charging mode, M... N2 and M P1 It is in the open state, only V OUT1 Through I AC1 / I AC2 Charging. In idle mode, turn on S1 and S2, V OUT1 and V OUT2 Simultaneously reduce. The controller detects V OUT1 and V OUT2 The voltage level generates a corresponding logic state, which will change V. OUT1 and V OUT2 Adjust to the hysteresis window [V] respectively REF1L V REF1H ] and [V REF2L V REF2H That is, within the first target voltage range and the second target voltage range. Throughout the regulation period, the rectifier's power loss is primarily controlled by the active diodes. Compared to current rectifier structures, this application uses NMOS instead of PMOS to implement the active diode structure, and reduces its number to three, thereby reducing power loss, achieving higher rectifier circuit efficiency, and saving rectifier chip area.

[0103] It is worth noting that in this embodiment, two PMOS transistors are provided, namely the first PMOS transistor 41 and the second PMOS transistor 42. During the operation of the rectifier, one PMOS transistor is turned on for each half cycle. That is, the rectifier charges twice in one cycle for full-wave rectification. Figure 13 As shown. Full-wave rectification offers the following advantages over half-wave rectification (charging once per cycle): higher rectification efficiency; less output DC voltage ripple, resulting in better power quality; and suitability for high-power applications, providing a more stable DC power supply.

[0104] For example, when I2 switches to heavy load mode, the rectifier's operating mode switches to charge distribution mode, such as... Figure 10 As shown, M N3 and M P1 It is in the open state. If I2 switches to heavy load mode, the voltage regulation (especially V) will be affected. OUT2 This becomes quite challenging. The worst-case scenario occurs in idle mode, where V... OUT1 and V OUT2 They are all decreasing. For example... Figure 11 As shown, due to the switch of I2 from light load to heavy load, V OUT2 It begins its descent on a faster path, first reaching V. REF2L That is, it is the minimum value within the second target voltage range. However, the above situation cannot trigger the dual-sided charging mode; otherwise, V AC1 and V AC2 This will increase significantly, thereby through M P1 and M P2 The body diode for V OUT1 Unnecessary charging. Until V OUT1 Reaching V REF1L The idling mode will only stop when the voltage is at its minimum within the first target voltage range. Therefore, it is unavoidable that V... OUT2 A significant voltage reduction. On the other hand, through the proposed charge distribution mode and another reference voltage (V) in control module 1. CD Let's solve it together. For example... Figure 12 As shown, when V OUT2 Reaching V CD At this time, the idle mode ends, and then the dual-sided charging mode begins. V OUT2 The descent stops and the increase begins. Additionally, at the end of the dual-sided charging mode, M is turned off. N2 From V OUT1 To V OUT2 A current path emerges and initiates the proposed charge distribution mode. Through this current path, V... OUT1 The accumulated charge at the point helps to alleviate V OUT2 The issue of insufficient charging current has been addressed. The duration of the charge distribution mode (T) has been optimized. CD ), to maintain M P1 The high gate-source voltage provides a small M P1 The on-resistance. After several cycles, V OUT2 Reaching V REF2H That is, the voltage is at its maximum value within the second target voltage range, triggering the idling mode. Therefore, the proposed charge distribution mode eliminates the large V... OUT2 The voltage dropped, and V was successfully reduced. OUT2 Adjust within the hysteresis window [V] CD VREF2H That is, within the third target voltage range.

[0105] Depend on Figure 3 It is known that the control module 1 includes: a first hysteresis comparator 11, a second hysteresis comparator 12, a third hysteresis comparator 13, a D flip-flop assembly 14, a logic gate assembly 15, an inverter chain delay circuit 16, and an inverter assembly 17, all electrically connected; the logic gate assembly 15 includes: a NOR gate, an AND gate, and an OR gate; the first hysteresis comparator 11 is used to determine the first DC output voltage V based on the... OUT1 First DC output voltage reference level V REF1 The first comparison result is obtained; the second hysteresis comparator 12 is used to determine the first comparison result based on the second DC output voltage V. OUT2 Second DC output voltage reference level V REF2 The second comparison result is obtained; the third hysteresis comparator 11 is configured to: based on the second DC output voltage reference level V REF2 Obtain the reference voltage V CD According to the second DC output voltage V REF2 Reference voltage V CD The logic gate component 15 generates a trigger signal based on the first, second, and third comparison results. This trigger signal controls the idle switch component 3, the first transistor component 4, the second transistor component 5, and the third transistor component 7 to open or close, ensuring that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range. The specific process of the logic gate component 15 generating the trigger signal based on the first, second, and third comparison results to control the idle switch component 3, the first transistor component 4, and the second transistor component 5 to open or close can be found in the four operating mode embodiments of the rectifier configuration described above, and will not be repeated here. G CD This represents the charge distribution mode trigger signal, used to control the rectifier to enter one of the four operating modes; G OFF The gate signal representing the idle mode switch is used to control the closing of the idle switch assembly 3.

[0106] In this embodiment, the control module 1 is further configured to: if the load current is under heavy load, control the first PMOS transistor 41 and the third NMOS transistor 53 to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the third target voltage range [V]. CD V REF2HThe third target voltage range is obtained from the reference voltage and the second DC output voltage reference level. The effect of setting the third target voltage range can be seen in the effect of the charge distribution mode described above, and will not be repeated here.

[0107] Depend on Figure 4 It is known that the first comparator 53 and the second comparator 54 include: a PMOS transistor assembly 541 and an NMOS transistor assembly 542 electrically connected; wherein, when the value of the signal to be compared input to the first comparator 53 or the second comparator 54 is greater than the positive value of the supply voltage of the first comparator 53 or the second comparator 54, the first comparator 53 or the second comparator 54 outputs a low level; when the value of the signal to be compared input to the first comparator 53 or the second comparator 54 is less than or equal to the positive value of the supply voltage of the first comparator 53 or the second comparator 54, the first comparator 53 or the second comparator 54 outputs a high level. Wherein, V IN V represents the input signal to be compared to the comparator. DD V represents the positive terminal of the comparator's supply voltage. B V represents the gate bias voltage of an NMOS transistor. SS V represents the negative terminal of the comparator's supply voltage. OUT This represents the output voltage of the comparator. The working principle of the first comparator 53 and the second comparator 54 is as follows: First, the two input terminals of the comparator receive analog signals; second, in the comparison stage, the two input signals are compared with a reference voltage (or another input signal); if the difference between the input signals exceeds a certain threshold (also known as the trigger level), the output state of the comparator will change; finally, the comparator outputs a binary signal, usually represented as a high level or a low level; the output signal reflects the magnitude relationship between the input signal and the reference voltage (or another input signal).

[0108] For example, the rectifier chip uses a 180nm complementary metal-oxide-semiconductor (CMOS) process and has a chip area of ​​1.63 mm². 2 V OUT1 and V OUT2 The maximum load currents I1 and I2 are 33 mA and 15 mA, respectively, and the maximum P OUT The value is 131 mW. The external resonant capacitor C... R1 and C R2 Both are 500 pF, and the external output capacitor C OUT1 and C OUT2 The values ​​are 150 nF and 200 nF, respectively.

[0109] For example, such as Figures 14 to 17This is a schematic diagram of the steady-state performance test of the rectifier, showing the test waveforms of the rectifier circuit input and output voltages and the NMOS gate voltage under different load conditions; under different light / heavy load combinations of I1 and I2, V OUT1 and V OUT2 Within the corresponding hysteresis windows, the voltages were successfully adjusted to 3.3V and 1.6V respectively. Figures 14 to 17 It can be seen that V OUT1 Maximum ripple and V OUT2 The maximum ripple is as small as 50 mV and 75 mV, respectively. Under steady-state conditions, G... N1 G N2 and G N3 This demonstrates the four operating modes of the rectifier. G N1 G N2 and G N3 When both are at high levels, it is in dual-sided charging mode; G N1 and G N2 When it is high, and G N3 When the level is low, it is in high-side charging mode; G N1 G N2 and G N3 When both are low, it is in idle mode; G N1 and G N2 When it is low, and G N3 When it is high, it is in charge distribution mode.

[0110] For example, such as Figures 18 to 19 This is a schematic diagram of the transient performance test of the rectifier, showing the two output voltage waveforms and the load switching signal when the load current changes abruptly. It demonstrates the negligible load transient response and the insignificant cross-regulation output between the two. When I2 changes from 1 mA to 15 mA when I1 is 33 mA, a negligible voltage drop is achieved under load switching due to the proposed charge distribution mode.

[0111] For example, Figure 20 To measure the efficiency of the rectifier circuit under different load conditions, the PMOS active diode was replaced with an NMOS active diode, and the number of high-power transistors was reduced to three. With I² equal to 1 mA, the proposed rectifier achieved the following efficiency under different load conditions: OUT A maximum energy conversion efficiency of 92.2% was achieved at 72.6 mW. With I2 equal to 15 mA, the rectifier circuit maintained an efficiency of over 80%, with a maximum energy conversion efficiency of 89.9%.

[0112] The above detailed embodiments further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A single-stage adjustable voltage rectifier system with multi-output full-wave rectification, characterized in that, include: A rectifier and a control module (1), wherein the rectifier is communicatively connected to the control module (1); The rectifier includes: an electrical connection generation module (2), an idler switch assembly (3), a first transistor assembly (4), a second transistor assembly (5), a first load assembly (6), a second load assembly (8), and a third transistor assembly (7); The generating module (2) includes: an electrically connected tap coil (21), a first resonant capacitor (22), and a second resonant capacitor (23), wherein the first resonant capacitor (22) and the second resonant capacitor (23) are connected in series and then connected in parallel with the tap coil (21); the tap end of the tap coil (21) is connected to the series connection point of the first resonant capacitor (22) and the second resonant capacitor (23); the idle switch assembly (3) includes: an electrically connected first idle switch (31) and a second idle switch (32), wherein the first idle switch (31) and the second idle switch (32) are connected in series, the first idle switch (31) is connected in parallel with the first resonant capacitor (22), and the second idle switch (32) is connected in parallel with the second resonant capacitor (23); The two input terminals of the first transistor assembly (4) are respectively connected to one end of the first resonant capacitor (22) and one end of the second resonant capacitor (23); the output terminal of the first transistor assembly (4) is connected to one end of the first load assembly; the input terminal of the third transistor assembly (7) is connected to the series connection point of the first resonant capacitor (22) and the second resonant capacitor (23), and the output terminal of the third transistor assembly (7) is connected to the second load assembly; the two input terminals of the second transistor assembly (5) are respectively connected to one end of the first resonant capacitor (22) and one end of the second resonant capacitor (23); the output terminal of the second transistor assembly (5) is connected to the common terminal of the first load assembly and the second load assembly; The generating module (2) is used to generate AC input voltage; The first transistor assembly (4), the second transistor assembly (5), and the third transistor assembly (7) are configured as follows: Based on the AC input voltage, a DC output voltage is generated; The first load component (6) and the second load component (8) are configured as follows: Obtain the DC output voltage; The control module (1) is configured as follows: Determine the DC output voltage reference level; The target voltage range is obtained based on the DC output voltage reference level; If the DC output voltage is not within the target voltage range, then the idle switch assembly (3), the first transistor assembly (4), the second transistor assembly (5), and the third transistor assembly (7) are controlled to open or close according to the DC output voltage and the DC output voltage reference level, so that the DC output voltage is within the target voltage range; The third transistor assembly (7) is configured with at least one PMOS transistor or NMOS transistor; the number of the PMOS transistor or the NMOS transistor is determined by the number of the second load assembly (8).

2. The single-stage adjustable voltage rectifier system with multi-output full-wave rectification according to claim 1, characterized in that, The first transistor assembly (4) includes: The first PMOS transistor (41) and the second PMOS transistor (42) are electrically connected; The first PMOS transistor (41) and the second PMOS transistor (42) are cross-connected.

3. The single-stage adjustable voltage rectifier system with multi-output full-wave rectification according to claim 2, characterized in that, The second transistor component (5) includes: The first NMOS transistor (51), the second NMOS transistor (52), the first comparator (53), and the second comparator (54) are electrically connected. The non-inverting input terminal of the first comparator (53) is connected to the drain terminal of the first NMOS transistor (51) as one input terminal of the second transistor assembly (5). The inverting input terminal of the first comparator (53) is connected to the source terminal of the first NMOS transistor (51) and then connected to the common terminal of the first load assembly and the second load assembly. The non-inverting input terminal of the second comparator (54) is connected to the drain terminal of the second NMOS transistor (52) as another input terminal of the second transistor assembly (5). The inverting input terminal of the second comparator is connected to the source terminal of the second NMOS transistor and then connected to the common terminal of the first load assembly and the second load assembly. The first NMOS transistor (51) and the second NMOS transistor (52) are active diode structures.

4. A single-stage adjustable voltage rectifier system with multi-output full-wave rectification according to claim 3, characterized in that, The first load component (6) includes a first load voltage regulator capacitor (61) and a first load resistor (62) connected in parallel, and the second load component (8) is configured with a plurality of load voltage regulator capacitors and load resistors; The first load stabilizing capacitor (61) is configured as follows: Obtain the first DC output voltage; The second load component (8) is configured as follows: Obtain the second DC output voltage.

5. A single-stage adjustable voltage rectifier system with multi-output full-wave rectification according to claim 4, characterized in that, The control module (1) is further configured as follows: Based on the second DC output voltage, obtain the load current of the second load component (8); Based on the load current, the load state of the load current is obtained; the load state includes: light load state and heavy load state; If the load current is in a light load state, control the idling switch assembly (3), the first transistor assembly (4), the second transistor assembly (5), and the third transistor assembly (7) to turn on or off, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range; If the load current is under heavy load, control the first PMOS transistor (41) and the third transistor assembly (7) to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range.

6. A single-stage adjustable voltage rectifier system with multi-output full-wave rectification according to claim 5, characterized in that, The control module (1) is further configured as follows: When the load current is in a light load state, if the first DC output voltage is less than the first DC output voltage reference level and the second DC output voltage is less than the second DC output voltage reference level, then control the first PMOS transistor (41), the second NMOS transistor (52), and the third transistor assembly (7) to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range; If the first DC output voltage is less than the first DC output voltage reference level and the second DC output voltage is greater than the second DC output voltage reference level, then control the first PMOS transistor (41) and the second NMOS transistor (52) to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range; If the first DC output voltage is greater than the first DC output voltage reference level and the second DC output voltage is greater than the second DC output voltage reference level, then the idle switch assembly (3) is controlled to open, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the second target voltage range.

7. A single-stage adjustable voltage rectifier system with multi-output full-wave rectification according to claim 6, characterized in that, The control module (1) includes: The electrical connections include a first hysteresis comparator (11), a second hysteresis comparator (12), a third hysteresis comparator (13), a D flip-flop assembly (14), a logic gate assembly (15), an inverter chain delay circuit (16), and an inverter assembly (17). The first hysteresis comparator (11) is used to obtain a first comparison result based on the first DC output voltage and the first DC output voltage reference level; The second hysteresis comparator (12) is used to obtain a second comparison result based on the second DC output voltage and the second DC output voltage reference level; The third hysteresis comparator (13) is configured as follows: The reference voltage is obtained based on the second DC output voltage reference level; Based on the second DC output voltage and the reference voltage, a third comparison result is obtained; The logic gate component (15) is used to generate a trigger signal based on the first comparison result, the second comparison result, and the third comparison result; the trigger signal is used to control the idle switch component (3), the first transistor component (4), the second transistor component (5), and the third transistor component (7) to turn on or off, so that the first DC output voltage is located within the first target voltage range and the second DC output voltage is located within the second target voltage range.

8. A single-stage adjustable voltage rectifier system with multi-output full-wave rectification according to claim 7, characterized in that, The control module (1) is further configured as follows: If the load current is under heavy load, control the first PMOS transistor (41) and the third transistor assembly (7) to turn on, so that the first DC output voltage is within the first target voltage range and the second DC output voltage is within the third target voltage range; the third target voltage range is obtained by the reference voltage and the reference level of the second DC output voltage.

9. A single-stage adjustable voltage rectifier system with multi-output full-wave rectification according to claim 3, characterized in that, The first comparator (53) and the second comparator (54) include: Electrically connected PMOS transistor assembly (541) and NMOS transistor assembly (542); Specifically, when the value of the signal to be compared input to the first comparator (53) or the second comparator (54) is greater than the positive value of the power supply voltage of the first comparator (53) or the second comparator (54), the first comparator (53) or the second comparator (54) outputs a low level; when the value of the signal to be compared input to the first comparator (53) or the second comparator (54) is less than or equal to the positive value of the power supply voltage of the first comparator (53) or the second comparator (54), the first comparator (53) or the second comparator (54) outputs a high level.

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