A digitally controlled oscillator calibration system

Abstract

The embodiment of the present specification discloses a digitally controlled oscillator calibration system. The system comprises a signal detection component, a phase discriminator, a digitally controlled oscillator gain module, a digital filter and a digitally controlled oscillator, wherein the digitally controlled oscillator is connected with the signal detection component, the signal detection component is connected with the phase discriminator, the phase discriminator is connected with the digitally controlled oscillator gain module, the digitally controlled oscillator gain module is connected with the digital filter, and the digital filter is connected with the digitally controlled oscillator. The embodiment of the present specification can not directly adjust the initial control word, but additionally generate a tuning control word for adjustment, so that the adjustment process is not affected by the size of the initial control word, and the adjustment can be performed with smaller code values, thereby improving the calibration accuracy.

Description

TECHNICAL FIELD

[0001] One or more embodiments of the present specification relate to semiconductor design technology, and more particularly, to a digitally controlled oscillator calibration system. BACKGROUND

[0002] In the working of an all digital phase-locked loop (ADPLL), the precision of the clock depends on the precision of the digitally controlled oscillator (DCO). However, in the actual working process, the output precision of the DCO will be affected when the temperature, voltage, manufacturing process, etc. change, resulting in a deviation in the precision of the clock. The prior art generally reduces the deviation by directly adjusting and controlling the initial control word of the system, but in order to ensure the normal operation and stability of the system, the initial control word corresponds to a larger value, so that the adjustment based on the initial control word also changes the code value by a larger value each time, and the calibration precision is not high. SUMMARY

[0003] To solve the above problems, one or more embodiments of the present specification describe a digitally controlled oscillator calibration system.

[0004] According to a first aspect, a digitally controlled oscillator calibration system is provided, the system comprising a signal detection component, a phase detector, a digitally controlled oscillator gain module, a digital filter and a digitally controlled oscillator, the digitally controlled oscillator being connected to the signal detection component, the signal detection component being connected to the phase detector, the phase detector being connected to the digitally controlled oscillator gain module, the digitally controlled oscillator gain module being connected to the digital filter, and the digital filter being connected to the digitally controlled oscillator;

[0005] The digitally controlled oscillator is configured to generate an output clock signal under the action of an initial control word, and send the output clock signal to the signal detection component;

[0006] The signal detection component is configured to receive the output clock signal and a reference clock signal, and determine a fractional phase of the digitally controlled oscillator;

[0007] The phase detector is configured to determine a total phase error of the digitally controlled oscillator according to the output clock signal, the reference clock signal and the fractional phase;

[0008] The digitally controlled oscillator gain module is configured to determine a digitally controlled oscillator gain according to the total phase error, and send the digitally controlled oscillator gain to the digital filter;

[0009] The digital filter is configured to generate a tuning control word based on the NCO gain and send the tuning control word to the NCO, so that the NCO generates a new output clock signal based on the tuning control word and the initial control word.

[0010] Preferably, the signal detection component comprises a reference phase accumulator, a time-to-digital converter and a variable phase accumulator.

[0011] The reference phase accumulator is configured to accumulate the frequency control word.

[0012] The variable phase accumulator is configured to count the number of output clock cycles.

[0013] The time-to-digital converter is configured to determine the fractional phase between the reference clock signal and the output clock signal.

[0014] Preferably, the phase detector is configured to determine an integer phase based on the reference clock signal transmitted by the reference phase accumulator and the output clock signal transmitted by the variable phase accumulator, and determine a total phase error based on the sum of the integer phase and the fractional phase.

[0015] Preferably, the initial control word is a physical control word, and the system further comprises a separate control module connected to the NCO and configured to generate the initial control word.

[0016] Preferably, the separate control module is disposed outside a phase-locked loop formed by the signal detection component, the phase detector, the NCO gain module, the digital filter and the NCO.

[0017] Preferably, the separate control module stores at least two different physical control words, and the separate control module is configured to select the initial control word from the physical control words based on a system control instruction.

[0018] Preferably, the system further comprises an NCO gain calibration module, and the NCO gain calibration module is connected to the phase detector and the NCO gain module, respectively.

[0019] The NCO gain calibration module is configured to determine two test gains that best match the total phase error based on a lookup table method, adjust the NCO based on the test gains to obtain test clock signals, select a target gain from the test gains based on the phase difference between the two test clock signals, and adjust the NCO gain to the target gain.

[0020] Preferably, the NCO gain calibration module is configured to select the target gain from the test gains based on the phase difference between the two test clock signals within a preset time length.

[0021] Preferably, the target gain is the test gain with small gain when the phase difference value is greater than the preset difference value, and the target gain is the test gain with large gain when the phase difference value is not greater than the preset difference value.

[0022] The system provided by the embodiment of the present specification can determine the gain of the numerically controlled oscillator according to the gain module of the numerically controlled oscillator after the total phase error is determined by the phase discriminator, and then generate a corresponding tuning control word by the digital filter and send it to the numerically controlled oscillator, so that the numerically controlled oscillator adjusts the output clock signal according to the tuning control word and the initial control word. In the above process, the initial control word is not directly adjusted, but an additional tuning control word is generated for adjustment, so that the adjustment process is not affected by the size of the initial control word, and the adjustment can be performed with smaller code values, thereby improving the calibration accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0024] Figure 1 is a structural schematic diagram of a numerically controlled oscillator calibration system in an embodiment of the present specification.

[0025] Figure 2 is a phase comparison schematic diagram of the test gain in a preset time length in an embodiment of the present specification. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application.

[0027] In the following description, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance. The following description provides several embodiments of the present application, and different embodiments can be replaced or combined, so the present application can also be considered to include all possible combinations of the same and / or different embodiments described. Therefore, if one embodiment includes features A, B, C, and another embodiment includes features B, D, the present application should also be considered to include one or more embodiments of all other possible combinations of A, B, C, and D, although the embodiment may not be explicitly described in the following.

[0028] The following description provides examples, and is not intended to limit the scope, applicability or example set forth in the claims. Alterations and further modifications of the described elements are possible without departing from the scope of the application. Various examples can omit, substitute, or add various procedures or components as appropriate. For instance, the methods described can be performed in an order different than described, and various steps can be added, omitted, or combined. Also, features described with respect to some examples can be combined in other examples.

[0029] Referring to Figure 1 , Figure 1 is a system structure schematic diagram of a numerically controlled oscillator calibration system provided by an embodiment of the present application. In the embodiment of the present application, the system comprises a signal detection component, a phase discriminator, a numerically controlled oscillator gain module, a digital filter, and a numerically controlled oscillator, the numerically controlled oscillator is connected with the signal detection component, the signal detection component is connected with the phase discriminator, the phase discriminator is connected with the numerically controlled oscillator gain module, the numerically controlled oscillator gain module is connected with the digital filter, and the digital filter is connected with the numerically controlled oscillator;

[0030] The numerically controlled oscillator is configured to generate an output clock signal under the action of an initial control word, and send the output clock signal to the signal detection component;

[0031] The signal detection component is configured to receive the output clock signal and a reference clock signal, and determine a fractional phase of the numerically controlled oscillator;

[0032] The phase discriminator is configured to determine a total phase error of the numerically controlled oscillator according to the output clock signal, the reference clock signal, and the fractional phase;

[0033] The numerically controlled oscillator gain module is configured to determine a numerically controlled oscillator gain according to the total phase error, and send the numerically controlled oscillator gain to the digital filter;

[0034] The digital filter is configured to generate a tuning control word according to the numerically controlled oscillator gain, and send the tuning control word to the numerically controlled oscillator, so that the numerically controlled oscillator generates a new output clock signal based on the tuning control word and the initial control word.

[0035] In the embodiment of the present application, the signal detection component, the phase detector, the digitally controlled oscillator gain module, the digital filter and the digitally controlled oscillator are connected in sequence to form a phase-locked loop. A frequency control word (fcw) is set in the system to determine the expected frequency of the digitally controlled oscillator DCO output. Assuming that the reference clock signal is 25M and the DCO output is 2.5G, the frequency control word is equal to 2.5G / 25M = 100. In addition, there is an initial control word pbank in the system, which is used to set the corresponding initial value of the digitally controlled oscillator to reduce the initial phase error and speed up the locking speed. When the system starts to work, the fcw and pbank are both given the default value set in advance. After the default value is given, the digitally controlled oscillator DCO will oscillate. The output clock signal ckv will pass through the signal detection component to detect the real-time phase corresponding to the output clock signal. At the same time, the reference clock signal refclk and the frequency control word fcw will also pass through the signal detection component to detect the corresponding reference phase. The detected phase data will be input into the phase detector PD to calculate the total phase error between the actual output clock signal and the reference clock signal. Then, the phase detector PD will send the total phase error to the digitally controlled oscillator gain module, which is configured with a mapping relationship between different phase differences and gains. Through the mapping relationship, the digitally controlled oscillator gain corresponding to the total phase error can be quickly determined. After the digitally controlled oscillator gain is input into the digital loop filter (DLF), it will be smoothed and filtered to further reduce the error. Since the gain is the ratio of the output frequency change amount to the input control word change amount, the control word change amount that needs to be adjusted can be determined according to the specific value of the digitally controlled oscillator gain, and then the corresponding tuning control word abank is generated and input into the digitally controlled oscillator. The tuning control word only represents the control word corresponding to the part that needs to be adjusted, so the digitally controlled oscillator will still combine the initial control word and the tuning control word to perform oscillation control based on the combined control word to output a new output clock signal, thereby adjusting the output precision of the DCO.

[0036] In an implementation manner, the signal detection component comprises a reference phase accumulator, a time-to-digital converter and a variable phase accumulator.

[0037] The reference phase accumulator is configured to accumulate the frequency control word.

[0038] The variable phase accumulator is configured to count the number of output clock cycles.

[0039] The time-to-digital converter is configured to determine the fractional phase between the reference clock signal and the output clock signal.

[0040] In the embodiments of the present application, the signal detection component mainly consists of a reference phase accumulator (RPA), a time-to-digital converter (TDC) and a variable phase accumulator (VPA). The reference phase accumulator accumulates the frequency control word to determine the reference clock signal according to the accumulation result, and the reference clock signal obtained by the accumulation is generally an integer. The time-to-digital converter inputs the reference clock signal refclk and the output clock signal ckv at the same time to calculate the fractional phase difference between the reference clock signal and the output clock signal. The variable phase accumulator counts the number of output clock cycles to determine the output clock signal according to the counting result, and the output clock signal counted is also generally an integer. Through the above three components, the integer signal of the reference clock signal and the output clock signal is collected, and the fractional phase of the reference clock signal and the output clock signal is calculated, so that the phase detection result is more accurate.

[0041] In an implementation, the phase detector is configured to determine an integer phase according to the reference clock signal transmitted by the reference phase accumulator and the output clock signal transmitted by the variable phase accumulator, and determine the total phase error according to the sum of the integer phase and the fractional phase.

[0042] In the embodiments of the present application, the reference clock signal transmitted by the reference phase accumulator and the output clock signal transmitted by the variable phase accumulator are integer signals, and the phase detector calculates the integer phase of the reference clock signal and the output clock signal, and then determines the total phase error according to the sum of the integer phase and the fractional phase obtained from the time-to-digital converter.

[0043] In an implementation, the initial control word is a physical control word, and the system further comprises an independent control module connected to the digitally controlled oscillator and configured to generate the initial control word.

[0044] In the embodiments of the present application, the initial control word is different from the tuning control word, and is a physical control word used to optimize the performance of the phase-locked loop, and is generated by an independent control module specially connected to the digitally controlled oscillator. The independent control module is responsible for generating or adjusting certain control signals, but does not directly participate in the phase detection and frequency adjustment of the loop.

[0045] In an implementation, the independent control module is arranged outside the phase-locked loop consisting of the signal detection component, the phase detector, the gain module of the digitally controlled oscillator, the digital filter and the digitally controlled oscillator.

[0046] In the embodiments of the present application, the independent control module is arranged outside the phase-locked loop of the system, so that the physical control word is separated from the loop of the phase-locked loop, the total delay of the loop is reduced, the structure of the loop is simplified, and the physical control word can be optimized and adjusted independently, thereby accelerating the locking process of the phase-locked loop.

[0047] In an implementation, the independent control module stores at least two different physical control words, and the independent control module is configured to select the initial control word from the physical control words according to the system control instruction.

[0048] In the embodiments of the present disclosure, the independent control module can pre-store a plurality of physical control words with different initial values. During system operation, the system control instruction set by the user is acquired to determine the approximate output clock range that the user wants the system to achieve, and then the physical control word that best matches the output clock range is selected from the physical control words as the initial control word, thereby improving the stability of the system and avoiding the need to greatly adjust the output clock for the tuning control word.

[0049] In an implementation, the system further comprises a digitally controlled oscillator gain calibration module connected with the phase detector and the digitally controlled oscillator gain module, respectively.

[0050] The digitally controlled oscillator gain calibration module is configured to determine two test gains that best match the total phase error according to a lookup table method, adjust the digitally controlled oscillator according to the test gains respectively to obtain test clock signals, and select a target gain from the test gains according to the phase difference between the two test clock signals, and adjust the digitally controlled oscillator gain to the target gain.

[0051] In the embodiments of the present application, considering that it is difficult to accurately adjust the loop in one adjustment process in actual situations, and the total phase error has a decimal value, if the tuning control word is set for each total phase error considering the decimal, too many tuning control words need to be set in advance, and the tuning control words are too subdivided, and the accuracy of adjustment cannot be significantly improved between the subdivided tuning control words. Therefore, in order to improve the processing efficiency, a certain number of tuning control words abank can be set in advance into the digitally controlled oscillator gain calibration module, each tuning control word corresponds to a gain, that is, a test gain, and a mapping table of the control word and the gain is constructed. The digitally controlled oscillator gain calibration module determines the two test gains that are most matched with the error gain corresponding to the total phase error by looking up the mapping table. Then, the digitally controlled oscillator is adjusted according to the test tuning control words corresponding to the two test gains, respectively, to detect the phases of the output clock signals after adjustment, and then the phase difference value of the two phase results is calculated. If the phase difference value is large, it means that the digitally controlled oscillator is very sensitive to the change of the control word, and a small gain needs to be used to avoid excessive adjustment and maintain the stability of the system. If the phase difference value is small, it means that the digitally controlled oscillator is not sensitive to the change of the control word, and a large gain can be used to improve the response speed of the system. Therefore, the gain selection strategy is determined according to the specific size of the phase difference value, and then the target gain is selected from the two test gains, and the digitally controlled oscillator gain is optimized and calibrated according to the target gain.

[0052] In an implementation manner, the digitally controlled oscillator gain calibration module is configured to select a target gain from the test gains according to a phase difference value of the two test clock signals within a preset time length.

[0053] In the embodiments of the present application, as shown in Figure 2 Assuming that the phase corresponding to the tuning control word abank_a is phe_a, and the phase corresponding to the tuning control word abank_b is phe_b, the phase diagrams of the two test clock signals are obtained, the phase difference value of the two phase diagrams within a preset time length is calculated, and then the gain selection strategy is determined according to the size of the phase difference value, and the target gain is selected from the test gains.

[0054] In an implementation manner, the target gain is the test gain with a small gain when the phase difference value is greater than a preset difference value, and the target gain is the test gain with a large gain when the phase difference value is not greater than the preset difference value.

[0055] In the embodiments of the present application, a preset difference is set. If the phase difference value is greater than the preset difference, it is considered that the phase difference value is large, and the test gain with small gain is selected. If the phase difference value is not less than the preset difference, it is considered that the phase difference value is small, and the test gain with large gain is selected.

[0056] The above description is merely that of example embodiments of this disclosure, and cannot limit the scope of this disclosure. That is, any equivalent changes and modifications made according to the teachings of this disclosure are still within the scope of this disclosure. Those skilled in the art, after considering the specification and practicing the disclosure herein, will readily conceive of other embodiments of this disclosure. This application is intended to cover any variations, uses, or adaptive changes of this disclosure that follow the general principles of this disclosure and include common knowledge or conventional technical means in the art not described in this disclosure. The specification and examples are merely considered as exemplary, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A digitally controlled oscillator calibration system, characterized by, The system comprises a signal detection component, a phase discriminator, a digitally controlled oscillator gain module, a digital filter and a digitally controlled oscillator, the digitally controlled oscillator is connected with the signal detection component, the signal detection component is connected with the phase discriminator, the phase discriminator is connected with the digitally controlled oscillator gain module, the digitally controlled oscillator gain module is connected with the digital filter, and the digital filter is connected with the digitally controlled oscillator; The digitally controlled oscillator is configured to generate an output clock signal under the action of an initial control word and send the output clock signal to the signal detection component; The signal detection component is configured to receive the output clock signal and a reference clock signal and determine a fractional phase of the digitally controlled oscillator; The phase discriminator is configured to determine a total phase error of the digitally controlled oscillator according to the output clock signal, the reference clock signal and the fractional phase; The digitally controlled oscillator gain module is configured to determine a digitally controlled oscillator gain according to the total phase error and send the digitally controlled oscillator gain to the digital filter; The digital filter is configured to generate a tuning control word according to the digitally controlled oscillator gain and send the tuning control word to the digitally controlled oscillator, so that the digitally controlled oscillator generates a new output clock signal based on the tuning control word and the initial control word.

2. The system of claim 1, wherein, The signal detection component comprises a reference phase accumulator, a time-to-digital converter and a variable phase accumulator; The reference phase accumulator is configured to accumulate a frequency control word; The variable phase accumulator is configured to count the number of output clock cycles; The time-to-digital converter is configured to determine a fractional phase between the reference clock signal and the output clock signal.

3. The system of claim 1, wherein, The initial control word is a physical control word, and the system further comprises an independent control module connected with the digitally controlled oscillator and configured to generate the initial control word.

4. The system of claim 3, wherein, The independent control module is arranged outside a phase-locked loop loop formed by the signal detection component, the phase discriminator, the digitally controlled oscillator gain module, the digital filter and the digitally controlled oscillator.

5. The system of claim 3, wherein, The independent control module stores at least two different physical control words, and the independent control module is configured to select the initial control word from the physical control words according to a system control instruction.

6. The system of claim 1, wherein, The system further comprises a digitally controlled oscillator gain calibration module connected with the phase discriminator and the digitally controlled oscillator gain module; The digitally controlled oscillator gain calibration module is configured to determine two test gains that are most matched with the total phase error according to a lookup table method, adjust the digitally controlled oscillator according to the test gains to obtain test clock signals, select a target gain from the test gains according to the phase difference between the two test clock signals, and adjust the digitally controlled oscillator gain to the target gain.

7. The system of claim 6, wherein, The digitally controlled oscillator gain calibration module is configured to select a target gain from the test gains according to the phase difference between the two test clock signals within a preset time length.

8. The system of claim 6, wherein, When the phase difference is greater than a preset difference value, the target gain is the test gain with a smaller gain, and when the phase difference is not greater than the preset difference value, the target gain is the test gain with a larger gain.

Images