Delay matching down-conversion receiving device for broadcasting station

Abstract

The invention discloses a broadcast station time delay matching down-conversion receiving device, relates to the technical field of broadcast signal monitoring and integrated circuit design, and solves the problem of inaccurate positioning and monitoring precision in the existing broadcast program signal monitoring work. The receiving device comprises a signal input end, an analog-to-digital converter, a clock generator, an A-path signal down converter, a B-path signal down converter, an A-path intermediate-frequency filter, a B-path intermediate-frequency filter, an A-path intermediate-frequency signal output end, a B-path signal output end and a system clock. According to the invention, two radio station signals with different frequencies can share one analog processing circuit and share one analog-to-digital converter, and down-conversion receiving can be simultaneously carried out on the two radio station signals only by triggering of one analog-to-digital conversion sampling clock. According to the method, a multiplier in a traditional down-conversion circuit does not exist, and accurate time delay matching can be realized before the two radio signals are subjected to subsequent processing, so that the accuracy of positioning monitoring is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of broadcast signal monitoring and integrated circuit design, and in particular to a delay matching down-conversion receiving device for a broadcasting station. Background Art

[0002] In the work of monitoring broadcast program signals, it is sometimes necessary to locate and monitor radio station signals. For example, the patent number is: ZL201610065637.8, and the patent name is: A method for quickly locating and monitoring illegal radio stations using reference signals. In the prior art, a positioning monitoring method is proposed, which is to synchronously receive the signal of the same illegal radio station at multiple preset fixed monitoring stations, and synchronously receive the signal of a legal radio station with a known position; after these signals are transmitted back to the monitoring center, by comparing the known position information of the legal radio station, the monitoring center can refer to this information to accurately calculate the coordinate position of the illegal radio station; it is worth noting that for any preset fixed monitoring station, when synchronously receiving the two different frequency signals of the illegal radio station and the legal radio station, the delay characteristics of the two receivers in signal processing must reach high The basic working principle of the receiver is that for each frequency signal, a down-conversion circuit is needed to convert the signal into an intermediate frequency signal, and then the clutter signal is filtered out through the built-in intermediate frequency bandpass filter. In this design, not only can a down-conversion circuit only process signals of one frequency, but also an analog-to-digital conversion circuit is required for each program. However, since the group delay characteristics of the bandpass filter are closely related to its bandwidth, and the circuits of the two receivers in actual production, especially those analog circuit parts that process high-frequency signals, inevitably have errors in frequency response, bandwidth control, and analog-to-digital conversion. These errors accumulated will directly affect the accuracy of positioning monitoring. In order to overcome this problem, it is urgent to design a broadcast station delay matching down-conversion receiving device to solve the above problems. Summary of the invention

[0003] The present invention provides a time delay matching down-conversion receiving device for a broadcasting station to solve the problem of inaccurate positioning monitoring in the existing broadcasting program signal monitoring work.

[0004] A broadcast station delay matching down-conversion receiving device, the receiving device comprising a signal input terminal, an analog-to-digital converter, a clock generator, a channel A signal down-converter, a channel B signal down-converter, a channel A intermediate frequency filter, a channel B intermediate frequency filter, a channel A intermediate frequency signal output terminal, a channel B signal output terminal and a system clock CLOCK;

[0005] The system clock CLOCK is used to provide a clock signal to the A-channel signal down-converter, the B-channel signal down-converter, the A-channel intermediate frequency filter and the B-channel intermediate frequency filter;

[0006] The A-channel signal and the B-channel signal are superimposed and input from the signal input terminal at the same time, and are converted into digital signals by the analog-to-digital converter. Under the control of the clock signal output by the clock generator, the digital signals are down-converted by the A-channel signal down-converter and the B-channel signal down-converter respectively. The converted signals are filtered out of the A-channel signal and the B-channel signal by the A-channel intermediate frequency filter and the B-channel intermediate frequency filter respectively. The intermediate frequency signal of the A-channel signal is output to the outside of the device through the A-channel intermediate frequency signal output terminal, and the intermediate frequency signal of the B-channel signal is output to the outside of the device through the B-channel signal output terminal.

[0007] Beneficial effects of the present invention:

[0008] The receiving device described in the present invention can share an analog processing circuit and a common analog-to-digital converter for two radio signals of different frequencies, and can simultaneously perform down-conversion reception on the two radio signals by being triggered by only one analog-to-digital conversion sampling clock.

[0009] The method of the present invention not only does not have a multiplier in a traditional down-conversion circuit, but also enables accurate time delay matching of two radio station signals before subsequent processing, thereby improving the accuracy of positioning monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is an overall block diagram of the delay matching down-conversion receiving device for a broadcasting station according to the present invention;

[0011] Figure 2 It is a principle block diagram of a clock generator in a broadcast station delay matching down-conversion receiving device according to the present invention;

[0012] Figure 3 This is a schematic diagram of the down-converter circuit in the broadcast station delay matching down-conversion receiving device of the present invention. DETAILED DESCRIPTION

[0013] Combination Figures 1 to 3 The present embodiment is described, a broadcast station delay matching down-conversion receiving device, the whole device is composed of a signal input terminal, an analog-to-digital converter, a clock generator, an A-channel signal down-converter, a B-channel signal down-converter, an A-channel intermediate frequency filter, a B-channel intermediate frequency filter, an A-channel intermediate frequency signal output terminal, a B-channel signal output terminal and a system clock CLOCK;

[0014] The system clock CLOCK is used to provide a clock signal to the A-channel signal down converter, the B-channel signal down converter, the A-channel intermediate frequency filter and the B-channel intermediate frequency filter;

[0015] The two broadcast signals are channel A signal and channel B signal, which are superimposed together and input from the signal input terminal at the same time, and are converted into superimposed digital signals by the same analog-to-digital converter; under the control of multiple clock signals output by the clock generator, the superimposed digital signals are down-converted by the channel A signal down-converter and the channel B signal down-converter respectively, and the converted signals are then filtered out of the channel A signal and the channel B signal by two identical digital filters, the channel A intermediate frequency filter and the channel B intermediate frequency filter, respectively, and the intermediate frequency signals are output from the channel A intermediate frequency signal output terminal and the channel B signal output terminal to the outside of the device respectively. The two intermediate frequency signals not only have the same frequency, but also have the same delay matching performance.

[0016] like Figure 1 As shown, the thick wires are parallel digital buses, and the thin wires are single conductors. The specific connections are as follows;

[0017] The signal input terminal is electrically connected to the analog input pin of the analog-to-digital converter;

[0018] The digital output terminal of the analog-to-digital converter is respectively connected to the analog-to-digital conversion data input terminal DATA of the A-channel signal down converter and the analog-to-digital conversion data input terminal DATA of the B-channel signal down converter through a bus;

[0019] The output end of the A-channel signal down converter is connected to the input end of the A-channel intermediate frequency filter through a bus;

[0020] The output end of the B-channel signal down converter is connected to the input end of the B-channel intermediate frequency filter through a bus;

[0021] The output end of the intermediate frequency filter of channel A is connected to the intermediate frequency signal output end of channel A through a bus;

[0022] The output end of the intermediate frequency filter of channel B is connected to the intermediate frequency signal output end of channel B through a bus;

[0023] The system clock CLOCK is used to provide a clock signal to the A-channel signal down-converter, the B-channel signal down-converter, the A-channel intermediate frequency filter, and the B-channel intermediate frequency filter; the system clock CLOCK is electrically connected to the clock signal input terminal CLK of the A-channel signal down-converter, the clock signal input terminal CLK of the B-channel signal down-converter, the clock input terminal of the A-channel intermediate frequency filter, and the clock input terminal of the B-channel intermediate frequency filter respectively;

[0024] The analog-to-digital sampling signal output terminal FS of the clock generator is electrically connected to the CP clock input terminal of the analog-to-digital converter, the analog-to-digital conversion clock terminal FS of the A-channel signal down-converter, and the analog-to-digital conversion clock terminal FS of the B-channel signal down-converter respectively;

[0025] The numerical output terminal MA of the clock generator is connected to the Gray code input terminal MG of the A-channel signal down converter by a bus; the numerical output terminal MB of the clock generator is connected to the Gray code input terminal MG of the B-channel signal down converter by a bus;

[0026] The output terminal FA of the clock generator is electrically connected to the local oscillator signal input terminal FD of the A-channel signal down converter;

[0027] The output terminal FB of the clock generator is electrically connected to the local oscillator signal input terminal FD of the B-channel signal down-converter.

[0028] In this embodiment, the analog-to-digital sampling signal output terminal FS of the clock generator outputs an analog-to-digital sampling clock signal fs, the numerical output terminal MA outputs the A-channel signal residual data ma, the output terminal FA outputs the A-channel local oscillator signal fa, the numerical output terminal MB outputs the B-channel signal residual data mb, and the output terminal FB outputs the B-channel local oscillator signal fb; the two intermediate frequency data output from the A-channel signal intermediate frequency output terminal and the B-channel signal intermediate frequency output terminal of the entire receiving device are only synchronized with the system clock CLOCK, and are not synchronized with the clock signal generated by any clock generator.

[0029] like Figure 2 As shown, Figure 2 The structure block diagram of the clock generator is shown in FIG. 1 . In addition to the analog-to-digital sampling signal output terminal FS, the numerical output terminal MA, the output terminal FA, the numerical output terminal MB and the output terminal FB, the output terminal of the clock generator also includes a reference oscillator, a voltage-controlled oscillator FS, a phase detector FS, an M Gray code synchronous counter, an L divider, a J divider, a phase detector FA, a K divider, a voltage-controlled oscillator FA, an A data latch, a V divider, a phase detector FB, a W divider, a voltage-controlled oscillator FB and a B data latch. The specific connections are as follows:

[0030] The output end of the reference oscillator is electrically connected to the input ends of the L frequency divider, the J frequency divider, and the V frequency divider respectively;

[0031] The output terminal of the L frequency divider is electrically connected to the first input terminal of the phase detector FS;

[0032] The output end of the phase detector FS is electrically connected to the input end of the voltage controlled oscillator FS;

[0033] The output end of the voltage controlled oscillator FS is electrically connected to the output end FS and the clock input end of the M Gray code synchronous counter respectively;

[0034] The overflow output terminal of the M Gray code synchronous counter is electrically connected to the second input terminal of the phase detector FS;

[0035] An output terminal of the J frequency divider is electrically connected to a first input terminal of the phase detector FA;

[0036] The output end of the phase detector FA is electrically connected to the input end of the voltage controlled oscillator FA;

[0037] The output end of the voltage controlled oscillator FA is electrically connected to the output end FA, the CP clock end of the A data latch, and the input end of the K frequency divider respectively;

[0038] The output end of the K frequency divider is electrically connected to the second input end of the phase detector FA;

[0039] The output terminal of the V frequency divider is electrically connected to the first input terminal of the phase detector FB;

[0040] The output end of the phase detector FB is electrically connected to the input end of the voltage controlled oscillator FB;

[0041] The output end of the voltage controlled oscillator FB is electrically connected to the output end FB, the CP clock end of the B data latch, and the input end of the W frequency divider respectively;

[0042] The output terminal of the W frequency divider is electrically connected to the second input terminal of the phase detector FB;

[0043] The output terminal Q of the A data latch is electrically connected to the numerical output terminal MA;

[0044] The output terminal Q of the B data latch is electrically connected to the value output terminal MB;

[0045] The data output terminal of the M Gray code synchronous counter is electrically connected to the D input terminal of the A data latch and the D input terminal of the A data latch respectively.

[0046] In the present embodiment, the analog-to-digital acquisition signal output terminal FS of the clock generator provides an analog-to-digital conversion clock for the analog-to-digital converter, the output terminal FA provides a local oscillator signal fa for the A-channel signal down-converter, and the output terminal FB provides a local oscillator signal fb for the B-channel signal down-converter; under the condition that the frequency of the reference oscillator is f, if the frequency division coefficient of the J divider is j and the frequency division coefficient of the K divider is k, then the frequency fa of the output signal at the output terminal FA is j*f / k; if the frequency division coefficient of the V divider is v and the frequency division coefficient of the W divider is w, then the frequency fb of the output signal at the output terminal FB is w*f / v; if the overflow value of the M Gray code synchronous counter is m and the frequency division coefficient of the L divider is l, then the frequency fs of the output signal at the analog-to-digital sampling signal output terminal FS is m*f / l; the M Gray code synchronous counter must be directly designed in the form of a synchronous sequential logic circuit, and the existing method of adding a binary to Gray code conversion encoder to the back end of the binary counter cannot be used in the present device. In this device, the overflow value of the M Gray code synchronous counter is m, which is determined by the bit width N of the digitized data and is 2 to the power of N. Taking 8 bits as an example to design the circuit, the value of m is 256.

[0047] In this embodiment, the function of the entire device can be achieved by either rising edge latching or falling edge latching. The circuit is designed by taking the rising edge latching method as an example; at the rising edge of the output signal at the output terminal FA, the A data latch latches the current value in the M Gray code synchronous counter, and then sends it to the numerical output terminal MA; at the rising edge of the output signal at the output terminal FB, the B data latch latches the current value in the M Gray code synchronous counter, and then sends it to the numerical output terminal MB.

[0048] The minimum frequency fx of the system clock CLOCK is determined by the maximum value fm of the local oscillator signal fa and the local oscillator signal fb, and the bit width N of the digitized data. fx must be higher than N+2 times of fm. The specific circuit is designed based on the bit width N=8 as an example.

[0049] The analog-to-digital sampling clock signal fs outputted from the analog-to-digital sampling signal output terminal FS of the clock generator must be more than 4 times higher than the highest frequency between the A-channel signal and the B-channel signal; the local oscillator signal fa must be lower than the frequency of the A-channel signal; the local oscillator signal fb must be lower than the frequency of the B-channel signal; regardless of whether it is the A-channel signal or the B-channel signal, the intermediate frequency of the down-converted output is equal to the signal frequency minus the frequency of the local oscillator signal.

[0050] like Figure 3 As shown, in this embodiment, Figure 3 The circuit structure diagram of the down converter is shown in Figure 1, where the thick line is a parallel digital bus and the thin line is a single wire. There are two down converters in the whole device, and their internal structures are exactly the same. In addition to the clock signal input terminal CLK, the local oscillator signal input terminal FD, the analog-to-digital conversion clock FS, the analog-to-digital conversion data input terminal DATA and the Gray code input terminal MG, each down converter also includes a positive and negative two-input AND gate U1, a positive and negative two-input OR gate U2, a positive and negative two-input AND gate U3, a D flip-flop U4, a positive and negative two-input AND gate U5, a D flip-flop U6, a D flip-flop U7, a data latch U8, a data latch U9, a data latch U10, a data latch U 11, Gray code to binary converter U12, loadable left shift counter U13, binary counter U14, D flip-flop U15, data selector U16, inverter U17, loadable right shift counter U18, three-input AND gate U19, four-input NOR gate U20, inverter U21, data latch U22, data selector U23, OR gate U24, data selector U25, OR gate U26, adder U27, data selector U28, data latch U29, data selector U30 and data output terminal DAX;

[0051] The clock signal input terminal CLK is electrically connected to the C input terminal of the D flip-flop U4, the C input terminal of the data latch U9, the C input terminal of the data latch U11, the C input terminal of the loadable left shift counter U13, the C input terminal of the binary counter U14, the C input terminal of the D flip-flop U15, the C input terminal of the loadable right shift counter U18, the C input terminal of the data latch U22 and the C input terminal of the data latch U29 respectively;

[0052] The local oscillator signal input terminal FD is electrically connected to the positive input terminal of the positive and negative two-input AND gate U5 and the D input terminal of the D flip-flop U6 respectively;

[0053] The analog-to-digital conversion clock FS is electrically connected to the C input terminal of the D flip-flop U6, the C input terminal of the D flip-flop U7, the C input terminal of the data latch U8, and the C input terminal of the data latch U10 respectively;

[0054] The analog-to-digital conversion data input terminal DATA is electrically connected to the D input terminal of the data latch U8 and the D input terminal of the data latch U10 respectively using a digital bus;

[0055] Gray code input terminal MG is electrically connected to the input terminal of Gray code to binary converter U12 by a digital bus;

[0056] The output terminal of the positive and negative two-input AND gate U1 is electrically connected to the first input terminal of the positive and negative two-input OR gate U2;

[0057] The Q output terminal of the D flip-flop U6 is electrically connected to the negative input terminal of the positive and negative two-input AND gate U5;

[0058] The output end of the positive and negative two-input AND gate U5 is electrically connected to the D input end of the D flip-flop U7 and the latch enable CE input end of the data latch U8 respectively;

[0059] The output terminal of the D flip-flop U7 is electrically connected to the positive input terminal of the positive and negative two-input AND gate U3, the D input terminal of the D flip-flop U4, and the latch enable CE input terminal of the data latch U10;

[0060] The Q output terminal of the D flip-flop U4 is electrically connected to the negative input terminal of the positive and negative two-input AND gate U3;

[0061] The output end of the positive and negative two-input AND gate U3 is respectively electrically connected to the second input end of the positive and negative two-input OR gate U2, the latch enable CE input end of the data latch U9, the latch enable CE input end C EY of the data latch U11 and the data load LD input end of the loadable left shift counter U13;

[0062] The output terminal of the positive and negative two-input OR gate U2 is electrically connected to the D input terminal of the D flip-flop U15;

[0063] The output end of the D flip-flop U15 is electrically connected to the positive input end of the positive and negative two-input AND gate U1, the shift enable SR input end of the left shift counter U13, the count enable CE end of the binary counter U14, the S0 input end of the data selector U16, the shift enable SR input end of the right shift counter U18, and the fourth input end of the four-input NOR gate U20;

[0064] The output end of the four-input NOR gate U20 is electrically connected to the data load enable LD input end of the loadable right shift counter U18, the S0 input end of the data selector U23, the first input end of the OR gate U24, and the second input end of the OR gate U26;

[0065] The output terminal of the loadable left shift counter U13 is electrically connected to the S0 input terminal of the data selector U25;

[0066] The output terminal of the OR gate U24 is electrically connected to the S0 input terminal of the data selector U30;

[0067] The output end of the three-input AND gate U19 is electrically connected to the negative input end of the positive and negative two-input AND gate U1, the synchronous clear CLR input end of the binary counter U14, the second input end of the OR gate U24, the first input end of the OR gate U26, the S0 input end of the data selector U28, and the latch enable CE input end of the data latch U29;

[0068] The output terminal of the OR gate U26 is electrically connected to the carry CI input terminal of the adder U27;

[0069] The Q0 output terminal of the binary counter U14 is electrically connected to the first input terminal of the three-input AND gate U19 and the first input terminal of the four-input NOR gate U20 respectively;

[0070] The Q1 output terminal of the binary counter U14 is electrically connected to the second input terminal of the three-input AND gate U19 and the second input terminal of the four-input NOR gate U20 respectively;

[0071] The Q2 output terminal of the binary counter U14 is electrically connected to the third input terminal of the three-input AND gate U19 and the third input terminal of the four-input NOR gate U20 respectively;

[0072] The output end of the Gray code to binary converter U12 is electrically connected to the D input end of the loadable left shift counter U13 by a digital bus;

[0073] The output terminal of the data latch U8 is electrically connected to the D input terminal of the data latch U9 by a digital bus;

[0074] The output terminal of the data latch U10 is electrically connected to the D input terminal of the data latch U11 by a digital bus;

[0075] The output terminal of the data latch U9 is electrically connected to the D1 input terminal of the data selector U30 by a digital bus;

[0076] The output terminal of the data latch U11 is electrically connected to the input terminal of the inverter U17 by a digital bus;

[0077] The output terminal of the inverter U17 is electrically connected to the D1 input terminal of the data selector U23 by a digital bus;

[0078] The output terminal of the data selector U23 is electrically connected to the D0 input terminal of the data selector U28 by a digital bus;

[0079] The output terminal of the data selector U16 is electrically connected to the D input terminal of the data latch U22 by a digital bus;

[0080] The output end of the data latch U22 is electrically connected to the input end of the inverter U21 and the D0 input end of the data selector U23 respectively by a digital bus;

[0081] The output terminal of the inverter U21 is electrically connected to the D1 input terminal of the data selector U28 by a digital bus;

[0082] The output terminal of the loadable right shift counter U18 is electrically connected to the D1 input terminal of the data selector U25 by a digital bus;

[0083] The output terminal of the data selector U25 is electrically connected to the D0 input terminal of the data selector U30 by a digital bus;

[0084] The output terminal of the data selector U28 is electrically connected to the A0 input terminal of the adder U27 by a digital bus;

[0085] The output terminal of the data selector U30 is electrically connected to the B0 input terminal of the adder U27 via a digital bus;

[0086] The S0 output terminal of the adder U27 is electrically connected to the D input terminal of the data latch U29, the D1 input terminal of the data selector U16, and the D input terminal of the loadable right shift counter U18 respectively by a digital bus;

[0087] The C0 output terminal of adder U27 is left floating;

[0088] The D0 input terminal of the data selector U16 and the D0 input terminal of the data selector U25 are grounded;

[0089] The output terminal of the data latch U29 is electrically connected to the data output terminal DAX via a digital bus.

[0090] exist Figure 3In the embodiment, the analog signal input from the analog-to-digital conversion data input terminal DATA is converted into digital data after being converted by the analog-to-digital converter; the D flip-flop U6, the positive and negative two-input AND gate U5, and the D flip-flop U7 form a first edge detector. Whenever a rising edge appears at the local oscillator signal input terminal FD, the data latch U8 and the data latch U10 will latch the data before and after the rising edge respectively; the D flip-flop U4 and the positive and negative two-input AND gate U3 form a second edge detector. When the data latch U10 completes latching the data after the rising edge of the local oscillator signal input terminal FD, the second edge detector will trigger the subsequent circuit to start executing the specific down-conversion calculation; the positive and negative two-input OR gate U2, the D flip-flop U15, the positive and negative two-input AND gate U1, the binary counter U14 and the three-input AND gate U19 forms a trigger hold counting circuit, which determines the number of calculations in the down-conversion calculation step; the three-input AND gate U19 is designed to set the synchronous clear terminal CLR of the binary counter U14 when the count value of the binary counter U14 accumulates from 0 to 7, so that the binary counter U14 can accumulate counts from 0 to 7, a total of 8 value states; if the circuit bit width is not 8 bits, then just change the Gray code to binary converter U12 to a binary AND gate element consistent with the circuit bit width and connect it to the output end of the binary counter U14, so that when the binary counter U14 counts to the binary value corresponding to the bit width, the synchronous clear terminal of the binary counter U14 is set; when the second edge detector detects the rising edge, the D flip-flop U15 delays the binary counter U14 by one clock before starting counting.

[0091] In the initial state, the data in the binary counter U14 is 0, and because the second edge detector does not detect any edge, the output of the D flip-flop U15 remains 0, resulting in the count enable terminal of the binary counter U14 also being 0, and the binary counter U14 will always keep the data at 0; only when the second edge detector successfully identifies the rising edge signal, the rising edge of the clock signal input terminal CLK that arrives subsequently will activate the circuit, thereby starting the following calculation steps;

[0092] At the rising edge of the first clock signal input terminal CLK, while the data latch U9 latches the data at the output terminal of the data latch U8, not only the data at the output terminal of the data latch U10 is latched by the data latch U11, but also the data at the output terminal of the Gray code to binary converter U12 is latched by the data latch U13; at this time, because the output of the D flip-flop U15 is 0, the data selector U16 sends the data 0 to the input terminal of the data latch U22, making the content of the data latch U22 0, and because the count enable terminal of the binary counter U14 is 0 at this time, the binary counter U14 still keeps the internal data at 0; only after the rising edge of the first clock signal input terminal CLK, the output of the D flip-flop U15 becomes 1, making the count enable terminal of the binary counter U14 valid, and the rising edge of the clock signal input terminal CLK that appears later will accumulate the value in the binary counter U14.

[0093] At the rising edge of the second clock signal input terminal CLK, the output of the four-input NOR gate U20 is 1, which makes the output of the OR gate U24 1, causing the data selector U30 to send the data in the data latch U9 to the B input terminal of the adder U27; at the same time, the data in the data latch U11 is inverted by the inverter U17, and appears at the output terminal of the data selector U23 because the output of the four-input NOR gate U20 is 1. At this time, because the output of the three-input AND gate U19 is 0, the A input terminal of the adder U27 will receive the opposite data to that in the data latch U11; and because the output of the four-input NOR gate U20 is 1, so that the data synchronization loading terminal LD ​​of the loadable right shift counter U18 is 1, and at the same time it causes the OR gate U26 to set the carry input terminal of the adder U27 to 1, so after the rising edge of the second clock signal input terminal CLK, the content in the data latch U22 is equal to the value in the data latch U9 plus the value in the data latch U11 plus 1; because when the circuit is connected, it is necessary to shift the output bus of the adder U27 right by one position and connect it to the bus D input terminal of the loadable right shift counter U18, so at this time the value in the loadable right shift counter U18 is equal to the value in the data latch U22 shifted right by one position.

[0094] At the rising edge of the third clock signal input terminal CLK, because the value in the binary counter U14 is no longer 0, the output of the four-input NOR gate U20 is 0, so the data selector U23 selects to output the data in the data latch U22 to the D0 input terminal of the data selector U28; because the value in the binary counter U14 is not equal to 7 at this time, the output of the three-input AND gate U19 is 0, causing the data selector U28 to send the data in the data latch U22 to the A input terminal of the adder U27; at this time, because the outputs of the four-input NOR gate U20 and the three-input AND gate U19 are both 0, the output of the OR gate U24 is also 0, causing the data selector U30 to send the data output by the data selector U25 to the B input terminal of the adder U27; the selection of the data selector U25 The end is electrically connected to the 7th bit of the loadable left shift counter U13, and the left shift enable end of the loadable left shift counter U13 and the right shift enable end of the loadable right shift counter U18 are connected to the count enable end of the binary counter U14, so when the binary counter U14 accumulates counts, the loadable left shift counter U13 will perform a left shift calculation at the same time, and the loadable right shift counter U18 will also perform a right shift calculation at the same time; if the 7th bit of the loadable left shift counter U13 is a high level, the data selector U25 selects the data output of the loadable right shift counter U18, otherwise the data output by the data selector U25 is 0; after the rising edge of the third clock signal input terminal CLK, the data calculated by the adder U27 will be saved in the data latch U22;

[0095] At the rising edge of the fourth to the eighth clock signal input terminal CLK, the circuit will repeat the effect produced at the rising edge of the third clock signal input terminal CLK, that is, if the 7th bit of the loadable left shift counter U13 is 1, then the value in the loadable right shift counter U18 is added to the value in the data latch U22, otherwise the value 0 is added to the value in the data latch U22, and the sum of the two calculations will be stored in the data latch U22; from the fourth to the eighth clock signal input terminal CLK, each rising edge will cause the data in the loadable left shift counter U13 to shift left by one bit, and will also cause the value in the loadable right shift counter U18 to shift right by one bit, and the value in the binary counter U14 to accumulate until the value in the binary counter U14 is equal to 7 after the rising edge of the eighth clock signal input terminal CLK;

[0096] At the rising edge of the ninth clock signal input terminal CLK, because the value in the binary counter U14 is equal to 7, the output of the three-input AND gate U19 is 1, so that the output of U15 in the trigger hold counting circuit becomes 0; the output of the three-input AND gate U19 is 1, which not only causes the data selector U28 to select the data in the data latch U22 and then send it to the A input terminal of the adder U27 after being inverted by the inverter U21, but also causes the data selector U30 to select the data in the data latch U9 and send it to the B input terminal of the adder U27; because the data lock enable terminal of the data latch U29 is 1, the sum of the adder U27 is latched by the data latch U29 and output from the data output terminal DAX; at the same time, because the synchronous clear terminal of the binary counter U14 is 1, the value in the binary counter U14 becomes 0; after the rising edge of the ninth clock signal input terminal CLK, the trigger hold counting circuit ends the circuit hold state, and the count enable terminal of the binary counter U14 becomes 0;

[0097] From the rising edge of the tenth clock signal input terminal CLK, the circuit returns to the initial state; it can be seen that this circuit can start by itself, even if the hardware reset circuit is not designed, then only the data obtained after the first round of calculation steps is wrong, and the repeated calculation steps can automatically return the circuit to the initial state. Therefore, there is no need to design a reset circuit, and the data obtained from the first round of calculation steps can be directly discarded to obtain the correct signal data in the subsequent period.

[0098] In this implementation manner, the digital data outputted from the output terminals DAX of the A-channel signal down-converter and the A-channel signal down-converter respectively need to pass through the two digital band-pass filters, the A-channel intermediate frequency filter and the B-channel intermediate frequency filter, respectively, to effectively filter out interference signals of other stray frequencies, and finally the intermediate frequency data of the A-channel signal is outputted from the A-channel signal intermediate frequency output terminal, and the intermediate frequency data of the B-channel signal is outputted from the B-channel signal output terminal; wherein the A-channel intermediate frequency filter and the B-channel intermediate frequency filter are exactly the same digital filters, and both work synchronously under the same system clock CLOCK, and will inevitably produce exactly the same time delay;

[0099] It can be seen that when the two broadcast signals are input into this device, they use the same analog circuit part and are converted into digital signals by the same analog-to-digital converter. Under the same system clock synchronization, they are digitally down-converted and the same digital filter is used to filter out noise. Finally, the two broadcast programs each obtain two intermediate frequency signals with the same frequency; therefore, the time delay of the two program contents can be accurately matched.

[0100] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A broadcast station delay matching down-conversion receiving device, characterized in that: The receiving device includes a signal input terminal, an analog-to-digital converter, a clock generator, a channel A signal down-converter, a channel B signal down-converter, a channel A intermediate frequency filter, a channel B intermediate frequency filter, a channel A intermediate frequency signal output terminal, a channel B signal output terminal and a system clock CLOCK; The system clock CLOCK is used to provide a clock signal to the A-channel signal down-converter, the B-channel signal down-converter, the A-channel intermediate frequency filter and the B-channel intermediate frequency filter; The A-channel signal and the B-channel signal are superimposed and input from the signal input terminal at the same time, and are converted into digital signals by the analog-to-digital converter. Under the control of the clock signal output by the clock generator, the digital signals are down-converted by the A-channel signal down-converter and the B-channel signal down-converter respectively. The converted signals are filtered out of the A-channel signal and the B-channel signal by the A-channel intermediate frequency filter and the B-channel intermediate frequency filter respectively. The intermediate frequency signal of the A-channel signal is output to the outside of the device through the A-channel intermediate frequency signal output terminal, and the intermediate frequency signal of the B-channel signal is output to the outside of the device through the B-channel signal output terminal.

2. The broadcast station delay matching down-conversion receiving device according to claim 1, characterized in that: The signal input terminal is electrically connected to the analog input pin of the analog-to-digital converter; The digital output end of the analog-to-digital converter is respectively connected to the analog-to-digital conversion data input end DATA of the A-channel signal down converter and the analog-to-digital conversion data input end DATA of the B-channel signal down converter through a bus; The output end of the A-channel signal down-converter is connected to the input end of the A-channel intermediate frequency filter through a bus; The output end of the B-channel signal down converter is connected to the input end of the B-channel intermediate frequency filter through a bus; The output end of the intermediate frequency filter of channel A is connected to the intermediate frequency signal output end of channel A through a bus; The output end of the intermediate frequency filter of channel B is connected to the intermediate frequency signal output end of channel B through a bus; The system clock CLOCK is used to provide a clock signal to the A-channel signal down-converter, the B-channel signal down-converter, the A-channel intermediate frequency filter, and the B-channel intermediate frequency filter; The system clock CLOCK is electrically connected to the clock signal input terminal CLK of the A-channel signal down-converter, the clock signal input terminal CLK of the B-channel signal down-converter, the clock input terminal of the A-channel intermediate frequency filter, and the clock input terminal of the B-channel intermediate frequency filter respectively; The analog-to-digital sampling signal output terminal FS of the clock generator is electrically connected to the CP clock input terminal of the analog-to-digital converter, the analog-to-digital conversion clock terminal FS of the A-channel signal down-converter, and the analog-to-digital conversion clock terminal FS of the B-channel signal down-converter respectively; The numerical output terminal MA of the clock generator is connected to the Gray code input terminal MG of the A-channel signal down converter by a bus; the numerical output terminal MB of the clock generator is connected to the Gray code input terminal MG of the B-channel signal down converter by a bus; The output terminal FA of the clock generator is electrically connected to the local oscillator signal input terminal FD of the A-channel signal down converter; The output terminal FB of the clock generator is electrically connected to the local oscillator signal input terminal FD of the B-channel signal down-converter.

3. The broadcast station delay matching down-conversion receiving device according to claim 1, characterized in that: The analog-to-digital sampling signal output terminal FS of the clock generator outputs an analog-to-digital sampling clock signal fs, the numerical output terminal MA outputs the residual data ma of the A-channel signal to the A-channel signal down-converter, the output terminal FA outputs the A-channel local oscillator signal fa to the A-channel signal down-converter, the numerical output terminal MB outputs the residual data mb of the B-channel signal to the B-channel signal down-converter, and the output terminal FB outputs the B-channel local oscillator signal fb to the B-channel signal down-converter; The two intermediate frequency data outputted through the intermediate frequency output terminal of the A-channel signal and the intermediate frequency output terminal of the B-channel signal are both synchronized with the system clock CLOCK.

4. The broadcast station delay matching down-conversion receiving device according to claim 1, characterized in that: The clock generator also includes a reference oscillator, a voltage-controlled oscillator FS, a phase detector FS, an M Gray code synchronous counter, an L frequency divider, a J frequency divider, a phase detector FA, a K frequency divider, a voltage-controlled oscillator FA, an A data latch, a V frequency divider, a phase detector FB, a W frequency divider, a voltage-controlled oscillator FB and a B data latch; The output end of the reference oscillator is electrically connected to the input ends of the L frequency divider, the J frequency divider, and the V frequency divider respectively; The output end of the L frequency divider is electrically connected to the first input end of the phase detector FS, the output end of the phase detector FS is electrically connected to the input end of the voltage-controlled oscillator FS, the output end of the voltage-controlled oscillator FS is electrically connected to the analog-to-digital sampling signal output end FS and the clock input end of the M Gray code synchronous counter respectively, and the overflow output end of the M Gray code synchronous counter is electrically connected to the second input end of the phase detector FS; The output end of the J frequency divider is electrically connected to the first input end of the phase detector FA, the output end of the phase detector FA is electrically connected to the input end of the voltage-controlled oscillator FA, the output end of the voltage-controlled oscillator FA is electrically connected to the output end FA, the CP clock end of the A data latch and the input end of the K frequency divider respectively; the output end of the K frequency divider is electrically connected to the second input end of the phase detector FA; The output end of the V frequency divider is electrically connected to the first input end of the phase detector FB, the output end of the phase detector FB is electrically connected to the input end of the voltage-controlled oscillator FB, the output end of the voltage-controlled oscillator FB is electrically connected to the output end FB, the CP clock end of the B data latch and the input end of the W frequency divider respectively; the output end of the W frequency divider is electrically connected to the second input end of the phase detector FB; The output terminal Q of the A data latch is electrically connected to the numerical output terminal MA; The output terminal Q of the B data latch is electrically connected to the value output terminal MB; The data output terminal of the M Gray code synchronous counter is electrically connected to the D input terminal of the A data latch and the D input terminal of the B data latch respectively.

5. The broadcast station delay matching down-conversion receiving device according to claim 4, characterized in that: The analog-to-digital sampling signal output terminal FS of the clock generator outputs an analog-to-digital sampling clock signal fs, the output terminal FA outputs an A-channel local oscillator signal fa to the A-channel signal down-converter, and the output terminal FB outputs a B-channel local oscillator signal fb to the B-channel signal down-converter; when the frequency of the reference oscillator is f, the frequency division coefficient of the J frequency divider is set to j, and the frequency division coefficient of the K frequency divider is set to k, then the frequency fa=j*f / k of the output signal at the output terminal FA; the frequency division coefficient of the V frequency divider is set to v, and the frequency division coefficient of the W frequency divider is set to w, then the frequency fb=w*f / v of the output signal at the output terminal FB; Assuming the overflow value of the M Gray code synchronous counter to be m and the frequency division coefficient of the L frequency divider to be l, the frequency fs of the output signal at the analog-to-digital sampling signal output terminal FS is equal to m*f / l; the overflow value m of the M Gray code synchronous counter is determined by the bit width N of the digitized data.

6. The broadcast station delay matching down-conversion receiving device according to claim 1, characterized in that: The structure of the A-channel signal down-converter is the same as that of the B-channel signal down-converter; both include a first edge detector composed of a D flip-flop U6, a positive and negative two-input AND gate U5, and a D flip-flop U7; a second edge detector composed of a D flip-flop U4 and a positive and negative two-input AND gate U3; a trigger holding counting circuit composed of a positive and negative two-input OR gate U2, a D flip-flop U15, a positive and negative two-input AND gate U1, a binary counter U14, and a three-input AND gate U19; When a rising edge appears at the local oscillator signal input terminal FD, the data latch U8 and the data latch U10 will latch the data before and after the rising edge respectively; when the data latch U10 completes latching the data after the rising edge of the local oscillator signal input terminal FD, the second edge detector triggers the subsequent circuit to start the down-conversion calculation; the three-input AND gate U19 is designed to set the synchronous clear terminal CLR of the binary counter U14 when the count value of the binary counter U14 accumulates from 0 to 7, so as to realize the binary counter U14 accumulating counts from 0 to 7, a total of 8 value states.

7. The broadcast station delay matching down-conversion receiving device according to claim 6, characterized in that: It also includes a data latch U8, a data latch U9, a data latch U10, a data latch U11, a Gray code to binary converter U12, a loadable left shift counter U13, a data selector U16, an inverter U17, a loadable right shift counter U18, a four-input NOR gate U20, an inverter U21, a data latch U22, a data selector U23, an OR gate U24, a data selector U25, an OR gate U26, an adder U27, a data selector U28, a data latch U29, a data selector U30 and a data output terminal DAX; The clock signal input terminal CLK is respectively connected to the C input terminal of the D flip-flop U4, the C input terminal of the data latch U9, the C input terminal of the data latch U11, the C input terminal of the loadable left shift counter U13, the C input terminal of the binary counter U14, the C input terminal of the D flip-flop U15, the C input terminal of the loadable right shift counter U18, the C input terminal of the data latch U22 and the C input terminal of the data latch U29; The local oscillator signal input terminal FD is connected to the positive input terminal of the positive and negative two-input AND gate U5 and the D input terminal of the D flip-flop U6 respectively; The analog-to-digital conversion clock FS is respectively connected to the C input terminal of the D flip-flop U6, the C input terminal of the D flip-flop U7, the C input terminal of the data latch U8, and the C input terminal of the data latch U10; The analog-to-digital conversion data input terminal DATA is connected to the D input terminal of the data latch U8 and the D input terminal of the data latch U10 respectively using a digital bus; Gray code input terminal MG is connected to the input terminal of Gray code to binary converter U12 by digital bus; The output terminal of the positive and negative two-input AND gate U1 is connected to the first input terminal of the positive and negative two-input OR gate U2; The Q output terminal of the D flip-flop U6 is connected to the negative input terminal of the positive and negative two-input AND gate U5; The output end of the positive and negative two-input AND gate U5 is connected to the D input end of the D flip-flop U7 and the latch enable CE input end of the data latch U8 respectively; The output terminal of the D flip-flop U7 is respectively connected to the positive input terminal of the positive and negative two-input AND gate U3, the D input terminal of the D flip-flop U4, and the latch enable CE input terminal of the data latch U10; The Q output terminal of the D flip-flop U4 is connected to the negative input terminal of the positive and negative two-input AND gate U3; The output end of the positive and negative two-input AND gate U3 is respectively connected to the second input end of the positive and negative two-input OR gate U2, the latch enable CE input end of the data latch U9, the latch enable CE input end C EY of the data latch U11 and the data load LD input end of the loadable left shift counter U13; The output terminal of the positive and negative two-input OR gate U2 is connected to the D input terminal of the D flip-flop U15; The output end of the D flip-flop U15 is respectively connected to the positive input end of the positive and negative two-input AND gate U1, the shift enable SR input end of the left shift counter U13, the count enable CE end of the binary counter U14, the S0 input end of the data selector U16, the shift enable SR input end of the right shift counter U18, and the fourth input end of the four-input NOR gate U20; The output end of the four-input NOR gate U20 is respectively connected to the data load enable LD input end of the loadable right shift counter U18, the S0 input end of the data selector U23, the first input end of the OR gate U24, and the second input end of the OR gate U26; The output terminal of the loadable left shift counter U13 is connected to the S0 input terminal of the data selector U25; The output terminal of the OR gate U24 is connected to the S0 input terminal of the data selector U30; The output end of the three-input AND gate U19 is respectively connected to the negative input end of the positive and negative two-input AND gate U1, the synchronous clear CLR input end of the binary counter U14, the second input end of the OR gate U24, the first input end of the OR gate U26, the S0 input end of the data selector U28, and the latch enable CE input end of the data latch U29; The output terminal of the OR gate U26 is connected to the carry CI input terminal of the adder U27; The Q0 output terminal of the binary counter U14 is connected to the first input terminal of the three-input AND gate U19 and the first input terminal of the four-input NOR gate U20 respectively; The Q1 output terminal of the binary counter U14 is connected to the second input terminal of the three-input AND gate U19 and the second input terminal of the four-input NOR gate U20 respectively; The Q2 output terminal of the binary counter U14 is connected to the third input terminal of the three-input AND gate U19 and the third input terminal of the four-input NOR gate U20 respectively; The output end of the Gray code to binary converter U12 is connected to the D input end of the loadable left shift counter U13 by a digital bus; The output terminal of the data latch U8 is connected to the D input terminal of the data latch U9 by a digital bus; The output terminal of the data latch U10 is connected to the D input terminal of the data latch U11 by a digital bus; The output terminal of the data latch U9 is connected to the D1 input terminal of the data selector U30 by a digital bus; The output of the data latch U11 is connected to the input of the inverter U17 by a digital bus; The output terminal of the inverter U17 is connected to the D1 input terminal of the data selector U23 by a digital bus; The output terminal of the data selector U23 is connected to the D0 input terminal of the data selector U28 by a digital bus; The output terminal of the data selector U16 is connected to the D input terminal of the data latch U22 by a digital bus; The output end of the data latch U22 is connected to the input end of the inverter U21 and the D0 input end of the data selector U23 respectively by a digital bus; The output terminal of the inverter U21 is connected to the D1 input terminal of the data selector U28 by a digital bus; The output terminal of the loadable right shift counter U18 is connected to the D1 input terminal of the data selector U25 by a digital bus; The output terminal of the data selector U25 is connected to the D0 input terminal of the data selector U30 by a digital bus; The output terminal of the data selector U28 is connected to the A0 input terminal of the adder U27 by a digital bus; The output terminal of the data selector U30 is connected to the B0 input terminal of the adder U27 by a digital bus; The S0 output terminal of the adder U27 is electrically connected to the D input terminal of the data latch U29, the D1 input terminal of the data selector U16 and the D input terminal of the loadable right shift counter U18 respectively by a digital bus; The C0 output terminal of the adder U27 is suspended; the D0 input terminal of the data selector U16 and the D0 input terminal of the data selector U25 are grounded; the output terminal of the data latch U29 is electrically connected to the data output terminal DAX via a digital bus.

8. The broadcast station delay matching down-conversion receiving device according to claim 1, characterized in that: The A-channel intermediate frequency filter and the B-channel intermediate frequency filter are completely identical digital filters.

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