Multi-master multi-slave full duplex communication method based on arbitration selection single-line multiplexing mechanism

Abstract

The invention discloses a multi-master multi-slave full-duplex communication method based on an arbitration selection single-line multiplexing mechanism, which comprises the following steps of: S1, carrying out arbitration based on line XOR and modulo 2 operation, and determining winning master equipment according to high-order priority; s2, the winning master device sends a slave device address and receives a slave device response completion selection; s3, the master device sends data from the input line through the master output, and the slave device receives the data; s4, the slave device sends data through the arbitration selection line, and the master device receives the data; s5, the master device and the slave device judge the data integrity according to the check bit; s6, synchronizing data sampling and transmission of the master device and the slave device through a clock line; s7, selecting a communication mode through a register, and adjusting a data transmission time sequence; and S8, the main device turns over the level for three times and sends a communication ending signal. Through arbitration selection and a single-line multiplexing mechanism, efficient and reliable full-duplex communication among multiple master devices and multiple slave devices is realized, and the communication efficiency and expansibility are improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism. Background Art

[0002] In modern electronic systems, multi-master and multi-slave communication is widely used in embedded systems, industrial automation and distributed computing environments, and is an important basis for achieving multi-device collaboration. However, the existing multi-master and multi-slave communication protocols still have many technical limitations and challenges in practical applications, and it is difficult to meet the requirements for efficiency, reliability and flexibility in complex communication scenarios. 2 Taking common protocols such as SPI (Serial Peripheral Interface) and SPI as examples, these traditional communication protocols have failed to fully solve key issues such as multi-master device competition arbitration, communication efficiency and bus utilization due to design limitations.

[0003] I 2 The I C protocol is a common multi-master and multi-slave communication protocol with low power consumption and high device compatibility. 2 The bus contention problem of I C is quite serious. Its arbitration mechanism is based on the wired AND operation of the master device and uses a simple low-level priority rule for arbitration. This method is prone to cause bus congestion in scenarios where multiple master devices compete. 2 The transmission rate of the I C protocol is limited, and the maximum rate it usually supports is only a few hundred kilobits per second (such as 100 kbps for standard mode and 400 kbps for fast mode), which cannot meet the needs in scenarios where high-speed data transmission is required. 2 The C protocol is highly dependent on clock signals in communication and is easily affected by noise, resulting in signal loss or errors. Especially in multi-master scenarios, due to the synchronization requirements of bus signals, the hardware design complexity increases, the scalability is poor, and it is difficult to adapt to the needs of high-bandwidth communication.

[0004] In contrast, the SPI protocol has an advantage in transmission rate, and its full-duplex communication mode allows master and slave devices to achieve parallel data transmission. However, the multi-master and multi-slave implementation of the SPI protocol is relatively complex and usually requires additional hardware support, such as additional chip select lines for device selection, which directly increases the complexity of hardware circuit design. In addition, the SPI protocol lacks a complete arbitration mechanism in a multi-master device environment, and cannot effectively solve the problem of multiple master devices competing for the bus, which is prone to bus conflicts. More importantly, the chip select mechanism of SPI limits the number of slave devices, has poor scalability, and cannot meet the needs of large-scale device access in complex systems.

[0005] Another common problem with the above protocols is the lack of reliability and integrity of data transmission. Traditional communication protocols usually only support simple parity check or cyclic redundancy check (CRC) for data verification, but in the face of noise interference, signal conflict or hardware failure in complex environments, the error rate of data transmission is still high. In addition, these protocols lack dynamic verification mechanisms. When the communication signal is interfered, real-time error detection and repair are often not possible, thus affecting the communication reliability of the system.

[0006] Clock synchronization is also an important technical challenge in multi-device communication. Existing communication protocols usually rely on a single master device to generate a global clock for clock signal generation and synchronization, which is easily affected by hardware jitter and signal interference, resulting in inconsistent data transmission. Especially in scenarios that require long-distance or high-frequency transmission, the real-time and stability of data transmission are difficult to guarantee due to the limitations of the clock synchronization mechanism.

[0007] Based on the above technical background, the existing multi-master and multi-slave communication protocols have several significant defects. First, in the scenario of multi-master device competition, the traditional protocol lacks an efficient and flexible arbitration mechanism, which easily causes waste of bus resources and reduced communication efficiency. Secondly, the rate and reliability of data transmission fail to meet the needs of modern high-bandwidth and high-real-time applications, especially when multiple devices communicate concurrently, the transmission mechanism of the existing protocol has a significant bottleneck. In addition, the hardware design of the traditional protocol is highly complex and has poor scalability, making it difficult to adapt to the flexible requirements for multi-device access in various scenarios. Finally, the technical deficiencies of the existing protocol in clock synchronization, data verification, and full-duplex communication implementation further limit its scope of application and performance.

[0008] Therefore, how to provide a multi-master and multi-slave full-duplex communication method based on an arbitration selection single-line multiplexing mechanism is a problem that those skilled in the art need to solve urgently. Summary of the invention

[0009] One purpose of the present invention is to propose a multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism. The present invention makes full use of communication protocol design, data link layer optimization and clock synchronization control technology, and describes in detail the process of realizing efficient communication of multiple master devices through bit-by-bit high priority arbitration, modulo-two operation arbitration selection mechanism and dynamic mode configuration. The method realizes full-duplex communication between master and slave devices on the basis of ensuring the simplification of hardware design, and has the advantages of high communication efficiency, fast and reliable arbitration, strong scalability and stable data transmission.

[0010] The multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism according to an embodiment of the present invention comprises the following steps:

[0011] S1, through the arbitration selection line, based on the line XOR and modulo 2 operation, all master devices send arbitration addresses bit by bit, detect the change of the arbitration selection line level, arbitrate according to the bit high priority, and determine the winning master device;

[0012] S2, the winning master device sends the slave device address through the master output slave input line, and the arbitration selection line waits for the response signal of the slave device. The slave device responds to the address query of the master device and performs slave device selection;

[0013] S3, the winning master device sends data to the selected slave device through the master output slave input line, and the slave device receives the data through the arbitration selection line;

[0014] S4, the selected slave device sends data to the master device through the arbitration selection line, and the master device receives data through the master output slave input line, thereby realizing full-duplex communication between the master device and the slave device;

[0015] S5. During data transmission, the master device and the slave device determine the integrity of the data based on the check bit;

[0016] S6. Signal synchronization is performed through the clock line. The master device synchronously sends the clock signal on the clock line to coordinate data sampling and transmission between the master device and the slave device.

[0017] S7, select the communication mode through the data change sampling high bit and the data change sampling low bit in the register, including mode 0, mode 1, mode 2 and mode 3, and determine the data transmission timing between the master device and the slave device;

[0018] S8. When the communication is completed, the master device continuously flips the level three times through the master output slave input line, defines the communication end signal, and terminates the current data transmission between the master device and the slave device.

[0019] Optionally, the S1 specifically includes:

[0020] S11, each master device sends the arbitration address bit by bit on the arbitration selection line, each bit of the address is sent according to the unit arbitration interval of the clock signal, and the high-order address is arbitrated first;

[0021] S12, each master device compares the current bit value of its arbitration address with the level state of the arbitration selection line. If the sent bit value is 1 and the level state of the arbitration selection line is 0, it is determined that the master device has lost arbitration and exits;

[0022] S13. For any master device, the relationship between its arbitration address bit value and the arbitration selection line level value is determined by modulo-2 operation. If the calculation result is not 0, it is determined that the master device has lost arbitration:

[0023] a i ⊕L i=0;

[0024] Among them, ⊕ represents the XOR operation, a i Indicates the arbitration address bit value currently sent by the master device, L i Indicates the current level status of the arbitration selection line;

[0025] S14, at the end of the unit arbitration interval, the master device that has not exited continues to send the next arbitration address and repeats the judgment process of S12 and S13 until all address bits are sent;

[0026] S15. After completing arbitration of all bits, the remaining master device is the arbitration winning device, outputs the arbitration result and restores the arbitration selection line to a high level, indicating the end of the arbitration process.

[0027] Optionally, the S2 specifically includes:

[0028] S21, after the arbitration is completed, the winning master device sends the target slave device address through the master output slave input line, and the address is a binary code of fixed length;

[0029] S22, during the sending of the target slave device address, the arbitration selection line remains at a low level, indicating that the master device is selecting the target slave device;

[0030] S23, the target slave device compares the received address value with its own preset device address to determine whether it matches:

[0031] R = B ⊕ A;

[0032] Wherein, R represents the matching result. If R=0, it indicates that the address matching is successful and the target slave device is ready to enter the communication state; if R≠0, the slave device remains in the idle state;

[0033] S24, after the target slave device successfully matches, it sends a response signal to the master device through the arbitration selection line. The response signal is a binary value. If the response signal value is 1, it means that the target slave device is ready to receive data. If the response signal value is 0, it means that the target slave device is not ready.

[0034] S25. After receiving the response signal, the winning master device determines whether the target slave device is available. If the response signal value is 1, the data transmission phase is entered; if the response signal value is 0, the master device re-initiates the slave device selection process.

[0035] Optionally, the S3 specifically includes:

[0036] S31, after the slave device selection is completed, the winning master device sends a data frame to the target slave device through the master output slave input line;

[0037] S32, the data frame is sent synchronously through the clock signal, the master device changes the data output state at each rising edge of the clock signal, and the target slave device samples the received data signal at each falling edge of the clock;

[0038] S33, the target slave device parses the received data field and check field to verify the data integrity:

[0039] R c =f(D ′ ,C ′ );

[0040] Among them, f(D ′ ,C ′ ) is the verification function, if R c =0, it means the data is complete; if R c ≠0, the target slave device generates an error flag;

[0041] S34, after receiving the complete data frame, the target slave device returns a data reception confirmation signal to the master device through the arbitration selection line. If the confirmation signal value is 1, it indicates that the data is received successfully. If the confirmation signal value is 0, it indicates that the data is received unsuccessfully.

[0042] S35. The winning master device determines the data transmission result according to the received confirmation signal. If the confirmation signal value is 1, the next communication process is entered; if the confirmation signal value is 0, the data frame is resent.

[0043] Optionally, the S4 specifically includes:

[0044] S41, after receiving the data frame sent by the master device and verifying it successfully, the target slave device loads its own data frame to be sent;

[0045] S42, the target slave device sends a data frame to the winning master device through the arbitration selection line. During the data transmission process, the clock signal synchronization is used to coordinate data sampling. The slave device changes the output state at the rising edge of the clock, and the master device samples and receives data at the falling edge of the clock.

[0046] S43, the winning master device performs integrity check on the received data field and check field of the target slave device;

[0047] S44, the winning master device parses the data field and performs corresponding operations according to the value of the data frame control field;

[0048] S45, if the check result value is 0, the winning master device sends a data reception confirmation signal to the target slave device through the master output slave input line, wherein the confirmation signal is 1, indicating that the data is received successfully, and the confirmation signal is 0, indicating that the data is received unsuccessfully;

[0049] S46. The target slave device performs an operation according to the state of the confirmation signal. If the value of the confirmation signal is 0, the target slave device resends the data frame; if the value of the confirmation signal is 1, the current data sending process ends.

[0050] Optionally, the S5 specifically includes:

[0051] S51, after completing the data transmission, the master device and the slave device perform a verification operation on the received complete data frame;

[0052] S52: The master device and the slave device respectively apply a verification algorithm to the received data field and the verification field to perform data integrity verification:

[0053]

[0054] Among them, R is the check result, m is the number of bits in the data field, and d′ i is the i-th bit of the received data field, mod2 is the modulo 2 operation, ⊕ represents the XOR operation, and C′ is the received check value;

[0055] S53, if the check result value is 0, the master device and the slave device respectively generate a data reception success flag, wherein the data reception success flag value is 1, indicating that the data is complete and ready to enter the next communication stage;

[0056] S54, if the check result value is not 0, the master device and the slave device generate a data reception failure flag, wherein the data reception failure flag value is 0, and trigger a resending mechanism, and the sender reconstructs and transmits the data frame;

[0057] S55, after completing the data verification, the master device and the slave device respectively parse the control field. If the control field indicates that the current communication phase is over, both parties clear the receiving and sending buffers to release communication resources;

[0058] S56. If the control field indicates entering the next communication phase, the master device and the slave device update the communication status table according to the verification result, store the verified data frames into the corresponding storage area, and wait for the next clock signal synchronization instruction.

[0059] Optionally, the S6 specifically includes:

[0060] S61, before data transmission starts, the winning master device sends a clock signal to the target slave device through a clock line, where the clock signal is generated by the master device;

[0061] S62, during the clock synchronization process, the master device and the slave device sample data according to the edge of the clock signal, the master device changes the output data state at the rising edge of the clock, and the slave device samples data at the falling edge of the clock;

[0062] S63, the slave device determines whether a complete data frame is received according to the timing rule of clock signal sampling. If a clock signal out of step or sampling error is detected, a retransmission request signal is sent through the arbitration selection line. If the retransmission request signal value is 1, if the retransmission request signal value is 0, it indicates normal;

[0063] S64. After receiving the retransmission request signal value of 1, the master device resends the current data frame and adjusts the clock signal frequency to match the sampling requirement of the target slave device:

[0064] f ′ =f×(1+Δt / T);

[0065] Among them, Δt represents the time error of clock drift, T is the original clock period; f ′ represents the adjusted clock frequency, and f is the original clock frequency;

[0066] S65. During the clock synchronization process, the master device and the slave device detect the integrity of the clock signal in real time:

[0067]

[0068] Among them, t n represents the nth edge time of the clock signal, T is the ideal clock period, C t represents the clock signal integrity parameter, t n+1 Indicates the n+1th edge time of the clock signal;

[0069] S66: After the clock signals of the master device and the slave device are synchronized, they enter the next data transmission phase, record the current clock synchronization status, and update the communication status table.

[0070] Optionally, the S7 specifically includes:

[0071] S71. The master device selects the data transmission mode by controlling the values ​​of the data change sampling high bit and the data change sampling low bit in the control register according to the communication requirements:

[0072] M = 2·DCSH + DCSL;

[0073] Among them, M represents the communication mode, DCSH represents the data change sampling high bit, and DCSL represents the data change sampling low bit:

[0074] When DCSH=0, DCSL=0, the mode is M=0;

[0075] When DCSH=0, DCSL=1, the mode is M=1;

[0076] When DCSH=1, DCSL=0, the mode is M=2;

[0077] When DCSH=1, DCSL=1, the mode is M=3;

[0078] S72. According to the selected communication mode, the master device and the slave device configure the data transmission timing, wherein:

[0079] Mode 0: The master device sends data on the rising edge of the clock, and the slave device receives data on the falling edge of the clock;

[0080] Mode 1: The master device sends data on the falling edge of the clock, and the slave device receives data on the rising edge of the clock;

[0081] Mode 2: The master device changes the data state during the high level of the clock, and the slave device samples the data during the low level of the clock;

[0082] Mode 3: The master device changes the data state during the clock low period, and the slave device samples the data during the clock high period;

[0083] S73, the master device broadcasts the communication mode configured by the register to all slave devices before the communication starts, the broadcast data is transmitted through the arbitration selection line, and the mode synchronization of all devices is completed under the synchronization of the clock signal;

[0084] S74. After receiving the communication mode broadcast signal, the slave device loads the current value of the mode register and verifies the mode synchronization state:

[0085] R m =MM′;

[0086] Where M is the communication mode set by the master device, and M′ is the mode value received by the slave device;

[0087] S75, after receiving the rebroadcast request signal, the master device resends the communication mode broadcast signal until the mode synchronization of all slave devices is completed;

[0088] S76. After the communication mode synchronization is completed, the master device and the slave device start data transmission according to the current communication mode, and record the current mode information in real time.

[0089] The beneficial effects of the present invention are:

[0090] The multi-master and multi-slave full-duplex communication method based on arbitration selection and single-line multiplexing mechanism proposed by the present invention solves the problems of low communication efficiency, serious bus competition, complex hardware design and limited bandwidth in the prior art. The arbitration selection mechanism of the present invention realizes efficient and reliable multi-master device competition arbitration through the combination of modulo-2 operation and line XOR, avoids the problems of bus blocking and resource waste caused by the simple arbitration mechanism in traditional protocols, and thus significantly improves communication efficiency. In addition, the present invention optimizes the flexibility and adaptability of data transmission through single-line multiplexing technology and dynamic mode selection function, so that the transmission timing between master and slave devices can be adjusted according to communication requirements, meeting the communication requirements of high real-time performance and high bandwidth in complex scenarios.

[0091] During the data transmission process, the present invention introduces a flexible verification mechanism, which further improves the reliability of data transmission by supporting parity check, cyclic redundancy check and dynamic error detection technology. The optimization of the clock synchronization mechanism ensures efficient coordination between the master device and the slave device by adjusting the clock frequency in real time and accurately controlling the timing error, avoiding communication errors caused by clock drift. At the same time, the full-duplex communication capability of the present invention enables the master device and the slave device to perform bidirectional data transmission in the same time period, fundamentally breaking through the performance bottleneck of the traditional half-duplex protocol.

[0092] The present invention adopts a simple and efficient architecture in hardware design, and realizes low-cost implementation of complex communication functions through the coordination of arbitration selection lines, master output slave input lines and clock lines. This design not only reduces the complexity of system hardware implementation, but also significantly enhances the scalability of the system, enabling it to support large-scale device access. Overall, the present invention provides an efficient, reliable and flexible multi-master and multi-slave communication solution, which is suitable for embedded systems, industrial automation, distributed computing and other fields, has significant advantages in communication efficiency, data reliability and system flexibility, and provides strong technical support for modern multi-device collaborative communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0093] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0094] Figure 1 A flow chart of a multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism proposed by the present invention;

[0095] Figure 2 The present invention provides a schematic diagram of a specific implementation process of the arbitration selection mechanism of the multi-master and multi-slave full-duplex communication method based on the arbitration selection single-line multiplexing mechanism. DETAILED DESCRIPTION

[0096] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0097] refer to Figure 1-2 , a multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism includes the following steps:

[0098] S1, through the arbitration selection line, based on the line XOR and modulo 2 operation, all master devices send arbitration addresses bit by bit, detect the change of the arbitration selection line level, arbitrate according to the bit high priority, and determine the winning master device;

[0099] S2, the winning master device sends the slave device address through the master output slave input line, and the arbitration selection line waits for the response signal of the slave device. The slave device responds to the address query of the master device and performs slave device selection;

[0100] S3, the winning master device sends data to the selected slave device through the master output slave input line, and the slave device receives the data through the arbitration selection line;

[0101] S4, the selected slave device sends data to the master device through the arbitration selection line, and the master device receives data through the master output slave input line, thereby realizing full-duplex communication between the master device and the slave device;

[0102] S5. During data transmission, the master device and the slave device determine the integrity of the data based on the check bit;

[0103] S6. Signal synchronization is performed through the clock line. The master device synchronously sends the clock signal on the clock line to coordinate data sampling and transmission between the master device and the slave device.

[0104] S7, select the communication mode through the data change sampling high bit and the data change sampling low bit in the register, including mode 0, mode 1, mode 2 and mode 3, and determine the data transmission timing between the master device and the slave device;

[0105] S8. When the communication is completed, the master device continuously flips the level three times through the master output slave input line, defines the communication end signal, and terminates the current data transmission between the master device and the slave device.

[0106] In this implementation manner, the S1 specifically includes:

[0107] S11, each master device sends the arbitration address bit by bit on the arbitration selection line, each bit of the address is sent according to the unit arbitration interval of the clock signal, and the high-order address is arbitrated first;

[0108] S12, each master device compares the current bit value of its arbitration address with the level state of the arbitration selection line. If the sent bit value is 1 and the level state of the arbitration selection line is 0, it is determined that the master device has lost arbitration and exits;

[0109] S13. For any master device, the relationship between its arbitration address bit value and the arbitration selection line level value is determined by modulo-2 operation. If the calculation result is not 0, it is determined that the master device has lost arbitration:

[0110] a i ⊕L i =0;

[0111] Among them, ⊕ represents the XOR operation, a i Indicates the arbitration address bit value currently sent by the master device, L i Indicates the current level status of the arbitration selection line;

[0112] S14, at the end of the unit arbitration interval, the master device that has not exited continues to send the next arbitration address and repeats the judgment process of S12 and S13 until all address bits are sent;

[0113] S15. After completing arbitration of all bits, the remaining master device is the arbitration winning device, outputs the arbitration result and restores the arbitration selection line to a high level, indicating the end of the arbitration process.

[0114] In this implementation, S2 specifically includes:

[0115] S21, after the arbitration is completed, the winning master device sends the target slave device address through the master output slave input line, and the address is a binary code of fixed length;

[0116] S22, during the sending of the target slave device address, the arbitration selection line remains at a low level, indicating that the master device is selecting the target slave device;

[0117] S23, the target slave device compares the received address value with its own preset device address to determine whether it matches:

[0118] R = B ⊕ A;

[0119] Wherein, R represents the matching result. If R=0, it indicates that the address matching is successful and the target slave device is ready to enter the communication state; if R≠0, the slave device remains in the idle state;

[0120] S24, after the target slave device successfully matches, it sends a response signal to the master device through the arbitration selection line. The response signal is a binary value. If the response signal value is 1, it means that the target slave device is ready to receive data. If the response signal value is 0, it means that the target slave device is not ready.

[0121] S25. After receiving the response signal, the winning master device determines whether the target slave device is available. If the response signal value is 1, the data transmission phase is entered; if the response signal value is 0, the master device re-initiates the slave device selection process.

[0122] In this implementation, S3 specifically includes:

[0123] S31, after the slave device selection is completed, the winning master device sends a data frame to the target slave device through the master output slave input line;

[0124] S32, the data frame is sent synchronously through the clock signal, the master device changes the data output state at each rising edge of the clock signal, and the target slave device samples the received data signal at each falling edge of the clock;

[0125] S33, the target slave device parses the received data field and check field to verify the data integrity:

[0126] R c =f(D ′ ,C ′ );

[0127] Among them, f(D ′ ,C ′ ) is the verification function, if R c =0, it means the data is complete; if R c ≠0, the target slave device generates an error flag;

[0128] S34, after receiving the complete data frame, the target slave device returns a data reception confirmation signal to the master device through the arbitration selection line. If the confirmation signal value is 1, it indicates that the data is received successfully. If the confirmation signal value is 0, it indicates that the data is received unsuccessfully.

[0129] S35. The winning master device determines the data transmission result according to the received confirmation signal. If the confirmation signal value is 1, the next communication process is entered; if the confirmation signal value is 0, the data frame is resent.

[0130] In this implementation manner, the S4 specifically includes:

[0131] S41, after receiving the data frame sent by the master device and verifying it successfully, the target slave device loads its own data frame to be sent;

[0132] S42, the target slave device sends a data frame to the winning master device through the arbitration selection line. During the data transmission process, the clock signal synchronization is used to coordinate data sampling. The slave device changes the output state at the rising edge of the clock, and the master device samples and receives data at the falling edge of the clock.

[0133] S43, the winning master device performs integrity check on the received data field and check field of the target slave device;

[0134] S44, the winning master device parses the data field and performs corresponding operations according to the value of the data frame control field;

[0135] S45, if the check result value is 0, the winning master device sends a data reception confirmation signal to the target slave device through the master output slave input line, wherein the confirmation signal is 1, indicating that the data is received successfully, and the confirmation signal is 0, indicating that the data is received unsuccessfully;

[0136] S46. The target slave device performs an operation according to the state of the confirmation signal. If the value of the confirmation signal is 0, the target slave device resends the data frame; if the value of the confirmation signal is 1, the current data sending process ends.

[0137] In this implementation manner, S5 specifically includes:

[0138] S51, after completing the data transmission, the master device and the slave device perform a verification operation on the received complete data frame;

[0139] S52: The master device and the slave device respectively apply a verification algorithm to the received data field and the verification field to perform data integrity verification:

[0140]

[0141] Among them, R is the check result, m is the number of bits in the data field, and d′ i is the i-th bit of the received data field, mod2 is the modulo 2 operation, represents XOR operation, C′ is the received check value;

[0142] S53, if the check result value is 0, the master device and the slave device respectively generate a data reception success flag, wherein the data reception success flag value is 1, indicating that the data is complete and ready to enter the next communication stage;

[0143] S54, if the check result value is not 0, the master device and the slave device generate a data reception failure flag, wherein the data reception failure flag value is 0, and trigger a resending mechanism, and the sender reconstructs and transmits the data frame;

[0144] S55, after completing the data verification, the master device and the slave device respectively parse the control field. If the control field indicates that the current communication phase is over, both parties clear the receiving and sending buffers to release communication resources;

[0145] S56. If the control field indicates entering the next communication phase, the master device and the slave device update the communication status table according to the verification result, store the verified data frames into the corresponding storage area, and wait for the next clock signal synchronization instruction.

[0146] In this implementation manner, S6 specifically includes:

[0147] S61, before data transmission starts, the winning master device sends a clock signal to the target slave device through a clock line, where the clock signal is generated by the master device;

[0148] S62, during the clock synchronization process, the master device and the slave device sample data according to the edge of the clock signal, the master device changes the output data state at the rising edge of the clock, and the slave device samples data at the falling edge of the clock;

[0149] S63, the slave device determines whether a complete data frame is received according to the timing rule of clock signal sampling. If a clock signal out of step or sampling error is detected, a retransmission request signal is sent through the arbitration selection line. If the retransmission request signal value is 1, if the retransmission request signal value is 0, it indicates normal;

[0150] S64. After receiving the retransmission request signal value of 1, the master device resends the current data frame and adjusts the clock signal frequency to match the sampling requirement of the target slave device:

[0151] f ′ =f×(1+Δt / T);

[0152] Among them, Δt represents the time error of clock drift, T is the original clock period; f ′ represents the adjusted clock frequency, and f is the original clock frequency;

[0153] S65. During the clock synchronization process, the master device and the slave device detect the integrity of the clock signal in real time:

[0154]

[0155] Among them, t n represents the nth edge time of the clock signal, T is the ideal clock period, C t represents the clock signal integrity parameter, t n+1 Indicates the n+1th edge time of the clock signal;

[0156] S66: After the clock signals of the master device and the slave device are synchronized, they enter the next data transmission phase, record the current clock synchronization status, and update the communication status table.

[0157] In this implementation manner, the S7 specifically includes:

[0158] S71. The master device selects the data transmission mode by controlling the values ​​of the data change sampling high bit and the data change sampling low bit in the control register according to the communication requirements:

[0159] M = 2·DCSH + DCSL;

[0160] Among them, M represents the communication mode, DCSH represents the data change sampling high bit, and DCSL represents the data change sampling low bit:

[0161] When DCSH=0, DCSL=0, the mode is M=0;

[0162] When DCSH=0, DCSL=1, the mode is M=1;

[0163] When DCSH=1, DCSL=0, the mode is M=2;

[0164] When DCSH=1, DCSL=1, the mode is M=3;

[0165] S72. According to the selected communication mode, the master device and the slave device configure the data transmission timing, wherein:

[0166] Mode 0: The master device sends data on the rising edge of the clock, and the slave device receives data on the falling edge of the clock;

[0167] Mode 1: The master device sends data on the falling edge of the clock, and the slave device receives data on the rising edge of the clock;

[0168] Mode 2: The master device changes the data state during the high level of the clock, and the slave device samples the data during the low level of the clock;

[0169] Mode 3: The master device changes the data state during the clock low period, and the slave device samples the data during the clock high period;

[0170] S73, the master device broadcasts the communication mode configured by the register to all slave devices before the communication starts, the broadcast data is transmitted through the arbitration selection line, and the mode synchronization of all devices is completed under the synchronization of the clock signal;

[0171] S74. After receiving the communication mode broadcast signal, the slave device loads the current value of the mode register and verifies the mode synchronization state:

[0172] R m =MM′;

[0173] Where M is the communication mode set by the master device, and M′ is the mode value received by the slave device;

[0174] S75, after receiving the rebroadcast request signal, the master device resends the communication mode broadcast signal until the mode synchronization of all slave devices is completed;

[0175] S76. After the communication mode synchronization is completed, the master device and the slave device start data transmission according to the current communication mode, and record the current mode information in real time.

[0176] Embodiment 1:

[0177] In order to verify the feasibility of the present invention in implementation, the present invention is applied to an industrial automation production line, which needs to connect multiple sensors and controllers at the same time to achieve real-time data acquisition and equipment control. Multiple master controllers in the production line need to work with multiple slave devices (such as sensors and actuators) through the same communication bus. 2 When the bus load is high, the C communication protocol often encounters contention conflicts, resulting in increased communication delays. At the same time, the production line's requirements for high real-time performance and high reliability make the traditional SPI communication protocol unable to support large-scale device access. In addition, the large number of device accesses leads to complex hardware design and poor scalability, making it difficult to meet the ever-changing production needs. In order to solve the above problems, the multi-master and multi-slave full-duplex communication method based on arbitration selection and single-line multiplexing mechanism proposed in the present invention is applied to this scenario.

[0178] In this industrial automation production line, the communication system consists of a master device and multiple slave devices. The master device includes three main controllers A, B and C, and the slave devices include ten sensors and five actuators. Through the communication method of the present invention, the master device and the slave device share a communication bus, including an arbitration selection line, a master output slave input line and a clock line. First, the master device completes arbitration through an arbitration selection mechanism. For example, within a time slice, master device A and master device B simultaneously try to access the bus. Through modulo-2 arbitration, master device A successfully obtains bus control and B exits this competition. Next, master device A selects the target slave device (sensor 1) through the broadcast address, and enters the data transmission stage after the slave device successfully matches.

[0179] During data transmission, the master device A uses mode 0 for communication, that is, data is sent on the rising edge of the clock, and the slave device samples on the falling edge of the clock. The master device A sends control instructions to sensor 1 and receives real-time data returned by the sensor. Due to the use of a single-line multiplexing mechanism and full-duplex communication, the transmission rate is increased to 2Mbps, which is much faster than the traditional I 2 The C communication protocol has been improved by 400%. Through the clock synchronization mechanism, the transmission bit error rate has been reduced to 0.02%, significantly improving the reliability of data transmission.

[0180] Table 1 Industrial production line communication protocol performance comparison table

[0181]

[0182] Table 2 Stability test data of the communication method of the present invention in 24-hour operation

[0183]

[0184] It can be seen from the comparison in Table 1 that the communication method of the present invention has excellent performance in industrial production line applications. Its data transmission rate reaches 2.0Mbps, which is I 2 The data processing efficiency is significantly improved, which is 5 times that of the C protocol and 1.33 times that of the SPI protocol. At the same time, the bit error rate is only 0.02%, which is much lower than that of I 2 The 0.10% of I C and 0.05% of SPI demonstrates extremely high data transmission reliability. In addition, the arbitration completion time only takes 10 microseconds, which is much faster than I 2 The C protocol is reduced by 71.4%, indicating that the present invention can make quick decisions when multiple master devices compete, thus improving communication efficiency. The present invention supports 15 slave devices to access, which is more convenient than I 2 The expansion capability is significantly enhanced with 8 C and 4 SPI, which is suitable for multi-device collaborative working scenarios. The bus utilization rate reaches 95%, which is much higher than that of I 2 The 65% of C and 78% of SPI are greatly improved, indicating that the present invention performs well in resource utilization and efficiency.

[0185] The data in Table 2 show that in 24-hour continuous operation, the present invention can transmit 72.0GB of data per hour, the number of bit errors is always less than 12 times, and the average delay is stable at about 5 milliseconds, ensuring the efficient operation of the system. The arbitration success rate is as low as 99.7%, indicating that the present invention has extremely high reliability in high-load, multi-master device scenarios.

[0186] By comparing the data in Table 1 and Table 2, it can be seen that the communication method of the present invention has significant advantages in performance and stability. Compared with the traditional protocol, the present invention not only performs well in data transmission rate, bus utilization and the number of slave devices supported, but also further improves the reliability of data transmission and the expansion capability of the system by optimizing the arbitration mechanism, verification mechanism and clock synchronization mechanism. The communication method of the present invention can not only solve the technical bottleneck in the traditional protocol, but also provide a more efficient and reliable solution for multi-device collaborative communication.

[0187] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism, characterized in that: The steps include: S1, through the arbitration selection line, based on the line XOR and modulo 2 operation, all master devices send arbitration addresses bit by bit, detect the change of the arbitration selection line level, arbitrate according to the bit high priority, and determine the winning master device; S2, the winning master device sends the slave device address through the master output slave input line, and the arbitration selection line waits for the response signal of the slave device. The slave device responds to the address query of the master device and performs slave device selection; S3, the winning master device sends data to the selected slave device through the master output slave input line, and the slave device receives the data through the arbitration selection line; S4, the selected slave device sends data to the master device through the arbitration selection line, and the master device receives data through the master output slave input line, thereby realizing full-duplex communication between the master device and the slave device; S5. During data transmission, the master device and the slave device determine the integrity of the data based on the check bit; S6. Signal synchronization is performed through the clock line. The master device synchronously sends the clock signal on the clock line to coordinate data sampling and transmission between the master device and the slave device. S7, select the communication mode through the data change sampling high bit and the data change sampling low bit in the register, including mode 0, mode 1, mode 2 and mode 3, and determine the data transmission timing between the master device and the slave device; S8. When the communication is completed, the master device continuously flips the level three times through the master output slave input line, defines the communication end signal, and terminates the current data transmission between the master device and the slave device.

2. The multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism according to claim 1 is characterized in that: The S1 specifically includes: S11, each master device sends the arbitration address bit by bit on the arbitration selection line, each bit of the address is sent according to the unit arbitration interval of the clock signal, and the high-order address is arbitrated first; S12, each master device compares the current bit value of its arbitration address with the level state of the arbitration selection line. If the sent bit value is 1 and the level state of the arbitration selection line is 0, it is determined that the master device has lost arbitration and exits; S13. For any master device, the relationship between its arbitration address bit value and the arbitration selection line level value is determined by modulo-2 operation. If the calculation result is not 0, it is determined that the master device has lost arbitration: a i ⊕L i =0; Among them, ⊕ represents the XOR operation, a i Indicates the arbitration address bit value currently sent by the master device, L i Indicates the current level status of the arbitration selection line; S14, at the end of the unit arbitration interval, the master device that has not exited continues to send the next arbitration address and repeats the judgment process of S12 and S13 until all address bits are sent; S15. After completing arbitration of all bits, the remaining master device is the arbitration winning device, outputs the arbitration result and restores the arbitration selection line to a high level, indicating the end of the arbitration process.

3. The multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism according to claim 1 is characterized in that: The S2 specifically includes: S21, after the arbitration is completed, the winning master device sends the target slave device address through the master output slave input line, and the address is a binary code of fixed length; S22, during the sending of the target slave device address, the arbitration selection line remains at a low level, indicating that the master device is selecting the target slave device; S23, the target slave device compares the received address value with its own preset device address to determine whether it matches: R = B ⊕ A; Wherein, R represents the matching result. If R=0, it indicates that the address matching is successful and the target slave device is ready to enter the communication state; if R≠0, the slave device remains in the idle state; S24, after the target slave device successfully matches, it sends a response signal to the master device through the arbitration selection line. The response signal is a binary value. If the response signal value is 1, it means that the target slave device is ready to receive data. If the response signal value is 0, it means that the target slave device is not ready. S25. After receiving the response signal, the winning master device determines whether the target slave device is available. If the response signal value is 1, the data transmission phase is entered; if the response signal value is 0, the master device re-initiates the slave device selection process.

4. The multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism according to claim 1, characterized in that: The S3 specifically includes: S31, after the slave device selection is completed, the winning master device sends a data frame to the target slave device through the master output slave input line; S32, the data frame is sent synchronously through the clock signal, the master device changes the data output state at each rising edge of the clock signal, and the target slave device samples the received data signal at each falling edge of the clock; S33, the target slave device parses the received data field and check field to verify the data integrity: R c =f(D′,C′); Among them, f(D′,C′) is the verification function. If R c =0, it means the data is complete; if R c ≠0, the target slave device generates an error flag; S34, after receiving the complete data frame, the target slave device returns a data reception confirmation signal to the master device through the arbitration selection line. If the confirmation signal value is 1, it indicates that the data is received successfully. If the confirmation signal value is 0, it indicates that the data is received unsuccessfully. S35. The winning master device determines the data transmission result according to the received confirmation signal. If the confirmation signal value is 1, the next communication process is entered; if the confirmation signal value is 0, the data frame is resent.

5. The multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism according to claim 1, characterized in that: The S4 specifically includes: S41, after receiving the data frame sent by the master device and verifying it successfully, the target slave device loads its own data frame to be sent; S42, the target slave device sends a data frame to the winning master device through the arbitration selection line. During the data transmission process, the clock signal synchronization is used to coordinate data sampling. The slave device changes the output state at the rising edge of the clock, and the master device samples and receives data at the falling edge of the clock. S43, the winning master device performs integrity check on the received data field and check field of the target slave device; S44, the winning master device parses the data field and performs corresponding operations according to the value of the data frame control field; S45, if the check result value is 0, the winning master device sends a data reception confirmation signal to the target slave device through the master output slave input line, wherein the confirmation signal is 1, indicating that the data is received successfully, and the confirmation signal is 0, indicating that the data is received unsuccessfully; S46. The target slave device performs an operation according to the state of the confirmation signal. If the value of the confirmation signal is 0, the target slave device resends the data frame; if the value of the confirmation signal is 1, the current data sending process ends.

6. The multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism according to claim 1, characterized in that: The S5 specifically includes: S51, after completing the data transmission, the master device and the slave device perform a verification operation on the received complete data frame; S52: The master device and the slave device respectively apply a verification algorithm to the received data field and the verification field to perform data integrity verification: Among them, R is the check result, m is the number of bits in the data field, and d′ i is the i-th bit of the received data field, mod2 is the modulo 2 operation, represents XOR operation, C′ is the received check value; S53, if the check result value is 0, the master device and the slave device respectively generate a data reception success flag, wherein the data reception success flag value is 1, indicating that the data is complete and ready to enter the next communication stage; S54, if the check result value is not 0, the master device and the slave device generate a data reception failure flag, wherein the data reception failure flag value is 0, and trigger a resending mechanism, and the sender reconstructs and transmits the data frame; S55, after completing the data verification, the master device and the slave device respectively parse the control field. If the control field indicates that the current communication phase is over, both parties clear the receiving and sending buffers to release communication resources; S56. If the control field indicates entering the next communication phase, the master device and the slave device update the communication status table according to the verification result, store the verified data frames into the corresponding storage area, and wait for the next clock signal synchronization instruction.

7. The multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism according to claim 1, characterized in that: The S6 specifically includes: S61, before data transmission starts, the winning master device sends a clock signal to the target slave device through a clock line, where the clock signal is generated by the master device; S62, during the clock synchronization process, the master device and the slave device sample data according to the edge of the clock signal, the master device changes the output data state at the rising edge of the clock, and the slave device samples data at the falling edge of the clock; S63, the slave device determines whether a complete data frame is received according to the timing rule of clock signal sampling. If a clock signal out of step or sampling error is detected, a retransmission request signal is sent through the arbitration selection line. If the retransmission request signal value is 1, if the retransmission request signal value is 0, it indicates normal; S64. After receiving the retransmission request signal value of 1, the master device resends the current data frame and adjusts the clock signal frequency to match the sampling requirement of the target slave device: f′=f×(1+Δt / T); Where Δt represents the time error of clock drift, T is the original clock period; f′ represents the adjusted clock frequency, and f is the original clock frequency; S65. During the clock synchronization process, the master device and the slave device detect the integrity of the clock signal in real time: Among them, t n represents the nth edge time of the clock signal, T is the ideal clock period, C t represents the clock signal integrity parameter, t n+1 Indicates the n+1th edge time of the clock signal; S66: After the clock signals of the master device and the slave device are synchronized, they enter the next data transmission phase, record the current clock synchronization status, and update the communication status table.

8. The multi-master and multi-slave full-duplex communication method based on arbitration selection single-line multiplexing mechanism according to claim 1, characterized in that: The S7 specifically includes: S71. The master device selects the data transmission mode by controlling the values ​​of the data change sampling high bit and the data change sampling low bit in the control register according to the communication requirements: M = 2·DCSH + DCSL; Among them, M represents the communication mode, DCSH represents the data change sampling high bit, and DCSL represents the data change sampling low bit: When DCSH=0, DCSL=0, the mode is M=0; When DCSH=0, DCSL=1, the mode is M=1; When DCSH=1, DCSL=0, the mode is M=2; When DCSH=1, DCSL=1, the mode is M=3; S72. According to the selected communication mode, the master device and the slave device configure the data transmission timing, wherein: Mode 0: The master device sends data on the rising edge of the clock, and the slave device receives data on the falling edge of the clock; Mode 1: The master device sends data on the falling edge of the clock, and the slave device receives data on the rising edge of the clock; Mode 2: The master device changes the data state during the high level of the clock, and the slave device samples the data during the low level of the clock; Mode 3: The master device changes the data state during the clock low period, and the slave device samples the data during the clock high period; S73, the master device broadcasts the communication mode configured by the register to all slave devices before the communication starts, the broadcast data is transmitted through the arbitration selection line, and the mode synchronization of all devices is completed under the synchronization of the clock signal; S74. After receiving the communication mode broadcast signal, the slave device loads the current value of the mode register and verifies the mode synchronization state: R m =M-M′; Where M is the communication mode set by the master device, and M′ is the mode value received by the slave device; S75, after receiving the rebroadcast request signal, the master device resends the communication mode broadcast signal until the mode synchronization of all slave devices is completed; S76. After the communication mode synchronization is completed, the master device and the slave device start data transmission according to the current communication mode, and record the current mode information in real time.

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