A folding hash processing circuit applied to a post-quantum cryptographic algorithm

Abstract

The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical field of cryptography. The application discloses a folding hash processing circuit applied to a post-quantum cryptography algorithm, and relates to the technical

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of post-quantum information security algorithm, hash algorithm, digital signal processing and circuit implementation, in particular to a folding hash processing circuit applied to post-quantum cryptographic algorithm. BACKGROUND

[0002] The standardization of the third generation secure hash algorithm SHA-3 (Secure Hash Algorithm 3) is initiated by the National Institution of Science and Technology (NIST) in the United States, aiming to supplement and enhance the existing SHA-2 standard. The standardized SHA-3 function can also be called Keccak-f

[1600] , which absorbs any input length of 1600 bits for processing, which can be regarded as a 5x5x64 three-dimensional cube, or a structure composed of 25 64-bit lanes. Each execution of Keccak operation requires 24 sub-round operations on the 1600 bits, and each sub-round contains five steps of θρπχι, the first four steps perform row and column confusion on the 1600 bits, and the last step introduces a round constant to destroy the symmetry of the original transformation.

[0003] In the existing post-quantum cryptographic algorithm to be standardized, SHA-3 is widely used. For example, in the lattice-based public key encryption scheme Kyber and the digital signature scheme Dilithium, SHA-3 is used to hash the message, generate key pairs, random numbers, etc. The security of the hash-based digital signature SPHINCS+ depends on the strong collision resistance of the hash function to ensure the security of the signing and verification process. In the hardware implementation of these algorithms, the implementation of the SHA-3 module occupies the most resource overhead, which directly affects the efficiency of the hardware implementation. However, in the practical application and implementation of post-quantum cryptographic algorithms, especially in Internet of Things (IoT) devices and embedded systems, lightweight application scenarios often have strict limitations on computing resources and energy consumption. Therefore, how to reduce the size of the data required for Keccak operation to improve the operation efficiency is of great significance to the practical application of subsequent post-quantum cryptographic algorithms. SUMMARY

[0004] The technical problem to be solved by the present application is that the existing hash processing circuit has low efficiency, and the present application provides a folding hash processing circuit applied to post-quantum cryptographic algorithm.

[0005] In order to solve the above technical problems, the present application provides a folding hash processing circuit applied to post-quantum cryptographic algorithm, comprising a storage module, a running module, an address control module and a counting module.

[0006] The storage module is configured to split the external input data into a plurality of intermediate data for storage and output the intermediate data in sequence.

[0007] The running module is configured to perform a hash function operation on the intermediate data to generate result data.

[0008] The address control module is configured to provide address data to control the input of the external input data and the result data into the storage module.

[0009] The counting module is configured to record the intra-cycle count and inter-cycle count of the intermediate data output by the storage module, transmit the inter-cycle count to the running module and the address control module, and transmit the intra-cycle count and the wheel constant control data to the running module.

[0010] Preferably, the storage module completes the readout of all intermediate data in each cycle and transmits the intermediate data to the running module for hash function operation to generate result data and transmit the result data back to the storage module. The storage module completes the operation of the external input data once every 25 cycles.

[0011] In each cycle, a group of intermediate data is read out in each clock cycle. The counting module records the intra-cycle count once every clock cycle. The counting module records the inter-cycle count once every cycle.

[0012] Preferably, the storage module includes 25 groups of channels, and the width of each of the 25 groups of channels is 16 bits.

[0013] The 25 groups of channels include 25-49 memories, and each group of channels includes at least one memory. The memories are connected in parallel. The width of the memory in each group of the 25 groups of channels is controlled by the number of shifts in the ρ step of the hash function operation corresponding to the channel.

[0014] Preferably, the read address of the memory in the same group of channels in the storage module is the same in each cycle, and the write address is controlled by the number of shifts in the ρ step of the hash function operation corresponding to the channel to which the memory belongs. Between different cycles, the read address of the memory in the even cycle is used as the write address of the previous odd cycle, and the read address of the memory in the odd cycle is used as the write address of the previous even cycle.

[0015] Preferably, the running module includes a first unit, a second unit, a third unit, a first selector, a second selector, and a third selector.

[0016] The first unit is used for running χ step and ι step in the hash function; the second unit is used for running θ step in the hash function; and the third unit is used for running ρ step and π step in the hash function.

[0017] The first unit is connected with the output terminal of the storage module through the input terminal of the first selector; the output terminal of the first unit is connected with the input terminal of the first selector and the input terminal of the second selector; the output terminal of the first selector is connected with the input terminal of the second unit; the output terminal of the second unit is connected with the input terminal of the second selector; the output terminal of the second selector is connected with the input terminal of the third unit; the selection terminals of the first selector, the second selector and the third selector are connected with the output terminal of the counting module; the input terminal of the third selector is connected with the output terminal of the second selector and the output terminal of the third unit; and the output terminal of the third selector is connected with the input terminal of the storage module.

[0018] Preferably, the running module further comprises a data preprocessing unit; the input terminal of the data preprocessing unit is connected with the output terminal of the third unit, and the output terminal of the data preprocessing unit is connected with the input terminal of the second unit.

[0019] The data preprocessing unit is used for selecting the last group of data from the output data of the third unit, and inputting the last group of data into the second unit as the input data of the second unit in the next round after processing.

[0020] Preferably, the data preprocessing unit comprises a plurality of parallel data preprocessing groups and a second exclusive OR gate; the data preprocessing group comprises a fourth selector, a register, a NOT gate, an AND gate and a first exclusive OR gate.

[0021] The input terminal of the fourth selector is connected with the output terminal of the register, and the output terminal of the fourth selector is connected with the input terminal of the register; the output terminal of the register is connected with the input terminal of the NOT gate; the output terminal of the NOT gate is connected with the input terminal of the AND gate; the output terminal of the AND gate and the output terminal of the register are connected with the input terminal of the first exclusive OR gate; the output terminal of the first exclusive OR gate is connected with the input terminal of the second exclusive OR gate; and the output terminal of the second exclusive OR gate is connected with the input terminal of the second unit.

[0022] Preferably, the first unit comprises a second NOT gate, a second AND gate and a third exclusive OR gate.

[0023] The input terminal of the second NOT gate and the input terminal of the second AND gate are connected with the input data of the first unit; the output terminal of the second NOT gate is connected with the input terminal of the second AND gate; and the output terminal of the second AND gate and the round constant data are connected with the input terminal of the third exclusive OR gate.

[0024] Preferably, the second unit comprises a fourth exclusive OR gate, a fifth exclusive OR gate, a sixth exclusive OR gate and a seventh exclusive OR gate.

[0025] The fourth exclusive-OR gate input end and the fifth exclusive-OR gate input end are connected with the second unit input data; the fourth exclusive-OR gate output end and the fifth exclusive-OR gate output end are connected with the sixth exclusive-OR gate input end; and the sixth exclusive-OR gate output end is connected with the seventh exclusive-OR gate input end.

[0026] Preferably, the third unit is used for mapping, shifting and obtaining the number of shifts of the third unit input data.

[0027] The embodiment of the present application has the following beneficial effects:

[0028] (1) The embodiment of the present application splits the external input data into multiple intermediate data, respectively outputs the intermediate data, and performs hash function operation processing on a single intermediate data, so that the size of the intermediate data in a single operation is much smaller than that of the original external input data, thereby accelerating the operation efficiency of the running module, further improving the efficiency of the practical application of the post-quantum cryptography algorithm, and significantly reducing the resource consumption of the hash structure implementation, and realizing efficient use of system resources.

[0029] (2) The embodiment of the present application designs the storage module and the running module, so that the memory alternately stores the running module output data in different cycles, and the running module selects and adjusts the χ step, the ι step, the θ step, the ρ step and the π step in the hash function operation. By performing different step operations on the storage module output data in different cycles, the hash function operation result of the external input data is accurately generated, and the data reading and writing and dependency problem in the folding hash structure are solved.

[0030] (3) The embodiment of the present application sets the running module, adds a data preprocessing unit, and uses the data preprocessing unit as a pre-data supplement device of the θ step. Before each round of θ step, the required partial data operation is sent to the θ step for operation, so that the running of the second unit reduces the redundant cycle and improves the running efficiency of the second unit. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0032] Figure 1 A folding hash processing circuit architecture diagram applied to a post-quantum cryptography algorithm is provided for the embodiment of the present application.

[0033] Figure 2A diagram illustrating the architecture of a data preprocessing unit in a folded hash processing circuit for a post-quantum cryptographic algorithm provided for implementation of the present invention;

[0034] Figure 3 A diagram illustrating the architecture of a first unit in a folded hash processing circuit for a post-quantum cryptographic algorithm provided for implementation of the present invention;

[0035] Figure 4 A diagram of the second unit architecture in a folded hash processing circuit for a post-quantum cryptographic algorithm provided for implementation of the present invention. DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0037] like Figure 1 As shown, the present embodiment discloses a folded hash processing circuit for a post-quantum cryptographic algorithm, the folded hash processing circuit for a post-quantum cryptographic algorithm comprising: a storage module 10, an operation module 20, an address control module 40, and a counting module 30. The storage module 10 is used to split external input data into multiple intermediate data for separate storage, and output the intermediate data in sequence. The operation module 20 is used to perform a hash function (SHA-3 function) operation on the intermediate data to generate result data. The address control module 40 is used to provide address data, thereby controlling the input of the external input data and result data into the storage module 10. The counting module 30 is used to record the intra-cycle count and inter-cycle count of the intermediate data output by the storage module 10. The counting module 30 is also used to transmit the inter-cycle count to the operation module 20 and the address control module 40, and transmit the intra-cycle count and round constant control data to the operation module 20.

[0038] Since the current SHA-3 functions all process 1600-bit external input data, this embodiment also processes 1600-bit data. However, the present invention can still be applied to SHA-3 functions for input data of other bits. And in this embodiment. The 1600-bit external input data is split into 4 intermediate data, which are stored separately and output in sequence. However, the present invention can still be applied to splitting the 1600-bit external input data into other numbers of intermediate data, which are stored separately and output in sequence. For example, splitting the 1600-bit external input data into 2, 8, 16, etc. nThe intermediate data is divided into 64 groups.

[0039] Specifically, the storage module 10 includes 25 groups of channels 110. Each group of channels 110 has a width of 16 bits. Each group of channels 110 includes 25-49 memories 111. Each group of channels 110 includes at least one memory 111. The memories 111 are connected in parallel. The width of the memory 111 in each group of the 25 groups of channels 110 is controlled by the number of shifts in the ρ step of the SHA-3 function operation corresponding to the channel 110. The depth of the memory 111 is 8. The depths 0-3 of all memories 111 of the 25 groups of channels 110 are used to receive 1600-bit external input data. The 1600-bit external input data is divided into 4 groups of intermediate data. The intermediate data is transmitted to the running module 20 for SHA-3 function operation processing to generate result data transmitted back to the storage module 10. Then, the result data is divided into 4 groups of intermediate data, and the 4 groups of intermediate data are sequentially transmitted to the running module 20 for SHA-3 function operation processing to generate result data transmitted back to the storage module 10. The storage module performs 25 rounds of cycles to complete the external input data operation processing once.

[0040] The storage module 10 completes the reading of the 4 groups of intermediate data in each cycle. In each clock cycle, one group of intermediate data is read out, and the count module 30 records a cycle count, with 0-3 representing the cycle count of the reading of the 4 groups of intermediate data. When the 4 groups of intermediate data are read, the count module 30 records a cycle count, i.e., the count module 30 records a cycle count every time a cycle operation is completed. The folding hash processing circuit applied to the post-quantum cryptography algorithm completes the SHA-3 function processing of 1600-bit external input data once. The count module 30 records 25 times, with 0-24 representing the cycle count of the 25 cycles.

[0041] In the 25 cycles, the SHA-3 function executed by the running module 20 is as follows:

[0042]

[0043] The χ, ι, θ, ρ, and π are the χ step, ι step, θ step, ρ step, and π step in the SHA-3 function operation, respectively. The i is the cycle count. The r i is the SHA-3 function executed by the running module 20.

[0044] In a round of period operation, the read address of the memory 111 in the same group of channels in the storage module 10 is the same, and the write address is controlled by the number of shifts in the p step of the hash function operation corresponding to the channel to which the memory belongs. Between different periods, the read address of the even period of the memory will be used as the write address of the previous odd period, and the read address of the odd period will be used as the write address of the previous even period. Specifically, the input 1600-bit external input data will be divided into 4 groups of intermediate data in depth. After transmission of each group of intermediate data, it will be transmitted to the positions of depths 4-7 of the memory 111. Until the 1600-bit external input data is transmitted from depths 0-3 of all the memories 111 to depths 4-7 of the memory 111, a round of period operation is completed. In the next round of period operation, the data in the storage module 10 will be read out from depths 4-7 of the memory 111 and transmitted to the SHA-3 function executed by the operation module 20. The processed result data is then transmitted to the positions of depths 0-3 of the memory 111. In different periods, the read address of the even period of the memory will be used as the write address of the previous odd period, and the read address of the odd period will be used as the write address of the previous even period.

[0045] The 25 groups of channels 110 include 25-49 memories 111. In this embodiment, the 25 groups of channels 110 include 49 memories 111. The width of each memory 111 is as follows:

[0046]

[0047]

[0048] Among them, except for the Aba group, every two memories 111 form a group (such as Abe0 and Abe1), and each group of memories 111 stores corresponding data. The width of the memory 111 is determined by the mapping of the p and π steps in the SHA-3 function. For each period of the two memories 111 of each group of channels, the read address is the same, and the write address is different by 1. For example, the Abe group is mapped from the Age group, and the number of shifts of the Age group is 44, and the remainder when divided by 16 is 12, so the width of the two memories 111 corresponding to the Abe group is 4 and 12.

[0049] The running module 20 comprises a first unit 210, a second unit 220, a third unit 230, a first selector 240, a second selector 250, a third selector 260 and a data preprocessing unit 270. The first unit 210 is configured to run the χ step and the ι step in the hash function. The second unit 220 is configured to run the θ step in the hash function. The third unit 230 is configured to run the ρ step and the π step in the hash function. The data preprocessing unit 270 is configured to select the last group of data in the input data of the second unit 220 and input the last group of data into the second unit 220 as the input data of the second unit 220 in the next round.

[0050] Specifically, the first unit 210 and the first selector 240 are connected with the output end of the storage module 10. The output end of the first unit 210 is connected with the input end of the first selector 240 and the second selector 250. The output end of the first selector 240 is connected with the input end of the second unit 220. The output end of the second unit 220 is connected with the input end of the second selector 250. The output end of the second selector 250 is connected with the input end of the third unit 230. The selection ends of the first selector 240, the second selector 250 and the third selector 260 are connected with the output end of the counting module 30. The input end of the third selector 260 is connected with the output end of the second selector 250 and the output end of the third unit 230. The output end of the third selector 260 is connected with the input end of the storage module 10. The input end of the data preprocessing unit 270 is connected with the output end of the second unit 220, and the output end is connected with the input end of the second unit 220. The periodic round count and the inter-periodic round count output by the counting module 30 are used to control the first selector 240, the second selector 250 and the third selector 260, so as to realize the selection and control of the execution of the first unit 210, the second unit 220 and the third unit 230. The output end of the counting module 30 is also connected with the first unit, which is used to output the round constant control data to the first unit 210, so as to control the round constant data added in the χ step and the ι step. The selection of the round constant is realized.

[0051] Referring to Figure 2 The data preprocessing unit 270 comprises a plurality of parallel data preprocessing groups and a second XOR gate 276. Each data preprocessing group comprises a fourth selector 271, a register 272, a NOT gate 273, an AND gate 274 and a first XOR gate 275. The number of the data preprocessing groups is five.

[0052] The fourth selector 271 is connected to the output of the register 272, and the output is connected to the input of the register 272. The output of the register 272 is connected to the input of the NOT gate 273. The output of the NOT gate 273 is connected to the input of the AND gate 274. The output of the AND gate 274 and the output of the register 272 are connected to the input of the first XOR gate 275. The input of the AND gate 274 of the other groups of registers 272 is connected. The output of the first XOR gate 275 of all groups is connected to the input of the second XOR gate 276. The output of the second XOR gate 276 is connected to the input of the second unit 220. Since the calculation of each intermediate data θ step needs to use the last group data of the previous one. According to the position of the shift and rotation, the position of the last group data of the intermediate data after the ι step is determined, and after the ρ and π calculation in the corresponding round period is taken out, the pre-calculation is carried out in the data preprocessing unit 270, and the calculation result (Bca, Bce, Bci, Bco, Bcu) is reserved. In the first period of the next round calculation, it is used as the input of the θ module, and the θ module also retains the result of the last slice after completing the calculation, which is used for operation in the next period of the round. Through the data preprocessing unit 270 as the front data supplement device of the θ step, the required part of the data is calculated and sent into the θ step for operation before each round of θ step, so that the operation of the second unit 220 is reduced. Redundant period, improve the operation efficiency of the second unit 220.

[0053] Referring to Figure 3 , the first unit 210 includes a second NOT gate 211, a second AND gate 212, and a third XOR gate 213. The number of the second NOT gate 211, the second AND gate 212, and the third XOR gate 213 is determined by the size of the input intermediate data. When the intermediate data increases, the number of the second NOT gate 211, the second AND gate 212, and the third XOR gate 213 will also increase.

[0054] Specifically, the input of the second NOT gate 211 and the input of the second AND gate 212 are connected to the input data of the first unit 210. The output of the second NOT gate 211 is connected to the input of the second AND gate 212. The output of the second AND gate 212 and the round constant data are connected to the input of the third XOR gate 213.

[0055] The processes of χ step and ι step are as follows:

[0056] A′[x, y, z] = A[x, y, z] ⊕ (A[(x+1)mod5, y, z] ⊕ 1) ∧ A[(x+2)mod5, y, z]

[0057] H[0, 0, z] = A′[0, 0, z] ⊕ RC(z)

[0058] Wherein, A'[x, y, z] is the result of χ step; H[0, 0, z] is the result of ι step; RC(z) is the round constant data. The χ step is used for XOR confusion operation on input data. The ι step is used for XOR confusion operation between the χ step result and the round constant data.

[0059] The round constant data table is as follows:

[0060]

[0061] The simplified round constant control data control table is as follows:

[0062]

[0063]

[0064] The count module 30 determines the position of data reading and writing and the sequence of calculation operation and determines the round constant control data through inter-round counting, so as to realize the control of round constant data.

[0065] Referring to Figure 4 , the second unit 220 includes a fourth XOR gate 221, a fifth XOR gate 222, a sixth XOR gate 223 and a seventh XOR gate 224.

[0066] The input end of the fourth XOR gate 221 and the input end of the fifth XOR gate 222 are connected with the input data of the second unit 220. The input end of the fourth XOR gate 221 is connected with the output data of the first selector 240. The input end of the fifth XOR gate 222 is connected with the output data of the data preprocessing unit 270. The output end of the fourth XOR gate 221 and the output end of the fifth XOR gate 222 are connected with the input end of the sixth XOR gate 223. The input end of the seventh XOR gate 224 is connected with the output end of the sixth XOR gate 223.

[0067] The process of the θ step is as follows:

[0068] C[x, z] = A[x, 0, z] XOR A[x, 1, z] XOR A[x, 2, z] XOR A[x, 3, z] XOR A[x, 4, z]

[0069] D[x, z] = C[(x-1)mod 5, z] XOR C[(x+1)mod 5, (z-1)mod 64]

[0070] A'[x, y, z] = A[x, y, z] XOR D[x, z]

[0071] The C[x, z] is the operation result of the fourth XOR gate 221.

[0072] The third unit is used for mapping and shifting the third unit input data, and obtaining the number of shifts of the third unit input data.

[0073] In summary, the folding hash processing circuit applied to the post-quantum cryptographic algorithm disclosed in the application splits the external input data into multiple intermediate data and outputs the intermediate data respectively. The single intermediate data is processed by the hash function operation, so that the size of the intermediate data in a single run is much smaller than the original external input data, thereby speeding up the operation efficiency of the running module. The efficiency of the actual application of the post-quantum cryptographic algorithm is improved as a whole, and the resource overhead of the hash structure implementation is significantly reduced, realizing the efficient use of system resources. And through the design of the storage module and the running module, the memory alternately stores the output data of the running module in different periods, and the running module selects and adjusts the χ step, ι step, θ step, ρ step and π step in the hash function operation. By performing different step operations on the output data of the storage module in different periods, the hash function operation result of the external input data is accurately generated, and the data reading and writing and dependency problem in the folding hash structure are solved.

[0074] The above only discloses a preferred embodiment of the application, of course, cannot limit the scope of the application, those skilled in the art can understand that the whole or part of the above-mentioned embodiment is implemented, and the equivalent changes made according to the claims of the application still belong to the scope covered by the application.

Claims

1. A folding hash processing circuit applied to a post-quantum cryptographic algorithm, characterized by, The application relates to a data processing device, which comprises a storage module, a running module, an address control module and a counting module. The storage module is used for splitting external input data into multiple intermediate data for storage and outputting the intermediate data in sequence. The running module is used for performing hash function operation processing on the intermediate data to generate result data. The address control module is used for providing address data to control the input of the external input data and the result data into the storage module. The counting module is used for recording the intra-period counting and inter-period counting of the intermediate data output by the storage module, transmitting the inter-period counting to the running module and the address control module, and transmitting the intra-period counting and wheel constant control data to the running module. The storage module completes the reading of all intermediate data in each period and transmits the intermediate data to the running module for hash function operation processing to generate result data which is transmitted back to the storage module; the storage module completes external input data operation processing once every 25 periods. 2.The folded hash processing circuit applied to a post-quantum cryptography algorithm of claim 1, wherein In each period, a group of intermediate data is read in each clock cycle; the counting module records the intra-period counting once every clock cycle; and the counting module records the inter-period counting once every period. The storage module comprises 25 groups of channels, and the width of each group of channels is 16 bits. 3.The folded hash processing circuitry for a post-quantum cryptography algorithm of claim 2, wherein, Each group of channels comprises 25-49 memories, and each group of channels comprises at least one memory; the memories are connected in parallel; and the width of the memory in each group of channels is controlled by the number of shifts in the rho step of the hash function operation corresponding to the channel. In each period, the reading address of the memory in the same group of channels in the storage module is the same, and the writing address is controlled by the number of shifts in the rho step of the hash function operation corresponding to the channel to which the memory belongs; between different periods, the reading address of the memory in the even period is used as the writing address of the previous odd period, and the reading address of the memory in the odd period is used as the writing address of the previous even period.

4. The folding hash processing circuitry for post-quantum cryptography algorithms of claim 3, wherein, The running module comprises a first unit, a second unit, a third unit, a first selector, a second selector and a third selector. 5.The folded hash processing circuit applied to a post-quantum cryptography algorithm of claim 1, wherein The first unit is used for running the chi step and the iota step of the hash function; the second unit is used for running the theta step of the hash function; and the third unit is used for running the rho step and the pi step of the hash function. The input end of the first unit and the output end of the storage module are connected; the output end of the first unit and the input end of the first selector and the second selector are connected; the output end of the first selector and the input end of the second unit are connected; the output end of the second unit and the input end of the second selector are connected; the output end of the second selector and the input end of the third unit are connected; the selection end of the first selector, the second selector and the third selector and the output end of the counting module are connected; the input end of the third selector and the output end of the third unit and the second selector are connected; and the output end of the third selector and the input end of the storage module are connected. ​ 6. The folding hash processing circuitry for post-quantum cryptography algorithms of claim 5, wherein, The operation module further comprises a data preprocessing unit; an input end of the data preprocessing unit is connected with an output end of the third unit, and an output end is connected with an input end of the second unit; The data preprocessing unit is used for selecting the last group of data in the third unit output data, and inputting the last group of data after processing into the second unit as the next round of second unit input data.

7. The folded hash processing circuit for a post-quantum cryptography algorithm according to claim 6, wherein, The data preprocessing unit comprises a plurality of parallel data preprocessing groups and a second XOR gate; the data preprocessing group comprises a fourth selector, a register, a NOT gate, an AND gate, and a first XOR gate; An input end of the fourth selector is connected with an output end of the register, and an output end is connected with an input end of the register; an output end of the register is connected with an input end of the NOT gate; an output end of the NOT gate is connected with an input end of the AND gate; an output end of the AND gate and an output end of the register are connected with an input end of the first XOR gate; an output end of the first XOR gate is connected with an input end of the second XOR gate; and an output end of the second XOR gate is connected with an input end of the second unit.

8. The folding hash processing circuitry for post-quantum cryptography algorithms of claim 5, wherein, The first unit comprises a second NOT gate, a second AND gate, and a third XOR gate; An input end of the second NOT gate and an input end of the second AND gate are connected with the first unit input data; an output end of the second NOT gate is connected with an input end of the second AND gate; an output end of the second AND gate and a round constant data are connected with an input end of the third XOR gate. 9.The folded hash processing circuit applied to a post-quantum cryptography algorithm of claim 5, wherein, The second unit comprises a fourth XOR gate, a fifth XOR gate, a sixth XOR gate, and a seventh XOR gate; An input end of the fourth XOR gate and an input end of the fifth XOR gate are connected with the second unit input data; an output end of the fourth XOR gate and an output end of the fifth XOR gate are connected with an input end of the sixth XOR gate; an output end of the sixth XOR gate is connected with an input end of the seventh XOR gate. 10.The folded hash processing circuitry for post-quantum cryptography applications of claim 5, wherein, The third unit is used for mapping and shifting the third unit input data, and obtaining a number of shifts of the third unit input data.

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