Transmitter, transceiver device, and communication system

Abstract

The embodiment of the invention provides a transmitter, a transceiving device and a communication system. The transceiver comprises a first output end and a second output end which are suitable for being coupled to a high level signal line and a low level signal line of a controller area network bus through a common mode inductor respectively; a differential input resistor coupled between the first output terminal and the second output terminal and coupled to a common mode potential; a main transmission circuit; the compensation component comprises a current compensation loop coupled to the first output end and the second output end, and is configured as follows: when a short circuit occurs between the high-level signal line and the first reference potential or a short circuit occurs between the low-level signal line and the second reference potential, the current compensation loop is coupled to the first output end and the second output end; the inductive current flowing through the common mode inductor is conducted through the current compensation loop to bypass the differential input resistor during output of the hidden signal. According to the embodiment of the invention, the short-circuit communication of the CAN bus can be supported under the condition that the common-mode inductor is arranged.

Description

Technical Field

[0001] The present disclosure relates to communication and electronic technologies, and more particularly, to a transmitter, a transceiver device including the transmitter, and a communication system. Background Art

[0002] Controller Area Network (CAN) is a serial communication bus used to implement distributed real-time control. CAN technology has the advantages of flexibility, anti-interference, and high scalability, thus providing a simple, efficient and reliable communication solution. At present, CAN technology is used in almost all automotive systems, and is also widely used in industrial automation, shipbuilding and other fields.

[0003] In the application of CAN technology, in order to improve electromagnetic compatibility (EMC), common-mode inductors can be set between CAN buses. However, the introduction of common-mode inductors will have an adverse effect on communication when a short circuit occurs on the CAN bus. In the event of a short circuit on the CAN bus, the freewheeling characteristics of the common-mode inductors will cause the voltage on the bus terminal of the transmitter circuit to be raised to an excessively high voltage level or pulled down to an excessively low voltage level, triggering the electrostatic discharge (ESD) protection action, thereby causing communication failure. Summary of the invention

[0004] In order to at least partially solve the above and other possible problems, embodiments of the present disclosure provide an improved transmitter, a transceiver device including the transmitter, and a communication system.

[0005] In a first aspect of the present disclosure, a transmitter is provided. The transmitter includes: a first output terminal and a second output terminal, adapted to be respectively coupled to a high-level signal line and a low-level signal line of a controller area network (CAN) bus via a common-mode inductor; a differential input resistor, coupled between the first output terminal and the second output terminal, and coupled to a common-mode potential; a main transmitting circuit, coupled to a first reference potential and a second reference potential lower than the first reference potential, and configured to output a dominant signal or a recessive signal at the first output terminal and the second output terminal according to an input signal; and a compensation component, including a current compensation loop coupled to the first output terminal and the second output terminal, and configured to: in the case of a short circuit between the high-level signal line and the first reference potential or a short circuit between the low-level signal line and the second reference potential, conduct the inductor current flowing through the common-mode inductor during the output of the recessive signal via the current compensation loop to bypass the differential input resistor.

[0006] In a second aspect of the present disclosure, a transceiver device is provided, comprising: a transmitter according to the first aspect; and a receiver.

[0007] In a third aspect of the present disclosure, a communication system is provided, comprising: a controller area network (CAN) bus; a common mode inductor; and a transceiver according to the second aspect, coupled to the CAN bus via the common mode inductor.

[0008] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present disclosure.

[0010] Figure 1 A schematic circuit diagram of a communication system according to an embodiment of the present disclosure is shown.

[0011] Figure 2 A schematic circuit diagram of a transmitter and a CAN bus component according to an embodiment of the present disclosure is shown.

[0012] Figure 3A and Figure 3B A schematic state diagram of a transmitter and a CAN bus component is shown when a high-level signal line of the CAN bus is short-circuited and a compensation component is not enabled according to an embodiment of the present disclosure.

[0013] Figure 4 A schematic state diagram of a transmitter and a CAN bus component is shown in a case where a high-level signal line of the CAN bus is short-circuited and a compensation component is enabled according to an embodiment of the present disclosure.

[0014] Figure 5A and Figure 5B A schematic state diagram of a transmitter and a CAN bus component is shown when a low-level signal line of the CAN bus is short-circuited and a compensation component is not enabled according to an embodiment of the present disclosure.

[0015] Figure 6 A schematic state diagram of a transmitter and a CAN bus component is shown when a low-level signal line of the CAN bus is short-circuited and a compensation component is enabled according to an embodiment of the present disclosure.

[0016] Figure 7An exemplary circuit structure diagram of a transmitter and a CAN bus component according to an embodiment of the present disclosure is shown.

[0017] Figure 8 An exemplary circuit diagram of a control circuit of a compensation component in a transmitter according to an embodiment of the present disclosure is shown.

[0018] Fig.9A , Fig. 9B , Fig. 10A and Fig. 10B A schematic state diagram of a transmitter and CAN bus components according to an embodiment of the present disclosure is shown.

[0019] Fig.11A and Fig. 11B The potential waveform diagrams of the first output terminal and the second output terminal before and after applying the compensation component in the transmitter 100 according to the embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0020] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. Those skilled in the art can obtain alternative technical solutions from the following description without departing from the spirit and scope of protection of the present disclosure.

[0021] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one example embodiment". Other explicit and implicit definitions may also be included below.

[0022] As mentioned above, the setting of common-mode inductors helps to improve the EMC compatibility and EMC performance of the CAN bus. Common-mode inductors can not only effectively filter out common-mode interference on the CAN bus without affecting differential signals, but also filter out common-mode interference generated by the signal line itself to the outside, thereby meeting the EMC requirements in vehicles and other industrial applications. However, due to the freewheeling characteristics of the inductor in the common-mode inductor (that is, the inductor current cannot change suddenly), the common-mode inductor will also have some negative effects on CAN communication, especially in the case of a short circuit on the CAN bus. When the high-level signal line of the CAN bus is short-circuited to the power supply, as the signal on the CAN bus changes from dominant to recessive, the common-mode inductor continues to store a large current in the dominant state. This large current will flow to the impedance inside the transmitter circuit and produce a large voltage drop, causing the voltage on the bus terminal of the transmitter circuit to be raised to the voltage that triggers the ESD protection, and ultimately causing the CAN communication to fail. Similarly, when the ground-level signal line of the CAN bus is short-circuited to the ground, as the signal on the CAN bus changes from dominant to recessive, a large current in the dominant state continues to exist on the common-mode inductor. This large current will flow to the impedance inside the transmitter circuit and produce a large voltage drop, causing the voltage on the bus terminal of the transmitter circuit to be pulled down to the voltage that triggers the ESD protection, ultimately causing CAN communication failure.

[0023] The embodiments of the present disclosure provide an improved transmitter solution. By introducing a compensation component in the transmitter, the larger residual current in the common-mode inductor can be guided to the current compensation loop in the compensation component in the case of a short circuit on the CAN bus, thereby avoiding the residual current from raising or lowering the voltage on the bus terminal of the transmitter and triggering ESD protection. Thus, even if a common-mode inductor is provided, and the high-level signal line of the CAN bus is short-circuited to the power supply or the low-level signal line is short-circuited to the ground, the transmitter and the CAN bus system connected thereto can still maintain normal CAN communication. Therefore, through the embodiments of the present disclosure, the EMC performance and EMC compatibility of the transmitter, the transceiver and the related node equipment can be improved by using the common-mode inductor, while the CAN communication in the short-circuit state can be improved at a lower cost, thereby improving the fault tolerance, reliability and flexibility of the system.

[0024] Figure 1 FIG. 1 shows a schematic circuit diagram of a communication system 10 according to an embodiment of the present disclosure. Figure 1As shown, the communication system 10 includes a plurality of electronic control units (ECUs) ECU1, ECU2, and ECU3 and a CAN bus assembly 200, and the CAN bus assembly 200 may include a CAN bus 210. Each ECU may serve as a communication node of the system and communicate with each other through the CAN bus assembly 200. It is understood that in addition to the ECU, the communication system 10 may also include other types of devices as communication nodes, and may include more than Figure 1 The present disclosure does not limit the communication nodes with more or fewer nodes shown in the figure. Each ECU as a communication node may include a transceiver. For example, ECU1 includes a transceiver 1000, and the transceiver 1000 may include a transmitter 100 and a receiver 300, whereby ECU1 can use the transmitter 100 to send a signal to the CAN bus component 200, or use the receiver 300 to receive a signal from the CAN bus component 200 to achieve communication with other ECUs or nodes. In addition, the communication system 10 also includes a common mode inductor 220. The common mode inductor 220 is coupled between the transceiver 1000 and the CAN bus 210 to help suppress the communication common mode signal and filter out the common mode interference to the outside world, thereby improving the EMC performance.

[0025] Figure 2 FIG. 2 shows a schematic circuit diagram of a transmitter 100 and a CAN bus component 200 according to an embodiment of the present disclosure. Figure 2 As shown, in the CAN bus component 200, the CAN bus 210 includes a high-level signal line CANH and a low-level signal line CANL, and the common-mode inductor 220 includes an inductor L0 and an inductor L1 that are magnetically coupled to each other. The transmitter 100 includes a first output terminal 111 and a second output terminal 112, and the first output terminal 111 and the second output terminal 112 are respectively coupled to the high-level signal line CANH and the low-level signal line CANL of the CAN bus 210 via the common-mode inductor 220. Specifically, the first output terminal 111 is coupled to the high-level signal line CANH via the inductor L0, and the second output terminal 112 is coupled to the low-level signal line CANL via the inductor L1.

[0026] The transmitter 100 further includes a differential input resistor 120, which is coupled between the first output terminal 111 and the second output terminal 112. The transmitter 100 may include a common mode generation circuit 140, which may select or set an appropriate common mode potential, such as a potential of 0V or 2.5V, according to different operating modes, and couple the appropriate common mode potential to the differential input resistor 120 to provide the common mode potential to the transmitter 100. As an example, the common mode potential selected or set by the common mode generation circuit 140 may be coupled to a middle position between both ends of the differential input resistor 120 via a tap.

[0027] The transmitter 100 also includes a main transmission circuit 130, which is coupled to a first reference potential and a second reference potential lower than the first reference potential. As an example, the first reference potential may be a power supply potential VCC, and the second reference potential may be a ground potential GND. The main transmission circuit 130 may output a dominant signal or a recessive signal at a first output terminal 111 and a second output terminal 112 according to an input signal TXD. Specifically, the main transmission circuit 130 may apply or stop applying the first reference potential and the second reference potential to the first input terminal 111 and the second input terminal 112, respectively, according to the input signal TXD. Thus, the transmitter 100 may controllably generate a differential voltage on the high-level signal line CANH and the low-level signal line CANL of the CAN bus 210 to transmit data, and a receiver of another node (e.g., ECU2 or ECU3) in the communication system 10 may receive data according to the generated differential voltage. When the voltage difference between the high-level signal line CANH and the low-level signal line CANL is large, the signal on the CAN bus 210 is called a dominant signal or is in a dominant state, and in the case of a dominant signal or a dominant state, the level of the input signal TXD of the transmitter 100 or the output signal of the receiver 300 can be low. When the voltage difference between the high-level signal line CANH and the low-level signal line CANL is small, the signal on the CAN bus 210 is called a recessive signal or is in a dominant state, and in the case of a recessive signal or a recessive state, the level of the input signal TXD of the transmitter 100 or the output signal of the receiver 300 can be high. When the CAN bus 210 is idle, the signal on the CAN bus 210 is in a recessive state.

[0028] According to an embodiment of the present disclosure, the transmitter 100 includes a compensation component 150, and the compensation component 150 includes a current compensation loop coupled to the first output terminal 111 and the second output terminal 112. In the case of a short circuit between the high-level signal line CANH and the first reference potential VCC, or a short circuit between the low-level signal line CANL and the second reference potential GND, the compensation component 150 can conduct the inductance current flowing through the common-mode inductor 220 via the current compensation loop to bypass the differential input resistor 120 during the output of the recessive signal. In this way, the compensation component 150 can guide the residual current on the common-mode inductor 220 that cannot be suddenly changed to the current compensation loop during the conversion of the CAN bus 210 from the dominant state to the recessive state, which avoids the residual current flowing into the differential input resistor 120 and the common-mode potential to cause the potential of the first output terminal 111 and the second output terminal 112 to rise or drop and trigger ESD protection. Thus, in the case of a short circuit on the CAN bus, the transmitter 100 can still support CAN communication in a system provided with a common-mode inductor.

[0029] Figure 3A and Figure 3B A schematic state diagram of the transmitter 100 and the CAN bus component 200 is shown in the case where a short circuit occurs at CANH of the CAN bus 210 and the compensation component 150 is not enabled.

[0030] exist Figure 3A In the example, the high-level signal line CANH is shorted to the first reference potential VCC at F1, and the input signal TXD is 0. At this time, the high-level signal line CANH and the low-level signal line CANL should be in a dominant state, and the first reference potential VCC is applied to the first output terminal 111, and the second reference potential GND is applied to the second output terminal 112 to generate a differential voltage on the CAN bus. The current I L1 The current flows from the short-circuit point F1 to the second reference potential GND via the high-level signal line CANH, the bus load resistor 230, the low-level signal line CANL, the inductance L1 of the common-mode inductor 220, the second output terminal 112, and the main transmitting circuit 130. In addition, since the first output terminal 111 and the high-level signal line CANH are both at the first reference potential VCC, no current flows through the inductance L0 of the common-mode inductor 220.

[0031] exist Figure 3B In the embodiment, the high-level signal line CANH is shorted to the first reference potential VCC at F1, and the input signal TXD is 1. At this time, the high-level signal line CANH and the low-level signal line CANL should be in a recessive state, and the first reference potential VCC stops being applied to the first output terminal 111, and the second reference potential GND stops being applied to the second output terminal 112. Since there is a current I flowing through the inductance L1 of the common-mode inductor 220 in the dominant state, L1 , and after switching to the recessive state, the current cannot change suddenly, so there is still a current I L1 The current I flows from the short-circuit point F1 through the bus load resistor 230 and through the inductor L1. In the recessive state, the path from the second output terminal 112 to the second reference potential GND through the main transmitting circuit 130 has been blocked, so the current I L1 After flowing through the inductor L1, the current I flows into the common mode potential selected or set by the common mode generating circuit 140 through the differential input resistor 120. As a result, the potential of the second output terminal 112 becomes the common mode potential and the current I L1 The voltage drop on the differential input resistor 120 is the sum of the voltage drops, which greatly increases the potential of the second output terminal 112. In addition, since the inductor L0 and the inductor L1 are magnetically coupled to each other, the current I flowing through the inductor L1 is L1 It will also induce a current I flowing through the inductor L0 L0 The induced current I L0The common mode potential will flow from the short-circuit point F1 through the inductor L0, the first output terminal 111 and the differential input resistor 120. As a result, the potential of the first output terminal 111 will become the common mode potential and the current I L0 The sum of the voltage drops on the differential input resistor 120 greatly increases the potential of the first output terminal 111. The increase in the potentials of the second output terminal 112 and the first output terminal 111 may trigger the ESD protection, thereby causing the CAN communication to fail.

[0032] Figure 4 FIG. 2 shows a schematic state diagram of the transmitter 100 and the CAN bus component 200 when a short circuit occurs in the CANH of the CAN bus 210 and the compensation component 150 is enabled according to an embodiment of the present disclosure. Figure 3B The same thing is that in Figure 4 In the example, the input signal TXD is also 1, and the high-level signal line CANH is also short-circuited to the first reference potential VCC at F1. Figure 3B The difference is that Figure 4 The transmitter 100 in the embodiment starts the compensation component 150. At this time, the high-level signal line CANH and the low-level signal line CANL should be in a recessive state, so that the main transmitting circuit 130 stops applying the first reference potential VCC to the first output terminal 111 and stops applying the second reference potential GND to the second output terminal 112. Since there is a current I flowing through the inductance L1 of the common-mode inductor 220 in the dominant state, L1 (See Figure 3A ), and after transitioning to the recessive state, the current cannot change suddenly, so there is still a current I L1 The current I flows from the short-circuit point F1 through the bus load resistor 230 and through the inductor L1. Although the path from the second output terminal 112 to the second reference potential GND through the main transmitting circuit 130 has been blocked, the compensation component 150 provides a current compensation loop to guide the current I L1 , so the residual current I of inductor L1 L1 The current I induced on the inductor L0 can flow into the second reference potential GND through the current compensation loop of the compensation component 150. L0 It can also flow into the second reference potential GND through the current compensation loop of the compensation component 150. Therefore, the compensation component 150 can avoid the continued current I of the common mode inductor when CANH is shorted to the first reference potential VCC. L0 and current I L1 The current flows through the differential input resistor 120 and thus further flows into the common mode potential, thereby raising the potentials of the first output terminal 111 and the second output terminal 112 .

[0033] Figure 5A and Figure 5BA schematic state diagram of the transmitter 100 and the CAN bus component 200 is shown in the case where a short circuit occurs in CANL of the CAN bus 210 and the compensation component 150 is not enabled.

[0034] exist Figure 5A In the example, the low-level signal line CANL is shorted to the second reference potential GND at F2, and the input signal TXD is 0. At this time, the high-level signal line CANH and the low-level signal line CANL should be in a dominant state, and the first reference potential VCC is applied to the first output terminal 111, and the second reference potential GND is applied to the second output terminal 112 to generate a differential voltage on the CAN bus. The current I L0 The first reference potential VCC flows into the short-circuit point F2 via the main transmitting circuit 130, the first output terminal 111, the inductance L0 of the common mode inductor 220, the high level signal line CANH, the bus load resistor 230, and the low level signal line CANL. In addition, since the second output terminal 112 and the low level signal line CANL are both at the second reference potential GND, no current flows through the inductance L1 of the common mode inductor 220.

[0035] exist Figure 5B In the embodiment, the low-level signal line CANL is shorted to the second reference potential GND at F2, and the input signal TXD is 1. At this time, the high-level signal line CANH and the low-level signal line CANL should be in a recessive state, and the first reference potential VCC stops being applied to the first output terminal 111, and the second reference potential GND stops being applied to the second output terminal 112. Since there is a current I flowing through the inductance L0 of the common-mode inductor 220 in the dominant state, L0 , and after transitioning to the recessive state, the current I L0 Cannot change suddenly, so there is still current I L0 Flows through the inductor L0, and further flows into the short-circuit point F2 via the high-level signal line CANH, the bus load resistor 230 and the low-level signal line CANL. In the recessive state, the path from the first output terminal 111 to the first reference potential VCC through the main transmitting circuit 130 has been blocked, so the current I L0 The common mode potential selected or set by the common mode generating circuit 140 flows to the inductor L0 via the differential input resistor 120. Thus, the potential of the first output terminal 111 becomes the common mode potential and the current I L0 The voltage drop difference on the differential input resistor 120 greatly lowers the potential of the first output terminal 111. In addition, since the inductor L0 and the inductor L1 are magnetically coupled to each other, the current I flowing through the inductor L0 is L0 It will also induce a current I flowing through the inductor L1 L1 The induced current I L1The common mode potential will flow into the short-circuit point F2 via the differential input resistor 120, the second output terminal 112, the inductor L1 and the low-level signal line CANL. As a result, the potential of the second output terminal 112 will become the common mode potential and the current I L1 The voltage drop difference on the differential input resistor 120 greatly lowers the potential of the second output terminal 112. The lowering of the potentials of the first output terminal 111 and the second output terminal 112 may trigger the ESD protection, thereby causing the CAN communication failure.

[0036] Figure 6 FIG. 2 shows a schematic state diagram of the transmitter 100 and the CAN bus component 200 when a short circuit occurs in CANL of the CAN bus 210 and the compensation component 150 is enabled according to an embodiment of the present disclosure. Figure 5B The same thing is that in Figure 6 In the example, the input signal TXD is also 1, and the low-level signal line CANL is also shorted to the second reference potential GND at F2. Figure 5B The difference is that Figure 6 A compensation component 150 is further introduced in the embodiment. At this time, the high-level signal line CANH and the low-level signal line CANL should be in a recessive state, so that the main transmitting circuit 130 stops applying the first reference potential VCC to the first output terminal 111 and stops applying the second reference potential GND to the second output terminal 112. Since there is a current I flowing through the inductance L0 of the common-mode inductor 220 in the dominant state, L0 (See Figure 5A ), and after transitioning to the recessive state, the current I L0 Cannot change suddenly, so there is still current I L0 The current I flows through the inductor L0 and further flows into the short-circuit point F2 via the high-level signal line CANH, the bus load resistor 230 and the low-level signal line CANL. Although the path from the first output terminal 111 to the first reference potential VCC through the main transmitting circuit 130 has been blocked, the compensation component 150 provides a current compensation loop to guide the current I L0 , so the residual current I of inductor L0 L0 The current compensation loop of the compensation component 150 can provide a path. Similarly, the current I induced on the inductor L1 L1 The current compensation loop of the compensation component 150 can also provide a path. It can be seen that the compensation component 150 can avoid the continued current I of the common mode inductor when CANL is shorted to the second reference potential GND. L0 and current I L1 The current flows through the differential input resistor 120 and thus flows out of the common mode potential, thereby pulling down the potentials of the first output terminal 111 and the second output terminal 112 .

[0037] It can be seen that, through the compensation component 150, even if a common-mode inductor is provided in the system and a short circuit of CANH to the first reference potential VCC or a short circuit of CANL to the second reference potential GND occurs, the transmitter 100 can still complete normal communication operations without triggering ESD protection, which improves the EMC performance and EMC compatibility while eliminating the adverse effects of the common-mode inductor, thereby improving the reliability of CAN communication.

[0038] In some embodiments of the present disclosure, the compensation component 150 is configured to conduct the inductor current of the common-mode inductor 220 via the current compensation loop in a manner that both the current magnitude and the current change rate are reduced. Specifically, the compensation component 150 can gradually reduce the conducted inductor current in a manner that the current change rate is reduced. In this way, not only the residual current on the common-mode inductor can be reduced, but also the induced potential on the common-mode inductor can be reduced to avoid generating new current, thereby better absorbing the residual energy on the common-mode inductor 220. As a result, the compensation component 150 can be removed from the transmitter 100 after a certain period of time to avoid the influence of the compensation component 150 on the CAN communication.

[0039] In some embodiments of the present disclosure, the compensation component 150 is configured to conduct the inductor current of the common-mode inductor 220 through the current compensation loop in a manner in which the current magnitude decays exponentially. Specifically, by conducting the current in an exponentially decaying manner, the compensation component 150 can ensure that the inductor current decays rapidly at a very high current change rate in the initial period, and gradually reduces the current change rate to zero or a level close to zero during the process of decaying to zero or a lower current level. In this way, the residual current and the induced potential of the common-mode inductor 220 can be reduced to zero or a very low level in a very short time, so that the absorption operation can be completed quickly and the compensation component 150 can be cut off from the transmitter 100, and the inductor current will not still exist or be generated after the compensation component 150 is cut off and flow through the differential input resistor 120.

[0040] Figure 7 FIG. 1 shows an exemplary circuit structure diagram of a transmitter 100 and a CAN bus component 200 according to an embodiment of the present disclosure. Figure 7 2 shows in detail the internal circuits of the compensation component 150 and the main transmission circuit 130. It is understood that the implementation of the compensation component 150 and the main transmission circuit 130 is not limited thereto, and other circuits and implementations consistent with the principles of the present disclosure may be used to implement them.

[0041] In some embodiments of the present disclosure, the main transmission circuit 130 includes a transmission logic circuit 131, a first drive switch PS1, and a second drive switch PS2. The first drive switch PS1 is coupled between the first reference potential VCC and the first output terminal 111, and the second drive switch PS2 is coupled between the second output terminal 112 and the second reference potential GND. The transmission logic circuit 131 is coupled to the control terminals of the first drive switch PS1 and the second drive switch PS2. When the input signal TXD is a first level (e.g., a level corresponding to 0), the transmission logic circuit 131 turns on the first drive switch PS1 and the second drive switch PS2 to apply the first reference potential VCC to the first output terminal 111 and the second reference potential GND to the second output terminal 112, thereby generating a differential voltage at the high-level signal line CANH and the low-level signal line CANL to present a dominant state. When the input signal TXD is a second level different from the first level (e.g., a level corresponding to 1), the transmission logic circuit 131 turns off the first drive switch PS1 and the second drive switch PS2 to stop applying the first reference potential VCC to the first output terminal 111 and stop applying the second reference potential GND to the second output terminal 112, thereby presenting a recessive state. In one embodiment, the main transmission circuit 130 also includes a diode PS3 and a diode PS4 for blocking a reverse voltage, wherein the diode PS3 is coupled between the first drive switch PS1 and the first output terminal 111, and the diode PS4 is coupled between the second output terminal 112 and the second drive switch PS2. As an example, the diode PS3 and the diode PS4 can be implemented using a body diode of a laterally diffused metal oxide semiconductor (LDMOS). That is, LDMOS tubes can be respectively provided at the positions where the diodes PS3 and PS4 are located, and the body diodes of the LDMOS tubes are used to prevent reverse voltage.

[0042] In some embodiments of the present disclosure, the current compensation loop of the compensation component 150 includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The first switch S1 is coupled between the first output terminal 111 and the intermediate node MD, the second switch S2 is coupled between the second output terminal 112 and the intermediate node MD, the third switch S3 is coupled between the intermediate node MD and the second reference potential GND, and the fourth switch S4 is coupled between the intermediate node MD and the first reference potential VCC. By controlling the on and off of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, a path from the first output terminal 111 and the second output terminal 112 to the second reference potential GND or to the first reference potential VCC can be effectively formed. For example, in the case where it is necessary to bypass the differential input resistor 120 and guide the inductor current to the second reference potential GND (for example Figure 4 ), the first switch S1, the second switch S2 and the third switch S3 can be turned on, and in the case where the differential input resistor 120 needs to be bypassed and the inductor current is guided to the first reference potential VCC (for example Figure 6 ), the first switch S1, the second switch S2 and the fourth switch S4 can be turned on. In this way, the current compensation loop can be implemented in a simple and reliable manner without causing a short circuit between the first output terminal 111, the second output terminal 112, the first reference potential VCC and the second reference potential GND in other stages where the inductor current does not need to be absorbed. Alternatively, the current compensation loop of the compensation component 150 can also remove one of the third switch S3 and the fourth switch S4 and retain the other. For example, when the transmitter 100 only needs to support communication in the case where the high-level signal line CANH is short-circuited to the first reference potential VCC, only a path from the first output terminal 111 and the second output terminal 112 to the second reference potential GND via the current compensation loop can be set, so the current compensation loop can include the first switch S1, the second switch S2 and the third switch S3 and remove the fourth switch S4. When the transmitter 100 only needs to support communication when the low-level signal line CANL is short-circuited to the second reference potential GND, only a path from the first reference potential VCC to the first output terminal 111 and the second output terminal 112 via the current compensation loop can be set, so the current compensation loop can include the first switch S1, the second switch S2 and the fourth switch S4 and remove the third switch S3.

[0043] In some embodiments of the present disclosure, the current compensation loop further includes a first resistor R1 and a second resistor R2, the first resistor R1 and the first switch S1 are coupled in series between the first output terminal 111 and the middle node MD, and the second resistor R2 and the second switch S2 are coupled in series between the second output terminal 112 and the middle node MD. With the help of the resistors R1 and R2, the current compensation loop can dissipate and attenuate the inductor current flowing through the current compensation loop faster, thereby absorbing the residual energy of the common mode inductor.

[0044] In some embodiments of the present disclosure, the current compensation loop further includes a first MOS transistor MOS1 and a second MOS transistor MOS2. The first MOS transistor MOS1 and the third switch S3 are coupled in series between the second reference potential GND and the middle node MD, and the second MOS transistor MOS2 and the fourth switch S4 are coupled in series between the first reference potential VCC and the middle node MD. By setting the first MOS transistor MOS1 and the second MOS transistor MOS2, the current reduction in the current compensation loop can be controlled in an advantageous manner after the current compensation loop connects the path to the second reference potential GND or connects the path from the first reference potential VCC. Specifically, according to the square law characteristics of the MOS tube, if the gate-source voltage of the MOS tube is properly controlled, the magnitude and rate of change of the current flowing through the MOS tube can be reduced. When a linearly decreasing voltage is applied between the gate and source of the MOS tube, the current flowing through the MOS tube can even decay in an ideal manner close to exponential decay, thereby quickly reducing the residual current and induced potential of the common-mode inductance in a shorter time. Alternatively, the current compensation loop of the compensation component 150 can also remove one of the first MOS transistor MOS1 and the second MOS transistor MOS2 and retain the other. For example, when the transmitter 100 only needs to support communication when the high-level signal line CANH is short-circuited to the first reference potential VCC, the branch of the fourth switch S4 and the second MOS tube MOS2 can be removed; and when the transmitter 100 only needs to support communication when the low-level signal line CANL is short-circuited to the second reference potential GND, the branch of the third switch S3 and the first MOS tube MOS1 can be removed.

[0045] In some embodiments of the present disclosure, the compensation component 150 further includes a first charge-discharge circuit 151 and a second charge-discharge circuit 152. The first charge-discharge circuit 151 includes a first capacitor C1, a first constant current source I1, a first charging switch CS1, and a first discharging switch DS1. The first capacitor C1 is connected across the gate and source of the first MOS transistor MOS1. The first charging switch CS1 is coupled to the first capacitor C1 and is used to charge the first capacitor C1. The series branch of the first constant current source I1 and the first discharging switch DS1 is coupled to the first capacitor C1 and is used to discharge the first capacitor C1. The second charge-discharge circuit 152 includes a second capacitor C2, a second constant current source I2, a second charging switch CS2, and a second discharging switch DS2. The second capacitor C2 is connected across the gate and source of the second MOS transistor MOS2. The second charging switch CS2 is coupled to the second capacitor C2 and is used to charge the second capacitor C2. The series branch of the second constant current source I2 and the second discharging switch DS2 is coupled to the second capacitor C2 and is used to discharge the second capacitor C2. Alternatively, the current compensation loop of the compensation component 150 may also remove one of the first charge-discharge circuit 151 and the second charge-discharge circuit 152 and retain the other. For example, when the transmitter 100 only needs to support communication in the case where the high-level signal line CANH is short-circuited to the first reference potential VCC and the branch of the fourth switch S4 and the second MOS transistor MOS2 is not set, the second charge-discharge circuit 152 may be removed, and when the transmitter 100 only needs to support communication in the case where the low-level signal line CANL is short-circuited to the second reference potential GND and the branch of the third switch S3 and the first MOS transistor MOS1 is not set, the first charge-discharge circuit 151 may be removed.

[0046] As an example, in the first charge and discharge circuit 151, the first charge switch CS1 can be coupled between the first capacitor C1 and the first reference potential VCC, and the first discharge switch DS1 and the first constant current source I1 can be coupled between the first capacitor C1 and the second reference potential GND. Thus, when the current compensation loop of the compensation component 150 does not need to conduct or guide the inductor current of the common-mode inductor, the first charge switch CS1 can be turned on to charge the first capacitor C1, and when the high-level signal line CANH is shorted to the first reference potential VCC and the current compensation loop of the compensation component 150 needs to conduct or guide the inductor current, the first charge switch CS1 can be turned off and the first discharge switch DS1 can be turned on, so as to discharge the first capacitor C1 with the constant current of the first constant current source I1. During the discharge process of the first capacitor C1, the capacitance value C of the first capacitor C1, the voltage u across the first capacitor C1, and the voltage u across the first capacitor C1 are connected. C , the current i of the first constant current source I1 d And the discharge time t d The relationship between C*uC =i d *t d This equation can be further transformed into C =i d *t d / C. It can be seen that the current i in the first constant current source I1 d When the current is fixed, the voltage u across the first capacitor C1 is C Can i d The rate of change of / C decreases linearly as the discharge time increases. In this way, when the high-level signal line CANH is short-connected to the first reference potential VCC, when the current compensation loop needs to conduct or guide the inductor current of the common-mode inductor 220, the discharge process of the first capacitor C1 can be used to apply a linearly decreasing gate-source voltage to the first MOS transistor MOS1. According to the square law characteristics of the MOS transistor, when the gate-source voltage decreases linearly, the current flowing through the first MOS transistor MOS1 can be reduced in a manner close to exponential decay, thereby reducing the magnitude and rate of change of the inductor current of the common-mode inductor 220 to zero or to a lower level close to zero in a relatively short time.

[0047] As an example, in the second charge and discharge circuit 152, the second charge switch CS2 can be coupled between the second capacitor C2 and the second reference potential GND, and the second discharge switch DS2 and the second constant current source I2 can be coupled between the second capacitor C2 and the first reference potential VCC. Thus, when the current compensation loop of the compensation component 150 does not need to conduct or guide the inductor current of the common-mode inductor, the second charge switch CS2 can be turned on to charge the second capacitor C2, and when the low-level signal line CANL is shorted to the second reference potential GND and the current compensation loop of the compensation component 150 needs to conduct or guide the inductor current, the second charge switch CS2 can be turned off and the second discharge switch DS2 can be turned on, so as to discharge the second capacitor C2 with the constant current of the second constant current source I2. During the discharge process of the second capacitor C2, the capacitance value C of the second capacitor C2, the voltage u across the second capacitor C2, and the voltage u across the second capacitor C2 are all equal to the capacitance value C of the second capacitor C2. C , the current i of the second constant current source I2 d And the discharge time t d The relationship between C*u C =i d *t d This equation can be further transformed into C =i d *t d / C. It can be seen that the current i in the second constant current source I2 d When the current is fixed, the voltage u across the second capacitor C2 is C Can id The rate of change of / C decreases linearly as the discharge time increases. In this way, when the low-level signal line CANL is shorted to the second reference potential GND, when the current compensation loop needs to conduct or guide the inductor current of the common-mode inductor 220, the discharge process of the second capacitor C2 can be used to apply a linearly reduced gate-source voltage to the second MOS transistor MOS2. According to the square law characteristics of the MOS transistor, when the gate-source voltage decreases linearly, the current flowing through the second MOS transistor MOS12 can be reduced in a manner close to exponential decay, thereby reducing the magnitude and rate of change of the inductor current of the common-mode inductor 220 to zero or to a lower level close to zero in a relatively short time.

[0048] In some embodiments of the present disclosure, the compensation component 150 further includes a first detection circuit 153, a first pulse generating circuit 154, a second detection circuit 156, and a second pulse generating circuit 157. The first detection circuit 153 and the first pulse generating circuit 154 are coupled in series to the first output terminal 111. The first detection circuit 153 is used to detect a short circuit of the high-level signal line CANH, and generates an indication signal when a short circuit occurs between the high-level signal line CANH and the first reference potential VCC, and the first pulse generating circuit 154 generates a first pulse signal SP1 with a predetermined pulse width based on the indication signal of the first detection circuit 153. The second detection circuit 156 and the second pulse generating circuit 157 are coupled in series to the second output terminal 112. The second detection circuit 156 is used to detect a short circuit of the low-level signal line CANL, and generates an indication signal when a short circuit occurs between the low-level signal line CANL and the second reference potential GND, and the second pulse generating circuit 157 generates a second pulse signal SP2 with a predetermined pulse width based on the indication signal of the second detection circuit 156. Alternatively, the current compensation loop of the compensation component 150 may also remove the second detection circuit 156 and the second pulse generating circuit 157 while retaining the first detection circuit 153 and the first pulse generating circuit 154, or remove the first detection circuit 153 and the first pulse generating circuit 154 while retaining the second detection circuit 156 and the second pulse generating circuit 157. For example, when the transmitter 100 only needs to support communication in the case where the high-level signal line CANH is short-circuited to the first reference potential VCC, only the first detection circuit 153 and the first pulse generating circuit 154 may be provided, and when the transmitter 100 only needs to support communication in the case where the low-level signal line CANL is short-circuited to the second reference potential GND, only the second detection circuit 156 and the second pulse generating circuit 157 may be provided.

[0049] The first detection circuit 153 and the second detection circuit 156 can use various appropriate detection methods to detect whether the high-level signal line CANH and the low-level signal line CANL are short-circuited. For example, the first detection circuit 153 can obtain the potential or current of the first output terminal 111 or a position near it, and use a comparator to compare the obtained potential or current with a predetermined threshold value to determine whether the high-level signal line CANH is short-circuited to the first reference potential VCC. The second detection circuit 156 can determine whether the low-level signal line CANL is short-circuited to the second reference potential GND in a similar manner. In addition, the first pulse generating circuit 154 or the second pulse generating circuit 157 can be implemented, for example, by a delay unit to generate a short pulse of a predetermined pulse width based on the indication signal provided by the corresponding detection circuit, thereby triggering the current compensation loop to be turned on to absorb the inductor current of the common-mode inductor. The pulse width duration of the short pulse should be short, because a long pulse width duration will cause the current compensation loop to be turned on for a long time and affect normal CAN communication or affect the normal recessive state. However, the duration of the predetermined pulse width cannot be too short. If the pulse width is too short, the inductor current may still be large when the current compensation loop is cut off, triggering ESD protection and causing communication failure. Therefore, the predetermined pulse width of the short pulse can be set according to the duration of the current compensation loop to reduce the current size and rate of change to the desired level. In one example, the pulse width of the short pulse generated by the first pulse generating circuit 154 or the second pulse generating circuit 157 can be set to hundreds of nanoseconds.

[0050] In some embodiments of the present disclosure, the compensation component 150 further includes a control circuit 155. The control circuit 155 can control the first switch S1, the second switch S2, the third switch S3, the first charging switch CS1, and the first discharging switch DS1 to be turned on and off based on the input signal TXD and the first pulse signal SP1. The control circuit 155 can control the first switch S1, the second switch S2, the fourth switch S4, the second charging switch CS2, and the second discharging switch DS2 to be turned on and off based on the input signal TXD and the second pulse signal SP2.

[0051] As an example, the control circuit 155 can perform different switch operations according to the input signal TXD indicating the dominant state and the recessive state and the first pulse signal SP1 and the second pulse signal SP2 indicating the short circuit of the CAN bus. Specifically, in the dominant state (e.g., TXD=0), the control circuit 155 directly turns off the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 to cut off the current compensation loop. In addition, in the dominant state, the control circuit 155 turns on the first charging switch CS1 and the second charging switch CS2 to charge the first capacitor C1 and the second capacitor C2, and turns off the first discharge switch DS1 and the second discharge switch DS2. After the transition from the dominant state (e.g., TXD=0) to the recessive state (e.g., TXD=1), the control circuit 155 will switch the states of each switch based on the first pulse signal SP1 and the second pulse signal SP2. For example, after the transition to the recessive state, during the period when the first pulse signal SP1 is at a high level (i.e., the high-level signal line CANH is detected to be short-circuited to the first reference potential VCC), the control circuit 155 turns on the first switch S1, the second switch S2, and the third switch S3 to form a path from the first output terminal 111 and the second output terminal 112 to the second reference potential GND using the current compensation loop. In addition, the control circuit 155 also turns off the first charging switch CS1 and turns on the first discharging switch DS1 to reduce the current flowing through the first MOS transistor MOS1 in a manner close to exponential decay. After the transition to the recessive state, during the period when the second pulse signal SP2 is at a high level (i.e., the low-level signal line CANL is detected to be short-circuited to the second reference potential GND), the control circuit 155 turns on the first switch S1, the second switch S2, and the fourth switch S4 to form a path from the first reference potential VCC to the first output terminal 111 and the second output terminal 112 using the current compensation loop. In addition, the control circuit 155 also turns off the second charging switch CS2 and turns on the second discharging switch DS2 to reduce the current flowing through the second MOS transistor MOS2 in a manner close to exponential decay.

[0052] Figure 8 FIG. 1 shows a schematic circuit diagram of a control circuit 155 in a compensation component 150 according to an embodiment of the present disclosure. Figure 7 and Figure 8As shown, the control circuit 155 may include an OR gate 1551, a first AND gate 1552, a second AND gate 1553, and a third AND gate 1554. The first pulse signal SP1 and the second pulse signal SP2 are input to the OR gate 1551, and the output of the OR gate 1551 and the input signal TXD are input to the first AND gate 1552 to generate a control signal SW0 for controlling the first switch S1 and the second switch S2. The first pulse signal SP1 and the input signal TXD are input to the second AND gate 1553 to generate a control signal SW1 for controlling the third switch S3, the first charging switch CS1, and the first discharging switch DS1. The second pulse signal SP2 and the input signal TXD are input to the third AND gate 1554 to generate a control signal SW2 for controlling the fourth switch S4, the second charging switch CS2, and the second discharging switch DS2. Figure 7 and Figure 8 In the example shown, the first switch S1, the second switch S2, the third switch S3, the first discharge switch DS1 and the second charge switch CS2 are high level triggered switch devices (e.g., NMOS tubes), while the fourth switch S4, the second discharge switch DS2 and the first charge switch CS1 are low level triggered switch devices (e.g., PMOS tubes). However, the types of the above switches are only exemplary, and the types of switches can be changed as needed, and the present disclosure is not limited to this.

[0053] In addition, it can be understood that the implementation of the control circuit 155 is not limited thereto, but can be implemented using other circuits and implementations consistent with the principles of the present disclosure. For example, the control circuit 155 can also be implemented using a microcontroller with built-in software or firmware.

[0054] Fig.9A , Fig. 9B , Fig. 10A and Fig. 10B Shows Figure 7 The schematic state diagram of the transmitter 100 and the CAN bus component 200 in FIG. Fig.9A , Fig. 9B , Fig. 10A and Fig. 10B To describe Figure 7 0014 is an exemplary working process of the transmitter 100 in FIG.

[0055] exist Fig.9A, the high-level signal line CANH is short-circuited to the first reference potential VCC at F1, and the input signal TXD is 0. The transmitting logic circuit 131 receives the input signal of TXD being 0 and turns on the first drive switch PS1 and the second drive switch PS2. As a result, the first reference potential VCC and the second reference potential GND are applied to the CAN bus 210, so that a differential voltage is generated on the CAN bus 210, thereby presenting a dominant state. At this time, although the first detection circuit 153 detects that the high-level signal line CANH is short-circuited to the first reference potential VCC, since TXD=0, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are all turned off, and the first capacitor C1 and the second capacitor C2 are charged to the power supply voltage via the corresponding charging switches. Fig.9A As shown, the current in the inductor L1 of the common mode inductor 220 flows into the second reference potential GND via the second output terminal 112 , the diode PS4 , and the second drive switch PS2 .

[0056] exist Fig. 9B , the high-level signal line CANH is short-circuited to the first reference potential VCC at F1, and the input signal TXD changes from 0 to 1. The transmission logic circuit 131 receives the input signal of TXD being 1 and turns off the first drive switch PS1 and the second drive switch PS2. As a result, the CAN bus 210 is transformed into a recessive state. The first detection circuit 153 detects that the high-level signal line CANH is short-circuited to the first reference potential VCC, and instructs the first pulse generation circuit 154 to generate the first pulse signal SP1. Since TXD=1, the first pulse signal SP1 causes the control signals SW0 and SW1 to become high levels, thereby triggering the first switch S1, the second switch S2, the third switch S3 and the first discharge switch DS1 to turn on, and causing the first charging switch CS1 to turn off. Thus, a path from the first output terminal 111 to the second reference potential GND via the first resistor R1, the first switch S1, the third switch S3 and the first MOS transistor MOS1 is formed, and a path from the second output terminal 112 to the second reference potential GND via the second resistor R2, the second switch S2, the third switch S3 and the first MOS transistor MOS1 is formed, and the first capacitor C1 starts to discharge. Fig. 9BAs shown, the residual current in the inductor L0 of the common-mode inductor 220 flows into the second reference potential GND via the first output terminal 111, the diode PS3 (as mentioned above, the diode PS3 is the body diode of the LDMOS, and the current actually flows through the channel of the LDMOS), the first resistor R1, the first switch S1, the third switch S3 and the first MOS transistor MOS1, and the residual current in the inductor L1 of the common-mode inductor 220 flows into the second reference potential GND via the second output terminal 112, the diode PS4, the second resistor R2, the second switch S2, the third switch S3 and the first MOS transistor MOS1, thereby bypassing the input differential resistor 120 and absorbing the inductor current in a manner close to exponential decay using the current compensation loop.

[0057] exist Fig. 10A , the low-level signal line CANL is short-circuited to the second reference potential GND at F2, and the input signal TXD is 0. The transmitting logic circuit 131 receives the input signal of TXD being 0 and turns on the first drive switch PS1 and the second drive switch PS2. As a result, the first reference potential VCC and the second reference potential GND are applied to the CAN bus 210, so that a differential voltage is generated on the CAN bus 210, thereby presenting a dominant state. At this time, although the second detection circuit 156 detects that the low-level signal line CANL is short-circuited to the second reference potential GND, since TXD=0, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are all turned off, and the first capacitor C1 and the second capacitor C2 are charged to the power supply voltage via the corresponding charging switches. Fig. 10A As shown, the current in the inductor L0 of the common mode inductor 220 flows from the first reference potential VCC through the first drive switch PS1 , the diode PS3 , and the first output terminal 111 through the inductor L0 .

[0058] exist Fig. 10B, the low level signal line CANL is short-circuited to the second reference potential GND at F2, and the input signal TXD changes from 0 to 1. The transmission logic circuit 131 receives the input signal of TXD being 1 and turns off the first drive switch PS1 and the second drive switch PS2. As a result, the CAN bus 210 is transformed into a recessive state. The second detection circuit 156 detects that the low level signal line CANL is short-circuited to the second reference potential GND, and instructs the first pulse generation circuit 157 to generate the second pulse signal SP2. Since TXD=1, the second pulse signal SP2 causes the control signal SW0 to become a high level and the control signal SW2 to become a low level, thereby triggering the first switch S1, the second switch S2, the fourth switch S4 and the second discharge switch DS2 to turn on, and causing the second charging switch CS2 to turn off. Thus, a path from the first reference potential VCC via the second MOS transistor MOS2, the fourth switch S4, the first switch S1 and the first resistor R1 to the first output terminal 111 and a path from the first reference potential VCC via the second MOS transistor MOS2, the fourth switch S4, the second switch S2 and the second resistor R2 to the second output terminal 112 are formed, and the second capacitor C2 starts to discharge. Fig. 10B As shown, the residual current in the inductor L0 of the common-mode inductor 220 flows through the inductor L0 from the first reference potential VCC via the second MOS transistor MOS2, the fourth switch S4, the first switch S1, the first resistor R1, the diode PS3 and the first output terminal 111, and the residual current in the inductor L1 of the common-mode inductor 220 flows through the inductor L1 from the first reference potential VCC via the second MOS transistor MOS2, the fourth switch S4, the second switch S2, the second resistor R2, the diode PS4 (as mentioned above, the diode PS4 is the body diode of the LDMOS, and the current actually flows through the channel of the LDMOS) and the second output terminal 112, thereby bypassing the input differential resistor 120 and absorbing the inductor current in a manner close to exponential decay using the current compensation loop.

[0059] Fig.11A and Fig. 11B The potential waveform diagrams of the first output terminal 111 and the second output terminal 112 before and after the compensation component 150 is enabled in the transmitter 100 are shown.

[0060] Fig.11A This involves a short circuit between the high-level signal line CANH of the CAN bus 210 and the first reference potential VCC. Fig.11AIn the embodiment of the present invention, as shown in the potential curve in the form of a dotted line, the potentials of the first output terminal 111 and the second output terminal 112 before enabling the compensation component 150 will rise to as high as 75.34961V and 73.84861V, respectively. It can be seen that when the high-level signal line CANH is short-circuited, the larger residual current on the common-mode inductor causes the potential of the first output terminal 111 and the second output terminal 112 to be raised to about 75V, which will trigger the ESD protection and cause the communication failure. Further, as shown in the potential curve in the form of a solid line, the potentials of the first output terminal 111 and the second output terminal 112 after enabling the compensation component 150 drop to 36.49728V and 34.55076V, respectively. It can be seen that the compensation component 150 can effectively suppress the inductor current from flowing through the differential input resistor 120 and attenuate the inductor current, thereby dropping the potential of the first output terminal 111 and the second output terminal 112 to below 37V, avoiding the triggering of the ESD protection and ensuring the normal communication.

[0061] Fig. 11B The situation that a short circuit occurs between the low-level signal line CANL of the CAN bus 210 and the second reference potential GND. Fig. 11B As shown in the potential curve in dotted form, the potentials of the first output terminal 111 and the second output terminal 112 before enabling the compensation component 150 will drop to as low as -54.43756V and -55.32758V, respectively. It can be seen that when the low-level signal line CANL is short-circuited, the large residual current on the common-mode inductor causes the potentials of the first output terminal 111 and the second output terminal 112 to be pulled down to about -55V, which will trigger the ESD protection and cause communication failure. Further, as shown in the potential curve in solid form, the potentials of the first output terminal 111 and the second output terminal 112 after enabling the compensation component 150 rise to -37.18297V and -37.57153V, respectively. It can be seen that the compensation component 150 can effectively suppress the inductor current from flowing through the differential input resistor 120 and attenuate the inductor current, thereby raising the potential of the first output terminal 111 and the second output terminal 112 to above -37V, avoiding triggering ESD protection and ensuring normal communication.

[0062] Through the teachings given in the above description and the related drawings, many modifications and other embodiments of the present disclosure given here will be recognized by those skilled in the art of the present disclosure. Therefore, it is to be understood that the embodiments of the present disclosure are not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included in the scope of the present disclosure. In addition, although the above description and the related drawings describe the example embodiments in the context of some example combinations of parts and / or functions, it should be appreciated that different combinations of parts and / or functions can be provided by alternative embodiments without departing from the scope of the present disclosure. In this regard, for example, other combinations of parts and / or functions that are different from those clearly described above are also expected to be within the scope of the present disclosure. Although specific terms are used here, they are only used in a general and descriptive sense and are not intended to be limited.

Claims

1. A transmitter (100), comprising: A first output terminal (111) and a second output terminal (112), adapted to be respectively coupled to a high level signal line (CANH) and a low level signal line (CANL) of a controller area network CAN bus (210) via a common mode inductor (220); A differential input resistor (120) coupled between the first output terminal (111) and the second output terminal (112) and coupled to a common mode potential; a main transmitting circuit (130) coupled to a first reference potential (VCC) and a second reference potential (GND) lower than the first reference potential (VCC), and configured to output a dominant signal or a recessive signal at the first output terminal (111) and the second output terminal (112) according to an input signal (TXD); as well as A compensation component (150) comprises a current compensation loop coupled to the first output terminal (111) and the second output terminal (112), and is configured to: when a short circuit occurs between the high-level signal line (CANH) and the first reference potential (VCC) or a short circuit occurs between the low-level signal line (CANL) and the second reference potential (GND), conduct the inductor current flowing through the common-mode inductor (220) via the current compensation loop during the output of the recessive signal to bypass the differential input resistor (120).

2. The transmitter (100) according to claim 1, wherein the compensation component (150) is configured to conduct the inductor current of the common-mode inductor (220) through the current compensation loop in a manner in which both the current magnitude and the current change rate are reduced.

3. The transmitter (100) according to claim 2, wherein the compensation component (150) is configured to conduct the inductor current of the common-mode inductor (220) through the current compensation loop in a manner in which the current magnitude decays exponentially.

4. The transmitter (100) according to any one of claims 1 to 3, wherein the current compensation loop comprises: A first switch (S1) coupled between the first output terminal (111) and a middle node (MD); A second switch (S2) coupled between the second output terminal (112) and the intermediate node (MD); as well as a third switch (S3) and / or a fourth switch (S4), wherein the third switch (S3) is coupled between the middle node (MD) and the second reference potential (GND), and the fourth switch (S4) is coupled between the middle node (MD) and the first reference potential (VCC).

5. The transmitter (100) according to claim 4, wherein the current compensation loop further comprises a first MOS transistor (MOS1) and / or the second MOS transistor (MOS2), the first MOS transistor (MOS1) and the third switch (S3) are coupled in series between the second reference potential (GND) and the middle node (MD), and the second MOS transistor (MOS2) and the fourth switch (S4) are coupled in series between the first reference potential (VCC) and the middle node (MD).

6. The transmitter (100) of claim 5, wherein the compensation component (150) further comprises: a first charge and discharge circuit (151), comprising a first capacitor (C1), a first constant current source (I1), a first charging switch (CS1) and a first discharging switch (DS1), wherein the first capacitor (C1) is connected across the gate and source of the first MOS tube (MOS1), the first charging switch (CS1) is coupled to the first capacitor (C1) and is configured to charge the first capacitor (C1), and a series branch of the first constant current source (I1) and the first discharging switch (DS1) is coupled to the first capacitor (C1) and is configured to discharge the first capacitor (C1); and / or The second charge and discharge circuit (152) comprises a second capacitor (C2), a second constant current source (I2), a second charging switch (CS2) and a second discharging switch (DS2), wherein the second capacitor (C2) is connected across the gate and source of the second MOS tube (MOS2), the second charging switch (CS2) is coupled to the second capacitor (C2) and is configured to charge the second capacitor (C2), and the series branch of the second constant current source (I2) and the second discharging switch (DS2) is coupled to the second capacitor (C2) and is configured to discharge the second capacitor (C2).

7. The transmitter (100) of claim 6, wherein the compensation component (150) further comprises: a first detection circuit (153) and a first pulse generating circuit (154) coupled in series to the first output terminal (111), the first detection circuit (153) being configured to generate a first indication signal when a short circuit occurs between the high-level signal line (CANH) and the first reference potential (VCC), and the first pulse generating circuit (154) being configured to generate a first pulse signal (SP1) having a predetermined pulse width based on the first indication signal; and / or A second detection circuit (156) and a second pulse generating circuit (157) are coupled in series to the second output terminal (112), wherein the second detection circuit (156) is configured to generate a second indication signal when a short circuit occurs between the low-level signal line (CANL) and the second reference potential (GND), and the second pulse generating circuit (157) is configured to generate a second pulse signal (SP2) having a predetermined pulse width based on the second indication signal.

8. The transmitter (100) of claim 7, wherein the compensation component (150) further comprises: The control circuit (155) is configured to control the turning on and off of the first switch (S1), the second switch (S2), the third switch (S3), the first charging switch (CS1) and the first discharging switch (DS1) based on the input signal (TXD) and the first pulse signal (SP1), and / or control the turning on and off of the first switch (S1), the second switch (S2), the fourth switch (S4), the second charging switch (CS2) and the second discharging switch (DS2) based on the input signal (TXD) and the second pulse signal (SP2).

9. The transmitter (100) according to claim 4, wherein the current compensation loop further comprises: A first resistor (R1) coupled in series with the first switch (S1) between the first output terminal (111) and the intermediate node (MD); as well as A second resistor (R2) is coupled in series with the second switch (S2) between the second output terminal (112) and the middle node (MD).

10. A transceiver device (1000), comprising: The transmitter (100) according to any one of claims 1 to 9; as well as Receiver (300).

11. A communication system (10), comprising: Controller Area Network (CAN) bus (210); Common mode inductor (220); as well as The transceiver device (1000) according to claim 10 is coupled to the CAN bus (210) via the common mode inductor (220).

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