A 32apsk parallel demodulation method and system

Abstract

The present application discloses a 32APSK parallel demodulation method and system, which first receives a radio frequency signal through an antenna and converts the radio frequency signal into an intermediate frequency signal through a receiving channel through frequency conversion processing, obtains an intermediate frequency digital signal through digital-to-analog conversion, groups the intermediate frequency digital signal in the data packet with two in-phase orthogonal carriers to obtain a mixed signal, and then filters the mixed signal through a low-pass filter to generate an in-phase baseband signal and an orthogonal baseband signal; the in-phase baseband signal and the orthogonal baseband signal are sequentially resampled, frequency offset estimated, carrier synchronized, coherently demodulated and judged to obtain the judged signal, and finally equalized to remove inter-symbol interference. The method has the advantages of low data dependence and high parallelism. After obtaining the I and Q signals, symbol synchronization and carrier synchronization are achieved by open loop, with high parallelism, and is suitable for 32APSK signal demodulation on GPU platforms and at any rate.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a 32APSK parallel demodulation method and system. Background Art

[0002] Amplitude Phase Shift Keying (APSK) modulation schemes offer high spectral efficiency, with lower peak-to-average ratios and greater dynamic range than Quadrature Amplitude Modulation (QAM) of the same order. Furthermore, with increasing space payloads and increasingly scarce communication bandwidth resources, increasing the modulation order to improve system spectrum efficiency has become a common approach. Consequently, 32APSK has been widely used in satellite communications. In recent years, Graphics Processing Units (GPUs) have made significant progress in general computing, their powerful parallel processing capabilities offering new solutions for signal processing.

[0003] Currently, the traditional 32APSK demodulation system is mainly implemented using a DSP-FPGA platform. After the intermediate frequency signal is sent to a high-speed ADC for digital-to-analog conversion, the digital signal is sent to the FPGA chip for digital down-conversion, resulting in two zero-IF in-phase / quadrature (I / Q) baseband signals. The baseband signals are sent to the symbol synchronization module and the carrier synchronization module, and then to the equalization module to complete the entire demodulation process.

[0004] In traditional demodulation schemes, the symbol synchronization module is implemented using a Gardner loop, and the carrier synchronization module is implemented using a four-phase loose-tail loop. Both modules are feedback loops. This continuous feedback adjustment requires frequent thread synchronization and increases the data dependency within the algorithm. This leads to poor parallelism and is not suitable for GPU platforms. Summary of the Invention

[0005] The purpose of this application is to overcome the existing technical defects and provide a 32APSK parallel demodulation method and system. After obtaining the I and Q signals, the open loop is used to achieve symbol synchronization and carrier synchronization. It has high parallelism and is suitable for GPU platforms and 32APSK signal demodulation at any rate.

[0006] The purpose of this application is achieved through the following technical solutions:

[0007] In a first aspect, the present application proposes a 32APSK parallel demodulation method, the method comprising:

[0008] The radio frequency signal is received by an antenna and converted into an intermediate frequency signal through intermediate frequency conversion by a receiving channel;

[0009] The intermediate frequency signal is converted into an intermediate frequency digital signal through digital-analog conversion, and the intermediate frequency digital signal is grouped according to a fixed length to obtain a fixed-length data packet;

[0010] The intermediate frequency digital signal in the data packet is mixed with two-phase quadrature carriers to obtain a mixed signal;

[0011] The mixed signal is filtered by a low-pass filter to generate an in-phase baseband signal and a quadrature baseband signal;

[0012] The in-phase baseband signal and the quadrature baseband signal are sequentially resampled, frequency offset estimated, symbol distribution determined, carrier synchronized, coherently demodulated, and judged to obtain a judged signal;

[0013] The judged signal is equalized to remove inter-symbol interference.

[0014] In a possible implementation, the fixed length L is in the range of Where f s is the sampling rate of digital-analog conversion, and Δf is the difference between the actual carrier frequency and the estimated carrier frequency.

[0015] In a possible implementation, the resampled signal sampling rate is rfs, rfs = rs·M, rs is the signal symbol rate, and M is the oversampling multiple.

[0016] In a possible implementation, the frequency offset f b estimated by resampling is f1 / 16, and f1 is the frequency at which the 16th power spectrum of the resampled signal peaks.

[0017] In a possible implementation, the symbol distribution determination step includes:

[0018] The number of sampling points of the first symbol is set to x, the number of complete symbols is set to y, each complete symbol contains M sampling points, the number of sampling points of the last symbol is set to z, and the integral value v corr is calculated. Where L is the signal grouping length, s(k) is the resampled signal, p is the symbol start point, and q is the symbol end point.

[0019] The resampled signal is multiplied by the estimated frequency offset f b to obtain the result s(t): s(t) = ((I(t) + j*Q(t))*exp(j·2·pi·f b t)) 8where I(t) is the in-phase baseband signal and Q(t) is the quadrature baseband signal;

[0020] The number of sampling points M is traversed, and v corr The number of sampling points x corresponding to the maximum value is determined.

[0021] In a possible implementation, the step of carrier synchronization comprises:

[0022] Step S5-1, the frequency f e is set to the range of [-rfs / (8*N), rfs / (8*N)], and the step is set to rfs / (4*N*U), the initial phase is set to the range of [0, π], and the step is set to π / V, N is the FFT length, U represents the number of equal divisions of the frequency interval, and V represents the number of equal divisions of the phase interval;

[0023] Step S5-2, a search signal r(t) is constructed:

[0024] Step S5-3, (U+1)*(V+1) cases are traversed, and an integral value v corr is calculated, the maximum value of the integral value corresponds to f1 and is the estimation result of the initial parameters , and the corresponding step is

[0025] Step S5-4, it is judged whether the iterative search condition is met, if not, step S5-5 is executed, and if yes, step S5-6 is executed.

[0026] Step S5-5, the parameter estimation result frequency f e is set to the range of [f es -f step , f es +f step ], the step is set to 2f step / U, the initial phase is set to the range of , and the step is set to Step S5-3 is returned.

[0027] Step S5-5, the parameter estimation result

[0028] In a possible implementation, the signal obtained by coherent demodulation according to the parameter estimation result is and

[0029]

[0030] In a second aspect, the application provides a 32APSK parallel demodulation system, which comprises a radio frequency receiving channel, an analog-digital conversion module, a data packet module, a quadrature down-conversion module, a low-pass filter module, a resampling module, a symbol synchronization module, a carrier synchronization module, a demodulation module and an equalization module.

[0031] The radio frequency receiving channel is used for converting the received radio frequency signal into an intermediate frequency signal through intermediate frequency conversion.

[0032] The analog-digital conversion module is used for converting the intermediate frequency signal into an intermediate frequency digital signal through analog-digital conversion.

[0033] The data packet module is used for grouping the intermediate frequency digital signal according to a fixed length to obtain a fixed-length data packet.

[0034] The quadrature down-conversion module is used for mixing the intermediate frequency digital signal in the data packet with two-phase quadrature carriers to obtain a mixed signal.

[0035] The low-pass filter module is used for filtering the mixed signal through a low-pass filter to generate an in-phase baseband signal and a quadrature baseband signal.

[0036] The resampling module is used for sequentially resampling the in-phase baseband signal and the quadrature baseband signal.

[0037] The symbol synchronization module is used for frequency offset estimation and symbol distribution determination.

[0038] The carrier synchronization module is used for carrier synchronization.

[0039] The demodulation module is used for coherent demodulation and decision to obtain a decided signal.

[0040] The equalization module is used for equalization processing of the decided signal to remove inter-symbol interference.

[0041] The above-mentioned main scheme and each further selected scheme of the application can be freely combined to form multiple schemes, all of which are the schemes that can be adopted and claimed by the application; and the application can be freely combined between (each non-conflict selection) and other selections. Those skilled in the art can understand that there are many combinations according to the prior art and common knowledge after understanding the schemes of the application, all of which are the technical schemes claimed by the application, and are not listed here.

[0042] The application discloses a 32APSK parallel demodulation method and system. First, an antenna receives a radio frequency signal, and the radio frequency signal is converted into an intermediate frequency signal through intermediate frequency conversion processing of a receiving channel, digital-to-analog conversion is performed to obtain an intermediate frequency digital signal, grouping is performed according to a fixed length to obtain a fixed-length data packet, the intermediate frequency digital signal in the data packet is mixed with two-way in-phase and quadrature carriers to obtain a mixed signal, and a low-pass filter is used to filter the mixed signal to generate an in-phase baseband signal and a quadrature baseband signal. The in-phase baseband signal and the quadrature baseband signal are sequentially subjected to resampling, frequency offset estimation, carrier synchronization, coherent demodulation and decision to obtain a decided signal, and finally, equalization processing is performed to remove inter-symbol interference. The method has the advantages of low data dependency and high parallelism. After I and Q signals are obtained, open loop is used to realize symbol synchronization and carrier synchronization, and the parallelism is high, so the method is suitable for GPU platforms and 32APSK signal demodulation under an arbitrary rate. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0044] Figure 1 A flowchart of a 32APSK parallel demodulation method proposed in the embodiments of the application is shown.

[0045] Figure 2 A flowchart of a receiving channel to data packet proposed in the embodiments of the application is shown.

[0046] Figure 3 A flowchart of resampling to equalization processing proposed in the embodiments of the application is shown.

[0047] Figure 4 A constellation diagram after low-pass filtering proposed in the embodiments of the application is shown.

[0048] Figure 5 A constellation diagram after coherent demodulation proposed in the embodiments of the application is shown.

[0049] Figure 6 An effect diagram after equalization proposed in the embodiments of the application is shown.

[0050] Figure 7 A bit error rate performance diagram after 32APSK demodulation proposed in the embodiments of the application is shown. DETAILED DESCRIPTION

[0051] Following specific examples illustrate the embodiments of the present application, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the specification. The present application can also be implemented or applied by means of other different specific embodiments, and various modifications or changes can be made to the details in the specification without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0052] All other embodiments obtained by those skilled in the art on the basis of the embodiments in the present application without making creative efforts fall within the scope of protection of the present application.

[0053] In a traditional demodulation scheme, a Gardner loop is used to implement a symbol synchronization module, and a four-phase Matsui loop is used to implement a carrier synchronization module. Both modules are feedback loops. This constant feedback adjustment requires frequent thread synchronization and increases data dependency within the algorithm, which has poor parallelism and is not suitable for a GPU platform.

[0054] Therefore, in order to solve the problems of a large number of feedback loops, serious data dependency, and inability to parallelize processing in a traditional 32APSK demodulation system and method, the embodiments of the present application propose a 32APSK parallel demodulation method and system, which has the advantages of low data dependency and high parallelism. After obtaining I and Q signals, the loop algorithm such as a Gardner loop and a four-phase Matsui loop in the traditional method is abandoned, and open-loop symbol synchronization and carrier synchronization are used. The parallelism is high, suitable for a GPU platform and 32APSK signal demodulation at any rate. Next, a detailed description is made.

[0055] Please refer to Figure 1 , Figure 1 A flowchart of a 32APSK parallel demodulation method proposed in the embodiments of the present application is shown. The method includes the following steps:

[0056] Step S1, receiving a radio frequency signal through an antenna and converting the radio frequency signal into an intermediate frequency signal through intermediate frequency processing in a receiving channel.

[0057] After the radio frequency signal is captured by the antenna, it enters the receiving channel. The signal is processed by frequency conversion (up-conversion or down-conversion) and converted into an intermediate frequency (IF) signal, which simplifies the subsequent circuit design, reduces the requirements for component performance, and facilitates signal processing.

[0058] Step S2, performing digital-to-analog conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal, and grouping the intermediate frequency digital signal according to a fixed length to obtain a fixed-length data packet.

[0059] The conversion of the intermediate frequency signal from the analog domain to the digital domain is converted into a digital signal by an analog-to-digital converter. In order to facilitate processing and transmission, the intermediate frequency digital signal is divided into fixed-length data packets, and the continuous digital signal stream is divided into fixed-length data blocks or data packets.

[0060] Figure 2 A flowchart of the acceptance channel to data packet according to the embodiment of the application is shown. First, the RF (radio frequency) receiving channel receives signals. Then, the signals are converted into a digital stream through IF (intermediate frequency) digital conversion. Next, at the center position of the data stream, the data is input into the "data packet" link and is split into smaller data packets (packet data).

[0061] The fixed length L is in the range of Where f s is the sampling rate of the digital-to-analog conversion, and Δf is the difference between the actual carrier frequency and the estimated carrier frequency.

[0062] Step S3, mixing the intermediate frequency digital signal in the data packet with two in-phase and quadrature carriers to obtain a mixed signal;

[0063] The intermediate frequency digital signal is multiplied by the locally generated in-phase and quadrature carriers to complete the conversion from intermediate frequency to baseband. The two generated signals represent the in-phase component I and the quadrature component Q of the original signal, respectively.

[0064] Step S4, filtering the mixed signal through a low-pass filter to generate an in-phase baseband signal and a quadrature baseband signal;

[0065] The mixed signal is filtered through a low-pass filter to filter out high-frequency noise and unwanted components, and to retain the baseband signal close to direct current, thereby obtaining pure I and Q baseband signals.

[0066] The signal symbol rate rs is obtained by receiving and digital-to-analog converting the signal, and quadrature down-converting and low-pass filtering the received digital signal to obtain a low-pass filtered constellation diagram, Figure 4 A low-pass filtered constellation diagram according to the embodiment of the application is shown.

[0067] Step S5, re-sampling, frequency offset estimation, symbol distribution determination, carrier synchronization, coherent demodulation, and decision are sequentially performed on the in-phase baseband signal and the quadrature baseband signal to obtain a decision signal.

[0068] Re-sampling adjusts the sampling rate of the signal according to the requirements of demodulation and processing, including up-sampling or down-sampling, to match the sampling rate requirements of subsequent processing links. Frequency offset estimation and symbol distribution estimate the frequency offset of the received signal relative to the local reference clock by analyzing the signal characteristics, and determine the starting position and distribution of each symbol based on this, to prepare for carrier synchronization. Carrier synchronization further accurately calculates the frequency and phase of the carrier based on the results of frequency offset estimation, to achieve accurate alignment of the carrier at the receiving end and the transmitting end. The parameters of frequency offset and carrier recovery are used to perform coherent demodulation on the baseband signal, i.e. to convert it back to the original data bit stream. This process includes judging the amplitude and phase according to the 32APSK modulation rules.

[0069] Re-sampling the low-pass filtered signal based on step S4 to obtain a re-sampled signal I r (t) and Q r (t), the sampling rate of the re-sampled signal is rfs, rfs = rs·M, rs is the signal symbol rate, and M is the oversampling multiple (integer).

[0070] Figure 3 A flowchart of re-sampling to equalization processing is shown, the frequency offset f b is f1 / 16, and f1 is the frequency at which the peak of the 16th power spectrum of the re-sampled signal is located.

[0071] First, set the step size of FFT to N, and divide the signal into segments of length N for frequency domain analysis. The signal s(k) is adjusted in sampling rate by re-sampling processing, so that it is more suitable for FFT analysis or matches the sampling rate of other parts of the system. Re-sampling can reduce or increase the number of sampling points to meet specific analysis requirements. The frequency spectrum of the re-sampled signal s(k) is calculated, and further 16th power operation is performed on the amplitude values of the frequency spectrum.

[0072] Find the frequency at which the peak value is located in the processed frequency spectrum. This peak value corresponds to the frequency component with the most concentrated energy in the signal, which should theoretically be close to the actual carrier frequency of the signal. By comparing the found peak frequency with the expected carrier frequency, we can calculate the difference between the two, i.e. the frequency offset.

[0073] The step of determining the symbol distribution includes:

[0074] Set the number of sampling points of the first symbol as x, the number of complete symbols as y, the number of sampling points contained in each complete symbol as M, and the number of sampling points of the last symbol as z, and calculate the integral value v corr : where L is the signal grouping length, s(k) is the re-sampled signal, p is the symbol starting point, and q is the symbol termination point.

[0075] the resampled signal and the estimated frequency offset f b the result of the constructed carrier multiplication s(t): s(t) = ((I(t) + j*Q(t))*exp(j·2·pi·f b t)) 8 where I(t) is the in-phase baseband signal, Q(t) is the quadrature baseband signal, and pi is π;

[0076] traversing the sampling point number M, in v corr the maximum value is determined to correspond to the sampling point number x.

[0077] The sampling point number of the first symbol is set to x, which refers to the sampling number in the received signal representing the first symbol. The number of complete symbols is y: which refers to the total number of complete symbols in the current processed data segment, excluding partial symbols. The sampling point number M of each complete symbol is the number of sampling points that a complete symbol should contain. The sampling point number z of the last symbol is similar to the first symbol, which may not meet M sampling points due to boundary effects.

[0078] L is the signal packet length, which is the total length of the signal segment being analyzed, including all symbols and possible partial symbols. s(k) is the resampled signal, which ensures that the signal is suitable for further processing. The integral value v corr After that, the estimated carrier (frequency and phase) in coherent demodulation is used to multiply the resampled signal,

[0079] Traverse 1, 2, 3, …, M, check each possible starting position within the range of each complete symbol length M, and find the most likely symbol boundary through integration or other decision criteria. By traversing the integral value, the starting position (x) corresponding to the maximum integral value is found, which represents the most accurate symbol starting point, and thus the symbol distribution of the entire sequence is determined.

[0080] In one possible implementation, the step of carrier synchronization includes:

[0081] Step S5-1, setting the range of frequency f e to [-rfs / (8*N), rfs / (8*N)], and the step to rfs / (4*N*U), and setting the range of initial phase to [0, π] and the step to π / V, where N is the FFT length, U represents the number of equal divisions of the frequency interval, and V represents the number of equal divisions of the phase interval;

[0082] Step S5-2, constructing a search signal r(t):

[0083] Step S5-3, traverse (U+1)·(V+1) cases and calculate integral value v corr , the maximum value of the integral value corresponds to f1 and is the estimation result of the initial parameter The corresponding step is

[0084] Step S5-4, judge whether it meets the iteration search condition, if not, execute step S5-5, if yes, execute step S5-6;

[0085] Step S5-5, set the frequency f e of the parameter estimation result to the range of [f es -f step , f es +f step ], the step is set to 2f step / U, set the initial phase to the range of , the step is set to Return to step S5-3;

[0086] Step S5-5, output the parameter estimation result

[0087] In the process of carrier synchronization, first initialize the search space, set the frequency f e to the range of [-rfs / (8*N), rfs / (8*N)], the step is set to rfs / (4*N*U), N represents the FFT length, U represents that the frequency interval is divided into how many parts, V represents that the phase interval is divided into how many parts, in the embodiment, U=16, V=16, which can be customized.

[0088] Set the initial phase to the range of [0, π], the step is set to π / V, then construct the search signal r(t), using the initialized frequency and phase range, a series of possible carrier signals are constructed by traversing different frequency and phase values. Next, traverse all possible frequency and phase combinations, calculate the integral value of the received signal multiplied by the constructed carrier signal under each combination. The frequency f1 and phase that the integral value is the largest are the estimation results of the initial parameters The corresponding step is

[0089] Then, make an iterative judgment, if the accuracy of the preliminary estimation is high enough, that is, the preset iteration end condition is reached, skip the refinement search and directly output the parameter estimation result Otherwise, enter the more refined search stage, update the search space, set the frequency f e of the last parameter estimation result to the range of [fes -f step , f es +f step ], step size is 2*f step / U; The range of f is set to The step size is set to Again, all (U+1)*(V+1) cases are traversed, and the integral value is calculated according to formula (3), and the largest integral value corresponds to f1 and f2 , which are the estimation results of the initial parameters The corresponding step size is Until the iteration search condition is met, the iteration is stopped. Finally, the best frequency and phase estimation values obtained after multiple iterations are output as the results of carrier synchronization.

[0090] In coherent demodulation, the best frequency and phase estimation values are used to construct a local carrier that matches the received signal. This carrier is strictly aligned in frequency and phase with the carrier of the received signal. The received resampled signal is multiplied by the constructed local carrier. The signal is shifted from the carrier to the baseband, so that the signal can directly reflect the amplitude and phase information of the original modulation data.

[0091] The signal obtained by coherent demodulation according to the parameter estimation results is and

[0092]

[0093] Since M times oversampling is used, each symbol period is divided into M equally spaced sampling points. The advantage of oversampling is to improve the anti-interference ability and timing accuracy. The M / 2+1th point is selected as the final value of the symbol. Figure 5 The constellation diagram after coherent demodulation proposed in the embodiments of the present application is shown.

[0094] In step S6, the signal after decision is processed for equalization to remove inter-symbol interference.

[0095] The demodulated signal is equalized to reduce or eliminate inter-symbol interference (ISI) and ensure accurate data. The equalizer compensates for the frequency characteristics of the channel, so that the waveform of each symbol at the receiving end is as close to the ideal state as possible.

[0096] The equalization module uses conventional constant modulus algorithm (CMA) and least mean square algorithm (LMS), which will not be described here. Figure 6 The effect diagram after equalization proposed in the embodiments of the present application is shown.

[0097] Figure 7 The bit error performance diagram after 32APSK demodulation by the embodiment of the application is shown, and the performance is comparable to that of the traditional algorithm using a feedback loop.

[0098] Compared with the prior art, the embodiment of the application has the following beneficial effects:

[0099] First, the data dependency is low, and the parallelism degree is high. After the I and Q signals are acquired, the embodiment of the application discards the loop algorithm such as the Gardner loop and the four-phase Matsui loop in the traditional method, and implements symbol synchronization and carrier synchronization in an open loop, so that the parallelism degree is high and the embodiment of the application is suitable for a GPU platform.

[0100] Second, the embodiment of the application is suitable for 32APSK signal demodulation at an arbitrary rate.

[0101] A possible implementation manner of a 32APSK parallel demodulation system is given below, which is used to execute each execution step and the corresponding technical effect of the 32APSK parallel demodulation method shown in the above embodiment and the possible implementation manner. The system comprises a radio frequency receiving channel, an analog-to-digital conversion module, a data packet module, a quadrature down-conversion module, a low-pass filter module, a resampling module, a symbol synchronization module, a carrier synchronization module, a demodulation module and an equalization module.

[0102] The radio frequency receiving channel is used to convert the received radio frequency signal into an intermediate frequency signal through frequency conversion processing.

[0103] The analog-to-digital conversion module is used to perform analog-to-digital conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal.

[0104] The data packet module is used to group the intermediate frequency digital signal according to a fixed length to obtain a fixed-length data packet.

[0105] The quadrature down-conversion module is used to mix the intermediate frequency digital signal in the data packet with two-phase quadrature carriers to obtain a mixed signal.

[0106] The low-pass filter module is used to filter the mixed signal through a low-pass filter to generate an in-phase baseband signal and a quadrature baseband signal.

[0107] The resampling module is used to sequentially resample the in-phase baseband signal and the quadrature baseband signal.

[0108] The symbol synchronization module is used to perform frequency offset estimation and symbol distribution determination.

[0109] The carrier synchronization module is used to perform carrier synchronization.

[0110] The demodulation module is used to perform coherent demodulation and decision to obtain a decided signal.

[0111] An equalization module is used to equalize the decision signal and remove the intersymbol interference.

[0112] The RF receiving channel is responsible for receiving the RF signal from the space or wired link and converting it to an intermediate frequency signal. The complexity of the subsequent processing is reduced and the unwanted out-of-band interference is filtered out. The intermediate frequency signal received by the analog-to-digital conversion module (AD) is converted into a digital signal so that the computer can process the signal. The data packet module divides the continuous digital signal into data packets for easy processing.

[0113] The quadrature down-conversion module converts the intermediate frequency digital signal to the baseband, separates the in-phase component (I channel) and the quadrature component (Q channel) of the signal, which is achieved by multiplying the locally generated quadrature carrier, realizing the complex representation of the signal. The low-pass filter module (LPF) filters out the frequency multiplication components in the I channel and Q channel signals due to the down-conversion operation, retains the baseband signal, and ensures the purity of the signal. The resampling module adjusts the sampling rate of the signal according to the system requirements, which may be used to match different system clocks or optimize processing efficiency, and sometimes also used to eliminate the clock deviation caused by the inconsistent processing speed of different parts.

[0114] The symbol synchronization module estimates and corrects the frequency deviation (frequency offset) between the received signal and the local clock, and determines the accurate starting time of each symbol. The carrier recovery module estimates and compensates the carrier frequency offset and phase offset in the received signal by analyzing the I channel and Q channel signals, realizes the accurate synchronization of the carrier, and ensures the accuracy of demodulation. The demodulation module uses the synchronization information obtained in the previous step to convert the baseband signal into the original data stream. For 32APSK, this means identifying 32 different amplitude and phase combinations corresponding to 32 possible data symbols. The equalization module uses an equalizer to compensate for distortion caused by the channel, such as multipath propagation effects, to further improve signal quality and ensure that data is correctly decoded.

[0115] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A 32APSK parallel demodulation method, characterized in that: The method comprises: Receive the radio frequency signal through the antenna and convert it into an intermediate frequency signal through the receiving channel through frequency conversion processing; Performing digital-to-analog conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal, and grouping the intermediate frequency digital signal into packets of fixed length to obtain fixed-length data packets; Mixing the intermediate frequency digital signal in the data packet with two in-phase and orthogonal carrier waves to obtain a mixed signal; The mixed signal is filtered by a low-pass filter to generate an in-phase baseband signal and a quadrature baseband signal; The steps of sequentially performing resampling, frequency offset estimation, symbol distribution determination, carrier synchronization, coherent demodulation, and determination on the in-phase baseband signal and the quadrature baseband signal to obtain a signal after determination, and determining the symbol distribution include: Set the number of sampling points of the first code element to x, the number of complete code elements to y, the number of sampling points contained in each complete code element to M, the number of sampling points of the last code element to z, and calculate the integral value v corr : Where L is the signal packet length, s(k) is the resampled signal, p is the code element starting point, and q is the code element ending point; The resampled signal and the estimated frequency offset f b The result of multiplying the constructed carrier wave s(t): s(t)=((I(t)+j*Q(t))*exp(j·2·pi·f b t)) 8 , where I(t) is the in-phase baseband signal and Q(t) is the quadrature baseband signal; Traverse the number of sampling points M, in v corr When the maximum value is obtained, the corresponding number of sampling points x is determined; The steps of carrier synchronization include: Step S5-1, frequency f e The range is set to [-rfs / (8*N), rfs / (8*N)], the step is set to rfs / (4·N·U), and the initial phase The range is set to [0, π], the step is set to π / V, N is the FFT length, U represents the number of equal parts of the frequency interval, and V represents the number of equal parts of the phase interval; Step S5-2: construct search signal r(t): Step S5-3, traverse (U+1)·(V+1) cases and calculate the integral value v corr , the maximum value of the integral value corresponds to f1 and The estimated results of the initial parameters The corresponding step is Step S5-4: Determine whether the iterative search condition is met. If not, proceed to step S5-5; if so, proceed to step S5-6; Step S5-5: frequency f e The range is set to [f es -f step , f es +f step ], the step is set to 2f step / U, change the initial phase The range is set to Stepping is set to Return to step S5-3; Step S5-5: Output parameter estimation results The judged signal is equalized to remove inter-code interference.

2. The 32APSK parallel demodulation method according to claim 1, wherein: The range of fixed length L is where f s is the sampling rate of the digital-to-analog conversion, and Δf is the difference between the actual carrier frequency and the estimated carrier frequency.

3. The 32APSK parallel demodulation method according to claim 2, wherein: The sampling rate of the resampled signal is rfs, rfs = rs·M, rs is the signal symbol rate, and M is the oversampling multiple.

4. The 32APSK parallel demodulation method according to claim 1, wherein: The frequency offset f obtained by resampling the frequency offset estimation b is f1 / 16, where f1 is the frequency at which the peak of the 16th power spectrum of the resampled signal is located.

5. The 32APSK parallel demodulation method according to claim 1, wherein: The signal obtained by coherent demodulation based on the parameter estimation results is and 6. A 32APSK parallel demodulation system, characterized in that: The system includes a radio frequency receiving channel, an analog-to-digital conversion module, a data packetization module, an orthogonal down-conversion module, a low-pass filtering module, a resampling module, a symbol synchronization module, a carrier synchronization module, a demodulation module and an equalization module; The RF receiving channel is used to convert the received RF signal into an intermediate frequency signal through frequency conversion; The analog-to-digital conversion module is used to perform digital-to-analog conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal; The data packetization module is used to group the intermediate frequency digital signal into fixed-length packets to obtain fixed-length data packets; The orthogonal down-conversion module is used to mix the intermediate frequency digital signal in the data packet with two in-phase and orthogonal carriers to obtain a mixed signal; A low-pass filtering module, configured to filter the mixed signal through a low-pass filter to generate an in-phase baseband signal and a quadrature baseband signal; A resampling module, used for sequentially resampling the in-phase baseband signal and the quadrature baseband signal; The symbol synchronization module is used to estimate frequency offset and determine symbol distribution. The symbol distribution determination includes: Set the number of sampling points of the first code element to x, the number of complete code elements to y, the number of sampling points contained in each complete code element to M, the number of sampling points of the last code element to z, and calculate the integral value v corr : Where L is the signal packet length, s(k) is the resampled signal, p is the code element starting point, and q is the code element ending point; The resampled signal and the estimated frequency offset f b The result of multiplying the constructed carrier wave s(t): s(t)=((I(t)+j*Q(t))*exp(j·2·pi·f b t)) 8 , where I(t) is the in-phase baseband signal and Q(t) is the quadrature baseband signal; Traverse the number of sampling points M, in v corr When the maximum value is obtained, the corresponding number of sampling points x is determined; Carrier synchronization module, used for carrier synchronization, carrier synchronization includes: Step S5-1, frequency f e The range is set to [-rfs / (8*N), rfs / (8*N)], the step is set to rfs / (4·N·U), and the initial phase The range is set to [0, π], the step is set to π / V, N is the FFT length, U represents the number of equal parts of the frequency interval, and V represents the number of equal parts of the phase interval; Step S5-2: construct search signal r(t): Step S5-3, traverse (U+1)·(V+1) cases and calculate the integral value v corr , the maximum value of the integral value corresponds to f1 and The estimated results of the initial parameters The corresponding step is Step S5-4: Determine whether the iterative search condition is met. If not, proceed to step S5-5; if so, proceed to step S5-6; Step S5-5: frequency f e The range is set to [f es -f step , f es +f step ], the step is set to 2f step / U, change the initial phase The range is set to The stepping is set to Return to step S5-3; Step S5-5: Output parameter estimation results A demodulation module, used for coherent demodulation and judgment to obtain the judged signal; The equalization module is used to perform equalization processing on the judged signal to remove inter-symbol interference.

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