FPGA (Field Programmable Gate Array) hardware error correction structure for optical fiber transmission Bayer image

Abstract

The invention discloses an FPGA hardware error correction structure, and relates to the field of optical fiber transmission. In the process of realizing Bayer image cross-board optical fiber transmission by the FPGA, the influence of individual effective data loss on the image quality can be effectively reduced. The structure is realized based on a dual-port BRAM, a cycle counting address is inserted to serve as a write address of the BRAM, and after the write-in number reaches a preset threshold value, data are read in sequence. According to the hardware design structure, the condition of continuous dislocation of subsequent data in a data packet caused by loss of a certain effective data is improved into the condition that only one error data word exists in the data packet, so that when a subsequent image is displayed, an error part is changed into a dead pixel from a stripe, the dead pixel is hardly perceived by naked eyes, and the image quality is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of FPGA optical fiber transmission, and specifically proposes a hardware design structure, aiming to reduce the influence of data loss on image quality during the process of implementing Bayer image cross-board optical fiber transmission in FPGA. Background Art

[0002] With the rapid development of CMOS image sensor technology, Bayer format image data has been widely used in the field of image acquisition. Bayer images have shown great potential in space observation, medical imaging, military reconnaissance and other fields due to their advantages of low cost, low power consumption and high-speed acquisition.

[0003] Fiber optic transmission uses light waves as information carriers and optical fibers as transmission media. Compared with electrical transmission, it has many advantages, including wide transmission bandwidth, large communication capacity, and low transmission loss.

[0004] FPGA (Field-Programmable Gate Array), or field programmable gate array, provides strong support for the processing and transmission of high-speed image digital signals due to its high parallel processing capability and flexible programmability.

[0005] Bayer image cross-board optical fiber transmission is realized based on FPGA. The receiving board receives the Bayer format image, converts it into RGB888 format (each pixel contains three components of R, G, and B, and each component is represented by 8 bits), and then processes and displays it. Due to the large amount of data and high transmission rate of image transmission, there is often a risk of data loss, which poses a severe challenge to subsequent data processing and image quality. The present invention aims at the problem of data loss in optical fiber transmission. By inserting an error correction structure at the receiving end, the influence of data loss on image quality is reduced. Summary of the invention

[0006] Through experimental detection, it was found that when the optical fiber transmission of Bayer images is based on FPGA, data words (that is, the data transmitted in one clock cycle of the optical fiber, and the bit width of the data word is the user data bit width of the optical fiber interface) will be lost at the receiving end. Due to the color pixel arrangement pattern of the Bayer image and the characteristics of the interpolation algorithm, when data words are lost, the received Bayer image converted to RGB888 format will show striped patterns, resulting in poor image quality.

[0007] The hardware error correction structure proposed in the present invention is based on a dual-port BRAM implementation. The loop count address inserted by the sending end is used as the write address of the BRAM. When the amount of written data triggers a trigger signal, it is read out in sequence. In this way, the continuous misalignment of subsequent data in the data packet caused by the loss of data words can be converted into an error in only one data word. When the received Bayer image is subsequently converted into an RGB888 image for display, the erroneous part changes from a stripe to a bad pixel, which is almost imperceptible to the naked eye. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 There are four pixel arrangements for Bayer images;

[0009] Figure 2 The sending and receiving waveforms of the Bayer image data packet;

[0010] Figure 3 Comparison between a normal image, an image with stripes due to data loss, and an image with bad pixels after error correction;

[0011] Figure 4 It is composed of 32-bit optical fiber data;

[0012] Figure 5 An error correction design structure inserted into the optical fiber receiving end. DETAILED DESCRIPTION

[0013] The Bayer format, also known as the Bayer array, is one of the main technologies for realizing the color image capture of CMOS (complementary metal oxide semiconductor) sensors. The principle of the Bayer format is to place a filter layer in front of the image sensor, and the filter points of the filter layer correspond one-to-one to the pixels of the image sensor. Each filter point can only pass one of the three colors of red, green, and blue, allowing the sensor to capture the light intensity values ​​of different colors at the single pixel level.

[0014] A Bayer format image consists of 1 / 2 green pixels, 1 / 4 red pixels, and 1 / 4 blue pixels. This distribution is based on the fact that the human eye is most sensitive to green light.

[0015] In the Bayer format, each pixel only includes one color information. When displaying the image, interpolation is required to fill in the missing other two color information. Generally, a linear interpolation compensation algorithm is used. Figure 1 Four pixel arrangements in the Bayer image are shown, and the middle pixel is the target pixel to be interpolated.

[0016] In (a) and (b), a22(R), a22(B) and b22(R), b22(B) are respectively the average values ​​of two adjacent identical color components known in the figure. In a22(R), a22 represents the pixel position, and R represents the red component of the pixel; similarly, B represents the blue component, and G represents the green component.

[0017] In (c) and (d), c22(G) and d22(G) directly take the average of the four known Gs in the domain graph, and c22(B) or d22(R) takes the average of the four known Bs or Rs in the domain graph.

[0018] For image boundary cases, mirror copying or zero padding is required to ensure that there are pixel values ​​in the area as interpolation references. The specific implementation is not further elaborated.

[0019] The interpolation display of the Bayer image depends on the pixel arrangement rule of RGB. It is foreseeable that if the arrangement rule is disrupted, the display quality of the image will be seriously affected.

[0020] When the optical fiber interface based on the FPGA development board transmits Bayer format images, the underlying protocol of the optical fiber is Aurora8b / 10b, and the data bit width after the optical fiber interface IP configuration is 32. During transmission, the Bayer format data (8 bits) of each pixel occupies the lower 8 bits, and the upper 24 bits are idle.

[0021] Data transmission and reception Figure 2 As shown, from Figure 2 The basic composition of a single data packet can be seen in the figure: gray represents custom information or invalid data. The number of valid data in the data packet, N, is a fixed value or is determined by a field in the custom information. After the receiving end detects the data start mark, it regards the subsequent N data_rec signals as valid data and writes them into the buffer.

[0022] In optical fiber transmission, due to the large amount of data transmitted and the high transmission rate, there is often a risk of data loss. After testing, it was found that in actual cross-board optical fiber transmission, a bit error would result in the loss of a 32-bit data word.

[0023] exist Figure 2 In the example, data2 is lost during transmission, resulting in the loss of data2 in the valid data received by the receiving end, and the subsequent data is also misaligned, but the misalignment is limited to the range of one data packet.

[0024] Since the R, G, and B color components of the Bayer format image are arranged in a certain pattern, the loss of data2 will destroy this pattern, resulting in striped patterns when the image is subsequently interpolated into the RGB888 format, affecting the display effect of the entire image. Figure 3In the figure, (a) is the normal interpolation display of the image, and (b) shows a possible situation where stripes appear due to data loss.

[0025] Each data bit width of optical fiber transmission is 32, and only the lower 8 bits are used to place valid data, and the upper 24 bits are idle. This patent proposes a design scheme that uses the upper 8 bits of optical fiber transmission data as a circular address count. Each data packet starts counting from 0, and starts again from 0 after counting to 255. The 32-bit data is composed of Figure 4 shown.

[0026] The design of the receiving end is as follows Figure 5 As shown, the fiber data is first processed by the unpacking module to obtain valid data. The valid data at this time may contain data misalignment, and a write enable signal wren is generated. The upper 8 bits of the data are used as the write address wr_addr of the dual-port BRAM, and the lower 8 bits are used as the write data wr_data, which are written into the BRAM. The fiber data unpacking module will generate a trigger signal based on the write threshold (reasonably set according to the BRAM size and the number of valid data in the data packet to avoid overwriting the unread data) to notify the read address control module to read the data. rd_addr also increases from 0 each time, counts to 255 and then returns to 0. The number of consecutive reads each time is consistent with the number of valid data in the data packet.

[0027] Inserting this design in the optical fiber transmission system can effectively improve the display effect of the Bayer format image received by the receiving end. If a bit error occurs during transmission, the valid data of a Bayer image pixel will be lost together with the high 8-bit address. When the data is written into the dual-port BRAM, the address will be skipped; when the data is read out, since the read address is continuous, the final rd_data will only have one erroneous data, and the subsequent data will not be misplaced, which is reflected in the Bayer format image. Since the original RGB component arrangement is not disrupted, the final interpolated image will not have striped patches, only bad pixels caused by erroneous data, such as Figure 3 As shown in (c) in the figure, it is almost imperceptible to the naked eye.

Claims

1. An FPGA hardware error correction structure for optical fiber transmission of Bayer images, characterized in that: The structure is used to reduce the impact of data loss on image quality when FPGA implements Bayer image cross-board optical fiber transmission. The main contents include loop counting address, dual-port BRAM, trigger signal generation and read address control module. During the Bayer image transmission process, the loss of a certain valid data will cause the subsequent data in the data packet to be continuously misplaced. The structure reduces the continuous misplaced data to only one erroneous data word in the data packet, thereby only generating bad pixels that are difficult to detect with the naked eye in the subsequent image display.

2. The loop counting address according to claim 1, characterized in that: An 8-bit loop count address is generated at the optical fiber data transmitting end in the following manner: each data packet starts counting from 0, and after counting to 255, it starts looping from 0 again. The upper 8 bits of the optical fiber transmission data are used to transmit the loop count address, and the Bayer image data is transmitted via the lower 8 bits of the optical fiber data bus.

3. The dual-port BRAM according to claim 1, characterized in that: Used to store received Bayer image data, the Bayer image data is written into the dual-port BRAM according to the cycle count address.

4. The trigger signal generation according to claim 1, characterized in that: When the amount of data written to the BRAM reaches a preset threshold, the trigger signal takes effect; the preset threshold is reasonably set according to the size of the dual-port BRAM and the number of valid data in each data packet to avoid overwriting of unread data.

5. The read address control module according to claim 1, characterized in that: It is connected to the dual-port BRAM and reads data from the dual-port BRAM in sequence after detecting that the trigger signal is valid.

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