Chip, control method thereof and electronic equipment
By putting the DMA module in a power-off state in the low-power mode of the chip and using the FIFO module to buffer data, the problem of difficulty in taking into account low power consumption and data integrity in the prior art is solved, and the dual goals of low power consumption and data integrity are achieved.
Patent Information
- Application Number
- CN202411796494.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-03-25
AI Technical Summary
It is difficult for existing chips to take into account both low power consumption and data integrity in low power consumption mode. Power down of DMA modules may lead to data loss, while power down will increase power consumption without power down.
Data is transported by putting the DMA module in a powered-down state in the low power mode of the chip and using the FIFO module as the data buffer until the DMA module restarts. At the same time, when the SWP module detects the arrival of external data, it automatically switches to the active state and stores the data in the FIFO module.
It realizes a significant reduction in chip power consumption in low-power mode, while ensuring data integrity and system reliability, avoiding data loss problems.
Smart Images
Figure CN119697738A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of chips, for example, to a chip and a control method thereof, and an electronic device. Background Art
[0002] As Moore's Law is gradually realized, the scale of chips is getting larger and larger, resulting in an increase in chip power consumption. In the field of mobile devices such as mobile phones and wearable devices, increased power consumption means a decrease in battery life, which seriously affects user experience. Therefore, low-power design has become an important topic in chip design, and low-power technology has been widely used in chips.
[0003] In the chip low power design scheme of the related art, a common practice is to keep the SWP (Single Wire Protocol) module and DMA (Direct Memory Access) module powered on in the low power mode of the chip, but to perform clock gating. Although this scheme can effectively reduce dynamic power consumption, due to the large area of the DMA module, its leakage current is also large, resulting in the total power consumption of the chip in the low power mode is still high.
[0004] In addition, if the DMA module is designed to not be powered off in low-power mode, although the data integrity can be maintained, it is also easy to cause power consumption problems. Conversely, if the DMA module is powered off in low-power mode, it is easy to cause data loss, affecting the normal operation of the system. It can be seen that the chip low-power design scheme in the related art is difficult to take into account both the low power consumption and data integrity of the chip at the same time.
[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.
[0007] The embodiments of the present disclosure provide a chip and a control method thereof, and an electronic device, which can achieve the dual goals of saving energy while maintaining data integrity in a low power consumption mode of the chip.
[0008] According to a first aspect of the present disclosure, a chip control method is provided, wherein a SWP module and a DMA module in the chip are both connected to a FIFO module, and the chip control method includes:
[0009] In the low power mode of the chip, the SWP module is controlled to maintain the suspended state and the DMA module is controlled to maintain the power-off state;
[0010] In response to the SWP module receiving external data, the control chip exits the low power consumption mode, the SWP module automatically switches to an active state, and controls the SWP module to store the data in the FIFO module;
[0011] Restart the DMA module and control the DMA module to move the data in the FIFO module.
[0012] In some embodiments, before the chip enters the low power consumption mode, the chip control method includes:
[0013] Open the wake-up channel of the SWP module and configure the SWP module to the suspended state;
[0014] The control chip enters low power consumption mode and powers off the DMA module.
[0015] In some embodiments, the control chip enters a low power consumption mode and powers off the DMA module, including:
[0016] The control chip enters low power mode and powers off the DMA module;
[0017] Pull up the sleep signal, pull down the processor ready signal and DMA enable signal, and turn off the SWP clock signal and DMA clock signal.
[0018] In some embodiments, in response to the SWP module receiving external data, the control chip exits the low power consumption mode, the SWP module automatically switches to an active state, and controls the SWP module to store data in the FIFO module, including:
[0019] In response to the SWP module receiving external data, the control chip starts to exit the low power consumption mode;
[0020] Pull down the sleep signal, pull up the processor ready signal, and turn on the SWP clock signal;
[0021] The SWP module automatically switches to the active state and controls the SWP module to store data into the FIFO module through the SWP clock signal.
[0022] In some embodiments, restarting the DMA module to control the DMA module to transfer data in the FIFO module includes:
[0023] Pull up the DMA enable signal and turn on the DMA clock signal;
[0024] The DMA module is controlled by the DMA clock signal to move data in the FIFO module.
[0025] In some embodiments, the chip further includes a memory, and the memory is connected to the processor and the DMA module; the chip control method further includes: in a low power consumption mode, controlling the memory to be in a power-off state; in response to the SWP module receiving external data, restarting the memory;
[0026] Controlling the DMA module to move the data in the FIFO module includes: controlling the DMA module to move the data in the FIFO module to the memory.
[0027] According to a second aspect of the present disclosure, a chip is provided, the chip including a processor, a SWP module, a DMA module and a FIFO module, the SWP module and the DMA module are both connected to the FIFO module; the processor is communicatively connected with the SWP module and the DMA module, and the processor is configured to execute the chip control method provided by the first aspect of the present disclosure.
[0028] In some embodiments, the chip further includes a memory connected to the processor and the DMA module.
[0029] According to a third aspect of the present disclosure, an electronic device is provided, and the electronic device includes the chip provided by the second aspect of the present disclosure.
[0030] In some embodiments, the electronic device also includes a slave chip; the chip provided in the second aspect of the present disclosure serves as a master chip, the master chip is connected to the slave chip through a SWP module, and the SWP module of the master chip is used to receive data sent by the slave chip.
[0031] The chip and control method thereof, and the electronic device provided by the embodiment of the present disclosure can achieve the following technical effects: in the low-power mode of the chip, the DMA module is in a power-off state, which means that when data transmission is not required, the DMA module will not consume power, thereby significantly reducing the power consumption of the chip in the low-power mode. When the SWP module detects that external data has arrived, the processor will respond quickly, first controlling the chip to exit the low-power mode, and the SWP module automatically switches to an active state to receive data. Then, the SWP module stores the received data in the FIFO module. As a buffer mechanism, the FIFO module can temporarily save data until the DMA module resumes working, ensuring that the data will not be lost due to the power failure of the DMA module. Subsequently, the processor will restart the DMA module so that it can transfer data from the FIFO module. This process ensures the integrity of the data and the reliability of the system, and even in the short time after the chip wakes up from the low-power mode, there are sufficient mechanisms to protect the data from loss. The above method not only solves the problem of data loss caused by the power failure of the DMA module in the low-power mode, but also effectively reduces the power consumption of the chip in the low-power mode, and successfully achieves the dual goals of energy saving and data integrity in the low-power mode.
[0032] The foregoing general description and the following description are exemplary and explanatory only and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:
[0034] Figure 1 is a schematic diagram of a chip provided by an embodiment of the present disclosure;
[0035] Figure 2 is a schematic diagram of an electronic device provided by an embodiment of the present disclosure;
[0036] Figure 3 is a schematic diagram of another electronic device provided by an embodiment of the present disclosure;
[0037] Figure 4 is a flowchart of a chip control method provided by an embodiment of the present disclosure;
[0038] Figure 5 is a flow chart of another chip control method provided by an embodiment of the present disclosure;
[0039] Figure 6 is a flow chart of another chip control method provided by an embodiment of the present disclosure;
[0040] Figure 7 It is a signal timing diagram of a chip provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0041] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0042] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.
[0043] Unless otherwise stated, the term "plurality" means two or more.
[0044] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.
[0045] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.
[0046] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.
[0047] As Moore's Law is gradually realized, the scale of chips is getting larger and larger, resulting in an increase in chip power consumption. In the field of mobile devices such as mobile phones and wearable devices, increased power consumption means a decrease in battery life, which seriously affects user experience. Therefore, low-power design has become an important topic in chip design, and low-power technology has been widely used in chips.
[0048] In the chip low power design scheme of the related art, a common approach is to keep the SWP module and DMA module powered on in the low power mode of the chip, but to perform clock gating. Although this scheme can effectively reduce dynamic power consumption, due to the large area of the DMA module, its leakage current is also large, resulting in the total power consumption of the chip in the low power mode is still high.
[0049] In addition, if the DMA module is designed not to be powered off in low-power mode, although the integrity of the data can be maintained, it is also easy to cause power consumption problems. On the contrary, if the DMA module is powered off in low-power mode, it is easy to cause data loss, affecting the normal operation of the system. Specifically, when the SWP module starts to receive data, since the DMA module is in a power-off state, the DMA module needs to be restarted after the chip wakes up, and the DMA module can move the data received by the SWP module. However, it takes a while to start the DMA module, during which the data received by the SWP module is easily lost, affecting the integrity of the data and the reliability of the system. It can be seen that the chip low-power design scheme in the related art is difficult to take into account both the low power consumption and data integrity of the chip.
[0050] Combination Figure 1As shown, an embodiment of the present disclosure provides a chip, which includes a processor, a SWP (Single Wire Protocol) module, a DMA (Direct Memory Access) module and a FIFO (First-In-First-Out) module. The SWP module and the DMA module are both connected to the FIFO module, and the processor is communicatively connected to the SWP module and the DMA module.
[0051] In the embodiments of the present disclosure, the processor may be a central processing unit (CPU), a microcontroller unit (MCU), a microprocessor (MPU) or a digital signal processor (DSP), etc.
[0052] In the disclosed embodiment, SWP is a single-line communication protocol, which is usually used for low-speed, short-distance data transmission. The SWP module is used to realize the communication between the chip to which it belongs and the external object (such as other chips). The SWP module uses a clock signal (SWP_CLK) to synchronize the sending and receiving of data. The data is transmitted through a single line (SWP_DATA), which can be unidirectional or bidirectional communication.
[0053] In the disclosed embodiment, the chip also includes a PHY (Physical Layer) module. The PHY module is responsible for the physical transmission of data, and mainly handles the physical transmission and reception of data, including signal encoding, decoding, modulation, demodulation, clock synchronization, etc. The SWP module is connected to the PHY module, and the SWP module receives external data or sends data to the outside through the PHY module. Specifically, when the SWP module outputs data to the outside, it can send the data to the PHY module, and the PHY module converts the data into a corresponding voltage signal and sends the voltage signal to the external object. The external object sends a current signal to the PHY module, and the PHY module converts the current signal into corresponding data, and then transmits the data to the SWP module.
[0054] In the disclosed embodiments, DMA is a data transfer technology that allows data to be transferred directly between memory and other components without the intervention of the processor. The DMA module is used to efficiently transfer data between the memory and other components of the chip, and is widely used in data transmission, embedded systems and high-performance computing.
[0055] In the embodiment of the present disclosure, FIFO is a data structure that follows the first-in-first-out principle. Data in the FIFO module are taken out in the order in which they enter, and the earliest data to enter is processed first.
[0056] In the disclosed embodiment, both the SWP module and the DMA module are connected to the FIFO module. External data received by the SWP module can be stored in the FIFO module, and the DMA module can move the data in the FIFO module.
[0057] In some embodiments, the chip further includes a memory, which is connected to the processor and the DMA module, and the DMA module transfers the data in the FIFO module to the memory. The memory may be a flash memory or a random access memory (RAM).
[0058] Combination Figure 2 As shown, an embodiment of the present disclosure provides an electronic device, and the electronic device includes the chip provided by the above embodiment, and the chip is arranged in the device body of the electronic device.
[0059] Combination Figure 3 As shown, an embodiment of the present disclosure provides an electronic device, and the electronic device includes the chip provided in the above embodiment, and the chip provided in the above embodiment serves as a master chip. The electronic device also includes a slave chip, and the master chip and the slave chip are both arranged in the device body of the electronic device. The master chip is connected to the slave chip through a SWP module, and the SWP module of the master chip is used to receive data sent by the slave chip. The slave chip is provided with a SWP module, and the SWP module of the master chip is connected to the SWP module of the slave chip, and the master chip and the slave chip send and receive data to each other through the SWP module. Among them, the slave chip can be a smart card, for example, the slave chip can be a UICC (Universal Integrated Circuit Card, universal integrated circuit card).
[0060] In the disclosed embodiment, both the master chip and the slave chip are provided with a PHY module. PHY is responsible for the physical transmission of data, and mainly processes the physical transmission and reception of data, including signal encoding, decoding, modulation, demodulation, clock synchronization, etc.
[0061] In the master chip, the SWP module is connected to the PHY module, and the SWP module receives data sent by the slave chip or sends data to the slave chip through the PHY module. Specifically, when the SWP module of the master chip outputs data, it can send the data to the PHY module, and the PHY module converts the data into a corresponding voltage signal and sends the voltage signal to the slave chip. The slave chip sends a current signal to the PHY module of the master chip, and the PHY module of the master chip converts the current signal into corresponding data, and then transmits the data to the SWP module of the master chip.
[0062] In the slave chip, the SWP module is connected to the PHY module, and the SWP module receives data sent by the master chip or sends data to the master chip through the PHY module. Specifically, when the SWP module of the slave chip outputs data to the outside, it can send the data to the PHY module, and the PHY module converts the data into a corresponding current signal and sends the current signal to the master chip. The master chip sends a voltage signal to the PHY module of the slave chip, and the PHY module of the slave chip converts the voltage signal into corresponding data, and then transmits the data to the SWP module of the slave chip.
[0063] In combination with the chip provided by the embodiment of the present disclosure, the embodiment of the present disclosure provides a chip control method, and the execution subject of the chip control method is a processor in the chip, such as Figure 4 As shown, the chip control method includes:
[0064] S401, the processor controls the SWP module to maintain a suspended state and the DMA module to maintain a power-off state in the low power consumption mode of the chip.
[0065] In the present embodiment, the suspended state of the SWP module is referred to as the Suspend State. In the suspended state, most functions of the SWP module will be turned off or slowed down to reduce power consumption. However, in the suspended state, the SWP module still maintains basic wake-up capabilities, so the SWP module can detect the arrival of external data, thereby triggering the chip to wake up from the low power mode.
[0066] S402, in response to the SWP module receiving external data, the processor controls the chip to exit the low power consumption mode, the SWP module automatically switches to the active state, and controls the SWP module to store the data into the FIFO module.
[0067] In some embodiments, the chip to which the processor belongs can be used as a master chip, and the master chip and the slave chip are deployed in the same electronic device. The external data received by the SWP module of the master chip can be data sent by the slave chip.
[0068] In the embodiment of the present disclosure, the active state of the SWP module refers to the Active State. In the Active State, all functions of the SWP module are fully activated, and it can receive and send data normally, ensuring the efficiency and reliability of data transmission.
[0069] S403: The processor restarts the DMA module to control the DMA module to transfer data in the FIFO module.
[0070] In the disclosed embodiment, the first step of starting a new DMA module is to power it and perform initialization configuration. The initialization configuration includes setting parameters such as the source address (the address of the FIFO module), the target address (such as the address of the memory), and the transfer length. These configurations ensure that the DMA module knows where to read data from, where to write data to, and how much data to transfer. Start data transfer: Once the DMA module is correctly configured, the processor will start the DMA to move the data in the FIFO module. The DMA module will automatically read the data from the FIFO module and move the data to the specified target address (such as the memory).
[0071] In the chip control method provided by the embodiment of the present disclosure, in the low power consumption mode of the chip, the DMA module is in a power-off state, which means that when data transmission is not required, the DMA module will not consume power, thereby significantly reducing the power consumption of the chip in the low power consumption mode. When the SWP module detects that external data has arrived, the processor will respond quickly, first controlling the chip to exit the low power consumption mode, and the SWP module automatically switches to an active state to receive data. Then, the SWP module stores the received data in the FIFO module. As a buffer mechanism, the FIFO module can temporarily save data until the DMA module resumes working, ensuring that the data will not be lost due to the power failure of the DMA module. Subsequently, the processor will restart the DMA module so that it can transfer data from the FIFO module. This process ensures the integrity of the data and the reliability of the system, and even in the short time after the chip wakes up from the low power consumption mode, there are sufficient mechanisms to protect the data from loss. The above method not only solves the problem of data loss caused by the power failure of the DMA module in the low power consumption mode, but also effectively reduces the power consumption of the chip in the low power consumption mode, and successfully achieves the dual goals of energy saving and data integrity in the low power consumption mode.
[0072] In some embodiments, before the chip enters the low power mode, the chip control method includes: opening the wake-up channel of the SWP module and configuring the SWP module to a suspended state; controlling the chip to enter the low power mode and powering off the DMA module.
[0073] In combination with the chip provided in the embodiment of the present disclosure, the embodiment of the present disclosure provides another chip control method, and the execution subject of the chip control method is the processor in the chip, such as Figure 5 As shown, the chip control method includes:
[0074] S501: The processor opens a wake-up channel of the SWP module and configures the SWP module to a suspended state.
[0075] In the disclosed embodiment, before the chip enters low power consumption, the wake-up channel of the SWP module is turned on, which means that the SWP module can detect the arrival of external data in low power consumption mode. Once the data is detected, the chip can be immediately triggered to exit the low power consumption mode, so that the chip can respond and process the data quickly. This greatly shortens the time delay from waking up from low power consumption mode to data processing, and improves the real-time performance of the system.
[0076] In the present embodiment, the suspended state of the SWP module is referred to as the Suspend State. In the suspended state, most functions of the SWP module will be turned off or slowed down to reduce power consumption. However, in the suspended state, the SWP module still maintains basic wake-up capabilities, so the SWP module can detect the arrival of external data, thereby triggering the chip to wake up from the low-power mode. When the wake-up channel is turned on, the SWP module can quickly send a wake-up signal when external data is detected, so that the chip switches from the low-power mode to the normal working mode.
[0077] S502, the processor controls the chip to enter a low power consumption mode and powers off the DMA module.
[0078] S503, the processor controls the SWP module to maintain a suspended state and the DMA module to maintain a power-off state in the low power consumption mode of the chip.
[0079] S504 , in response to the SWP module receiving external data, the processor controls the chip to exit the low power consumption mode, the SWP module automatically switches to an active state, and controls the SWP module to store the data into the FIFO module.
[0080] S505: The processor restarts the DMA module to control the DMA module to transfer data in the FIFO module.
[0081] In some embodiments, the control chip enters a low power consumption mode and powers off the DMA module, including: controlling the chip to enter a low power consumption mode and powers off the DMA module; pulling up the sleep signal, pulling down the processor ready signal and the DMA enable signal, and turning off the SWP clock signal and the DMA clock signal.
[0082] In some embodiments, in response to the SWP module receiving external data, the control chip exits the low power mode, the SWP module automatically switches to an active state, and controls the SWP module to store data in the FIFO module, including: in response to the SWP module receiving external data, the control chip starts to exit the low power mode; pulls down the sleep signal, pulls up the processor ready signal, and turns on the SWP clock signal; the SWP module automatically switches to an active state, and controls the SWP module to store data in the FIFO module through the SWP clock signal.
[0083] In some embodiments, restarting the DMA module and controlling the DMA module to move data in the FIFO module includes: pulling up a DMA enable signal and turning on a DMA clock signal; and controlling the DMA module to move data in the FIFO module through the DMA clock signal.
[0084] In combination with the chip provided in the embodiment of the present disclosure, the embodiment of the present disclosure provides another chip control method, and the execution subject of the chip control method is the processor in the chip, such as Figure 6 As shown, the chip control method includes:
[0085] S601: The processor opens a wake-up channel of the SWP module and configures the SWP module to a suspended state.
[0086] S602, the processor controls the chip to enter a low power consumption mode and powers off the DMA module.
[0087] S603, the processor pulls up the sleep signal, pulls down the processor ready signal and the DMA enable signal, and turns off the SWP clock signal and the DMA clock signal.
[0088] In the disclosed embodiment, pulling up the sleep signal can indicate that the chip enters a low power consumption mode. Pulling down the processor ready signal and the DMA enable signal ensures that the processor and the DMA module stop working, thereby reducing the power consumption caused by the processor, the memory, and the DMA module. Turning off the SWP clock signal and the DMA clock signal can reduce dynamic power consumption. Optionally, the oscillator (OSC) can be further turned off to stop outputting the system clock signal and reduce dynamic power consumption.
[0089] S604: In the low power consumption mode of the chip, the processor controls the SWP module to maintain a suspended state and the DMA module to maintain a power-off state.
[0090] S605 , the processor controls the chip to exit the low power consumption mode in response to the SWP module receiving external data.
[0091] S606, the processor pulls down the sleep signal, pulls up the processor ready signal, turns on the SWP clock signal, and the SWP module automatically switches to the active state. The SWP module is controlled by the SWP clock signal to store data into the FIFO module.
[0092] In the disclosed embodiment, pulling down the sleep signal can indicate that the chip exits the low power mode and enters the normal working mode. Pulling up the processor ready signal indicates that the processor is ready to start normal work. Turning on the SWP clock signal to restore the normal output of the SWP clock signal allows the SWP module to resume normal work. When the chip starts to exit the low power mode, the oscillator is turned on in time to output the system clock signal normally, so that the processor starts to work normally.
[0093] In the disclosed embodiment, the SWP module can transmit data according to the timing of the SWP clock signal. Specifically, the SWP clock signal can be pulled high and low periodically, and each time the SWP clock signal is pulled high, the SWP module stores a data in the FIFO module.
[0094] S607, the processor pulls up the DMA enable signal and turns on the DMA clock signal.
[0095] In the embodiment of the present disclosure, when the processor starts working, the DMA enable signal is pulled high to start the DMA module, and the clock signal of the DMA module is restored so that the DMA module can work normally.
[0096] S608: The processor controls the DMA module to move data in the FIFO module through the DMA clock signal.
[0097] In the disclosed embodiment, the DMA module can perform data transmission according to the timing of the DMA clock signal. Specifically, the DMA clock signal can be periodically pulled high and low, and each time the DMA clock signal is pulled high, the DMA module moves a data in the FIFO module.
[0098] In some embodiments, the chip further includes a memory connected to the processor and the DMA module. The chip control method further includes: in a low power consumption mode, controlling the memory to be in a power-off state; and restarting the memory in response to the SWP module receiving external data.
[0099] Controlling the DMA module to move the data in the FIFO module includes: controlling the DMA module to move the data in the FIFO module to the memory.
[0100] In some embodiments, pulling the sleep signal high, pulling the processor ready signal and the DMA enable signal low, and turning off the SWP clock signal and the DMA clock signal include: pulling the sleep signal high, pulling the processor ready signal, the memory ready signal and the DMA enable signal low, and turning off the SWP clock signal and the DMA clock signal.
[0101] In the disclosed embodiment, pulling up the sleep signal can indicate that the chip enters a low power consumption mode. Pulling down the processor ready signal, the memory ready signal, and the DMA enable signal ensures that the processor, the memory, and the DMA module stop working, thereby reducing the power consumption caused by the processor, the memory, and the DMA module. Turning off the SWP clock signal and the DMA clock signal can reduce dynamic power consumption.
[0102] In some embodiments, pulling down the sleep signal, pulling up the processor ready signal, and turning on the SWP clock signal includes: pulling down the sleep signal, pulling up the processor ready signal and the memory ready signal, and turning on the SWP clock signal.
[0103] In the disclosed embodiment, pulling down the sleep signal can indicate that the chip exits the low power mode and enters the normal working mode. Pulling up the processor ready signal and the memory ready signal indicates that the processor and the memory are ready to start normal work. Turning on the SWP clock signal to restore the normal output of the SWP clock signal allows the SWP module to resume normal work. When the chip starts to exit the low power mode, the oscillator is turned on in time to output the system clock signal normally, so that the processor starts to work normally.
[0104] Figure 7 is a signal timing diagram of a chip provided by an embodiment of the present disclosure. Figure 7 In the figure, the sleep signal is represented by SLEEP, the processor ready signal is represented by CPU_RDY, the DMA enable signal is represented by DMA_EN, the DMA clock signal is represented by DMA_ACK, the SWP clock signal is represented by SWP_CLK, the system clock signal is represented by SYSCLK, the state of the SWP module is represented by SWP_STATE, the state of the SWP module includes the suspended state (SUSPEND) and the active state (ACTIVE), and the amount of data in the FIFO module is represented by FIFO_DATA_CNT.
[0105] Combination Figure 7 As shown in the figure, when preparing to enter the low power mode, the processor opens the wake-up channel of the SWP module and configures the SWP module to the suspended state. The processor controls the chip to enter the low power mode and powers off the DMA module. The processor pulls up the sleep signal, pulls down the processor ready signal, the memory ready signal and the DMA enable signal, and turns off the SWP clock signal and the DMA clock signal. In the low power mode of the chip, the processor controls the SWP module to maintain the suspended state and the DMA module to maintain the powered-off state.
[0106] The external chip (such as a slave chip) starts to send data, and the SWP module receives the external data. The amount of data in the FIFO module begins to increase. In response to the SWP module receiving external data, the processor controls the chip to exit the low power mode. The processor pulls down the sleep signal, pulls up the processor ready signal and the memory ready signal, and turns on the SWP clock signal. The processor SWP module automatically switches to an active state, and the SWP clock signal can be periodically pulled up and down. Each time the SWP clock signal is pulled up, the SWP module stores a data in the FIFO module, and the amount of data in the FIFO module begins to increase. Taking the example that the external core sends a total of 6 data, when the amount of data in the FIFO module accumulates to 3, the processor pulls up the DMA enable signal and turns on the DMA clock signal. The DMA clock signal can be periodically pulled up and down. Each time the DMA clock signal is pulled up, the DMA module moves a data in the FIFO module, and the amount of data in the FIFO module begins to increase or decrease until the amount of data in the FIFO module becomes 0.
[0107] In some embodiments, the memory in the chip is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The processor executes functional applications and data processing by running the program instructions / modules stored in the memory, that is, implementing the NFC signal detection method in the above embodiments.
[0108] In some embodiments, the memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc.
[0109] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.
[0110] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.
[0111] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.
[0112] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.
[0113] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.
Claims
1. A chip control method, characterized in that: The SWP module and DMA module in the chip are both connected to the FIFO module. The chip control method includes: In the low power mode of the chip, the SWP module is controlled to maintain the suspended state and the DMA module is controlled to maintain the power-off state; In response to the SWP module receiving external data, the control chip exits the low power consumption mode, the SWP module automatically switches to an active state, and controls the SWP module to store the data in the FIFO module; Restart the DMA module and control the DMA module to move the data in the FIFO module.
2. The chip control method according to claim 1, characterized in that: Before the chip enters low power mode, it includes: Open the wake-up channel of the SWP module and configure the SWP module to the suspended state; The control chip enters low power consumption mode and powers off the DMA module.
3. The chip control method according to claim 2, characterized in that: The control chip enters low power mode and powers down the DMA module, including: The control chip enters low power consumption mode and powers off the DMA module; Pull up the sleep signal, pull down the processor ready signal and DMA enable signal, and turn off the SWP clock signal and DMA clock signal.
4. The chip control method according to claim 3, characterized in that: In response to the SWP module receiving external data, the control chip exits the low power mode, the SWP module automatically switches to the active state, and controls the SWP module to store the data into the FIFO module, including: In response to the SWP module receiving external data, the control chip starts to exit the low power consumption mode; Pull down the sleep signal, pull up the processor ready signal, and turn on the SWP clock signal; The SWP module automatically switches to the active state and controls the SWP module to store data into the FIFO module through the SWP clock signal.
5. The chip control method according to claim 3, characterized in that: Restart the DMA module and control the DMA module to move the data in the FIFO module, including: Pull up the DMA enable signal and turn on the DMA clock signal; The DMA module is controlled by the DMA clock signal to move data in the FIFO module.
6. The chip control method according to claim 1, characterized in that: The chip also includes a memory, which is connected to the processor and the DMA module; The chip control method further includes: in a low power consumption mode, controlling the memory to be in a power-off state; in response to the SWP module receiving external data, restarting the memory; Controlling the DMA module to move the data in the FIFO module includes: controlling the DMA module to move the data in the FIFO module to the memory.
7. A chip, characterized in that: It includes a processor, a SWP module, a DMA module and a FIFO module, wherein the SWP module and the DMA module are both connected to the FIFO module; The processor is communicatively connected with the SWP module and the DMA module, and the processor is configured to execute the chip control method according to any one of claims 1 to 6.
8. The chip according to claim 7, characterized in that: The device also includes a memory, which is connected to the processor and the DMA module.
9. An electronic device, characterized in that: Comprising the chip as claimed in claim 7 or 8.
10. The electronic device according to claim 9, characterized in that: Also includes slave chips; The chip as claimed in claim 7 or 8 is used as a master chip, the master chip is connected to the slave chip through the SWP module, and the SWP module of the master chip is used to receive data sent by the slave chip.