Semiconductor structure and its preparation method

Abstract

A semiconductor structure and its fabrication method are disclosed. The semiconductor structure includes: a wire stack structure comprising a plurality of wire layers spaced apart along a vertical direction, each wire layer including a first wire portion and a second wire portion, the wire layers extending along a first direction; a memory structure located on one side of the wire stack structure along a second direction, the memory structure being electrically connected to the first wire portion; a contact plug located on the other side of the wire stack structure along the second direction, the contact plug being electrically connected to the first wire portion; and a shielding structure at least sandwiched between adjacent second wire portions in the vertical direction. The above semiconductor structure can reduce parasitic capacitance within the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is a powerful means to break through existing technological barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM that includes multilayer horizontal cells (MHC), typically comprising bit lines, transistors, and capacitors stacked on a substrate, has met the aforementioned requirements. As the integration density of semiconductor structures increases, the number of memory cells they can accommodate also increases, resulting in superior semiconductor structure performance.

[0004] However, as the number of stacked layers increases, the parasitic capacitance within the semiconductor structure becomes larger and larger. Therefore, there is an urgent need for a new semiconductor structure architecture to improve the integration density of the semiconductor structure and reduce the parasitic capacitance within the semiconductor structure. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a wire stack structure, the wire stack structure including a plurality of wire layers spaced apart along a vertical direction, each wire layer including a first wire portion and a second wire portion, the wire layers extending along a first direction; a storage structure located on one side of the wire stack structure along a second direction, the storage structure being electrically connected to the wire layers; a contact plug located on the other side of the wire stack structure along the second direction, the contact plug being electrically connected to the first wire portion; and a shielding structure, the shielding structure being at least sandwiched between adjacent second wire portions in the vertical direction.

[0006] In some embodiments, the semiconductor structure further includes a substrate; the projection of the conductive layer on the substrate is annular, the conductive layer includes two first conductive portions arranged in parallel along a second direction, and two second conductive portions are respectively connected to the two ends of the two first conductive portions; the memory structure includes a first memory structure and a second memory structure, the first memory structure and the second memory structure are respectively located on opposite sides of the conductive stack structure.

[0007] In some embodiments, the second conductor portion includes a first sub-portion, a second sub-portion, and a third sub-portion connected in sequence, the first sub-portion and the third sub-portion respectively connecting two first conductor portions, and the first sub-portion, the second sub-portion, and the third sub-portion surrounding a first groove; the shielding structure includes a vertical shielding portion and a horizontal shielding portion, the vertical shielding portion being located within the first groove and extending in the vertical direction, and the horizontal shielding portion being located between adjacent second conductor portions in the vertical direction.

[0008] In some embodiments, the shielding structure includes a conductive shielding layer and a dielectric shielding layer sandwiched between the conductive shielding layer and the second conductor portion, wherein the dielectric shielding layer conformally covers the surface of the second conductor portion.

[0009] In some embodiments, a plurality of contact plugs are arranged at intervals along a first direction, and the plurality of contact plugs are electrically connected to a plurality of first conductive portions in a one-to-one correspondence; the contact plugs include vertical conductive portions and conductive connection portions, the conductive connection portions are in contact with the corresponding first conductive portions, and the size of the conductive connection portions in a second direction is larger than the size of the vertical conductive portions in a second direction; the semiconductor structure further includes: a spacer layer surrounding the sidewall of the vertical conductive portion, the spacer layer being in contact with the conductive stack structure.

[0010] In some embodiments, the storage structure includes a storage layer located in the same layer as each conductor layer. The storage layer includes a plurality of storage cells spaced apart along a first direction. Each storage cell includes a transistor structure and a capacitor structure. One end of the transistor structure along a second direction is electrically connected to a corresponding first conductor portion, and the other end is electrically connected to the capacitor structure.

[0011] According to a second aspect of the present disclosure, another semiconductor structure is provided, comprising: a substrate; a wire stack structure including a plurality of wire layers spaced apart in a vertical direction, the wire layers extending in a first direction, the wire layers including a first wire layer and a second wire layer spaced apart in a second direction, the projections of the first wire layer and the second wire layer on the substrate being annular; a first memory structure and a second memory structure located on both sides of the wire stack structure in the second direction, the first memory structure being electrically connected to the first wire layer, and the second memory structure being electrically connected to the second wire layer; a contact plug located between the first wire layer and the second wire layer, the contact plug being electrically connected to both the first wire layer and the second wire layer; and a shielding structure, the shielding structure being at least sandwiched between adjacent wire layers in the vertical direction.

[0012] In some embodiments, both the first conductor layer and the second conductor layer include a first conductor portion and second conductor portions located at both ends of the first conductor portion, and the first conductor portion and the second conductor portion enclose a strip-shaped groove; the shielding structure includes a vertical shielding portion and a horizontal shielding portion, the vertical shielding portion is located in the strip-shaped groove and extends in the vertical direction, and the horizontal shielding portion is located between adjacent second conductor portions in the vertical direction.

[0013] In some embodiments, a plurality of contact plugs are spaced apart along a first direction, and the plurality of contact plugs are electrically connected to a first conductor layer and a second conductor layer located in the corresponding layer, respectively; the contact plugs include a vertical conductive portion and a conductive connection portion, the conductive connection portion being in contact with both the first conductor layer and the second conductor layer located in the corresponding layer, and the dimension of the conductive connection portion in the second direction being larger than the dimension of the vertical conductive portion in the second direction; the semiconductor structure further includes: a spacer layer surrounding the sidewall of the vertical conductive portion, the spacer layer being in contact with the conductor stack structure.

[0014] According to a third aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: forming a wire stack structure, the wire stack structure including a plurality of wire layers spaced apart along a vertical direction, each wire layer including a first wire portion and a second wire portion, the wire layers extending along a first direction; forming a memory structure located on one side of the wire stack structure along a second direction, the memory structure being electrically connected to the wire layers; forming a contact plug located on the other side of the wire stack structure along the second direction, the contact plug being electrically connected to the first wire portion; and forming a shielding structure, the shielding structure being at least sandwiched between adjacent second wire portions in the vertical direction.

[0015] In some embodiments, the semiconductor structure further includes a substrate; the projection of the conductive layer on the substrate is annular; forming a contact plug located on the other side of the conductive stack structure along a second direction includes: forming a filling dielectric layer in a strip-shaped groove enclosed by the conductive layer, the filling dielectric layer penetrating the conductive stack structure in a vertical direction; forming a plurality of vertical plug holes spaced apart along a first direction in the filling dielectric layer, and each vertical plug hole having a different depth; forming a spacer layer on the sidewall of the vertical plug hole; forming a connecting hole communicating with the bottom of the vertical plug hole, the connecting hole exposing a portion of the sidewall of the corresponding first conductive portion; filling the vertical plug hole and the connecting hole with a contact plug.

[0016] In some embodiments, a first dielectric layer is sandwiched between adjacent conductor layers in the vertical direction. The conductor layer includes two first conductor portions arranged parallel to each other in a second direction, and two second conductor portions are respectively connected to the two ends of the two first conductor portions. Forming a shielding structure includes: forming a first groove in a filling dielectric layer to expose the second conductor portions; removing the first dielectric layer between adjacent second conductor portions in the vertical direction along the first groove to form a conductor gap; forming a shielding structure in the conductor gap and the first groove. The shielding structure includes a conductive shielding layer and a dielectric shielding layer sandwiched between the conductive shielding layer and the second conductor portions. The dielectric shielding layer conformally covers the surface of the second conductor portions.

[0017] In this embodiment, by providing contact plugs electrically connected to the conductor layers in the second direction, the formation of additional stepped structure regions for connecting the conductor layers can be avoided, thereby effectively improving the integration density of the semiconductor structure. Furthermore, by providing a shielding structure coupled to the conductor layers, parasitic capacitance between conductor layers can be effectively reduced, signal interference between adjacent conductor layers can be decreased, thereby improving the overall electrical performance of the semiconductor structure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0020] Figure 2 This is a three-dimensional schematic diagram of a semiconductor structure according to another exemplary embodiment;

[0021] Figure 3A It is based on Figure 2 A top view schematic diagram of the semiconductor structure is shown;

[0022] Figure 3B This is a top view schematic diagram of a semiconductor structure according to another exemplary illustration;

[0023] Figure 3C This is a top view schematic diagram of a semiconductor structure according to yet another exemplary illustration;

[0024] Figure 3D This is a top view schematic diagram of a semiconductor structure as illustrated in another example;

[0025] Figure 4 This is a three-dimensional schematic diagram of a semiconductor structure according to yet another exemplary embodiment;

[0026] Figure 5 It is based on Figure 4 A top view schematic diagram of the semiconductor structure is shown;

[0027] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0028] Figure 7-15 These are top and cross-sectional views of a semiconductor structure during the fabrication process according to embodiments of this disclosure. Detailed Implementation

[0029] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0030] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0031] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0032] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0033] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0034] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0035] Three-dimensional dynamic random access memory (DRAM) typically comprises bit lines, transistors, and capacitors stacked on a substrate. Taking a semiconductor structure containing horizontal bit lines and vertical word lines as an example, parasitic capacitance exists between the stacked bit lines in the vertical direction. When the number of stacked layers is large, the presence of parasitic capacitance can easily affect the overall electrical performance of the semiconductor structure, and may even cause the semiconductor structure to malfunction. Therefore, how to improve the integration density of semiconductor structures and eliminate parasitic capacitance in the stacked structure has always been a problem that urgently needs to be solved in this field.

[0036] In view of this, in order to solve the above problems, this disclosure provides a semiconductor structure and a method for preparing the same.

[0037] Figure 1 This is a three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment. Figure 2 This is a three-dimensional schematic diagram of a semiconductor structure according to another exemplary embodiment. Figure 3A It is based on Figure 2 The diagram shown is a top view of a semiconductor structure. Figure 3B This is a top view schematic diagram of a semiconductor structure according to another exemplary illustration. Figure 3C This is a top view schematic diagram of a semiconductor structure illustrated in yet another example. Figure 3D This is a top view schematic diagram of a semiconductor structure, as illustrated in another example. Figure 4 This is a three-dimensional schematic diagram of a semiconductor structure according to yet another exemplary embodiment. Figure 5 It is based on Figure 4 The diagram shown is a top view of a semiconductor structure, which will be discussed below in conjunction with... Figures 1 to 5 The semiconductor structure is explained.

[0038] Reference Figure 1 As shown, the semiconductor structure includes a wire stack structure CL, which includes a plurality of wire layers 110 spaced apart along a vertical direction D3. Each wire layer 110 includes a first wire portion 110a and a second wire portion 110b, and extends along a first direction D1. A memory structure MG is located on one side of the wire stack structure CL along a second direction D2 and is electrically connected to the first wire portion 110a. A contact plug 210 is located on the other side of the wire stack structure CL along the second direction D2 and is electrically connected to the first wire portion 110a. A shielding structure 310 is at least sandwiched between adjacent second wire portions 110b in the vertical direction D3.

[0039] In the semiconductor structure provided in this disclosure, firstly, by providing a contact plug electrically connected to the first conductive portion along a second direction, it is possible to avoid forming additional stepped structure regions for connecting each conductive layer, thereby effectively improving the integration density of the semiconductor structure. Secondly, by providing a shielding structure coupled to the second conductive portion, it is possible to effectively reduce parasitic capacitance between conductive layers and reduce signal interference between adjacent conductive layers, thereby improving the overall electrical performance of the semiconductor structure. Thirdly, by integrating both the contact plug and the shielding structure in the region where the conductive layers are located, it is possible to further improve the integration density of the semiconductor structure and ensure the reliability of the semiconductor structure.

[0040] In some embodiments, a semiconductor structure is formed on a substrate 100, the material of which includes semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art.

[0041] In some embodiments, the multiple wire layers 110 included in the wire stack structure CL can serve as bit lines in a three-dimensional dynamic random access memory (DRAM). In other examples, the wire layers 110 can serve as word lines in a three-dimensional DRAM. The wire layers 110 extend along a first direction D1 parallel to the plane of the substrate 100, and the multiple wire layers 110 are spaced apart along a third direction D3 perpendicular to the plane of the substrate 100. The material of the wire layers 110 can be conductive materials including semiconductor materials (e.g., doped polycrystalline silicon), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The wire layers 110 can also be a multilayer structure; for example, the wire layers 110 can be a bilayer structure composed of a metal semiconductor compound and a conductive metal nitride.

[0042] In some embodiments, the conductor layer 110 includes a first conductor portion 110a and a second conductor portion 110b, wherein the second conductor portion 110b may be located at at least one end of the first conductor portion 110a along the first direction D1, for example, the second conductor portion 110b may be located at both ends of the first conductor portion 110a along the first direction. The projection of the first conductor portion 110a along the second direction D2 coincides with the projection of the storage structure MG along the second direction, the size of the first conductor portion 110a along the first direction D1 is less than or equal to the size of the storage structure MG along the first direction D1, and the projection of the second conductor portion 110b along the second direction D2 does not coincide with or only partially coincides with the projection of the storage structure MG along the second direction D2.

[0043] In one example, the projection of the second conductor portion 110b along the second direction D2 coincides only with the projection of the two columns of memory cells MC located at both ends of the first direction D1 in the memory structure MG along the second direction D2, and does not coincide at least partially with the projection of the memory cells MC located in the middle column of the memory structure MG along the second direction D2, wherein a column of memory cells MC refers to a plurality of memory cells MC stacked in the vertical direction D3.

[0044] In some embodiments, the first conductor portion 110a may be located at both ends of the second conductor portion 110b along the first direction D1, and the projection of the second conductor portion 110b along the second direction D2 falls into the projection of the storage structure MG along the second direction D2, that is, the size of the second conductor portion 110b along the first direction D1 is smaller than the size of the storage structure MG along the first direction D1.

[0045] In some embodiments, the storage structure MG includes a storage layer ML located in the same layer as each conductor layer 110. The storage layer ML includes a plurality of storage cells MC arranged at intervals along a first direction D1. Each storage cell MC includes a transistor structure 120 and a capacitor structure 130. One end of the transistor structure 120 along a second direction D2 is electrically connected to a corresponding first conductor portion 110a, and the other end is electrically connected to the capacitor structure 130.

[0046] The transistor structure 120 includes a first source-drain 122, a second source-drain 124, and a channel layer 123 located between the first source-drain 122 and the second source-drain 124. The transistor structure 120 also includes a word line structure 121. The first source-drain 122, the channel layer 123, and the second source-drain 124 are arranged sequentially along a second direction D2. The word line structure 121 extends along a vertical direction D3 and is coupled to the channel layer 123. The word line structure 121 includes a word line dielectric layer and a word line conductive layer. The word line dielectric layer is located between the word line conductive layer and the channel layer 123. The word line structure 121 can cover at least one sidewall of the channel layer 123 to form a single-gate transistor, a dual-gate transistor, or a full-ring gate transistor. The conductive layer 110 serves as a bit line and is electrically connected to one of the first source-drain 122 and the second source-drain 124. The capacitor structure 130 is electrically connected to the other of the first source-drain 122 and the second source-drain 124. The capacitor structure can be a cylindrical or columnar structure, comprising a lower electrode, a dielectric layer, and an upper electrode. The lower and upper electrodes are made of metallic materials, such as Ti, Ta, W, Cu, Al, TiN, TaN, or combinations thereof. The dielectric layer can be a high-dielectric-constant material, such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate. In other examples, the memory cell MC can also be other types of memory cells, such as phase-change memory cells or resistive switching memory cells.

[0047] In some embodiments, the contact plugs 210 and the storage structure MG are located on opposite sides of the wire stack structure CL along the second direction D2. The number of contact plugs 210 is proportional to the number of layers in the storage structure MG. For example, if multiple contact plugs 210 are coupled one-to-one with multiple storage layers ML, then the number of contact plugs 210 is the same as the number of layers in the storage structure MG. Figure 1The illustration uses three contact plugs 210 and three storage layers ML as an example. The actual number of contact plugs 210 and the number of layers in the storage structure MG can be more. Multiple contact plugs 210 are arranged at intervals along the first direction D1. The projection of each contact plug 210 along the second direction D2 can be offset from or only partially overlap with the projection of each storage cell MC along the second direction D2 along the first direction D1. Multiple contact plugs 210 are electrically connected to multiple first conductor portions 110a in a one-to-one correspondence; that is, the first conductor portion 110a of each conductor layer 110 is electrically connected to a corresponding contact plug 210. The multiple contact plugs 210 have different heights in the vertical direction D3. For example, the top surfaces of the multiple contact plugs 210 are flush with each other, but the bottom surface of each contact plug 210 is flush with the conductor layer 110 located in the same layer. Multiple contact plugs 210 electrically connected to the wire stack structure CL form a stepped structure, which saves the area occupied by the semiconductor structure in the first direction D1, thereby improving the integration of the semiconductor structure.

[0048] In some embodiments, the contact plug 210 includes a vertical conductive portion 211 and a conductive connection portion 212. The conductive connection portion 212 contacts a corresponding first conductive portion 110a. The dimension of the conductive connection portion 212 in the second direction D2 is larger than the dimension of the vertical conductive portion 211 in the second direction D2. The vertical conductive portion 211 does not contact the first conductive portion 110a. The dimension of the conductive connection portion 212 in the first direction D1 may also be larger than the dimension of the vertical conductive portion 211 in the first direction D1, that is, the projection of the vertical conductive portion 211 on the substrate 100 lies within the projection of the corresponding conductive connection portion 212 on the substrate 100. It is understood that the conductive layer 110 located in the same layer as the contact plug 210 refers to the conductive layer 110 located in the same layer as the conductive connection portion 212 in the contact plug 210, that is, the conductive layer 110 electrically connected to the contact plug 210. The material of the contact plug 210 includes a conductive material, and the material of the contact plug 210 may be the same as the material of the conductive layer 110.

[0049] In some embodiments, the shielding structure 310 is located only between adjacent second conductive portions 110b in the vertical direction D3 and not between first conductive portions 110a. The projection of the shielding structure 310 on the substrate 100 covers the projection of the second conductive portions 110b on the substrate 100.

[0050] In some embodiments, the shielding structure 310 includes a conductive shielding layer 310a and a dielectric shielding layer 310b sandwiched between the conductive shielding layer 310a and the second conductive portion 110b. The dielectric shielding layer 310b conformally covers the surface of the second conductive portion 110b. The dielectric shielding layer 310b covers at least the top and bottom surfaces of the second conductive portion 110b, and may also cover a portion of the side surfaces of the second conductive portion 110b. The dielectric shielding layer 310b prevents short circuits between the conductive shielding layer 310a and the second conductive portion 110b.

[0051] In some embodiments, the conductive shielding layer 310a is made of a conductive material, and the dielectric shielding layer 310b is made of an insulating material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxynitride, which are materials with low dielectric constants. The shielding structure 310 and the second conductive portion 110b constitute a MIM (Metal-Insulator-Metal) shielding capacitor. Since the capacitance of the MIM shielding capacitor itself is relatively small, it can reduce the parasitic capacitance between the second conductive portions 110b.

[0052] In some embodiments, the shielding structure 310 may extend along the vertical direction D3. For example, the shielding structure 310 includes an integrally formed vertical shielding portion 311 and a horizontal shielding portion 312, wherein the vertical shielding portion 311 extends along the vertical direction D3, and the horizontal shielding portion 312 protrudes along the second direction D2 from the sidewall of the vertical shielding portion 311 and is located between adjacent second conductor portions 110b in the vertical direction D3. The parasitic capacitance between all conductor layers 110 in the conductor stacking structure CL is reduced through a shielding structure 310, thereby improving the control efficiency of the shielding structure 310.

[0053] In some embodiments, refer to Figure 2 and Figure 3A and 3B As shown, the projection of the conductive layer 110 onto the substrate 100 is annular. The conductive layer 110 includes two first conductive portions 110a arranged parallel to each other along the second direction D2, and two second conductive portions 110b respectively connecting the two ends of the two first conductive portions 110a. The storage structure MG includes a first storage structure MG1 and a second storage structure MG2. The first storage structure MG1 and the second storage structure MG2 are located on opposite sides of the two first conductive portions 110a in the conductive stack structure CL and are mirror-symmetrical along the axis of the first direction D1. The storage structure MG and the contact plug 210 are located on the outer and inner sides of the annular conductive layer 110, respectively, and the shielding structure 310 is also located on the inner side of the annular conductive layer 110.

[0054] In some embodiments, the second conductor portion 110b includes a first sub-portion 110b1, a second sub-portion 110b2, and a third sub-portion 110b3 connected in sequence. The first sub-portion 110b1 and the third sub-portion 110b3 are respectively connected to two first conductor portions 110a. The first sub-portion 110b1, the second sub-portion 110b2, and the third sub-portion 110b3 form a first groove C1. The vertical shielding portion 311 of the shielding structure 310 is located in the first groove C1 and extends along the vertical direction D3. The horizontal shielding portion 312 is located between adjacent second conductor portions 110b in the vertical direction D3.

[0055] In some embodiments, the first conductive portion 110a and the second conductive portion 110b are alternately connected to form an annular structure. The contact plug 210 is located in the strip-shaped groove enclosed by the annular structure and is connected to both first conductive portions 110a located on the same layer on both sides. The projection of the second conductive portion 110b on the substrate 100 is U-shaped, so that the first conductive portion 110a electrically connected to the first storage structure MG1 and the first conductive portion 110a electrically connected to the second storage structure MG2 are electrically connected to each other. The first storage structure MG1 and the second storage structure MG2 share the conductive layer 110 to improve the control efficiency of the storage structure. The storage layers ML located on the same layer on both sides can be controlled by a single contact plug 210, thereby reducing the number of contact plugs 210. In addition, by providing the second conductor portion 110b at both ends of the first conductor portion 110a, sufficient space is reserved for the contact plug 210, and the contact plug 210 can be evenly distributed along the first direction D1, so as to reduce the parasitic capacitance between the contact plugs 210 and the parasitic capacitance between the contact plug 210 and the second conductor portion 110b.

[0056] In some embodiments, refer to Figure 3A As shown, the projection of the first conductor portion 110a along the second direction D2 coincides with the projection of the storage structure MG along the second direction. The size of the first conductor portion 110a along the first direction D1 is greater than or equal to the size of the storage structure MG along the first direction D1. The projection of the second conductor portion 110b along the second direction D2 does not coincide with the projection of the storage structure MG along the second direction D2.

[0057] In some embodiments, refer to Figure 3B As shown, the projections of the first conductor portion 110a and the second conductor portion 110b along the second direction D2 both coincide with the projection of the storage structure MG along the second direction. The size of the first conductor portion 110a along the first direction D1 is smaller than the size of the storage structure MG along the first direction D1, and the projection of the second conductor portion 110b along the second direction D2 only partially coincides with the projection of the storage structure MG along the second direction D2.

[0058] In some embodiments, refer to Figure 3CAs shown, the first conductive portion 110a and the second conductive portion 110b are arranged along the first direction D1. For example, half of the conductive layer 110 is used as the first conductive portion 110a, and the other half is used as the second conductive portion 110b. The size ratio of the first conductive portion 110a and the second conductive portion 110b along the first direction D1 can be from 1:1 to 2:1. The projections of the first conductive portion 110a and the second conductive portion 110b on the substrate 100 are both U-shaped. The shielding structure 310 and the contact plug 210 are respectively disposed in two regions of the conductive layer 110, which facilitates control over the space ratio occupied by the shielding structure 310 and the contact plug 210.

[0059] In some embodiments, refer to Figure 3D As shown, the conductive layer 110 includes two second conductive portions 110b arranged parallel to each other along the second direction D2, and two first conductive portions 110a respectively connect to the two ends of the two second conductive portions 110b. The projections of the first conductive portions 110a onto the substrate 100 are all U-shaped, and the projections of the second conductive portions 110b onto the substrate 100 are strip-shaped. A shielding structure 310 is disposed in the middle of the conductive layer 110, and contact plugs 210 are disposed at both ends of the conductive layer 110.

[0060] In some embodiments, the semiconductor structure further includes a spacer layer 220 surrounding the sidewall of the vertical conductive portion 211 of the contact plug 210. The spacer layer 220 contacts the sidewall of the wire stack structure CL, and may also contact the upper surface of the conductive connection portion 212 of the contact plug 210. The spacer layer 220 contacts the wire layer 110 above the corresponding guide layer 110 of the contact plug 210, that is, the spacer layer 220 is used to separate the contact plug 210 from the non-corresponding wire layer 110. The spacer layer 220 may be a low dielectric constant material.

[0061] Reference Figure 4 and Figure 5As shown, this disclosure also provides a semiconductor structure, including: a substrate 100; a wire stack structure CL, the wire stack structure CL including a plurality of wire layers 110 spaced apart along a vertical direction D3, the wire layers 110 extending along a first direction D1, the wire layers D1 including a first wire layer 111 and a second wire layer 112 spaced apart along a second direction D2, the projection of the first wire layer 111 and the second wire layer 112 on the substrate 100 being annular; a first memory structure MG1 and a second memory structure MG2 located on both sides of the wire stack structure CL along the second direction D2, the first memory structure MG1 being electrically connected to the first wire layer 111, and the second memory structure MG2 being electrically connected to the second wire layer 112; a contact plug 210 located between the first wire layer 111 and the second wire layer 112, the contact plug 210 being electrically connected to both the first wire layer 111 and the second wire layer 112; and a shielding structure 310, the shielding structure 310 being at least sandwiched between adjacent wire layers 110 in the vertical direction D3.

[0062] In the semiconductor structure provided in this disclosure, firstly, by providing contact plugs electrically connected to the conductive layers along a second direction, it is possible to avoid forming additional stepped structural regions for connecting the various conductive layers, thereby effectively improving the integration density of the semiconductor structure. Secondly, by providing a shielding structure coupled to the conductive layers, it is possible to effectively reduce parasitic capacitance between conductive layers and reduce signal interference between adjacent conductive layers, thereby improving the overall electrical performance of the semiconductor structure. Thirdly, by integrating both the contact plugs and the shielding structure in the region where the conductive layers are located, it is possible to further improve the integration density of the semiconductor structure and ensure the reliability of the semiconductor structure.

[0063] In some embodiments, the first storage structure MG1 and the second storage structure MG2 are respectively connected to two discrete conductive layers 110, and the discrete first conductive layers 111 and 112 are coupled to each other through contact plugs 210, so that the first conductive layers 111 and 112 on the same layer are electrically connected to each other, and the first conductive layers 111 and 112 on different layers are electrically isolated from each other, thereby reducing mutual interference between the two storage structures. The storage structure MG and the contact plugs 210 are respectively located on both sides of the annular conductive layer 110 along the second direction D2, and the shielding structure 310 is located inside the annular conductive layer 110.

[0064] In some embodiments, the first storage structure MG1 and the first conductor layer 111, the second storage structure MG2 and the second conductor layer 112 are respectively located on opposite sides of the contact plug 210 along the second direction and are mirror-symmetrical along the axis of the first direction D1.

[0065] In some embodiments, the first memory structure MG1 and the second memory structure MG2 each include a memory layer ML located on the same layer as each conductor layer 110. The memory layer ML includes a plurality of memory cells MC arranged at intervals along a first direction D1. Each memory cell MC includes a transistor structure 120 and a capacitor structure 130. One end of the transistor structure 120 is electrically connected to a corresponding first conductor portion 110a along a second direction D2, and the other end is electrically connected to the capacitor structure 130. The transistor structure 120 includes a first source-drain 122, a second source-drain 124, and a channel layer 123 located between the first source-drain 122 and the second source-drain 124. The transistor structure 120 also includes a word line structure 121.

[0066] In some embodiments, the projection of the shielding structure 310 onto the substrate 100 covers the projection of the conductive layer 110 onto the substrate 100. The first conductive layer 111 includes a first conductive portion 111a and second conductive portions 111b located at both ends of the first conductive portion 111a along the first direction D1. The second conductive layer 112 includes a first conductive portion 112a and second conductive portions 112b located at both ends of the first conductive portion 112a along the first direction D1. The projection of the second conductive portions 111b / 112b onto the substrate 100 can be rectangular or U-shaped. When the projection of the second conductive portions 111b / 112b onto the substrate 100 is U-shaped, the second conductive portion 111b of the first conductive layer 111 includes a first sub-portion 111b1, a second sub-portion 111b2, and a third sub-portion 111b3 connected in sequence, and the second conductive portion 112b of the second conductive layer 112 includes a first sub-portion 112b1, a second sub-portion 112b2, and a third sub-portion 112b3 connected in sequence.

[0067] In some embodiments, the groove formed by the second conductor portions 111b / 112b and the gap between the first conductor portions 111a / 112a together constitute a strip groove. The shielding structure 310 also fills the strip groove and extends vertically in the direction D3. Multiple first conductor layers 111 are shielded by one shielding structure 310, and multiple second conductor layers 112 are shielded by one shielding structure 310. In some examples, the shielding structures 310 corresponding to the first conductor layers 111 and the shielding structures 310 corresponding to the second conductor layers 112 are electrically connected to each other, thereby controlling the entire conductor stack structure CL through one shielding structure, further improving the control efficiency of the shielding structure 310.

[0068] In some embodiments, the contact plug 210 includes a vertical conductive portion 211 and a conductive connection portion 212. The conductive connection portion 212 contacts a corresponding first conductive layer 111 and a second conductive layer 112. The dimension of the conductive connection portion 212 in the second direction D2 is larger than the dimension of the vertical conductive portion 211 in the second direction D2. The vertical conductive portion 211 does not contact the first conductive layer 111 and the second conductive layer 112. The semiconductor structure also includes a spacer layer 220 surrounding the sidewall of the vertical conductive portion 211 of the contact plug 210. The spacer layer 220 contacts the sidewall of the conductive layer stack structure CL. The spacer layer 220 serves to separate the contact plug 210 from the non-corresponding conductive layer 110.

[0069] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figures 7 to 15 This is a schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure. The following will be combined with… Figures 6 to 15 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail, wherein, Figures 7 to 15 The left-middle image is a top-view schematic diagram of the semiconductor structure fabrication process. Figures 7 to 15 The image on the right is a cross-sectional view of the semiconductor structure fabrication process. Figures 7 to 13 The right figure in the diagram is a schematic cross-sectional view along section AA' in the left figure. Figures 14 to 15 The right image in the diagram is a sectional view along section BB' in the left image. (Refer to...) Figure 6 As shown, the preparation method includes at least the following steps:

[0070] S610: Forming a conductor stacking structure, the conductor stacking structure including a plurality of conductor layers spaced apart along the vertical direction, each conductor layer including a first conductor portion and a second conductor portion, the conductor layer extending along the first direction;

[0071] S620: Form a memory structure located on one side of the wire stack structure along the second direction, the memory structure being electrically connected to the wire layer;

[0072] S630: A contact plug is formed on the other side of the wire stack structure along the second direction, and the contact plug is electrically connected to the first wire portion;

[0073] S640: A shielding structure is formed, which is at least sandwiched between adjacent second conductor portions in the vertical direction.

[0074] It should be understood that Figure 6 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 6The steps shown can be adjusted in order according to actual needs. For example, the storage structure can be formed first, followed by the wire stack structure, or vice versa. As another example, the contact plug can be formed first, followed by the shielding structure, or vice versa.

[0075] Understandable Figures 7 to 15 Taking the second conductor portion 110b located at both ends of the first conductor portion 110a as an example, it can be as follows: Figure 3A The projection of the second conductor portion 110b along the second direction D2 shown does not coincide with the projection of the storage structure MG along the second direction D2. Alternatively, it could be as follows: Figure 3B The projection of the second conductor portion 110b along the second direction D2 coincides with the projection of the storage structure MG along the second direction D2. In other examples, it could be as follows: Figure 3C The second conductor portion 110b and the first conductor portion 110a shown are the two halves of the conductor layer 110, or as... Figure 3D The first conductor section 110a shown is located at both ends of the second conductor section 110b.

[0076] Reference Figure 7 As shown, the semiconductor structure also includes a substrate 100 on which a memory structure MG is formed. The memory structure MG includes a memory layer ML stacked in the vertical direction D3. The memory layer ML includes multiple memory cells MC arranged at intervals along the first direction D1. Each memory cell MC includes a transistor structure 120 and a capacitor structure 130. The transistor structure 120 includes a first source / drain 122, a second source / drain 124, and a channel layer 123 located between the first source / drain 122 and the second source / drain 124. The transistor structure 120 also includes a word line structure 121. One end of the transistor structure 120 along the second direction D2 is electrically connected to a corresponding first semiconductor layer 101, and the other end is electrically connected to the capacitor structure 130. Two memory structures MG can also be arranged along the second direction D2 and are mirror-symmetrical along the axis of the first direction D1. The two memory structures MG are connected by a stacked structure formed by the first semiconductor layer 101 and the first dielectric layer 102. The first semiconductor layer 101 and the memory layer ML are located on the same layer. The first semiconductor layer 101 can be made of monocrystalline silicon, and the first dielectric layer 102 can be made of an insulating material. After forming a stack of monocrystalline silicon layers and silicon germanide layers alternately by epitaxial processing, the silicon germanide layers are removed and the first dielectric layer 102 is filled.

[0077] Reference Figure 8As shown, the stacked structure formed by the first semiconductor layer 101 and the first dielectric layer 102 is etched to form a stripe T1. The dimensions of the stripe T1 along the first direction D1 and the second direction D2 are both smaller than the dimensions of the stacked structure along the first direction D1 and the second direction D2, and the projection of the remaining stacked structure onto the substrate 100 is annular. The dimension of the stripe T1 along the first direction D1 is larger than the dimension of the memory structure MG along the first direction D1, and the projection of the stripe T1 along the second direction D2 overlaps the projection of the memory structure MG along the second direction D2. In other examples, the projection of the remaining stacked structure onto the substrate 100 may be U-shaped.

[0078] Reference Figure 9 As shown, the first semiconductor layer 101 exposed by the groove T1 is removed and replaced with a conductive layer 110. Multiple conductive layers 110 are stacked at intervals along the vertical direction D3 to form a conductive stack structure. Each conductive layer 110 includes a first conductive portion 110a and a second conductive portion 110b. The first semiconductor layer 101 can be removed by a wet etching process to form gaps between the remaining first dielectric layers 102. The gaps and groove T1 are filled with conductive material layers. The conductive material layers located in the groove T1 are removed, while the conductive material layers located in the gaps are retained as conductive layer 110. The conductive layer 110 can be a double-layer structure, including a metal semiconductor compound covering the surface of the first source / drain electrode 122 and a conductive metal nitride covering the surface of the metal semiconductor compound and filling the gaps. The metal semiconductor compound can be a metal silicide such as cobalt silicide to reduce the contact resistance between the first source / drain electrode 122 and the conductive layer 110.

[0079] In some embodiments, forming a contact plug located on the other side of the wire stack structure along the second direction includes: referencing Figure 10 As shown, a filling dielectric layer 103 is formed in the strip-shaped groove T1 enclosed by the conductor layer 110, and the filling dielectric layer 103 penetrates the conductor stack structure in the vertical direction D3; Refer to Figure 11 As shown, a plurality of vertical plug holes T2 are formed in the filling medium layer 103 at intervals along the first direction D1, and the depth of each vertical plug hole T2 is different; refer to Figure 12 As shown, a spacer layer 220 is formed on the sidewall of the vertical plug hole T2; a connecting hole T3 is formed communicating with the bottom of the vertical plug hole T2, and the connecting hole T3 exposes a portion of the sidewall of the corresponding first wire portion 110a; refer to Figure 13 As shown, contact plugs 210 are filled in the vertical plug hole T2 and the connecting hole T3.

[0080] In some embodiments, with Figure 11Taking the formation of three vertically spaced plug holes T2 along the first direction D1 as an example, the three vertically spaced plug holes T2 are used to form three contact plugs corresponding to the three memory layers ML respectively. The bottom surface of the vertically spaced plug holes T2 is flush with the top surface of the conductor layer 110 corresponding to each memory layer ML. The depth of the three vertically spaced plug holes T2 arranged in the first direction D1 can increase sequentially or change discontinuously. The projection of the vertically spaced plug holes T2 in the second direction D2 can be offset from or only partially overlap with the projection of each memory cell MC along the second direction D2 along the first direction D1.

[0081] In some embodiments, an atomic layer deposition process can be used to form a conformal spacer material layer covering the inner wall of the vertical plug hole T2 to improve the step coverage for the high aspect ratio vertical plug hole T2. After forming the conformal spacer material layer covering the inner wall of the vertical plug hole T2, the spacer material layer located at the bottom of the vertical plug hole T2 is removed to retain the spacer material layer located on the sidewall of the vertical plug hole T2 as spacer layer 220. Spacer layer 220 can be an insulating material and can be a double-layer structure composed of a silicon oxide layer and a silicon nitride layer. The bottom of the vertical plug hole T2 exposes the top surface of the remaining filling dielectric layer 103. Wet etching is performed along the vertical plug hole T2 to deepen the vertical plug hole T2, forming a connecting hole T3 that exposes part of the sidewall of the corresponding first conductor portion 110a. The material of the filling dielectric layer 103 is a low dielectric constant material.

[0082] In some embodiments, for a semiconductor structure containing N storage layers ML, N-1 vertical plug holes T2 are first formed, and then N connecting holes T3 are formed, wherein the N-1 connecting holes T3 are connected to the N-1 vertical plug holes T2 in a one-to-one correspondence to form a contact plug, and the other connecting hole T3 is used alone to form a contact plug.

[0083] In some embodiments, a first dielectric layer 102 is sandwiched between adjacent conductor layers 110 in the vertical direction D3. Each conductor layer 110 includes two first conductor portions 110a arranged parallel to each other along the second direction D2, and two second conductor portions 110b are respectively connected to the two ends of the two first conductor portions 110a; forming a shielding structure 310, including: [reference] Figure 14 As shown, a first groove C1 is formed in the filling dielectric layer 103 to expose the second conductor portion 110b; the first dielectric layer 102 between adjacent second conductor portions 110b in the vertical direction D3 is removed along the first groove C1 to form a conductor gap; refer to Figure 15 As shown, a shielding structure 310 is formed in the gap between the conductors and the first groove C1. The shielding structure 310 includes a conductive shielding layer 310a and a dielectric shielding layer 310b sandwiched between the conductive shielding layer 310a and the second conductor portion 110b. The dielectric shielding layer 310b conformally covers the surface of the second conductor portion 110b.

[0084] After removing the first dielectric layer 102, a wire gap with a projected annular shape is formed, exposing the top, bottom, and inner walls of each wire layer 110. First, a dielectric shielding layer 310b is deposited to conformally cover the exposed surface of the second wire portion 110b. The thickness of the dielectric shielding layer 310b is less than half the distance between the wire layers 110. Then, a conductive shielding layer 310a is filled into the remaining wire gap and the space of the first groove C1. The end face of the dielectric shielding layer 310b along the second direction D2 is flush with the end face of the wire layer 110 along the second direction D2.

[0085] In some embodiments, the projection of each contact plug 210 along the second direction D2 may be offset from the projection of each memory cell MC along the second direction D2 along the first direction D1. After removing the first dielectric layer 102 between adjacent second conductor portions 110b in the vertical direction D3, the dielectric layer between the memory cells MCs exposed by the conductor gap is further etched to widen the conductor gap. In the widened conductor gap,

[0086] It should be noted that the first direction D1 and the second direction D2 used in this disclosure are horizontal directions parallel to the plane where the substrate 100 is located, and the first direction D1 intersects the second direction D2. For example, the first direction D1 can be perpendicular to the second direction D2. The vertical direction D3 is the direction that intersects the plane where the substrate 100 is located. For example, the vertical direction D3 is perpendicular to the plane where the substrate 101 is located. That is, the first direction D1, the second direction D2, and the vertical direction D3 are all perpendicular to each other.

[0087] In some embodiments, the semiconductor structure includes a memory, which may be a dynamic random access memory or a memory known in the art, such as a phase change memory or a ferroelectric memory.

[0088] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0089] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A conductor stacking structure, comprising a plurality of conductor layers spaced apart along a vertical direction, each conductor layer comprising a first conductor portion and a second conductor portion, the conductor layer extending along a first direction; A storage structure located on one side of the conductor stack structure along the second direction, the storage structure being electrically connected to the conductor layer; A contact plug located on the other side of the wire stacking structure along the second direction, the contact plug being electrically connected to the first wire portion; A shielding structure, wherein the shielding structure is at least sandwiched between adjacent second conductor portions in the vertical direction; The semiconductor structure further includes a substrate; The projection of the conductive layer on the substrate is annular, and the conductive layer includes two first conductive portions arranged in parallel along a second direction, with the two second conductive portions respectively connecting the two ends of the two first conductive portions; The storage structure includes a first storage structure and a second storage structure, which are located on opposite sides of the wire stack structure.

2. The semiconductor structure according to claim 1, characterized in that, The second conductor portion includes a first sub-portion, a second sub-portion, and a third sub-portion connected in sequence. The first sub-portion and the third sub-portion are respectively connected to two first conductor portions. The first sub-portion, the second sub-portion, and the third sub-portion form a first groove. The shielding structure includes a vertical shielding part and a horizontal shielding part. The vertical shielding part is located in the first groove and extends along the vertical direction, and the horizontal shielding part is located between adjacent second conductor parts in the vertical direction.

3. The semiconductor structure according to claim 1, characterized in that, The shielding structure includes a conductive shielding layer and a dielectric shielding layer sandwiched between the conductive shielding layer and the second conductor portion, wherein the dielectric shielding layer conformally covers the surface of the second conductor portion.

4. The semiconductor structure according to claim 1, characterized in that, The plurality of contact plugs are arranged at intervals along the first direction, and the plurality of contact plugs are electrically connected to the plurality of first wire portions in a one-to-one correspondence; the contact plug includes a vertical conductive portion and a conductive connection portion, the conductive connection portion is in contact with the corresponding first wire portion, and the dimension of the conductive connection portion in the second direction is larger than the dimension of the vertical conductive portion in the second direction; The semiconductor structure also includes: A spacer layer surrounds the sidewall of the vertical conductive part, and the spacer layer is in contact with the wire stack structure.

5. The semiconductor structure according to claim 1, characterized in that, The storage structure includes a storage layer located on the same layer as each of the conductor layers. The storage layer includes a plurality of storage cells arranged at intervals along a first direction. Each storage cell includes a transistor structure and a capacitor structure. One end of the transistor structure along the second direction is electrically connected to the corresponding first conductor portion, and the other end is electrically connected to the capacitor structure.

6. A semiconductor structure, characterized in that, include: Substrate; A wire stacking structure includes a plurality of wire layers spaced apart in a vertical direction, the wire layers extending in a first direction, and the wire layers including a first wire layer and a second wire layer spaced apart in a second direction, wherein the projections of the first wire layer and the second wire layer on the substrate are annular. A first storage structure and a second storage structure are located on both sides of the wire stack structure along the second direction, the first storage structure being electrically connected to the first wire layer and the second storage structure being electrically connected to the second wire layer; A contact plug located between the first conductor layer and the second conductor layer, the contact plug being electrically connected to both the first conductor layer and the second conductor layer; A shielding structure, wherein the shielding structure is at least sandwiched between adjacent conductor layers in the vertical direction.

7. The semiconductor structure according to claim 6, characterized in that, Both the first conductor layer and the second conductor layer include a first conductor portion and a second conductor portion located at both ends of the first conductor portion, and the first conductor portion and the second conductor portion form a strip-shaped groove; The shielding structure includes a vertical shielding part and a horizontal shielding part. The vertical shielding part is located in the strip groove and extends along the vertical direction, and the horizontal shielding part is located between adjacent second conductor parts in the vertical direction.

8. The semiconductor structure according to claim 6, characterized in that, The plurality of contact plugs are arranged at intervals along the first direction, and the plurality of contact plugs are electrically connected to the first conductor layer and the second conductor layer located in the corresponding layer respectively; the contact plug includes a vertical conductive part and a conductive connection part, the conductive connection part is in contact with both the first conductor layer and the second conductor layer located in the corresponding layer, and the dimension of the conductive connection part in the second direction is larger than the dimension of the vertical conductive part in the second direction; The semiconductor structure also includes: A spacer layer surrounds the sidewall of the vertical conductive part, and the spacer layer is in contact with the wire stack structure.

9. A method for fabricating a semiconductor structure, characterized in that, include: A conductor stacking structure is formed, the conductor stacking structure comprising a plurality of conductor layers spaced apart along a vertical direction, each conductor layer comprising a first conductor portion and a second conductor portion, the conductor layer extending along a first direction; A storage structure is formed on one side of the conductor stack structure along the second direction, and the storage structure is electrically connected to the conductor layer; A contact plug is formed on the other side of the wire stack structure along the second direction, and the contact plug is electrically connected to the first wire portion; A shielding structure is formed, wherein the shielding structure is at least sandwiched between adjacent second conductor portions in the vertical direction; The semiconductor structure also includes a substrate; Wherein, the projection of the conductive layer on the substrate is annular; forming a contact plug located on the other side of the conductive stack structure along the second direction includes: A filling dielectric layer is formed in the strip-shaped groove enclosed by the conductor layer, and the filling dielectric layer penetrates the conductor stack structure along the vertical direction; A plurality of vertical plug holes are formed in the filling medium layer at intervals along the first direction, and each of the vertical plug holes has a different depth; A spacer layer is formed on the sidewall of the vertical plug hole; A connecting hole is formed at the bottom of the vertical plug hole, and the connecting hole exposes a portion of the sidewall of the corresponding first wire portion; Contact plugs are filled into the vertical plug hole and the connecting hole.

10. The preparation method according to claim 9, characterized in that, A first dielectric layer is sandwiched between adjacent conductor layers in the vertical direction. The conductor layer includes two first conductor portions arranged in parallel along the second direction, and two second conductor portions are respectively connected to the two ends of the two first conductor portions. The shielding structure includes: A first groove is formed in the filling dielectric layer to expose the second conductor portion; The first dielectric layer between adjacent second conductor portions in the vertical direction is removed along the first groove to form a conductor gap; The shielding structure is formed in the gap between the conductors and the first groove. The shielding structure includes a conductive shielding layer and a dielectric shielding layer sandwiched between the conductive shielding layer and the second conductor portion. The dielectric shielding layer conformally covers the surface of the second conductor portion.

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